An on-chip compact dual-core dual-path quality factor enhancement source degradation fully differential low-noise amplifier

Abstract

This invention discloses an on-chip compact dual-core dual-path quality factor enhancement source degradation fully differential low-noise amplifier, comprising four MOS transistors, gate-source capacitors, DC blocking capacitors, bias resistors, and inductors. Four source half-turn inductors form a first transformer, and two gate-end inductors coupled together form a second transformer, which is nested within the first transformer. The first and second transformers constitute a multiplexed four-turn coupled transformer, simultaneously achieving source degradation imaginary and real part matching within the same transformer area. In differential operation, the currents in both signal paths enhance the magnetic flux, improving the effective inductance and quality factor of the inductors. This achieves on-chip integration of gate-end inductors in the Sub-6GHz band, optimizing noise, gain, and area efficiency.

Description

Technical Field

[0001] This invention relates to microwave monolithic integrated circuits and microelectronics technology, and particularly to an on-chip compact dual-core dual-path quality factor enhancement source degradation fully differential low-noise amplifier. Background Technology

[0002] With the popularization of the Internet of Things and the continuous evolution towards 5G / 6G networks, wireless communication has transformed from human-to-human connections to ubiquitous machine-to-machine communication, becoming indispensable. The coexistence of multiple standards such as Wi-Fi, Bluetooth, and ZigBee in the 2.4 GHz unlicensed band has driven a growing demand for low-power, low-cost, and highly integrated RF receivers in the Sub-6 GHz band.

[0003] In traditional receiver systems, the low-noise amplifier (LNO) in the first stage is crucial for weak signal reception, and its noise figure directly determines the sensitivity of the entire front-end system. In traditional LNO design, low power consumption and small footprint are often difficult to achieve simultaneously. Inductor-based LNO amplifiers can offer better performance, but the complex coupling network leads to a larger footprint; conversely, inductor-free designs can achieve a smaller footprint, but usually at the cost of higher power consumption.

[0004] Furthermore, common-source low-noise amplifiers (LNAs) can achieve synchronization noise matching by introducing a source-degraded inductor to align the conjugate of the input impedance with the noise impedance. However, the demand for small area and low power consumption in the Sub-6GHz front-end presents significant challenges to the design of high-performance source-degraded LNAs. To achieve better performance, the gate-matching inductor typically needs to be placed off-chip, which usually means additional wasted area in microsystems.

[0005] Therefore, in the Sub-6 GHz band, how to implement the gate-matching inductor of the source degradation structure using on-chip inductors without occupying additional area, while improving the quality factor of the source degradation inductor and the gate-matching inductor, reducing the noise figure of the low-noise amplifier, and increasing the gain is an urgent problem to be solved. Summary of the Invention

[0006] The purpose of this invention is to provide an on-chip compact dual-core dual-path quality factor enhanced source degradation fully differential low-noise amplifier.

[0007] The technical solution to achieve the purpose of this invention is as follows: an on-chip compact dual-core dual-path quality factor enhancement source degradation fully differential low-noise amplifier, comprising: a first PMOS transistor, a second NMOS transistor, a third PMOS transistor, a fourth NMOS transistor, a first gate-source capacitor, a second gate-source capacitor, a third gate-source capacitor, a fourth gate-source capacitor, a first DC blocking capacitor, a second DC blocking capacitor, a third DC blocking capacitor, and a fourth DC blocking capacitor; a first bias resistor, a second bias resistor, a third bias resistor, a fourth bias resistor, a first source-end inductor, a second source-end inductor, a third source-end inductor, a fourth source-end inductor, a first gate-end inductor, and a second gate-end inductor, wherein:

[0008] The first source inductor, the second source inductor, the third source inductor, and the fourth source inductor are all half-turn inductors, which together constitute the first transformer. The first source inductor and the second source inductor are coupled to each other, and the third source inductor and the fourth source inductor are coupled to each other. The first gate inductor and the second gate inductor are coupled to each other, which constitute the second transformer. The first transformer and the second transformer are nested together, and the second transformer is nested inside the first transformer.

[0009] The source of the first PMOS transistor is connected to one end of the first source inductor, and the other end of the first source inductor is connected to the power supply; the source of the second NMOS transistor is connected to one end of the second source inductor, and the other end of the second source inductor is grounded; the drain of the first PMOS transistor is connected to the drain of the second NMOS transistor, serving as the non-inverting output terminal of the low-noise amplifier.

[0010] The source of the third PMOS transistor is connected to one end of the third source inductor, and the other end of the third source inductor is connected to the power supply; the source of the fourth NMOS transistor is connected to one end of the fourth source inductor, and the other end of the fourth source inductor is grounded; the drain of the third PMOS transistor is connected to the drain of the fourth NMOS transistor, serving as the inverting output terminal of the low-noise amplifier.

[0011] The gate of the first PMOS transistor is connected to one end of the first DC blocking capacitor and one end of the first bias resistor. The gate of the second NMOS transistor is connected to one end of the second DC blocking capacitor and one end of the second bias resistor. The other end of the first DC blocking capacitor is connected to the other end of the second DC blocking capacitor and is connected to one end of the first gate inductor.

[0012] The gate of the third PMOS transistor is connected to one end of the third DC blocking capacitor and one end of the third bias resistor. The gate of the fourth NMOS transistor is connected to one end of the fourth DC blocking capacitor and one end of the fourth bias resistor. The other end of the third DC blocking capacitor is connected to the other end of the fourth DC blocking capacitor and connected to one end of the second gate inductor. The other ends of the first bias resistor and the third bias resistor are connected to each other for receiving a first bias voltage. The other ends of the second bias resistor and the fourth bias resistor are connected to each other for receiving a second bias voltage.

[0013] The second end of the first gate inductor and the other end of the second gate inductor serve as the non-inverting input and the inverting input of the low-noise amplifier, respectively.

[0014] Furthermore, the first gate-source capacitor is connected between the gate and source of the first PMOS transistor; the second gate-source capacitor is connected between the gate and source of the second NMOS transistor; the third gate-source capacitor is connected between the gate and source of the third PMOS transistor; and the fourth gate-source capacitor is connected between the gate and source of the fourth NMOS transistor.

[0015] Furthermore, the first PMOS transistor and the second NMOS transistor constitute the first inverter amplification core, and the third PMOS transistor and the fourth NMOS transistor constitute the second inverter amplification core. The first inverter amplification core and the second inverter amplification core are arranged symmetrically.

[0016] Furthermore, in the first transformer, the first source-end inductor and the second source-end inductor are tightly coupled, and their coupling coefficient k s12 ≥0.7, the third source inductor and the fourth source inductor are tightly coupled, and their coupling coefficient k s34 ≥0.7; In the second transformer, the first gate inductor and the second gate inductor are tightly coupled, with a coupling coefficient k g12 ≥0.8.

[0017] Furthermore, in differential mode, when the input signal is in the positive half-cycle, the current flowing through the first source inductor and the second source inductor are in the same direction, forming an enhanced magnetic flux in the upper half-cycle. In addition, the current flowing through the first gate inductor is in the same direction as the current flowing through the first source inductor and the second source inductor, which further enhances the total magnetic flux. The two currents are injected into the first inverter amplification core at the same time, forming the first signal path.

[0018] When the input signal is in the negative half-cycle, the current flowing through the third source inductor and the fourth source inductor is in the same direction, forming an enhanced magnetic flux in the lower half-cycle. In addition, the current flowing through the second gate inductor is in the same direction as the current flowing through the third and fourth source inductors, which further enhances the total magnetic flux. The two currents are injected into the second inverter amplification core at the same time, forming the second signal path.

[0019] Furthermore, the first transformer is the source degradation inductor of the low-noise amplifier, and the second transformer is the gate-end series resonant matching network of the low-noise amplifier.

[0020] Furthermore, the low-noise amplifier operates in the Sub-GHz band.

[0021] Furthermore, the inductance values ​​L of the first source-end inductor, the second source-end inductor, the third source-end inductor, and the fourth source-end inductor are... s The capacitance C of the first gate-source capacitor, the second gate-source capacitor, the third gate-source capacitor, and the fourth gate-source capacitor. gs The transconductance g of the first PMOS transistor and the third PMOS transistor m1 And the transconductance g of the second NMOS transistor and the fourth NMOS transistor m2 To achieve real-part matching of the input impedance to a set value (typically 50Ω), the following relationship must be satisfied:

[0022] ;

[0023] Among them, Z re The real part matching impedance is set.

[0024] Furthermore, the effective inductance L of the first gate inductor and the second gate inductor g The inductance values ​​L of the first source-end inductor, the second source-end inductor, the third source-end inductor, and the fourth source-end inductor s And the capacitance C of the first gate-source capacitor, the second gate-source capacitor, the third gate-source capacitor, and the fourth gate-source capacitor. gs The following relationship must be satisfied to achieve imaginary part matching of the input impedance to a set value (usually set to 0Ω):

[0025] ;

[0026] Among them, Z im The imaginary matching impedance is set, freq is the operating frequency of the low-noise amplifier, and k is the frequency of the low-noise amplifier. g12 is the coupling coefficient between the first gate inductance and the second gate inductance.

[0027] An electronic device comprising the aforementioned on-chip compact dual-core dual-path quality factor enhanced source degradation fully differential low-noise amplifier.

[0028] Compared with the prior art, the significant advantages of this invention are:

[0029] 1) A compact on-chip dual-core dual-path quality factor enhanced source degradation fully differential low-noise amplifier was designed, operating in the 2.4 GHz unlicensed frequency band. It achieves on-chip integration of gate-matching inductors and maintains a high quality factor.

[0030] 2) The four-turn transformer structure simultaneously achieves impedance matching between the gate matching inductor and the source degraded inductor, optimizing the noise figure and reducing power consumption. The four-turn transformer consists of a nested first transformer T1 and a second transformer T2, which reduces chip area while avoiding negative coupling between inductors and reducing production costs.

[0031] 3) Using a toroidal inductor formed by combining half-turn inductors as the source degradation inductor enhances the inductance quality factor and effectively reduces the losses introduced by the source degradation inductor.

[0032] 4) Match the gate terminals of the differential circuit with inductor L g1 L g2 The mutual coupling enhances the quality factor and doubles the effective inductance value, thus enabling an on-chip design of a gate-matched inductor for the Sub-6 GHz band.

[0033] 5) It adopts a fully differential dual-core structure, which, combined with a four-turn transformer, forms two signal paths, promoting mutual reinforcement of differential currents and further improving circuit performance. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the circuit structure and principle.

[0035] Figure 2 A comparison chart showing the improvement in inductor performance.

[0036] Figure 3 The gain and noise figure frequency response curves are shown.

[0037] Figure 4 This is a comparison chart of performance with traditional structures.

[0038] Figure 5 This is a chip layout. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0040] This invention provides an on-chip compact dual-core dual-path quality factor enhanced source degradation fully differential low-noise amplifier. Based on a nested on-chip transformer structure, it simultaneously achieves source degradation imaginary and real part matching within the same transformer area. While realizing on-chip integration of Sub-6 GHz band gate-end inductors, it significantly improves the effective inductance and quality factor of the inductors, thereby optimizing the amplifier's noise performance, gain, and area efficiency.

[0041] I. Circuit Composition and Component Functions

[0042] like Figure 1 As shown, an on-chip compact dual-core dual-path quality factor enhancement source degradation fully differential low-noise amplifier specifically includes:

[0043] First PMOS transistor M1, second NMOS transistor M2, third PMOS transistor M3, fourth NMOS transistor M4;

[0044] First gate-source capacitance C gs1 Second gate-source capacitance C gs2 Third gate-source capacitance C gs3 Fourth gate-source capacitance C gs4 These are used to set the impedance characteristics of each transistor input node;

[0045] First gate inductance L g1 Second gate inductor L g2 ;

[0046] First DC blocking capacitor C d1 Second DC blocking capacitor C d2 The third DC blocking capacitor C d3 Fourth DC blocking capacitor C d4 ;

[0047] First source inductor L s1 Second source inductor L s2 Third source inductor L s3 Fourth source inductor L s4 ;

[0048] First bias resistor R b1 Second bias resistor R b2 Third bias resistor R b3 Fourth bias resistor R b4 and the first and second bias voltages V bias1 and V bias2 .

[0049] Among them, the first source inductor L s1 Second source inductor L s2 Third source inductor L s3 and the fourth source inductor Ls4 Both are half-turn inductors, which together form the first transformer T1 through close magnetic coupling, serving as the source degradation inductor. The first gate inductor L... g1 Second gate inductance L g2 A second transformer T2 is constructed through tight magnetic coupling, serving as a series resonant matching inductor at the gate terminals. To achieve a compact layout, the second transformer T2 is nested inside the first transformer T1, together forming a four-turn transformer structure.

[0050] II. Specific Connection Relationships

[0051] The specific circuit connection relationship of this invention is as follows:

[0052] The source of the first PMOS transistor M1 is connected to the first source inductor L. s1 One end, the first source inductor L s1 The other end is connected to the power supply V. DD The source of the second NMOS transistor M2 is connected to the second source inductor L. s2 One end, the second source inductor L s2 The other end is grounded V SS The drain of the first PMOS transistor M1 is connected to the drain of the second NMOS transistor M2, and together they serve as the non-inverting output terminal OUTP of the low-noise amplifier.

[0053] The source of the third PMOS transistor M3 is connected to the third source inductor L. s3 One end, the third source inductor L s3 The other end is connected to the power supply V. DD The source of the fourth NMOS transistor M4 is connected to the fourth source inductor L. s4 One end, the fourth source inductor L s4 The other end is grounded V SS The drain of the third PMOS transistor M3 is connected to the drain of the fourth NMOS transistor M4, and together they serve as the inverting output terminal OUTN of the low-noise amplifier.

[0054] The gate of the first PMOS transistor M1 is connected to the first DC blocking capacitor C. d1 One end and the first bias resistor R b1 One end. The gate of the second NMOS transistor M2 is connected to the second DC blocking capacitor C. d2 One end and the second bias resistor R b2 One end of the first DC blocking capacitor C. d1 The other end is connected to the second DC blocking capacitor C d2 After the other end is connected, they are both connected to the first gate inductor L. g1 One end.

[0055] The gate of the third PMOS transistor M3 is connected to the third DC blocking capacitor C.d3 One end and the third bias resistor R b3 One end. The gate of the fourth NMOS transistor M4 is connected to the fourth DC blocking capacitor C. d4 One end and the fourth bias resistor R b4 One end. The third DC blocking capacitor C. d3 The other end is connected to the fourth DC blocking capacitor C d4 After the other end is connected, they are connected together to the second gate inductor L. g2 One end.

[0056] First bias resistor R b1 With the third bias resistor R b3 The other end is connected to receive the first bias voltage V from the outside. bias1 The second bias resistor R b2 and the fourth bias resistor R b4 The other ends are connected together to receive a second bias voltage V from the outside. bias2 .

[0057] First gate inductance L g1 The other end serves as the non-inverting input terminal INP of the low-noise amplifier, and the second gate inductor L... g2 The other end serves as the inverting input INN of the low-noise amplifier.

[0058] First gate-source capacitance C gs1 The second gate-source capacitance C is connected between the gate and source of the first PMOS transistor M1. gs2 It is connected between the gate and source of the second NMOS transistor M2. The third gate-source capacitance C gs3 It is connected between the gate and source of the third PMOS transistor M3. The fourth gate-source capacitance C gs4 It is connected between the gate and source of the fourth NMOS transistor M4.

[0059] Figure 1 In the example shown, metal layer M9 is represented by a green coil, metal layer M8 by a dark green coil, and metal layer AP by a light gray coil. Each transformer coil in the figure is indicated by a solid line and arrow to show the current flow direction. Those skilled in the art can use this information to... Figure 1 The current flow shown in the diagram makes it easy to determine the corresponding terminals of each inductor coil.

[0060] III. Working Principle and Dual-Path Mechanism

[0061] Dual-core amplification structure: The first PMOS transistor M1 and the second NMOS transistor M2 form the first inverter amplification core, i.e., core-1; the third PMOS transistor M3 and the fourth NMOS transistor M4 form the second inverter amplification core, i.e., core-2. The two cores are arranged symmetrically to provide fully differential amplification function.

[0062] The differential input signal is coupled to the two amplification cores via the second transformer T2. For the positive half-cycle signal, current flows in from the non-inverting input terminal INP, through the first gate inductor L. g1 First DC blocking capacitor C d1 Drive the first PMOS transistor M1, and simultaneously through the second DC blocking capacitor C d2 Drive the second NMOS transistor M2 to form a current from VDD through the first source inductor L s1 To the first PMOS transistor M1, from VSS through the second source inductor L s2 The current to M2 ultimately flows through the drains of the first PMOS transistor M1 and the second NMOS transistor M2, and is output from the positive output terminal OUTP. The negative half-cycle current flows in from the inverting input terminal INN, through the second gate inductor L... g2 The third DC blocking capacitor C d3 Drives the third PMOS transistor M3, and simultaneously through the fourth DC blocking capacitor C d4 Drive the fourth NMOS transistor M4 to form a current from VDD through the third source inductor L s3 To the third PMOS transistor M3, from VSS through the fourth source inductor L s4 The current flowing to the fourth NMOS transistor M4 eventually flows through the drain terminals of the third PMOS transistor M3 and the fourth NMOS transistor M4, and is output from the inverting output terminal OUTN.

[0063] Dual-path mechanism:

[0064] This is the key to improving the performance of this invention. For example... Figure 1 As shown by the current arrow, in differential operating mode, current flows through the first source inductor L. s1 With the second source inductor L s2 The currents in these two parts are in the same direction, and their complementary currents enhance each other, forming an enhanced magnetic flux in the upper half-cycle. Additionally, the current flowing through the first gate terminal inductor L... g1 The current flowing through the first source inductor L s1 Second source inductor L s2 The currents are in the same direction, further enhancing the total magnetic flux. Both currents are injected into core-1 simultaneously, marking it as the first signal path, i.e., path-1; the current flows through the third source inductor L. s3 With the fourth source inductor L s4 The currents in these two parts are in the same direction, and their complementary currents enhance each other, forming an enhanced magnetic flux in the lower half-cycle. Additionally, the current flowing through the second gate terminal inductor L... g2 The current flowing through the third source inductor L s3 Fourth source inductor L s4The currents are in the same direction, further enhancing the total magnetic flux. Both currents are injected simultaneously into core-2, designated as the second signal path, i.e., path-2. This significantly enhances the magnetic flux within the first transformer T1 and the second transformer T2. This magnetic field superposition effect of the currents in the same direction is equivalent to significantly increasing the effective inductance L and quality factor Q of each inductor, thereby reducing noise, increasing gain, and effectively reducing power consumption.

[0065] IV. Specific Design Methods and Parameter Determination

[0066] The following steps can be followed to design the low-noise amplifier of this invention to ensure optimal noise and impedance matching in the target frequency band (e.g., Sub-6 GHz):

[0067] Step 1: Based on the overall power consumption specifications of the low-noise amplifier in the system, determine the transconductance g required by the first pair of PMOS transistors M1 and M3. m1 And the transconductance g required by the second pair of NMOS transistors M2 and M4 m2 .

[0068] Step 2: Calculate the source degenerate network parameters to achieve real part matching. The real part of the input impedance of the source degenerate structure is determined by the source inductance (L). s1 L s2 L s3 L s4 The sensitivity value L) s Gate-source capacitance (C) gs1 C gs2 C gs3 C gs4 The capacitance value C gs and transistor transconductance g m1 g m2 This is jointly determined. To achieve real-part matching with the source impedance, the following relationship must be satisfied:

[0069] ;

[0070] Among them, Z re The target real part value (typically 50Ω) is matched to the set input impedance. L can be determined using this formula based on the selected operating frequency freq. s With C gs The ratio relationship is determined, and the specific value is determined by combining the process library and simulation.

[0071] Step 3: Calculate the gate-end matching inductance parameters to achieve imaginary part matching. The gate-end inductance and gate-source capacitance resonate at the operating frequency freq to cancel the imaginary part of the input impedance. The required effective inductance value L of the gate-end inductance is... g It should meet the following requirements:

[0072] ;

[0073] Among them, Z im The imaginary part of the input impedance is matched to a target value (typically tending to 0Ω). Due to the coupling effect of the second transformer T2, the single gate-end inductance (L... g1 or L g2 The physical sense value can be designed to be approximately L. g / 2.

[0074] Step 4: Set the four sensitivity values ​​to L s half-turn inductor (L) s1 L s2 L s3 L s4 The transformers are arranged in a tightly coupled manner to form the first transformer T1, with a coupling coefficient k. s12 With k s34 It should be as high as possible (e.g., ≥0.7). The two sensitivity values ​​are approximately L. g / 2 inductance (L g1 L g2 The second transformer T2 is arranged in a tightly coupled manner, with a coupling coefficient k. g12 It should also be as high as possible (e.g., ≥0.8). Nest T2 inside T1 to form an area-efficient four-turn transformer structure, and optimize the layout so that parasitic coupling between the two does not affect the overall impedance matching.

[0075] Step 5: Based on the above preliminary parameters, build the complete circuit and determine the DC blocking capacitor (C). d1 ~C d4 ), bias resistor (R) b1 ~R b4 The values ​​of other components such as )

[0076] V. Applications and Extensions

[0077] This invention discloses an on-chip compact dual-core dual-path quality factor enhanced source-degraded fully differential low-noise amplifier, which is particularly suitable for Sub-6 GHz wireless communication systems with stringent requirements for power consumption, area, and noise performance. It can be widely used in devices such as smartphones, tablets, IoT terminals, and base station RF front-ends.

[0078] Based on the same inventive concept, the present invention also provides an electronic device comprising the on-chip compact dual-core dual-path quality factor enhancement source degradation fully differential low-noise amplifier described in any of the above technical solutions.

[0079] Example

[0080] To verify the effectiveness of this invention, a specific design embodiment applied to the 2.4 GHz ISM band is provided, and its key parameters are shown in Table 1:

[0081] Table 1 Key Parameter Values ​​of Low Noise Amplifier

[0082]

[0083] like Figure 2 As shown, due to the flux enhancement effect of co-directional coupling, the effective inductance of the source inductor increases from approximately 506 pH when isolated to approximately 870 pH after coupling, and the quality factor Q at 2.4 GHz significantly improves from 12.6 to 23.9. The effective inductance of the gate inductor increases from approximately 5.32 nH to approximately 9.88 nH, and the quality factor Q improves from 13.2 to 17.8.

[0084] like Figure 3 As shown, this amplifier achieves a maximum gain of 15.64 dB and a minimum noise figure of 1.04 dB under the TT process corner simulation; a maximum gain of 14.71 dB and a minimum noise figure of 0.88 dB under the FF process corner simulation; and a maximum gain of 14.61 dB and a minimum noise figure of 1.26 dB under the SS process corner simulation.

[0085] like Figure 4 As shown, under the condition of achieving the same input real impedance matching as the traditional source degraded structure and achieving maximum gain matching, the required gate physical inductance value of this invention is reduced from 7nH to 4nH; under the condition of achieving the same input real impedance matching as the traditional source degraded structure and achieving minimum noise matching, the required gate physical inductance value of this invention is reduced from 8nH to 5nH. The required gate physical inductance value for both matching methods is only about half that of the traditional structure. Simulation results show that, under ideal conditions, this invention reduces the noise figure by 0.2 dB and increases the gain by 3 dB.

[0086] Figure 5 The chip layout of the design is shown, with a core circuit area of ​​only about 0.16 mm², demonstrating its ability to achieve high performance in a tiny area.

[0087] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0088] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. An on-chip compact dual-core dual-path quality factor enhancement-type source degradation fully differential low-noise amplifier, characterized in that, include: a first PMOS transistor M1, a second NMOS transistor M2, a third PMOS transistor M3, a fourth NMOS transistor M4, a first gate-source capacitor C gs1 , a second gate-source capacitor C gs2 , a third gate-source capacitor C gs3 , a fourth gate-source capacitor C gs4 , a first direct-current blocking capacitor C d1 , a second direct-current blocking capacitor C d2 , a third direct-current blocking capacitor C d3 , a fourth direct-current blocking capacitor C d4 , a first bias resistor R b1 , a second bias resistor R b2 , a third bias resistor R b3 , a fourth bias resistor R b4 , a first source-end inductor L s1 , a second source-end inductor L s2 , a third source-end inductor L s3 , a fourth source-end inductor L s4 , a first gate-end inductor L g1 , and a second gate-end inductor L g2 , wherein: The first source inductor L s1 Second source inductor L s2 Third source inductor L s3 With the fourth source inductor L s4 Both are half-turn inductors, which together constitute the first transformer T1, wherein the first source inductor L s1 With the second source inductor L s2 Mutually coupled, the third source inductor L s3 With the fourth source inductor L s4 Mutually coupled; the first gate terminal inductor L g1 Second gate inductance L g2 They are coupled together to form a second transformer T2; the first transformer T1 and the second transformer T2 are nested together, and the second transformer T2 is nested inside the first transformer T1. The source of the first PMOS transistor M1 is connected to the first source inductor L. s1 One end, the first source inductor L s1 The other end is connected to the power supply V. DD The source of the second NMOS transistor M2 is connected to the second source inductor L. s2 One end, the second source inductor L s2 The other end is grounded V SS The drain of the first PMOS transistor M1 is connected to the drain of the second NMOS transistor M2, serving as the non-inverting output terminal OUTP of the low-noise amplifier. The source of the third PMOS transistor M3 is connected to the third source inductor L. s3 One end of the third source inductor L s3 The other end is connected to the power supply V. DD The source of the fourth NMOS transistor M4 is connected to the fourth source inductor L. s4 At one end, the fourth source inductor L s4 The other end is grounded V SS The drain of the third PMOS transistor M3 is connected to the drain of the fourth NMOS transistor M4, serving as the inverting output terminal OUTN of the low-noise amplifier. The gate of the first PMOS transistor M1 is connected to the first DC blocking capacitor C. d1 One end and the first bias resistor R b1 At one end, the gate of the second NMOS transistor M2 is connected to the second DC blocking capacitor C. d2 One end and the second bias resistor R b2 At one end, the first DC blocking capacitor C d1 The other end is connected to the second DC blocking capacitor C d2 The other end is connected and connected to the first gate inductor L. g1 One end; The gate of the third PMOS transistor M3 is connected to the third DC blocking capacitor C. d3 One end and the third bias resistor R b3 At one end, the gate of the fourth NMOS transistor M4 is connected to the fourth DC blocking capacitor C. d4 One end and the fourth bias resistor R b4 At one end, the third DC blocking capacitor C d3 The other end is connected to the fourth DC blocking capacitor C d4 The other end is connected and connected to the second gate inductor L. g2 One end; the first bias resistor R b1 With the third bias resistor R b3 The other end is connected to the first bias voltage V. bias1 The second bias resistor R b2 With the fourth bias resistor R b4 The other end is connected to the other end to receive the second bias voltage V. bias2 ; The first gate inductor L g1 Second gate inductance L g2 The other end serves as the non-inverting input INP and the inverting input INN of the low-noise amplifier, respectively.

2. The low-noise amplifier according to claim 1, characterized in that, The first gate-source capacitance C gs1 The second gate-source capacitance C is connected between the gate and source of the first PMOS transistor M1. gs2 The third gate-source capacitor C is connected between the gate and source of the second NMOS transistor M2. gs3 The fourth gate-source capacitor C is connected between the gate and source of the third PMOS transistor M3. gs4 It is connected between the gate and source of the fourth NMOS transistor M4.

3. The low-noise amplifier according to claim 1, characterized in that, The first PMOS transistor M1 and the second NMOS transistor M2 constitute the first inverter amplification core, and the third PMOS transistor M3 and the fourth NMOS transistor M4 constitute the second inverter amplification core. The first inverter amplification core and the second inverter amplification core are arranged symmetrically.

4. The low-noise amplifier according to claim 1, characterized in that, In the first transformer T1, the first source-end inductor L s1 With the second source inductor L s2 Tight coupling, with a coupling coefficient k s12 ≥0.7, the third source inductance L s3 With the fourth source inductor L s4 Tight coupling, with a coupling coefficient k s34 ≥0.7; In the second transformer T2, the first gate terminal inductance L g1 With the second gate inductor L g2 Tight coupling, coupling coefficient k g12 ≥0.

8.

5. The low-noise amplifier according to claim 3, characterized in that, In differential operating mode, when the input signal is in the positive half-cycle, the current flows through the first source inductor L. s1 With the second source inductor L s2 The currents flow in the same direction, creating an enhanced magnetic flux in the upper half-cycle. Additionally, the current flows through the first gate terminal inductor L... g1 The current flowing through the first source inductor L s1 Second source inductor L s2 The currents are in the same direction, which further enhances the total magnetic flux. The two currents are injected into the first inverter amplification core at the same time, forming the first signal path. When the input signal is in the negative half-cycle, current flows through the third source inductor L. s3 With the fourth source inductor L s4 The currents flow in the same direction, creating an enhanced magnetic flux in the lower half-cycle. Additionally, the current flows through the second gate inductor L... g2 The current flowing through the third source inductor L s3 and the fourth source inductor L s4 The currents are in the same direction, which further enhances the total magnetic flux. The two currents are injected into the second inverter amplification core at the same time, forming the second signal path.

6. The low-noise amplifier according to claim 1, characterized in that, The first transformer T1 is the source degradation inductor of the low-noise amplifier, and the second transformer T2 is the gate-end series resonant matching network of the low-noise amplifier.

7. The low-noise amplifier according to claim 1, characterized in that, The low-noise amplifier operates in the 2.4 GHz unlicensed frequency band.

8. The low-noise amplifier according to claim 1, characterized in that, The first source inductor L s1 Second source inductor L s2 Third source inductor L s3 Fourth source inductor L s4 The value of L s The first gate-source capacitance C gs1 Second gate-source capacitance C gs2 Third gate-source capacitance C gs3 Fourth gate-source capacitance C gs4 The capacitance value C gs The transconductance g of the first PMOS transistor M1 and the third PMOS transistor M3 m1 And the transconductance g of the second NMOS transistor M2 and the fourth NMOS transistor M4 m2 The following relationship must be satisfied to achieve real part matching of the input impedance to a set value: ； Among them, Z re The real part matching impedance is set.

9. The low-noise amplifier according to claim 8, characterized in that, The first gate inductor L g1 With the second gate inductor L g2 Effective Sensitivity Value L g The first source inductor L s1 Second source inductor L s2 Third source inductor L s3 Fourth source inductor L s4 The value of L s and the first gate-source capacitance C gs1 Second gate-source capacitance C gs2 Third gate-source capacitance C gs3 Fourth gate-source capacitance C gs4 The capacitance value C gs The following relationship must be satisfied to achieve imaginary part matching of the input impedance to a set value: ； Among them, Z im The imaginary matching impedance is set, freq is the operating frequency of the low-noise amplifier, and k is the frequency of the low-noise amplifier. g12 For the first gate inductance L g1 With the second gate inductor L g2 The coupling coefficient.

10. An electronic device, characterized in that, Including the on-chip compact dual-core dual-path quality factor enhanced source degradation fully differential low-noise amplifier as described in any one of claims 1 to 9.

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