NRZ-TI-DACs system oriented to QAM wireless transmission and data processing method of NRZ-TI-DACs system

Abstract

The invention discloses a QAM wireless transmission oriented NRZ-TI-DACs system and a data processing method thereof, and belongs to the field of ultra-wideband signal generation, and the system comprises a digital signal processor, a phase shift clock, two paths of high-speed DACs, an auxiliary DAC and a superposition output circuit. The method comprises the following steps that: a high-frequency digital input sequence generates two paths of two-frequency-division digital sequences and one path of three-frequency-division compensation digital sequence which are subjected to compensation processing through an improved differential decomposition algorithm of a digital signal processor; the two paths of two-way frequency division digital sequences are respectively sent to two paths of high-speed DACs, and the compensation sequences are sent to an auxiliary DAC; two paths of same-frequency out-phase clocks are used for driving the corresponding DACs respectively; finally, the analog signals output by the three paths of DACs are superposed, and ultra-wideband analog signals are synthesized and output. Through cooperation of an algorithm and hardware, DAC output peak values are effectively limited, system power consumption is reduced, waveform stability is enhanced, lossless data conversion is realized, and low bit error rate and symbol error rate are ensured.

Description

Technical Field

[0001] This invention belongs to the field of DAC combination to generate ultra-wideband signals, and specifically relates to an NRZ-TI-DACs system for QAM wireless transmission and its data processing method. Background Technology

[0002] Currently, common systems for generating ultra-wideband signals based on multiple DACs can be categorized into time-domain interleaved DACs (TI-DAC), frequency-domain interleaved DACs (FI-DAC), and time-frequency interleaved DACs (JFTI-DAC). The time-domain interleaving method uses periodically interleaved clocks to drive multiple DACs to switch at different times, then utilizes the superposition principle of analog signals to synthesize high-frequency signals. The frequency-domain interleaving method uses additional carrier channels to load the DAC output signals onto different frequency bands, achieving continuous ultra-wideband signal generation. Within the time-domain interleaving method, based on the characteristics of the DAC output signal, it can be further divided into Return-to-Zero (RZ) mode and Non-Return-to-Zero (NRZ) mode. Using RZ mode, the DAC can be controlled to operate in either the first or second half of the cycle before synthesis. Synthesis in RZ-TI-DAC mode within a DAC is generally limited to dual-DAC waveform synthesis; for RZ-DAC synthesis with more DACs (AMUX-DAC), analog multiplexers or high-frequency switches are typically used to control only one DAC to output at a time, thereby achieving ultra-wideband output. Time-frequency interleaving fully utilizes return-to-zero synthesis and frequency domain interleaving features to achieve broadband signal output. For the synthesis of non-return-to-zero modes (NRZ-TI-DAC) within a DAC, the output signals of multiple DAC channels will undergo analog superposition, resulting in complex broadband signals, but information extraction is difficult. One data processing method for NRZ-TI-DACs utilizes a differential algorithm, which theoretically can achieve perfect signal recovery, but the output of independent DAC channels may become infinitely large. Therefore, currently, there are no practically applied hardware modules or chips based on NRZ-TI-DACs. Summary of the Invention

[0003] To address the challenges of recovering wideband waveforms generated by NRZ-TI-DACs in existing technologies, as well as the divergence of independent DAC channel outputs under differential algorithms, this paper proposes an NRZ-TI-DACs system and its data processing method for QAM wireless transmission. This method effectively controls the infinite expansion of data from independent DAC channels while ensuring that the superimposed output signal perfectly preserves the original input desired signal, thus guaranteeing the feasibility of the NRZ-TI-DACs system.

[0004] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0005] An NRZ-TI-DACs system for QAM wireless transmission includes a digital signal processor, a phase-shifting clock, a first high-speed DAC, a second high-speed DAC, an auxiliary DAC, and a superposition output circuit. The digital signal processor has one input data channel and three output data channels. The input data channel receives one high-frequency digital input sequence. The three output data channels are defined as a first data channel, a second data channel, and a compensation data channel, respectively connected to the input terminals of the first high-speed DAC, the second high-speed DAC, and the auxiliary DAC. The digital signal processor executes an improved differential decomposition algorithm on the received high-frequency digital input sequence, generating two compensated 2-division digital sequences in the first and second data channels, and generating a 3-division compensated digital sequence in the compensation data channel. The phase-shifting clock generates two clocks with the same frequency, the second clock being 180° phase-shifted relative to the first clock. The first clock drives the first high-speed DAC and the auxiliary DAC, and the second clock drives the second high-speed DAC. The superposition output circuit, connected to the output terminals of the first high-speed DAC, the second high-speed DAC, and the auxiliary DAC, superimposes the three analog output signals to synthesize a single ultra-wideband analog signal.

[0006] Furthermore, the sampling rates of the first and second high-speed DACs are both half the sampling rate of the high-frequency digital input sequence; the sampling rate of the auxiliary DAC is one-third of the sampling rate of the high-frequency digital input sequence.

[0007] Furthermore, the superimposed output circuit is a composite circuit structure on a printed circuit board or a circuit structure based on an adder.

[0008] This invention also protects a data processing method for an NRZ-TI-DACs system for QAM wireless transmission, comprising the following steps:

[0009] Step 1: Input a high-frequency digital input sequence to the digital signal processor. The digital signal processor, based on the improved differential decomposition algorithm, compensates the two 2-frequency-divided digital sequences generated by the decomposition by introducing a 3-frequency-divided compensation digital sequence. Finally, the two 2-frequency-divided digital sequences after compensation are output through the first data channel and the second data channel, and a 3-frequency-divided compensation digital sequence is output through the compensation data channel.

[0010] Step 2: Send the two 2-division digital sequences to the first high-speed DAC and the second high-speed DAC respectively, and send the one 3-division compensated digital sequence to the auxiliary DAC;

[0011] Step 3: Use two in-phase clocks generated by phase-shifting clocks to drive the first high-speed DAC, the auxiliary DAC, and the second high-speed DAC, respectively.

[0012] Step 4: Superimpose the analog signals output from the first high-speed DAC, the second high-speed DAC, and the auxiliary DAC to synthesize an ultra-wideband analog signal corresponding to the original high-frequency digital input sequence, thereby realizing the conversion from digital signal to analog signal.

[0013] Furthermore, the steps for the digital signal processor to execute the improved differential decomposition algorithm are as follows:

[0014] Let the compensation digital sequence be denoted as Original input sequence minus Input sequence after compensation ;

[0015] Based on the compensated input sequence Perform difference decomposition according to odd and even periods, and output two frequency-divided digital sequences, i.e. and ;

[0016] The odd-period and even-period operating modes are as follows:

[0017] In the odd cycle: First data channel: Second data channel: ;

[0018] Even period: First data channel: Second data channel: ;

[0019] And the initial data for the first cycle is set as follows: ; .

[0020] Furthermore, the compensation occurs after at least three cycles, with the data settings remaining unchanged in the first cycle: ; .

[0021] Furthermore, the generation of the compensated digital sequence includes two steps: direction determination and compensation data acquisition.

[0022] The direction determination is achieved by multiplying the current channel's hold value by the current input sequence value and comparing the product with 0 to determine whether the current hold value and the input sequence are in the same direction.

[0023] The compensation data is obtained using any of the following methods:

[0024] a) Based on the current held value, after determining the compensation direction, output the corresponding positive or negative value according to the direction, and maintain it for 3 cycles;

[0025] b) Combining the current held value and the three future input sequence values ​​to be transmitted, directly calculate the absolute value data of the four values, calculate the proportional relationship between the values, and output a positive or negative value after proportional adjustment based on the direction determination result, and maintain it for 3 cycles.

[0026] Furthermore, the sampling rate of the auxiliary DAC is 1 / 3 of the sampling rate of the high-frequency digital input sequence, and each value of the supplementary data channel is maintained for 3 cycles; when the compensation occurs in an odd period, the value of the second data channel will be compensated; when the compensation occurs in an even period, the value of the first data channel will be compensated.

[0027] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0028] This invention adds a compensation channel, which includes improvements to the differential numerical decomposition method and additional hardware assistance, enabling the differential output to converge to a certain range, thereby reducing the implementation difficulty of the NRZ-TI-DACs-based system.

[0029] This invention ensures that the high-frequency DAC with a sampling rate of 1 / 2 can operate at the Nyquist rate by adding an auxiliary DAC with a 1 / 3 rate, thereby limiting the maximum output voltage of the high-frequency DAC, reducing the overall power consumption, and enhancing the stability of the synthesized waveform.

[0030] This invention employs a hardware compensation method, without subjecting the data to forced processing such as peak limiting, thereby achieving lossless data transformation and ideal synthesis, and ensuring the bit error rate and symbol error rate of the method applied in the complete system. Attached Figure Description

[0031] Figure 1 This is a diagram illustrating the implementation architecture of the NRZ-TI-DACs system based on the auxiliary channel of this invention.

[0032] Figure 2 This is a schematic diagram of the digital signal differential decomposition of the NRZ-TI-DACs system of the present invention;

[0033] Figure 3 This is a schematic diagram showing the location of the NRZ-TI-DACs system of the present invention in a typical communication system;

[0034] Figure 4 This is a schematic diagram illustrating waveform decomposition, synthesis, and sampling based on the NRZ-TI-DACs system of this invention;

[0035] Figure 5 The output waveforms for the compensation data assistance and non-intervention methods of this invention are shown. Detailed Implementation

[0036] To make the technical solution of the present invention clearer, the technical solution of the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments.

[0037] like Figure 1 As shown, this invention provides an NRZ-TI-DACs system for QAM wireless transmission, including a digital signal processor, a phase-shifting clock, a first high-speed DAC, a second high-speed DAC, an auxiliary DAC, and a superposition output circuit. The digital signal processor is configured with one input data channel and three output data channels. The input data channel is used to receive one high-frequency digital input sequence. The three output data channels are defined as the first data channel, the second data channel, and the compensation data channel, and are respectively connected to the input terminals of the first high-speed DAC, the second high-speed DAC, and the auxiliary DAC. The digital signal processor processes the received high-frequency digital input sequence... The system executes an improved differential decomposition algorithm to generate two compensated 2-division digital sequences in the first and second data channels, and one 3-division compensated digital sequence in the compensated data channel. A phase-shifting clock is used to generate two clocks with the same frequency, and the phase of the second clock is offset by 180° relative to the first clock. The first clock is used to drive the first high-speed DAC and the auxiliary DAC, and the second clock is used to drive the second high-speed DAC. A superposition output circuit is connected to the output terminals of the first high-speed DAC, the second high-speed DAC, and the auxiliary DAC to superimpose the three analog output signals and synthesize them into one ultra-wideband analog signal.

[0038] Specifically, the sampling rates of the first and second high-speed DACs are both half the sampling rate of the high-frequency digital input sequence; the sampling rate of the auxiliary DAC is one-third of the sampling rate of the high-frequency digital input sequence.

[0039] Specifically, the superimposed output circuit is a composite circuit structure on a printed circuit board or a circuit structure based on an adder.

[0040] like Figure 2 As shown, the digital signal processor of the NRZ-TI-DACs system converts the sequence to be converted. After differential decomposition, the compensated digital sequences that have been down-clocked by 2 times are output from the first data channel and the second data channel, respectively, and sent to the first high-speed DAC and the second high-speed DAC of the DAC chipset. Then, waveform superposition is achieved at the analog end.

[0041] like Figure 3As shown, the NRZ-TI-DACs system provided by this invention is located after the system digital signal processor in a typical communication system. The input signal is a QAM signal. The digital signal processor of the NRZ-TI-DACs system and the system digital signal processor use the same digital signal processor. The signals output by the DAC of the NRZ-TI-DACs system are superimposed, and the superimposed signal is sent to the radio frequency front end. Figure 4 A schematic diagram of waveform decomposition, synthesis, and sampling based on the NRZ-TI-DACs system is presented. The input sequence is a QAM sequence, which can be considered a stepped waveform. After differential decomposition, frequency down-conversion, and analog superposition by the NRZ-TI-DACs system, the final synthesized analog signal is almost identical to the waveform corresponding to the original input sequence. This high fidelity ensures that the ADC at the receiver can accurately sample the signal using a standard sampling method, meeting the requirements. Figure 3 The data transmission requirements of the communication system shown.

[0042] This invention provides a data processing method for an NRZ-TI-DACs system for QAM wireless transmission, comprising the following steps:

[0043] Step 1: Input one high-frequency digital input sequence to the digital signal processor. The digital signal processor, based on the improved differential decomposition algorithm, compensates the two 2-frequency digital sequences generated by the decomposition by introducing a 3-frequency-compensated digital sequence. Finally, it outputs the two 2-frequency-compensated digital sequences and one 3-frequency-compensated digital sequence after compensation.

[0044] Step 2: Send the two 2-division digital sequences to the first high-speed DAC and the second high-speed DAC respectively, and send the one 3-division compensated digital sequence to the auxiliary DAC;

[0045] Step 3: Use two in-phase clocks generated by phase-shifting clocks to drive the first high-speed DAC, the auxiliary DAC, and the second high-speed DAC, respectively.

[0046] Step 4: Superimpose the analog signals output from the first high-speed DAC, the second high-speed DAC, and the auxiliary DA to synthesize an ultra-wideband analog signal corresponding to the original high-frequency digital input sequence, thereby realizing the conversion from digital signal to analog signal.

[0047] Specifically, the steps of the digital signal processor executing the improved differential decomposition algorithm are as follows:

[0048] Let the compensation digital sequence be denoted as Original input sequence minus Input sequence after compensation ;

[0049] Based on the compensated input sequence Perform difference decomposition according to odd and even periods, and output two frequency-divided digital sequences, i.e. and ;

[0050] The odd-period and even-period operating modes are as follows:

[0051] In the odd cycle: First data channel: Second data channel: ;

[0052] Even-period: First data channel: Second data channel: ;

[0053] And the initial data for the first cycle is set as follows: ; ;

[0054] In traditional difference algorithms, that is, when At that time, its output waveform is as follows Figure 5 As shown in the case without auxiliary intervention, the signal diverges over time, meaning the DAC channel needs to output an increasingly larger analog signal, exceeding the capacity of the actual device and thus becoming unfeasible. This invention introduces an auxiliary DAC in hardware and a compensation sequence into the algorithm. , the original input sequence Replace with It participates in differential operations, effectively suppressing output divergence, and at the same time, it limits the output peak value of each DAC channel, ensuring the feasibility and stability of the system.

[0055] Specifically, the compensation occurs after at least three cycles, with the data settings remaining unchanged in the first cycle: ; .

[0056] Specifically, the generation of the compensated digital sequence includes two steps: direction determination and compensation data acquisition.

[0057] The direction determination is achieved by multiplying the current channel's hold value by the current input sequence value and comparing the product with 0 to determine whether the current hold value and the input sequence are in the same direction.

[0058] The compensation data is obtained using any of the following methods:

[0059] a) Based on the current held value, after determining the compensation direction, output the corresponding positive or negative value according to the direction, and maintain it for 3 cycles. The execution result is as follows: Figure 5 The output waveform for "Auxiliary intervention current point determination" is shown in the figure.

[0060] b) Combining the current held value and the three future input sequence values ​​to be transmitted, directly calculate the absolute values ​​of the four values. After determining the proportional relationship between the values, based on the direction determination result, output a proportionally adjusted positive or negative value, and maintain it for 3 cycles. The execution result is as follows: Figure 5 The output waveform is shown in the "Auxiliary intervention combined with the current point and the three future points to determine the output waveform".

[0061] Specifically, the sampling rate of the auxiliary DAC is 1 / 3 of the sampling rate of the high-frequency digital input sequence. Each value of the compensation data channel is maintained for 3 cycles, so each data change is a multiple of 3. When compensation occurs in an odd cycle, the value of the second data channel will be compensated; when compensation occurs in an even cycle, the value of the first data channel will be compensated. This method allows for reverse constraint of the output channel value at different times, thereby suppressing the data from developing towards infinity or infinity. Although data suppression is good, the peak value constraint range still needs to be adjusted based on the proportion of the compensation data. The adjustment proportion needs to be determined based on the difference between the current sequence values ​​of the two data channels. Figure 5 As shown, the data at positions 24-25 on the horizontal axis indicates that the improved method can not only effectively limit the peak value of the output waveform, but also balance the output fluctuation to varying degrees, enabling the NRZ-TI-DACs system to be successfully applied to practical systems.

[0062] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Any modifications, equivalent substitutions, or improvements made by those skilled in the art within the scope of the technology disclosed in this invention, based on the technical solution and concept of the present invention, should be included within the protection scope of this invention. Therefore, the protection scope of this invention should be determined by the scope of the claims.

Claims

1. An NRZ-TI-DACs system for QAM wireless transmission, characterized in that, The system includes a digital signal processor (DSP), a phase-shifting clock, a first high-speed DAC, a second high-speed DAC, an auxiliary DAC, and a superposition output circuit. The DSP has one input data channel and three output data channels. The input data channel receives one high-frequency digital input sequence. The three output data channels are defined as a first data channel, a second data channel, and a compensation data channel, respectively connected to the input terminals of the first high-speed DAC, the second high-speed DAC, and the auxiliary DAC. The DSP executes an improved differential decomposition algorithm on the received high-frequency digital input sequence, generating two compensated 2-division digital sequences in the first and second data channels, and generating a 3-division compensated digital sequence in the compensation data channel. The phase-shifting clock generates two clocks with the same frequency, the second clock being 180° phase-shifted relative to the first clock. The first clock drives the first high-speed DAC and the auxiliary DAC, and the second clock drives the second high-speed DAC. The superposition output circuit is connected to the output terminals of the first high-speed DAC, the second high-speed DAC, and the auxiliary DAC. It is used to superimpose the three analog output signals and synthesize them into one ultra-wideband analog signal.

2. The NRZ-TI-DACs system for QAM wireless transmission according to claim 1, characterized in that, The sampling rates of the first and second high-speed DACs are both half the sampling rate of the high-frequency digital input sequence; the sampling rate of the auxiliary DAC is one-third of the sampling rate of the high-frequency digital input sequence.

3. The NRZ-TI-DACs system for QAM wireless transmission according to claim 1, characterized in that, The superposition output circuit is a composite circuit structure on a printed circuit board or a circuit structure based on an adder.

4. A data processing method for an NRZ-TI-DACs system for QAM wireless transmission, characterized in that, The NRZ-TI-DACs system for QAM wireless transmission according to any one of claims 1 to 3 includes the following steps: Step 1: Input a high-frequency digital input sequence to the digital signal processor. The digital signal processor, based on the improved differential decomposition algorithm, compensates the two 2-frequency-divided digital sequences generated by the decomposition by introducing a 3-frequency-divided compensation digital sequence. Finally, the two 2-frequency-divided digital sequences after compensation are output through the first data channel and the second data channel, and a 3-frequency-divided compensation digital sequence is output through the compensation data channel. Step 2: Send the two 2-division digital sequences to the first high-speed DAC and the second high-speed DAC respectively, and send the one 3-division compensated digital sequence to the auxiliary DAC; Step 3: Use two in-phase clocks generated by phase-shifting clocks to drive the first high-speed DAC, the auxiliary DAC, and the second high-speed DAC, respectively. Step 4: Superimpose the analog signals output from the first high-speed DAC, the second high-speed DAC, and the auxiliary DAC to synthesize an ultra-wideband analog signal corresponding to the original high-frequency digital input sequence, thereby realizing the conversion from digital signal to analog signal.

5. The data processing method for an NRZ-TI-DACs system for QAM wireless transmission according to claim 4, characterized in that, The steps of a digital signal processor executing an improved difference decomposition algorithm are as follows: Let the compensation digital sequence be denoted as Original input sequence minus Input sequence after compensation ; Based on the compensated input sequence Perform difference decomposition according to odd and even periods, and output two frequency-divided digital sequences, i.e. and ; The odd-period and even-period operating modes are as follows: In the odd cycle: First data channel: Second data channel: ; Even period: First data channel: Second data channel: ; And the initial data for the first cycle is set as follows: ; .

6. The data processing method for an NRZ-TI-DACs system for QAM wireless transmission according to claim 5, characterized in that, Compensation occurs after at least three cycles, with the data settings remaining unchanged in the first cycle: ; .

7. The data processing method for an NRZ-TI-DACs system for QAM wireless transmission according to claim 6, characterized in that, The generation of the compensated digital sequence includes two steps: direction determination and compensation data acquisition. The direction determination is achieved by multiplying the current channel's hold value by the current input sequence value and comparing the product with 0 to determine whether the current hold value and the input sequence are in the same direction. The compensation data is obtained using any of the following methods: a) Based on the current held value, after determining the compensation direction, output the corresponding positive or negative value according to the direction, and maintain it for 3 cycles; b) Combining the current held value and the three future input sequence values ​​to be transmitted, directly calculate the absolute value data of the four values, calculate the proportional relationship between the values, and output a positive or negative value after proportional adjustment based on the direction determination result, and maintain it for 3 cycles.

8. The data processing method for an NRZ-TI-DACs system for QAM wireless transmission according to claim 7, characterized in that, The sampling rate of the auxiliary DAC is 1 / 3 of the sampling rate of the high-frequency digital input sequence, and each value of the supplementary data channel is maintained for 3 cycles; when the compensation occurs in an odd period, the value of the second data channel will be compensated; when the compensation occurs in an even period, the value of the first data channel will be compensated.

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