Circuit board with semi-solder mask defined pads and method of manufacturing same

Abstract

The invention relates to a circuit board with a semi-solder mask defining pad and a method of manufacturing the same. In accordance with various embodiments of the present disclosure, a circuit board is provided that includes a substrate, a metal layer covering a portion of the substrate and forming at least one metal pad, and a solder resist layer at least partially covering the metal layer and defining at least one opening. The at least one opening corresponds to the at least one metal pad such that opposing first and second edges of the metal pad are exposed within the at least one opening and opposing third and fourth edges of the metal pad are covered by the solder resist layer.

Description

Technical Field

[0001] The exemplary embodiments of this disclosure generally relate to circuit board pads, and more specifically, to circuit board pads defined by a semi-solder resist layer. Background Technology

[0002] A solder pad is an exposed area of ​​metal (usually copper) on a printed circuit board (PCB) where component leads are soldered. Based on how the solder pad is formed, there are basically three different types of solder pads: solder mask limited (SMD) pads, non-solder mask limited (NSMD) pads, and semi-solder mask limited (SSMD) pads.

[0003] SMD pads are defined by holes in the solder mask. In this type of SMD pad, the holes in the solder mask are smaller than the underlying copper pads applied to the copper layer. In NSMD pads, there is a gap between the edge of the copper pad and the solder mask. That is, the solder mask does not overlap with the copper pad.

[0004] In a semi-solder resist defined (SSMD) pad, at least one edge is defined by solder resist, and the remainder is defined by copper pads. Figure 1 A PCB 100 is shown, comprising a substrate 102 having one or more conductive layers 104 (typically including copper) where traces have been etched to form electrical connections, and a solder mask layer 106 on top of the copper layers 104. Openings in the solder mask layer are positioned to expose portions of the copper layer so that components, wire leads, etc., can be soldered onto the PCB. Such exposed areas of the copper layer are referred to as solder pads.

[0005] Figure 1 The PCB 100 has twelve SSMD pads 110 (six along the top edge and six along the bottom edge). As... Figure 1 As shown, all SSMD pads 110 have three SMD sides and one NSMD side (the top edge is NSMD for each of the six pads along the top; the bottom edge is NSMD for each of the six pads along the bottom). Each SSMD pad 110 has a corresponding opening in a copper pad 112 and solder mask 106, such that there is an exposed portion of the substrate 114 on one side of the copper pad 112 and the three sides 116 of the copper pad are covered by the solder mask 106. Because the solder mask is typically translucent, the bottom edge of the copper pad is slightly visible on each SMD side (this is in...). Figure 1 (Used as dashed lines in the middle).

[0006] Make the top and bottom edges NSMD edges (e.g.) Figure 1 As shown, it enables "edge" inspection of solder joints (i.e., visual inspection from the top and bottom edges of the PCB), which is ideal in many cases.

[0007] When solder mask is applied to a PCB, registration errors may occur, meaning the solder mask is not precisely placed in the intended location. This registration error, typically up to 30 micrometers, is usually acceptable and is planned for in the PCB design. Such registration errors generally do not cause any problems with SMD or NSMD pads because sufficient overlap has been established in the design to accommodate registration errors within specific tolerances. However, this registration error in SSMD pads can lead to inconsistent pad dimensions, which in turn can cause other problems with the PCB structure (especially in very small PCBs).

[0008] consider Figure 1 The example PCB 100 illustrates this. If the solder mask is moved left or right (within a specific tolerance), the pad sizes will remain consistent because the amount of copper pads uncovered on one side due to the movement is equal to the amount of copper pads covered on the other side. However, if the solder mask is moved up or down, some pads will become larger and some will become smaller. For example, if the solder mask is moved up, the top row pads will become smaller (because more of their bottom edges are now covered by the solder mask), and the bottom row pads will become larger (because less of their top edges are now covered by the solder mask). Conversely, if the solder mask is moved down, the top row pads will become larger (because less of their top edges are now covered by the solder mask), and the bottom row pads will become smaller (because more of their bottom edges are now covered by the solder mask).

[0009] Because a predetermined amount of solder is applied to each pad, too much solder is applied if the pad is too small due to registration errors, and too little solder is applied if the pad is too large. Components with two pads, or more complex components with a dual in-line package (DIP) pad layout (which has pads of this type), are typically more susceptible to the adverse effects of such registration errors. If the two pads (or two rows of pads) are incorrectly sized due to solder mask registration errors, it can lead to a variety of problems. For example, the component may not be able to be placed horizontally on the PCB, resulting in dry solder joints. This effect is even more pronounced in small reflowable packages.

[0010] The applicant has identified numerous technical challenges and difficulties associated with SSMD pads in PCBs. Through the application of effort, ingenuity, and innovation, the applicant has solved the problems related to SSMD pads in PCBs by developing the solution implemented in this disclosure, which will be described in detail below. Summary of the Invention

[0011] The various embodiments described herein relate to a circuit board having one or more SSMD pads, and a method for manufacturing a circuit board having one or more SSMD pads.

[0012] According to various embodiments of the present disclosure, a circuit board is provided, comprising a substrate, a metal layer covering a portion of the substrate and forming at least one metal pad, and a solder mask layer at least partially covering the metal layer and defining at least one opening. The at least one opening corresponds to at least one metal pad, such that opposing first and second edges of the metal pad are exposed within the at least one opening, and opposing third and fourth edges of the metal pad are covered by the solder mask layer.

[0013] In some embodiments, at least one metal pad has a first dimension and a second dimension that is substantially perpendicular to the first dimension of the at least one metal pad, at least one opening has a first dimension and a second dimension that is substantially perpendicular to the first dimension of the at least one opening, the first dimension of the at least one metal pad is substantially parallel to the first dimension of the at least one opening, the second dimension of the at least one metal pad is substantially parallel to the second dimension of the at least one opening, the first dimension of the at least one opening is greater than or equal to the first dimension of the at least one metal pad plus twice a predetermined mask registration error tolerance, and the second dimension of the at least one metal pad is greater than or equal to the second dimension of the at least one opening plus twice the predetermined mask registration error tolerance.

[0014] In some embodiments, at least one metal pad is generally rectangular, and at least one opening is generally rectangular.

[0015] In some embodiments, the edge of at least one opening is adjacent to the edge of the substrate.

[0016] In some embodiments, the substrate includes an organic substrate.

[0017] In some embodiments, the metal layer comprises copper.

[0018] In some embodiments, the circuit board includes a grid array.

[0019] According to various embodiments of the present disclosure, a method of manufacturing a circuit board is provided, the method comprising forming at least one metal pad by a metal layer covering a portion of a substrate; and applying a solder mask layer that at least partially covers the metal layer and defines at least one opening. The at least one opening corresponds to the at least one metal pad, such that opposing first and second edges of the metal pad are exposed within the at least one opening, and opposing third and fourth edges of the metal pad are covered by the solder mask layer.

[0020] The above overview is provided merely to summarize some exemplary embodiments to provide a basic understanding of some aspects of this disclosure. Therefore, it should be understood that the above embodiments are merely examples and should not be construed as limiting the scope or spirit of this disclosure in any way. It should also be understood that, in addition to the embodiments outlined herein, the scope of this disclosure includes many potential embodiments, some of which will be further described below. Attached Figure Description

[0021] The description of the illustrative embodiments can be read in conjunction with the accompanying drawings. It should be understood that, for the sake of simplicity and clarity, the elements shown in the drawings are not necessarily drawn to scale unless otherwise stated. For example, the dimensions of some elements may be exaggerated relative to other elements unless otherwise stated. Embodiments incorporating the teachings of this disclosure are shown and described with reference to the accompanying drawings presented herein, wherein:

[0022] Figure 1 This is a top view of a circuit board with traditional SSMD pads.

[0023] Figure 2A This is a top view of an example circuit board having example SSMD pads according to some embodiments of the present disclosure;

[0024] Figure 2B yes Figure 2A A close-up view of example SSMD pads on an example circuit board; and

[0025] Figure 3 This is based on some embodiments of the present disclosure and has solder mask registration errors. Figure 2A A top view of an example circuit board. Detailed Implementation

[0026] Some embodiments of this disclosure will now be described more fully below with reference to the accompanying drawings, which illustrate some, but not all, of these embodiments. In fact, these disclosures may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure may meet applicable legal requirements. The same numerals always refer to the same elements.

[0027] As used herein, terms such as “front,” “back,” and “top” are used for explanatory purposes in the examples provided below to describe the relative positions of certain elements or parts of elements. Furthermore, as will be apparent to those skilled in the art from this disclosure, the terms “generally” and “approximately” indicate that the referenced element or related description is accurate within applicable engineering tolerances.

[0028] As used herein, the term “comprising” means including but not limited to, and should be interpreted in the manner in which it is typically used in the patent context. The use of broader terms such as including, comprising, and having should be understood as support for narrower terms such as “consisting of,” “substantially consisting of,” and “largely consisting of.”

[0029] The phrases “in one embodiment”, “according to one embodiment”, etc., generally mean that a particular feature, structure or characteristic following the phrase may be included in at least one embodiment of this disclosure, and may be included in more than one embodiment of this disclosure (importantly, such phrases do not necessarily refer to the same embodiment).

[0030] The terms “example” or “exemplary” are used herein to mean “served as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or superior to other implementations.

[0031] If the specification states that an element or feature "may," "can," "may," "should," "will," "preferably," "possibly," "usually," "optionally," "for example," "often," or "maybe" (or other such language) is included or has the feature, then the particular element or feature does not need to be included or have that feature. Such an element or feature may be optionally included in some embodiments or may be excluded.

[0032] Various embodiments of this disclosure overcome the aforementioned technical challenges and difficulties, and provide various technical improvements and advantages based on, for example, but not limited to, providing a PCB including one or more SSMD pads and methods of manufacturing the PCB, wherein two opposite edges are defined by a solder mask layer (i.e., SMD) and another two opposite edges are defined by copper pads (i.e., NSMD).

[0033] In various embodiments, the value of the copper pad being wider than the solder mask opening (in one direction, such as horizontal) is greater than twice the allowable solder mask registration error, and the value of the copper pad being narrower than the solder mask opening is greater than twice the allowable solder mask registration error in the vertical (e.g., vertical) direction.

[0034] In various embodiments, the solder mask layout is designed such that precise placement of the solder mask will result in the exposed portion of the substrate on each of the two opposite sides of the pad being at least as large as the permissible solder mask registration error, and will result in the covered portion of the copper pad on each of the other two opposite sides of the pad being at least as large as the permissible solder mask registration error. As a result, as further described below, the SSMD pads of various embodiments allow vertical (top or bottom) and / or horizontal (left or right) solder mask registration errors within predetermined tolerances without altering the dimensions of the exposed copper portion of the pad.

[0035] Figure 2A An example circuit board with multiple example SSMD pads is shown according to some embodiments of the present disclosure. Figure 2B yes Figure 2A A close-up view of example SSMD pads on an example circuit board. Figure 2A As shown, the example PCB 200 includes a substrate 202 with one or more conductive layers 204 (typically including copper), where traces have been etched to form electrical connections, and a solder mask layer 206 on top of the copper layer 204. Because the solder mask is typically translucent, the underside edge of the copper pads is slightly visible on each SMD side (this is in...). Figure 2A and 2B (Indicated by dashed lines). In various embodiments, circuit board 200 may be a grid array. In various embodiments, the substrate may include an organic substrate; however, any suitable type of substrate may be used.

[0036] Figure 2A The PCB 200 has twelve SSMD pads 210 (six along the top edge and six along the bottom edge). As... Figure 2A and Figure 2B As shown, each SSMD pad 210 has a corresponding opening 218 in a copper pad 212 and a solder mask layer 206, such that there are exposed portions of the substrate 114a, 114b on opposite sides of the copper pad 112, and the other two opposite sides 116a, 116b of the copper pad are covered by the solder mask layer 206. That is, Figure 2A and Figure 2B The copper pad 212 has two opposing SMD sides ( Figure 2A and Figure 2B (Left and right sides), where the copper edges 216a and 216b are covered by solder mask, and two opposing NSMD sides ( Figure 2A and Figure 2B The top and bottom of the SSMD pads are exposed, with the edges of the copper and adjacent portions 214a, 214b of the substrate exposed. In various embodiments, the exposed metal portions of the SSMD pads are rectangular. In various embodiments, because each SSMD pad has an exposed substrate adjacent to the outer edge of the PCB, “edge-to-edge” inspection of the solder joints is possible (i.e., visual inspection from the top and bottom edges of the PCB).

[0037] like Figure 2BAs shown, the copper pad 212 has a first dimension A and a second dimension B that is generally perpendicular to the first dimension A, and the opening 218 defined by the solder mask has a first dimension C and a second dimension D that is generally perpendicular to the first dimension C. The first dimension A of the copper pad 212 is generally parallel to the first dimension C of the solder mask opening 218, and the second dimension B of the copper pad 212 is generally parallel to the second dimension D of the solder mask opening 218. Figure 2B In the arrangement, dimensions A and C can be considered as height, while dimensions B and D can be considered as width.

[0038] In various embodiments, the first dimension C of the solder mask opening 218 is greater than or equal to the first dimension A of the copper pad 212 plus twice the predetermined mask registration error tolerance, and the second dimension B of the copper pad 212 is greater than or equal to the second dimension D of the solder mask opening 218 plus twice the predetermined mask registration error tolerance.

[0039] In one example embodiment, the first dimension A of the copper pad 212 is 0.400 mm, the second dimension B of the copper pad 212 is 0.525 mm, the first dimension C of the solder mask opening 218 is 0.550 mm, and the second dimension D of the solder mask opening 218 is 0.425 mm. In this example embodiment, the exposed portion of the copper pad is 0.400 mm × 0.425 mm. In this example embodiment, the predetermined mask registration error tolerance is 0.030 mm.

[0040] In various embodiments, SSMD pads, with two opposite edges being SMD and the other two opposite edges being NSMD, accommodate solder mask registration errors (the maximum permissible amount) in any direction without changing the pad size. In various embodiments, if the solder mask moves left or right (within a specific tolerance), the pad size remains consistent (as in the prior art) because the amount of movement of a copper pad uncovered on one side is equal to the amount of movement of a copper pad covered on the other side. Similarly, if the solder mask moves up or down, the pad size remains consistent. Because the gap between the copper pads and the solder mask is greater than the permissible registration error, upward movement of the solder mask will not cause the solder mask to cover any bottom edge of the top row pads, and downward movement of the solder mask will not cause the solder mask to cover any top edge of the bottom row pads.

[0041] exist Figure 3 The diagram shows that the solder mask layer 206 has moved upwards by less than the predetermined mask registration error tolerance. (As shown...) Figure 3As shown, in the top row of SSMD pads, the exposed substrate 214b at the bottom of each SSMD pad has become smaller, but no additional amount of exposed portion in the top row of SSMD pads is covered by the solder mask. Therefore, despite the upward movement of the solder mask, the size of the exposed portion of the copper pad remains unchanged. Similarly, in the bottom row of SSMD pads, the upward movement of the solder mask 206 has exposed more substrate adjacent to the top edge of each copper pad, but has not changed the size of the exposed portion of the copper pad.

[0042] Although not illustrated, if the solder mask 206 has been moved downwards by less than a predetermined mask registration error tolerance, the exposed substrate at the top of each SSMD pad in the bottom row will become smaller, but no additional amount of exposed portion will be covered by the solder mask. Similarly, in the top row of SSMD pads, the exposed substrate at the bottom of each SSMD pad will become larger, but the size of the exposed portion of the copper pad will not change. Although not illustrated, if the solder mask 206 has been moved to the left or right, the additional amount of copper pad now covered on one side will be equal to the additional amount of copper pad now uncovered on the other side.

[0043] Because the exposed metal portion of the SSMD remains consistent across all embodiments despite this solder mask offset, the amount of solder deposited will be consistent and equal.

[0044] Various embodiments of this disclosure provide one or more of the following advantages: better package placement with reduced tilt, tighter assembly tolerances, smaller solder volume, while maintaining joint reliability because tilt does not cause dry bonding issues, maintaining post-assembly visual inspection of the joints, and maintaining solder mask separation between adjacent joints.

[0045] While tilt and placement tolerances are critical for optical packaging, embodiments of this disclosure are applicable to at least all small-size grid array (LGA) packages based on organic substrates with solder mask to improve mechanical assembly tolerances, solder joint uniformity, and reliability. In various embodiments with square pad arrangements, placement tolerances can be improved in both the X and Y directions. In various embodiments during testing, because the solder mask openings are elongated, more clearance area is available for testing spring pin contact pads without cutting off the edges of the solder mask, which could lead to poor electrical contact and receptacle contamination risks.

[0046] in conclusion

[0047] With the guidance provided in the foregoing description and the accompanying drawings, those skilled in the art to which this disclosure pertains will conceive of many modifications and other embodiments of the disclosure set forth herein. Although the drawings illustrate only certain elements of the apparatus and systems described herein, it should be understood that various other elements may be used in conjunction with the system. Therefore, it should be understood that this disclosure is not limited to the specific embodiments disclosed, and that modifications and other embodiments are intended to be included within the scope of the appended claims. Furthermore, the steps in the above-described methods do not necessarily occur in the order described in the drawings, and in some cases, one or more of the described steps may occur substantially simultaneously, or additional steps may be included. Although specific terminology is used herein, it is used in a general and descriptive sense only and not for limiting purposes.

[0048] While various embodiments based on the principles disclosed herein have been shown and described above, those skilled in the art can modify them without departing from the spirit and guidance of this disclosure. The embodiments described herein are merely representative and not restrictive. Many variations, combinations, and modifications are possible within the scope of this disclosure. Alternative embodiments resulting from combining, integrating, and / or omitting features of the embodiments are also within the scope of this disclosure. Therefore, the scope of protection is not limited by the foregoing description.

[0049] Furthermore, the section headings used herein are for the purpose of maintaining consistency with the recommendations under 37C.FR1.77 or to provide organizational clues. These headings should not limit or characterize the disclosure as set forth in any of the claims that may arise from this disclosure.

[0050] While this detailed description has illustrated some embodiments of the present disclosure, the appended claims cover other embodiments of the present disclosure that differ from the described embodiments according to various modifications and improvements. For example, the appended claims can cover any form of circuit board with SSMD pads, such as a grid array. As another example, the appended claims can cover wafer-level chip-scale packages in which an RDL layer is formed on the back side of the wafer, typically comprising a polyimide layer, followed by a copper wiring layer, and finally a solder mask layer to form pads.

[0051] In the appended claims, unless the specific terms “means for…” or “steps for…” are used in a given claim, the claim is not intended to be interpreted in accordance with paragraph 6 of 35 U.SC112.

Claims

1. A circuit board, comprising: Substrate; A metal layer that covers a portion of the substrate and forms at least one metal pad; as well as A solder mask layer, at least partially covering a metal layer and defining at least one opening, the at least one opening corresponding to the at least one metal pad, such that opposing first and second edges of the metal pad are exposed within the at least one opening, and opposing third and fourth edges of the metal pad are covered by the solder mask layer.

2. The circuit board according to claim 1, wherein the at least one metal pad has a first dimension and a second dimension substantially perpendicular to the first dimension of the at least one metal pad; The at least one opening has a first dimension and a second dimension that is substantially perpendicular to the first dimension of the at least one opening; The first dimension of the at least one metal pad is generally parallel to the first dimension of the at least one opening; The second dimension of the at least one metal pad is generally parallel to the second dimension of the at least one opening; The first dimension of the at least one opening is greater than or equal to the first dimension of the at least one metal pad plus twice the predetermined mask registration error tolerance; and The second dimension of the at least one metal pad is greater than or equal to the second dimension of the at least one opening plus twice the predetermined mask registration error tolerance.

3. The circuit board of claim 1, wherein the at least one metal pad is generally rectangular; and The at least one of the openings is generally rectangular.

4. The circuit board of claim 1, wherein the edge of the at least one opening is adjacent to the edge of the substrate.

5. The circuit board according to claim 1, wherein the substrate comprises an organic substrate.

6. The circuit board of claim 1, wherein the metal layer comprises copper.

7. The circuit board of claim 1, wherein the circuit board comprises a grid array.

8. A circuit board, comprising: Substrate; A metal layer that covers a portion of the substrate and forms at least one metal pad; as well as A solder mask layer, at least partially covering a metal layer and defining at least one opening, the at least one opening corresponding to the at least one metal pad, such that opposing first and second edges of the metal pad are exposed within the at least one opening, and opposing third and fourth edges of the metal pad are covered by the solder mask layer. The at least one metal pad has a first dimension and a second dimension that is substantially perpendicular to the first dimension; The at least one opening has a first dimension and a second dimension that is substantially perpendicular to the first dimension; The first dimension of the at least one metal pad is generally parallel to the first dimension of the at least one opening; The second dimension of the at least one metal pad is generally parallel to the second dimension of the at least one opening; The first dimension of the at least one opening is greater than or equal to the first dimension of the at least one metal pad plus twice the predetermined mask registration error tolerance; as well as The second dimension of the at least one metal pad is greater than or equal to the second dimension of the at least one opening plus twice the predetermined mask registration error tolerance.

9. The circuit board of claim 8, wherein the at least one metal pad is generally rectangular; and The at least one of the openings is generally rectangular.

10. The circuit board of claim 8, wherein the edge of the at least one opening is adjacent to the edge of the substrate.

11. The circuit board of claim 8, wherein the substrate comprises an organic substrate.

12. The circuit board of claim 8, wherein the metal layer comprises copper.

13. The circuit board of claim 8, wherein the circuit board comprises a grid array.

14. A method for manufacturing a circuit board, the method comprising: At least one metal pad is formed by a metal layer covering a portion of the substrate; and A solder mask is applied that at least partially covers a metal layer and defines at least one opening, the at least one opening corresponding to the at least one metal pad, such that opposite first and second edges of the metal pad are exposed within the at least one opening, and opposite third and fourth edges of the metal pad are covered by the solder mask.

15. The method of claim 14, wherein the at least one metal pad has a first dimension and a second dimension substantially perpendicular to the first dimension of the at least one metal pad; The at least one opening has a first dimension and a second dimension that is substantially perpendicular to the first dimension of the at least one opening; The first dimension of the at least one metal pad is generally parallel to the first dimension of the at least one opening; The second dimension of the at least one metal pad is generally parallel to the second dimension of the at least one opening; The first dimension of the at least one opening is greater than or equal to the first dimension of the at least one metal pad plus twice the predetermined mask registration error tolerance; and The second dimension of the at least one metal pad is greater than or equal to the second dimension of the at least one opening plus twice the predetermined mask registration error tolerance.

16. The method of claim 14, wherein the at least one metal pad is substantially rectangular; and The at least one of the openings is generally rectangular.

17. The method of claim 14, wherein the edge of the at least one opening is adjacent to the edge of the substrate.

18. The method of claim 14, wherein the substrate comprises an organic substrate.

19. The method of claim 14, wherein the metal layer comprises copper.

20. The method of claim 14, wherein the circuit board comprises a grid array.

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