Memory structure and forming method thereof, memory circuit and working method thereof

Abstract

The invention discloses a memory structure and a forming method thereof, a memory circuit and a working method of the memory circuit, and the memory structure comprises a plurality of memory unit structures located on a substrate, each memory unit structure comprises a first word line grid, a second word line grid and a stacked grid structure located between the first word line grid and the second word line grid, the stacked gate structure comprises a first floating gate, a second floating gate and a control gate, a first opening exposing the surface of the substrate is formed between the first floating gate and the second floating gate, and the control gate is located in the first opening and located on the top surfaces of the first floating gate and the second floating gate; the first floating gate, the second floating gate, the first word line gate and the second word line gate are respectively arranged along a first direction; the source doping region is located in the substrate at the bottom of the first opening; the first drain doping region and the second drain doping region are beneficial to reducing the area of the storage unit, controlling the height of the storage unit and improving the integration level of a process window and a chip.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a memory structure and its formation method, a memory circuit and its operation method. Background Technology

[0002] Flash memory is a type of non-volatile memory that can retain data for a long time without a current supply, meaning that data is not lost when power is off. Floating-gate flash memory structures are widely used in various embedded electronic products such as financial IC cards and automotive electronics because they save chip area and increase storage integration density.

[0003] However, with the development of semiconductor device technology, the performance requirements for flash memory devices are becoming increasingly stringent. The performance of existing floating-gate flash memory structures still needs further optimization. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a memory structure and its formation method, a memory circuit and its operation method, so as to improve the performance of flash memory devices.

[0005] To solve the above-mentioned technical problems, the present invention provides a memory structure, comprising: a substrate; a plurality of memory cell structures located on the substrate, the memory cell structures including a first word line gate and a second word line gate, and a stacked gate structure located between the first word line gate and the second word line gate, the stacked gate structure including a first floating gate, a second floating gate and a control gate, a first opening exposing the surface of the substrate being provided between the first floating gate and the second floating gate, the control gate being located within the first opening and on the top surface of the first floating gate and the second floating gate, the first floating gate and the second floating gate, the first word line gate and the second word line gate being arranged along a first direction; a source doped region located within the substrate at the bottom of the first opening; a first drain doped region and a second drain doped region, the first drain doped region being located within the substrate on one side of the memory cell structure, and the second drain doped region being located within the substrate on the other side of the memory cell structure.

[0006] Optionally, the stacked gate structure further includes: a first sidewall located between the control gate and the first word line gate, between the control gate and the second word line gate, and on the top surfaces of the first floating gate and the second floating gate; the memory cell structure further includes: a second sidewall located on the substrate surface and between the stacked gate structure and the first word line gate, and the second word line gate.

[0007] Optionally, the memory cell structure further includes: a third sidewall, located on the sidewalls of the first word line gate and the second word line gate away from the stacked gate structure; a first lightly doped region and a first halo ring doped region, the first lightly doped region and the first halo ring doped region being located in the substrate on the side of the first word line gate away from the stacked gate structure, the doping depth of the first halo ring doped region being greater than the doping depth of the first lightly doped region; a second lightly doped region and a second halo ring doped region, the second lightly doped region and the second halo ring doped region being located in the substrate on the side of the second word line gate away from the stacked gate structure, the doping depth of the second halo ring doped region being greater than the doping depth of the second lightly doped region.

[0008] Optionally, the memory cell structure further includes: a first floating gate dielectric layer located between the first floating gate and the substrate; a second floating gate dielectric layer located between the second floating gate and the substrate; the stacked gate structure further includes: a control gate dielectric layer located on the control gate sidewall and between the control gate and the first floating gate, the second floating gate, and the substrate.

[0009] Accordingly, the present invention also provides a method for forming a memory structure, comprising: providing a substrate; forming a plurality of memory cell structures on the substrate, the memory cell structures including a first word line gate and a second word line gate, and a stacked gate structure located between the first word line gate and the second word line gate, the stacked gate structure including a first floating gate, a second floating gate and a control gate, a first opening exposing the surface of the substrate being provided between the first floating gate and the second floating gate, the control gate being located within the first opening and on the top surface of the first floating gate and the second floating gate, the first floating gate and the second floating gate, the first word line gate and the second word line gate being arranged along a first direction; forming a source doped region in the substrate at the bottom of the first opening; forming a first drain doped region in the substrate on one side of the memory cell structure, and forming a second drain doped region in the substrate on the other side.

[0010] Optionally, the stacked gate structure further includes: a first sidewall located between the control gate and the first word line gate, between the control gate and the second word line gate, and on the top surfaces of the first floating gate and the second floating gate; the memory cell structure further includes: a second sidewall located on the substrate surface and between the stacked gate structure and the first word line gate, and the second word line gate.

[0011] Optionally, the method for forming the memory cell structure includes: forming an initial floating gate material layer and a hard mask layer on the surface of the substrate, the hard mask layer having a second opening and a first sidewall located on the sidewall of the second opening, the initial floating gate material layer having the first opening, the first opening being located at the bottom of the second opening and communicating with the second opening, the bottom of the second opening exposing a portion of the surface of the initial floating gate material layer; forming the source doped region in the substrate at the bottom of the first opening; forming the control gate in the first opening and the second opening; removing the hard mask layer to expose a portion of the surface of the initial floating gate material layer; using the control gate as a mask, etching the initial floating gate material layer until the substrate surface is exposed, forming the first floating gate and the second floating gate; forming the second sidewall on the sidewall of the stacked gate structure; and forming the first word line gate and the second word line gate on the sidewall of the second sidewall, respectively.

[0012] Optionally, the method for forming the initial floating gate material layer and the hard mask layer includes: forming a floating gate material layer on the surface of the substrate; forming a mask material layer on the surface of the floating gate material layer; patterning the mask material layer and forming a second opening in the mask material layer, the second opening exposing a portion of the floating gate material layer, thereby forming the hard mask layer with the mask material layer; forming a first sidewall on the sidewall of the second opening; etching the portion of the floating gate material layer exposed by the second opening and forming the first opening in the floating gate material layer, thereby forming the initial floating gate material layer with the floating gate material layer.

[0013] Optionally, the stacked gate structure further includes: a first floating gate dielectric layer located between the first floating gate and the substrate; a second floating gate dielectric layer located between the second floating gate and the substrate; the method for forming the first floating gate dielectric layer and the second floating gate dielectric layer includes: forming a floating gate dielectric material layer on the surface of the substrate before forming the floating gate material layer; the floating gate dielectric material layer is etched to form the first floating gate dielectric layer and the second floating gate dielectric layer.

[0014] Optionally, the method further includes: forming a protective layer on the surface of the control gate before removing the hard mask layer; the method of forming the first word grid and the second word grid includes: after forming the second sidewall, forming a word grid material layer on the substrate surface, the sidewall of the second sidewall, and the top surface of the protective layer; planarizing the word grid material layer until the top surface of the protective layer is exposed to form a transition word grid; patterning the transition word grid to form the first word grid and the second word grid; and removing the protective layer.

[0015] Optionally, the top surface of the control gate is flush with the top surface of the hard mask layer; the method of forming the control gate and the protective layer includes: forming a control gate material layer in the first opening and the second opening, and on the surface of the hard mask layer; planarizing the control gate material layer until the surface of the hard mask layer is exposed to form the control gate; and forming the protective layer on the surface of the control gate.

[0016] Optionally, the top surface of the control gate is lower than the top surface of the hard mask layer, and the protective layer is formed within the second opening; the method for forming the control gate and the protective layer includes: forming a control gate material layer within the first opening and the second opening, and on the surface of the hard mask layer; planarizing the control gate material layer until the surface of the hard mask layer is exposed to form a transition control gate; etching the transition control gate to form the control gate and a groove located on the control gate; and forming the protective layer within the groove.

[0017] Optionally, the memory cell structure further includes: a third sidewall, located on the sidewalls of the first word line gate and the second word line gate away from the stacked gate structure; before forming the third sidewall, it further includes: forming a first lightly doped region and a first halo ring doped region in the substrate on the side of the first word line gate away from the stacked gate structure, wherein the doping depth of the first halo ring doped region is greater than the doping depth of the first lightly doped region; and forming a second lightly doped region and a second halo ring doped region in the substrate on the side of the second word line gate away from the stacked gate structure, wherein the doping depth of the second halo ring doped region is greater than the doping depth of the second lightly doped region.

[0018] Accordingly, the present invention also provides a memory circuit, comprising: a plurality of memory cells arranged in an array along a first direction, wherein the memory cell structure formed between each pair of adjacent memory cells in the first direction comprises: a substrate; a first word line gate and a second word line gate, and a stacked gate structure located between the first word line gate and the second word line gate, the stacked gate structure comprising a first floating gate, a second floating gate and a control gate, wherein a first opening is provided between the first floating gate and the second floating gate to expose the surface of the substrate, the control gate is located within the first opening and on the top surface of the first floating gate and the second floating gate, the first floating gate and the second floating gate, the first word line gate and the second word line gate being arranged along the first direction; and a source doped region located at the bottom of the first opening. The memory cell structure includes: a first drain doped region and a second drain doped region, wherein the first drain doped region is located in the substrate on one side of the memory cell structure, and the second drain doped region is located in the substrate on the other side of the memory cell structure; a word line electrically connected to the first word line gate or the second word line gate of the memory cell in the same row; a bit line electrically connected to the first drain doped region and the second drain doped region of the memory cell in the same column; a source line electrically connected to the source doped region of the memory cell in the same row; and a control gate line electrically connected to the control gate of the memory cell in the same row. The control gate line is used to apply a first erase voltage, and the source line is used to apply a second erase voltage. The first erase voltage is less than the second erase voltage, which allows electrons to be released from the first floating gate or the second floating gate to the source doped region.

[0019] Optionally, it further includes: a programming unit for applying a first programming voltage to the control gate line of the selected memory cell, applying a second programming voltage to its source line, and applying a first constant current to its bit line, wherein the first programming voltage is greater than the second programming voltage, so as to program the first floating gate or the second floating gate of the selected memory cell.

[0020] Optionally, it further includes: a read unit, configured to apply a 0V voltage to the control gate line and the source line of the selected memory cell, apply a read voltage to its bit line, and read the current output from each bit line.

[0021] Optionally, it further includes: an erasure unit, configured to apply a first erasure voltage to the control gate line of the selected memory cell and a second erasure voltage to its source line, wherein the first erasure voltage is a negative voltage and the second erasure voltage is a positive voltage, so as to erase the stored information in the selected memory cell.

[0022] Optionally, the erasure unit is also used to place all the word lines and bit lines in a floating state.

[0023] Accordingly, the technical solution of the present invention also provides a method for operating the above-mentioned memory circuit, including: a programming operation, applying a first programming voltage to the control gate line of the selected memory cell, applying a second programming voltage to its source line, and applying a first constant current to its bit line, wherein the first programming voltage is greater than the second programming voltage, to program the first floating gate or the second floating gate of the selected memory cell; a reading operation, applying a 0V voltage to the control gate line and the source line of the selected memory cell respectively, applying a reading voltage to its bit line, and reading the current output from each bit line; and an erasing operation, applying a first erasing voltage to the control gate line of the selected memory cell and applying a second erasing voltage to its source line, wherein the first erasing voltage is less than the second erasing voltage, to erase the stored information in the memory cell.

[0024] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0025] In the memory structure provided by the present invention, the control gate is located between the first floating gate and the second floating gate, and on the top surface of the first floating gate and the second floating gate, so that the control gate has a large coupling area with the first floating gate and the second floating gate respectively. The above structure omits the erase gate, but by applying a voltage difference between the control gate and the source doped region, electrons can be released from the first floating gate or the second floating gate to the source doped region, thereby realizing the erase operation. This helps to reduce the area of ​​the memory cell, and since the area occupied by the control gate is large, the thickness of the control gate can be reduced without affecting its resistance, which helps to control the height of the memory cell and improve the process window and chip integration.

[0026] In the method for forming a memory structure provided by the present invention, the control gate is located between the first floating gate and the second floating gate, and on the top surface of the first floating gate and the second floating gate, so that the control gate has a large coupling area with the first floating gate and the second floating gate respectively. The above structure omits the erase gate, but by applying a voltage difference between the control gate and the source doped region, electrons can be released from the first floating gate or the second floating gate to the source doped region, thereby realizing the erase operation. This helps to reduce the area of ​​the memory cell, and since the area occupied by the control gate is large, the thickness of the control gate can be reduced without affecting its resistance, which helps to control the height of the memory cell and improve the process window and chip integration.

[0027] In the memory circuit provided by the present invention, the control gate line is used to apply a first erase voltage, and the source line is used to apply a second erase voltage. The first erase voltage is less than the second erase voltage, which allows electrons to be released from the first floating gate or the second floating gate to the source doped region. The erase operation can be realized without setting an erase gate in the memory structure, thereby reducing the area of ​​the memory cell. Furthermore, since the control gate occupies a large area, the thickness of the control gate can be reduced without affecting its resistance, which is beneficial for controlling the height of the memory cell and improving the process window and chip integration.

[0028] In the working method of the memory circuit provided by the technical solution of the present invention, the erase operation involves applying a first erase voltage to the control gate line of the selected memory cell and applying a second erase voltage to its source line. The first erase voltage is less than the second erase voltage, so as to erase the stored information in the memory cell. The erase operation can be realized without setting an erase gate in the memory structure, which helps to reduce the area of ​​the memory cell. Moreover, since the area occupied by the control gate is large, the thickness of the control gate can be reduced without affecting its resistance, which helps to control the height of the memory cell and improve the process window and chip integration. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of a memory structure;

[0030] Figures 2 to 15 This is a schematic diagram of the steps in the method for forming a memory structure according to an embodiment of the present invention;

[0031] Figure 16 This is a schematic diagram of a memory circuit according to an embodiment of the present invention. Detailed Implementation

[0032] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0033] As described in the background section, the performance of existing floating-gate flash memory structures still needs further optimization. A memory structure will now be described and analyzed in conjunction with this study.

[0034] Figure 1 This is a schematic diagram of a memory structure.

[0035] Please refer to Figure 1The memory includes: a substrate 100; a memory cell structure located on the substrate 100, the memory cell structure including two word line gates 101 and an erase gate 102 located between the two word line gates 101, a floating gate 103 located between the erase gate 102 and each of the word line gates 101, a control gate 104 and a first hard mask layer 105, the control gate 104 being located on the floating gate 103, and the first hard mask layer 105 being located on the control gate 104; a second hard mask layer 105 located on each of the word line gates 101. Hard mask layer 106; third hard mask layer 107 located on the erase gate 102; first sidewall 108 located on the floating gate 103 and on the sidewalls of the control gate 104 and the first hard mask layer 105; second sidewall 109 located on the sidewalls of the floating gate 103, the first sidewall 108, and each word line gate 101; common source doped region 110 located in the substrate 100 at the bottom of the erase gate 102; drain doped regions 111 located in the substrate 100 on both sides of the memory cell structure.

[0036] In the above memory structure, the control gate 104 is coupled to the floating gate 103, and the charge increase or decrease of the floating gate 103 is controlled by an electric field. As the requirements for chip integration gradually increase, the width of the control gate 104 (the dimension along the surface direction of the substrate 100) is also getting smaller and smaller. In order to reduce its resistance, it is necessary to have a certain thickness (the dimension perpendicular to the surface direction of the substrate 100), which results in a relatively high memory cell height.

[0037] However, the height requirements of the memory cells in the above-mentioned memory structure also limit its application. For example, when integrating the above-mentioned memory structure with the High-K Metal Gate (HKMG) process, the active area of ​​the memory region needs to be recessed to meet the planarization requirements of the mechanical chemical polishing (CMP) process in the HKMG process. This results in more mask layers, more complex processes, and is not conducive to reducing process costs.

[0038] To address the aforementioned problems, this invention provides a memory structure and its formation method, as well as a memory circuit and its operation method. In this invention, a control gate is located between a first floating gate and a second floating gate, and on the top surface of both the first and second floating gates. This allows the control gate to have a large coupling area with both the first and second floating gates. The above structure omits the erase gate, but by applying a voltage difference between the control gate and the source doped region, electrons can be released from the first or second floating gate to the source doped region, thereby achieving the erase operation. This reduces the area of ​​the memory cell, and because the control gate occupies a large area, its thickness can be reduced without affecting its resistance. This also facilitates control over the height of the memory cell, improving the process window and chip integration density.

[0039] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0040] Figures 2 to 15 This is a schematic diagram of the steps in the method for forming a memory structure according to an embodiment of the present invention.

[0041] Please refer to Figure 2 Substrate 200 is provided.

[0042] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate is made of silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0043] Subsequently, a plurality of memory cell structures are formed on the substrate 200. The memory cell structure includes a first word line gate and a second word line gate, and a stacked gate structure located between the first word line gate and the second word line gate. The stacked gate structure includes a first floating gate, a second floating gate, and a control gate. A first opening is provided between the first floating gate and the second floating gate, exposing the surface of the substrate 200. The control gate is located within the first opening and on the top surface of the first floating gate and the second floating gate. The first floating gate and the second floating gate, the first word line gate and the second word line gate are respectively arranged along a first direction.

[0044] In this embodiment, the stacked gate structure further includes a first sidewall located between the control gate and the first word line gate, between the control gate and the second word line gate, and on the top surface of the first floating gate and the second floating gate.

[0045] In this embodiment, the memory cell structure further includes a second sidewall, located on the substrate surface and between the stacked gate structure, the first word line gate, and the second word line gate.

[0046] In this embodiment, please refer to the method for forming the storage cell structure. Figures 3 to 5 An initial floating gate material layer and a hard mask layer located on the surface of the initial floating gate material layer are formed on the surface of the substrate 200.

[0047] Please refer to Figure 3 A floating gate material layer 201 is formed on the surface of the substrate 200; a mask material layer 203 is formed on the surface of the floating gate material layer 201.

[0048] In this embodiment, before forming the floating gate material layer 201, a floating gate dielectric material layer 202 is also formed on the surface of the substrate 200. The floating gate dielectric material layer 202 is used to form the first floating gate dielectric layer and the second floating gate dielectric layer.

[0049] The material of the mask material layer 203 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

[0050] In this embodiment, the mask material layer 203 includes a first mask material layer (not shown in the figure) and a second mask material layer (not shown in the figure) located on the surface of the first mask material layer, forming a double-layer structure. The material of the first mask material layer is silicon oxide, and the material of the second mask material layer is silicon nitride.

[0051] In other embodiments, the number of mask material layers is not limited to two layers; it can be a single layer or multiple layers.

[0052] Please refer to Figure 4 The mask material layer 203 is patterned, and a second opening 204 is formed in the mask material layer 203. The second opening 204 exposes a portion of the floating gate material layer 201, and the hard mask layer 205 is formed by the mask material layer 203.

[0053] In this embodiment, the first sidewall 206 is formed on the sidewall of the second opening 204 before the first opening is formed.

[0054] Specifically, the first sidewall 206 is formed on the two opposite sidewalls of the second opening 204 along the first direction X, and the first direction X is parallel to the surface direction of the substrate 200.

[0055] Please refer to Figure 5 The portion of the floating gate material layer 201 exposed by the second opening 204 is etched to form the first opening 207 within the floating gate material layer 201, thereby forming the initial floating gate material layer 208 with the floating gate material layer 201.

[0056] Here, the hard mask layer 205 formed has a second opening 204, the sidewall of the second opening 204 has a first sidewall 206, the initial floating grid material layer 208 has a first opening 207, the first opening 207 is located at the bottom of the second opening 204 and communicates with the second opening 204, and the bottom of the second opening 204 exposes part of the surface of the initial floating grid material layer 208.

[0057] In this embodiment, the floating gate dielectric material layer 202 at the bottom of the first opening 207 is also etched until the surface of the substrate 200 is exposed.

[0058] Please refer to Figure 6 The source doped region 209 is formed in the substrate 200 at the bottom of the first opening 207.

[0059] Subsequently, the control gate is formed within the first opening 207 and the second opening 204.

[0060] In this embodiment, a protective layer is also formed on the top surface of the control gate before the hard mask layer 205 is removed.

[0061] In this embodiment, the top surface of the control gate is lower than the top surface of the hard mask layer 205, and the protective layer is formed in the second opening.

[0062] In this embodiment, the method for forming the control gate and the protective layer is described in reference [reference needed]. Figure 7 and Figure 8 .

[0063] Please refer to Figure 7 A control gate material layer (not shown) is formed in the first opening 207 and the second opening 204, and on the surface of the hard mask layer 205; the control gate material layer is planarized until the surface of the hard mask layer 205 is exposed to form a transition control gate 210.

[0064] In this embodiment, before forming the control gate material layer, a control gate dielectric material layer (not shown in the figure) is also formed in the first opening 207 and the second opening 204, and on the surface of the hard mask layer 205; the control gate dielectric layer 211 is formed by the control gate dielectric material layer.

[0065] In this embodiment, the material of the control gate dielectric layer 211 includes silicon oxide.

[0066] In other embodiments, the control gate dielectric layer can be other dielectric material layers, such as an ONO (silicon oxide / silicon nitride / silicon oxide) structure.

[0067] In this embodiment, the stacked gate structure further includes the control gate dielectric layer 211.

[0068] Please refer to Figure 8 The transition control gate 210 is etched to form the control gate 212 and a groove (not shown in the figure) located on the control gate 212; the protective layer 213 is formed in the groove.

[0069] The protective layer 213 is made of a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride. In this embodiment, the protective layer 213 is made of silicon oxide.

[0070] The method for forming the protective layer 213 includes: forming a protective material layer (not shown in the figure) in the groove and on the surface of the hard mask layer 205; planarizing the protective material layer until the hard mask layer 205 is exposed.

[0071] In another embodiment, the top surface of the control gate is flush with the top surface of the hard mask layer; the method of forming the control gate and the protective layer includes: forming a control gate material layer in the first opening and the second opening and on the surface of the hard mask layer; planarizing the control gate material layer until the surface of the hard mask layer is exposed to form the control gate; and forming the protective layer on the surface of the control gate.

[0072] Please refer to Figure 9 Remove the hard mask layer 205 to expose part of the surface of the initial floating gate material layer 208.

[0073] The method for removing the hard mask layer 205 includes one or a combination of dry etching and wet etching processes. In this embodiment, a wet etching process is used to remove the hard mask layer 205.

[0074] Please refer to Figure 10 Using the control gate 212 as a mask, the initial floating gate material layer 208 is etched until the surface of the substrate 200 is exposed, forming the first floating gate 2141 and the second floating gate 2142. The first floating gate 2141 and the second floating gate 2142 are arranged along the first direction X to form a stacked gate structure.

[0075] Specifically, the initial floating grid material layer 208 is etched using the protective layer 213 and the first sidewall 206 as a mask.

[0076] In this embodiment, the stacked gate structure further includes: a first floating gate dielectric layer 2151 located between the first floating gate 2141 and the substrate 200; and a second floating gate dielectric layer 2152 located between the second floating gate 2142 and the substrate 200.

[0077] Specifically, the floating gate dielectric material layer 202 is etched to form the floating gate dielectric layer 2151 and the second floating gate dielectric layer 2152.

[0078] Please refer to Figure 11 The second sidewall 216 is formed on the sidewall of the stacked grid structure.

[0079] The material of the second sidewall 216 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride. In this embodiment, the material of the second sidewall 216 is silicon nitride.

[0080] In this embodiment, the second sidewall 216 is a single-layer structure.

[0081] In other embodiments, the second sidewall may be a multi-layered structure.

[0082] Subsequently, a first character line grid and a second character line grid are formed on the side wall of the second side wall 216.

[0083] In this embodiment, the method for forming the first word line grid and the second word line grid is described in reference [reference needed]. Figures 12 to 13 .

[0084] Please refer to Figure 12 A word line grid material layer (not shown) is formed on the surface of the substrate 200, the sidewall of the second sidewall 216, and the top surface of the protective layer 213; the word line grid material layer is planarized until the top surface of the protective layer 213 is exposed to form a transition word line grid 217.

[0085] In this embodiment, the transition word grid 217 is also etched so that the protective layer 213 protrudes relative to the transition word grid 217, and then the protective layer 213 is removed.

[0086] In another embodiment, the protective layer can be removed first, and then the transition word line grid and the control grid can be planarized so that the transition word line grid is flush with the control grid.

[0087] In this embodiment, before forming the word line grid material layer, a word line dielectric material layer is also formed on the surface of the substrate 200, the sidewall of the second sidewall 216, and the top surface of the protective layer 213, and the word line grid material layer is formed on the surface of the word line dielectric material layer.

[0088] Please refer to Figure 13 The transition word line gate 217 is graphically represented to form the first word line gate 2181 and the second word line gate 2182, forming a memory cell structure. The memory cell structure includes the first word line gate 2181 and the second word line gate 2182, as well as a stacked gate structure located between the first word line gate 2181 and the second word line gate 2182. The stacked gate structure includes a first floating gate 2141, a second floating gate 2142, and a control gate 212.

[0089] The second sidewall 216 is used to achieve electrical isolation between the first word line grid 2181 and the first floating grid 2141, and between the second word line grid 2182 and the second floating grid 2142.

[0090] The first sidewall 206 and the second sidewall 216 are used for electrical isolation between the control gate 212 and the first word line gate 2181, and between the control gate 212 and the second word line gate 2182. Since no erase gate is provided, the first sidewall 206 and the second sidewall 216 can be made thicker to achieve lateral isolation between the control gate 212 and the first word line gate 2181 and the second word line gate 2182 on both sides. This eliminates the need for an isolation structure above the control gate 212 to achieve electrical isolation, further facilitating a reduction in the height of the memory cell.

[0091] In this embodiment, the word line dielectric material layer is etched to form a first word line gate dielectric layer (not shown in the figure) and a second word line gate dielectric layer (not shown in the figure). Specifically, the first word line gate dielectric layer is formed between the first word line gate 2181 and the substrate 200 and the stacked gate structure, and the second word line gate dielectric layer is formed between the second word line gate 2182 and the substrate 200 and the stacked gate structure.

[0092] Subsequently, a first drain doped region is formed in the substrate 200 on one side of the memory cell structure, and a second drain doped region is formed in the substrate 200 on the other side.

[0093] Subsequently, a first drain doped region is formed in the substrate on one side of the memory cell structure, and a second drain doped region is formed in the substrate on the other side.

[0094] In this embodiment, the memory cell structure further includes a third sidewall, formed on the sidewalls of the first word line gate and the second word line gate away from the stacked gate structure. Specifically, before forming the third sidewall, please refer to... Figure 14 .

[0095] Please refer to Figure 14 A first lightly doped region 2191 and a first halo doped region 2201 are formed in the substrate 200 on the side of the first word gate 2181 away from the stacked gate structure. The doping depth of the first halo doped region 2201 is greater than the doping depth of the first lightly doped region 2191. A second lightly doped region 2192 and a second halo doped region 2202 are formed in the substrate 200 on the side of the second word gate 2182 away from the stacked gate structure. The doping depth of the second halo doped region 2202 is greater than the doping depth of the second lightly doped region 2192.

[0096] The first lightly doped region 2191 is used to connect the channel below the first word line gate 2181, and the second lightly doped region 2192 is used to connect the channel below the second word line gate 2182 and weaken the hot carrier effect (HCI); the first halo ring doped region 2201 and the second halo ring doped region 2202 are used to reduce the source-drain punch-through probability.

[0097] Please refer to Figure 15 A first drain doped region 2211 is formed in the substrate 200 on one side of the memory cell structure, and a second drain doped region 2212 is formed in the substrate 200 on the other side.

[0098] Thus, in the formed memory cell structure, the control gate has a large coupling area with the first floating gate and the second floating gate, respectively. The above structure omits the erase gate, but by applying a voltage difference between the control gate 212 and the source doped region 209, electrons can be released from the first floating gate 2141 or the second floating gate 2142 to the source doped region 209, thereby realizing the erase operation. This helps to reduce the area of ​​the memory cell, and since the control gate 212 occupies a large area, the thickness of the control gate 212 can be reduced without affecting its resistance, which is beneficial for controlling the height of the memory cell and improving the process window and chip integration.

[0099] In this embodiment, a third sidewall 222 is formed on the sidewalls of the first word line gate 2181 and the second word line gate 2182 away from the stacked gate structure; after the third sidewall 222 is formed, the first drain doped region 2211 and the second drain doped region 2212 are formed.

[0100] Accordingly, one embodiment of the present invention also provides a memory structure formed using the above method. Please refer to [the original text]. Figure 15 The system includes: a substrate 200; a plurality of memory cell structures located on the substrate 200, the memory cell structures including a first word line gate 2181 and a second word line gate 2182, and a stacked gate structure located between the first word line gate 2181 and the second word line gate 2182, the stacked gate structure including a first floating gate 2141, a second floating gate 2142 and a control gate 212, wherein a first opening 207 is provided between the first floating gate 2141 and the second floating gate 2142 to expose the surface of the substrate 200 (e.g., ...). Figure 5As shown), the control gate 212 is located within the first opening 207 and on the top surface of the first floating gate 2141 and the second floating gate 2142. The first floating gate 2141 and the second floating gate 2142, the first word line gate 2181 and the second word line gate 2182 are respectively arranged along the first direction X; the source doped region 209 is located within the substrate 200 at the bottom of the first opening 207; the first drain doped region 2211 and the second drain doped region 2212 are located within the substrate 200 on one side of the memory cell structure, and the second drain doped region 2212 is located within the substrate 200 on the other side of the memory cell structure.

[0101] Thus, in the above-described memory cell structure, the control gate has a large coupling area with the first floating gate and the second floating gate, respectively. The above structure omits the erase gate, but by applying a voltage difference between the control gate 212 and the source doped region 209, electrons can be released from the first floating gate 2141 or the second floating gate 2142 to the source doped region 209, thereby realizing the erase operation. This helps to reduce the area of ​​the memory cell, and since the control gate 212 occupies a large area, the thickness of the control gate 212 can be reduced without affecting its resistance, which is beneficial for controlling the height of the memory cell and improving the process window and chip integration.

[0102] In this embodiment, the stacked gate structure further includes a first sidewall 216 located between the control gate 212 and the first word line gate 2141, between the control gate 212 and the second word line gate 2142, and located on the top surface of the first floating gate 2141 and the second floating gate 2142.

[0103] In this embodiment, the memory cell structure further includes a second sidewall 216, located on the surface of the substrate 200 and between the stacked gate structure, the first word line gate 2141, and the second word line gate 2142.

[0104] In this embodiment, the storage cell structure further includes a third sidewall 222, which is located on the sidewalls of the first word line gate 2181 and the second word line gate 2182 away from the stacked gate structure.

[0105] In this embodiment, the memory cell structure further includes: a first lightly doped region 2191 and a first halo-ring doped region 2201, wherein the first lightly doped region 2191 and the first halo-ring doped region 2201 are located in the substrate 200 on the side of the first word line gate 2181 away from the stacked gate structure, and the doping depth of the first halo-ring doped region 2201 is greater than the doping depth of the first lightly doped region 2191; a second lightly doped region 2192 and a second halo-ring doped region 2202, wherein the second lightly doped region 2192 and the second halo-ring doped region 2202 are located in the substrate 200 on the side of the second word line gate 2202 away from the stacked gate structure, and the doping depth of the second halo-ring doped region 2202 is greater than the doping depth of the second lightly doped region 2192.

[0106] In this embodiment, the memory cell structure further includes: a first floating gate dielectric layer 2151 located between the first floating gate 2141 and the substrate 200; and a second floating gate dielectric layer 2152 located between the second floating gate 2142 and the substrate 200.

[0107] In this embodiment, the stacked gate structure further includes: a control gate dielectric layer 211 located on the sidewall of the control gate 212 and between the control gate 212 and the first floating gate 2141, the second floating gate 2142, and the substrate 200.

[0108] Figure 16 This is a schematic diagram of the structure of a memory according to an embodiment of the present invention.

[0109] Accordingly, one embodiment of the present invention also provides a memory circuit, the memory circuit including a plurality of memory cells arranged in an array along a first direction X, wherein the memory cell structure formed between each pair of adjacent memory cells in the first direction X is described in [the following text is missing]. Figure 15 Based on, refer to Figure 16The system includes: a substrate 200; a first word line gate 2181 and a second word line gate 2182; and a stacked gate structure located between the first word line gate 2181 and the second word line gate 2182. The stacked gate structure includes a first floating gate 2141, a second floating gate 2142, and a control gate 212. A first opening 207 (as shown in the figure) is provided between the first floating gate 2141 and the second floating gate 2142, exposing the surface of the substrate 200. The control gate 212 is located within the first opening 207 and between the first floating gate 2141 and the second floating gate 2142. On the top surface of 2, the first floating gate 2141 and the second floating gate 2142, the first word line gate 2181 and the second word line gate 2182 are respectively arranged along the first direction X; the source doped region 209 is located in the substrate 200 at the bottom of the first opening 207; the first drain doped region 2211 and the second drain doped region 2212 are located in the substrate 200 on one side of the memory cell structure, and the second drain doped region 2212 is located in the substrate 200 on the other side of the memory cell structure; word line WL i-1 / WL i Electrically connected to the first word line gate 2181 or the second word line gate 2182 of the same row of memory cells; bit line BL j It is electrically connected to the first drain doped region 2211 and the second drain doped region 2212 of the same column memory cell; the source line SL i / 2 The source doped region 209 of the adjacent memory cell is electrically connected; the control gate line CG i / 2 The control gate 212 is electrically connected to the same-line storage cell, and the control gate line CG i / 2 The source line SL is used to apply the first erase voltage. i / 2 This is used to apply a second erase voltage, where the first erase voltage is less than the second erase voltage, which allows electrons to be released from the first floating gate or the second floating gate into the source doped region.

[0110] Here, the erase operation can be achieved without setting an erase gate in the memory structure, which helps to reduce the area of ​​the memory cell. Furthermore, since the control gate occupies a large area, the thickness of the control gate can be reduced without affecting its resistance, which helps to control the height of the memory cell and improve the process window and chip integration.

[0111] It should be noted that i is an even number and j is a positive integer, where i represents the row number of the storage unit in the array and j represents the column number of the storage unit in the array. Figure 16 Cell1, indicated by the dashed line, comprises two adjacent memory cells, as shown below. Figure 15 The storage cell structure shown is one of the aforementioned structures. Additionally, Figure 16The number of rows and columns shown are for illustrative purposes only and can be adjusted in other embodiments according to actual needs.

[0112] In this embodiment, the memory circuit further includes: a programming unit for controlling the control gate line CG of the selected memory cell. i / 2 Apply the first programming voltage to its source line SL i / 2 Apply a second programming voltage to its bit line BL j A first constant current is applied, and the first programming voltage is greater than the second programming voltage, to program the first floating gate 2141 or the second floating gate 2142 of the selected memory cell.

[0113] In this embodiment, the memory circuit further includes: a read unit, used for reading the control gate line CG of the selected memory cell. i / 2 and the source line SL i / 2 Apply 0V voltage to its bit line BL. j Apply an erase voltage and read from each of the bit lines BL. j Output current.

[0114] In this embodiment, the memory circuit further includes: an erasure unit, used for erasing the control gate line CG of the selected memory cell. i / 2 Apply the first erase voltage and apply SL to its source line. i / 2 A second erase voltage is applied, wherein the first erase voltage is a negative voltage and the second erase voltage is a positive voltage, to erase the stored information in the selected storage cell.

[0115] In this embodiment, the erasure unit is also used to erase all the word lines WL i-1 / WL i and the bit line BL j All are placed in a floating state to prevent other storage units from being accidentally accessed.

[0116] Accordingly, this embodiment of the invention also provides a method for operating the above-described memory circuit; please refer to further details. Figure 15 and Figure 16 This includes: programming operations, and control gate lines CG of the selected memory cells. i / 2 Apply the first programming voltage to its source line SL i / 2 Apply a second programming voltage to its bit line BL j A first constant current is applied, and the first programming voltage is greater than the second programming voltage, to program the first floating gate 2141 or the second floating gate 2142 of the selected memory cell; a read operation is performed on the control gate line CG of the selected memory cell. i / 2 and the source line SL i / 2Apply 0V voltage to its bit line BL. j Apply a read voltage and read from each of the stated bit lines BL. j Output current; erase operation, for the control gate line CG of the selected memory cell. i / 2 Apply a first erase voltage to its source line SL i / 2 A second erase voltage is applied, wherein the first erase voltage is less than the second erase voltage, to erase the stored information in the storage cell.

[0117] Here, the erase operation can be achieved without setting an erase gate in the memory structure, which helps to reduce the area of ​​the memory cell. Furthermore, since the control gate occupies a large area, the thickness of the control gate can be reduced without affecting its resistance, which helps to control the height of the memory cell and improve the process window and chip integration.

[0118] To explain the various operating states in the memory circuit, a detailed description will be provided below in conjunction with Table 1 and the accompanying drawings.

[0119]

[0120] Table 1 Operating Status of Memory Circuits

[0121] Please continue to refer to this. Figure 15 and Figure 16 Based on Table 1, the operating states of the memory circuit are as follows:

[0122] 1. Programming Operations:

[0123] The control gate line CG of the selected memory cell i / 2 Apply the first programming voltage to its source line SL i / 2 Apply a second programming voltage to its bit line BL j A first constant current is applied, and the first programming voltage is greater than the second programming voltage, to program the first floating gate 2141 or the second floating gate 2142 of the selected memory cell.

[0124] Taking Cell1 as an example, the memory cell in the first row and first column is selected for programming. A first programming voltage is applied to the control gate line CG1, a second programming voltage is applied to the source line SL1, a first constant current is applied to the bit line BL1, and charge is injected into the first floating gate 2141 to realize the programming of the memory cell.

[0125] The first programming voltage range is 6.0V~10.0V, the second programming voltage range is 3.5V~6.5V, and the first constant current range is 1.0μA~6.0μA.

[0126] In this embodiment, the first programming voltage is 8.0V, the second programming voltage is 4.5V, and the first constant current is 2μA (where V... dp (Programming voltage at 2μA current).

[0127] 2. Read operation:

[0128] The control gate line CG of the selected memory cell i / 2 and the source line SL i / 2 Apply 0V voltage to its bit line BL. j Apply a read voltage and read from each of the stated bit lines BL. j Output current.

[0129] Continuing with Cell1 as an example, a read operation is performed on the memory cell in the first row and first column. A 0V voltage is applied to its control gate line CG1 and source line SL1, and a read voltage is applied to the bit line BL1. The current output from each bit line is read. Here, the same read voltage is also applied to unselected bit lines (such as BL2). The state of the memory cell is determined by detecting the difference in bit line current.

[0130] The reading voltage range is 0.4V~1.0V.

[0131] In this embodiment, the reading voltage is 0.8V.

[0132] 3. Erasing operation:

[0133] The control gate line CG of the selected memory cell i / 2 Apply the first erase voltage and apply SL to its source line. i / 2 A second erase voltage is applied, wherein the first erase voltage is less than the second erase voltage, to erase the stored information in the storage cell.

[0134] Taking Cell1 as an example, the memory cell in the first row and first column is selected for erasure operation. A first erasure voltage is applied to its control gate line CG1, and a second erasure voltage is applied to its source line SL1, so that electrons are released from the first floating gate 2141 to the source doped region 2201.

[0135] The first erase voltage range is -10.0V to 0V; the second erase voltage range is 0V to 10V.

[0136] In this embodiment, the first erase voltage is -8.0V and the second erase voltage is 8.0V.

[0137] In this embodiment, all word lines and bit lines are also placed in a floating state, such as word line WL1, word line WL2, bit line BL1 and bit line BL2, to prevent other memory cells from being accidentally operated.

[0138] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A memory structure, characterized in that, include: Substrate; A plurality of memory cell structures located on a substrate, the memory cell structures including a first word line gate and a second word line gate, and a stacked gate structure located between the first word line gate and the second word line gate, the stacked gate structure including a first floating gate, a second floating gate and a control gate, a first opening exposing the substrate surface between the first floating gate and the second floating gate, the control gate being located within the first opening and on the top surface of the first floating gate and the second floating gate, the first floating gate and the second floating gate, the first word line gate and the second word line gate being arranged along a first direction; The source doped region is located within the substrate at the bottom of the first opening; A first drain doped region and a second drain doped region, wherein the first drain doped region is located in the substrate on one side of the memory cell structure, and the second drain doped region is located in the substrate on the other side of the memory cell structure.

2. The method for forming the memory structure as described in claim 1, characterized in that, The stacked gate structure further includes: a first sidewall located between the control gate and the first word line gate, between the control gate and the second word line gate, and on the top surfaces of the first floating gate and the second floating gate; the memory cell structure further includes: a second sidewall located on the substrate surface and between the stacked gate structure and the first word line gate, and the second word line gate.

3. The memory structure as described in claim 1, characterized in that, The memory cell structure further includes: a third sidewall, located on the sidewalls of the first word line gate and the second word line gate away from the stacked gate structure; a first lightly doped region and a first halo-ring doped region, the first lightly doped region and the first halo-ring doped region being located in the substrate on the side of the first word line gate away from the stacked gate structure, the doping depth of the first halo-ring doped region being greater than the doping depth of the first lightly doped region; a second lightly doped region and a second halo-ring doped region, the second lightly doped region and the second halo-ring doped region being located in the substrate on the side of the second word line gate away from the stacked gate structure, the doping depth of the second halo-ring doped region being greater than the doping depth of the second lightly doped region.

4. The memory structure as described in claim 1, characterized in that, The memory cell structure further includes: a first floating gate dielectric layer located between the first floating gate and the substrate; a second floating gate dielectric layer located between the second floating gate and the substrate; the stacked gate structure further includes: a control gate dielectric layer located on the control gate sidewall and between the control gate and the first floating gate, the second floating gate, and the substrate.

5. A method for forming a memory structure, characterized in that, include: Provide substrate; A plurality of memory cell structures are formed on the substrate. The memory cell structure includes a first word line gate and a second word line gate, and a stacked gate structure located between the first word line gate and the second word line gate. The stacked gate structure includes a first floating gate, a second floating gate, and a control gate. A first opening is provided between the first floating gate and the second floating gate to expose the surface of the substrate. The control gate is located within the first opening and on the top surface of the first floating gate and the second floating gate. The first floating gate and the second floating gate, the first word line gate and the second word line gate are respectively arranged along a first direction. A source doped region is formed within the substrate at the bottom of the first opening; A first drain doped region is formed in the substrate on one side of the memory cell structure, and a second drain doped region is formed in the substrate on the other side.

6. The method for forming the memory structure as described in claim 5, characterized in that, The stacked gate structure further includes: a first sidewall located between the control gate and the first word line gate, between the control gate and the second word line gate, and on the top surfaces of the first floating gate and the second floating gate; the memory cell structure further includes: a second sidewall located on the substrate surface and between the stacked gate structure and the first word line gate, and the second word line gate.

7. The method for forming the memory structure as described in claim 6, characterized in that, The method for forming the memory cell structure includes: forming an initial floating gate material layer and a hard mask layer on the surface of the substrate, the hard mask layer having a second opening and a first sidewall located on the sidewall of the second opening, the initial floating gate material layer having the first opening, the first opening being located at the bottom of the second opening and communicating with the second opening, the bottom of the second opening exposing a portion of the surface of the initial floating gate material layer; forming the source doped region in the substrate at the bottom of the first opening; forming the control gate in the first opening and the second opening; removing the hard mask layer to expose a portion of the surface of the initial floating gate material layer; using the control gate as a mask, etching the initial floating gate material layer until the substrate surface is exposed, forming the first floating gate and the second floating gate; forming the second sidewall on the sidewall of the stacked gate structure; and forming the first word line gate and the second word line gate on the sidewall of the second sidewall, respectively.

8. The method for forming the memory structure as described in claim 7, characterized in that, The method for forming the initial floating gate material layer and the hard mask layer includes: forming a floating gate material layer on the surface of a substrate; forming a mask material layer on the surface of the floating gate material layer; patterning the mask material layer and forming a second opening in the mask material layer, the second opening exposing a portion of the floating gate material layer, thereby forming the hard mask layer with the mask material layer; forming a first sidewall on the sidewall of the second opening; etching the portion of the floating gate material layer exposed by the second opening to form the first opening in the floating gate material layer, thereby forming the initial floating gate material layer with the floating gate material layer.

9. The method for forming the memory structure as described in claim 8, characterized in that, The stacked gate structure further includes: a first floating gate dielectric layer located between the first floating gate and the substrate; a second floating gate dielectric layer located between the second floating gate and the substrate; the method for forming the first floating gate dielectric layer and the second floating gate dielectric layer includes: forming a floating gate dielectric material layer on the surface of the substrate before forming the floating gate material layer; the floating gate dielectric material layer is etched to form the first floating gate dielectric layer and the second floating gate dielectric layer.

10. The method for forming the memory structure as described in claim 7, characterized in that, Also includes: A protective layer is formed on the surface of the control gate before the hard mask layer is removed; The method for forming the first word grid and the second word grid includes: after forming the second sidewall, forming a word grid material layer on the substrate surface, the sidewall of the second sidewall, and the top surface of the protective layer; planarizing the word grid material layer until the top surface of the protective layer is exposed to form a transition word grid; patterning the transition word grid to form the first word grid and the second word grid; and removing the protective layer.

11. The method for forming the memory structure as described in claim 10, characterized in that, The top surface of the control gate is flush with the top surface of the hard mask layer; the method of forming the control gate and the protective layer includes: forming a control gate material layer in the first opening and the second opening, and on the surface of the hard mask layer; planarizing the control gate material layer until the surface of the hard mask layer is exposed to form the control gate; and forming the protective layer on the surface of the control gate.

12. The method for forming the memory structure as described in claim 10, characterized in that, The top surface of the control gate is lower than the top surface of the hard mask layer, and the protective layer is formed within the second opening; The method for forming the control gate and the protective layer includes: forming a control gate material layer in the first opening and the second opening, and on the surface of the hard mask layer; planarizing the control gate material layer until the surface of the hard mask layer is exposed to form a transition control gate; etching the transition control gate to form the control gate and a groove located on the control gate; and forming the protective layer in the groove.

13. The method for forming the memory structure as described in claim 5, characterized in that, The memory cell structure further includes: a third sidewall, located on the sidewalls of the first word line gate and the second word line gate away from the stacked gate structure; before forming the third sidewall, it further includes: forming a first lightly doped region and a first halo ring doped region in the substrate on the side of the first word line gate away from the stacked gate structure, wherein the doping depth of the first halo ring doped region is greater than the doping depth of the first lightly doped region; and forming a second lightly doped region and a second halo ring doped region in the substrate on the side of the second word line gate away from the stacked gate structure, wherein the doping depth of the second halo ring doped region is greater than the doping depth of the second lightly doped region.

14. A memory circuit, characterized in that, include: A plurality of storage cells arranged in an array along a first direction, wherein the storage cell structure formed between each pair of adjacent storage cells along the first direction includes: Substrate; A first word line gate and a second word line gate, and a stacked gate structure located between the first word line gate and the second word line gate, the stacked gate structure including a first floating gate, a second floating gate and a control gate, a first opening exposing the substrate surface between the first floating gate and the second floating gate, the control gate being located within the first opening and on the top surface of the first floating gate and the second floating gate, the first floating gate and the second floating gate, the first word line gate and the second word line gate being arranged along a first direction; The source doped region is located within the substrate at the bottom of the first opening; A first drain doped region and a second drain doped region, wherein the first drain doped region is located in the substrate on one side of the memory cell structure, and the second drain doped region is located in the substrate on the other side of the memory cell structure; The word line is electrically connected to the first word line gate or the second word line gate of the memory cell in the same row; The bit line is electrically connected to the first drain doped region and the second drain doped region of the memory cell in the same column; The source line is electrically connected to the source doped region of the adjacent memory cell; A control gate line is electrically connected to the control gate of the adjacent memory cell. The control gate line is used to apply a first erase voltage, and the source line is used to apply a second erase voltage. The first erase voltage is less than the second erase voltage, which allows electrons to be released from the first floating gate or the second floating gate to the source doped region.

15. The memory circuit as described in claim 14, characterized in that, Also includes: A programming unit is configured to apply a first programming voltage to the control gate line of a selected memory cell, apply a second programming voltage to its source line, and apply a first constant current to its bit line, wherein the first programming voltage is greater than the second programming voltage, so as to program the first floating gate or the second floating gate of the selected memory cell.

16. The memory circuit as described in claim 14, characterized in that, Also includes: The read unit is configured to apply a 0V voltage to the control gate line and the source line of the selected memory cell, apply a read voltage to its bit line, and read the current output from each bit line.

17. The memory circuit as described in claim 14, characterized in that, Also includes: An erase unit is configured to apply a first erase voltage to the control gate line of a selected memory cell and a second erase voltage to its source line, wherein the first erase voltage is a negative voltage and the second erase voltage is a positive voltage, so as to erase the stored information in the selected memory cell.

18. The memory circuit as described in claim 17, characterized in that, The erasure unit is also used to place all the word lines and bit lines in a floating state.

19. A method of operating a memory circuit as described in any one of claims 14 to 18, characterized in that, include: The programming operation involves applying a first programming voltage to the control gate line of the selected memory cell, applying a second programming voltage to its source line, and applying a first constant current to its bit line. The first programming voltage is greater than the second programming voltage, so as to program the first floating gate or the second floating gate of the selected memory cell. The read operation involves applying a 0V voltage to the control gate line and the source line of the selected memory cell, applying a read voltage to its bit line, and reading the current output from each bit line. The erase operation involves applying a first erase voltage to the control gate line of the selected memory cell and a second erase voltage to its source line, wherein the first erase voltage is less than the second erase voltage, so as to erase the stored information in the memory cell.

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