Cascode shield gate trench power semiconductor device and preparation method thereof

Abstract

The invention relates to a power semiconductor device technology, in particular to a common-source shield gate trench power semiconductor device and a preparation method thereof. Comprising an epitaxial layer formed on a substrate; a plurality of alternately arranged P-type columns or N-type columns longitudinally extending from the surface of the epitaxial layer to the upper surface of the substrate; the grooves divide the doped region into first doped regions and second doped regions which are alternately arranged; the first control gate is located at the lower part of the groove, and the shielding dielectric layer is formed on the surface of the side wall of the groove above the first control gate; the second control gate is positioned above the first control gate; the first contact electrode penetrates through the covering dielectric layer and is connected with the first contact region; the second contact electrode penetrates through the covering dielectric layer and is connected with the second contact region; and the first substrate electrode and the second substrate electrode penetrate through the covering dielectric layer and are connected with the P-type column or the N-type column. According to the bidirectional power device provided by the invention, symmetrical high-voltage bidirectional blocking, low channel loss and excellent dynamic characteristics can be realized on a single chip.

Description

Technical Field

[0001] This invention relates to power semiconductor device technology, specifically to a common-source shielded gate trench power semiconductor device and its fabrication method. Background Technology

[0002] With the rapid development of consumer electronics, industrial power supplies, and servers, the requirements for power switching devices in power electronic systems are becoming increasingly stringent. Especially in applications requiring bidirectional energy flow control and multi-channel power supply switching, such as consumer electronics with wired charging, reverse OTG power supply, and wireless charging capabilities, and server power systems requiring hot-swapping and redundancy, traditional unidirectional power switching devices are no longer sufficient. The core of these applications lies in the need for a power switch capable of bidirectionally blocking current to achieve safe and efficient isolation and switching between different power channels.

[0003] Currently, power switching solutions for achieving bidirectional turn-off include connecting two discrete power MOSFETs back-to-back or using a mechanical relay. While connecting two discrete power MOSFETs back-to-back can achieve bidirectional turn-off, it suffers from high on-resistance due to the series connection, large package size, and high cost. Although mechanical relays have bidirectional conductivity, they have inherent drawbacks such as slow switching speed, short lifespan, and contact arcing, making them unsuitable for high-frequency and high-efficiency applications.

[0004] To further improve integration and performance, existing technologies have proposed various monolithic integrated bidirectional device structures. However, traditional planar or trench power MOSFET structures are mainly optimized for unidirectional operation, and their body diode becomes a performance bottleneck when reverse biased, resulting in a significantly lower reverse breakdown voltage than the forward breakdown voltage and a severe asymmetry in bidirectional blocking characteristics. Furthermore, these structures generally face challenges in bidirectional applications such as high specific on-resistance, large switching losses, and poor reverse recovery characteristics of the body diode.

[0005] Shielded Gate Trench (SGT) MOSFET structures effectively improve the electric field distribution by introducing a shielded gate, thereby enhancing the device's unidirectional breakdown voltage and switching performance. A significant characteristic is that the dielectric layer thickness between the gate and drain (GD) is much greater than that of the gate oxide layer, resulting in a much higher breakdown voltage between the gate and drain than between the gate and source. This provides crucial assurance for gate reliability in high-voltage applications. Nevertheless, current research and applications of shielded gate trench technology are primarily focused on unidirectional devices, and its structural advantages have not yet been fully realized in truly symmetrical bidirectional power switches.

[0006] In the prior art, Chinese patent CN213660381U discloses a bidirectional power device. This device forms a doped region in the epitaxial layer, sets a channel region at the bottom of the trench, and reduces the bulk resistance of the device through a conductive channel connected to the substrate, thereby improving the performance of the bidirectional power device. However, the channel region and the doped region of this device have the same doping type, which means that the device cannot achieve effective turn-off when the gate voltage is zero or negative during the switching process. Leakage path always exists, causing the threshold voltage to lose its controllability, severely limiting the operating frequency of the device, and significantly reducing the overall reliability. Summary of the Invention

[0007] To address the aforementioned problems, the present invention aims to provide a common-source shielded gate trench power semiconductor device; furthermore, the present invention aims to provide a method for fabricating a common-source shielded gate trench power semiconductor device.

[0008] A common-source shielded gate trench power semiconductor device includes: a substrate; an epitaxial layer formed on the substrate; a plurality of alternately arranged P-type pillars or N-type pillars extending longitudinally from the surface of the epitaxial layer to the upper surface of the substrate; a doped region formed in the epitaxial layer; a plurality of trenches formed in the doped region, the trenches dividing the doped region into alternately arranged first doped regions and second doped regions; a gate oxide layer formed on the surface of the lower sidewall of the trench; a first control gate formed in the trench, located in the lower part of the trench, and in contact with the gate oxide layer; and a shielding dielectric layer formed on the sidewall of the trench above the first control gate. The wall surface; a second control gate, formed within the trench, located above the first control gate and in contact with the shielding dielectric layer; a first contact region, formed in the first doped region; a second contact region, formed in the second doped region; a cover dielectric layer, formed on the upper part of the epitaxial layer, wherein a plurality of contact holes are formed on the cover dielectric layer, and the contact holes respectively form: a first contact electrode, which passes through the cover dielectric layer and is connected to the first contact region; a second contact electrode, which passes through the cover dielectric layer and is connected to the second contact region; a first substrate electrode and a second substrate electrode, which pass through the cover dielectric layer and are connected to the P-type pillar or the N-type pillar.

[0009] The common-source shielded gate trench power semiconductor device of the present invention includes a channel region formed in the epitaxial layer at the bottom of the trench, the channel region enclosing the bottom of the trench; the channel region is in contact with the first doped region and the second doped region; the doping type of the channel region is the same as the type of the epitaxial layer.

[0010] The common-source shielded gate trench power semiconductor device of the present invention has a distance of 10 μm to 100 μm between the first substrate electrode and the second substrate electrode, and a depth of 0.1 μm to 50 μm for the multiple trenches (9); the substrate is a silicon substrate, the thickness h1 of the epitaxial layer is 1 μm to 100 μm, and the distance between adjacent P-type pillars or N-type pillars is 10 μm to 100 μm.

[0011] The common-source shielded gate trench power semiconductor device of the present invention has the following characteristics: the distance h3 between the surface of the first control gate and the surface of the epitaxial layer is greater than the distance h4 between the surface of the second control gate and the surface of the epitaxial layer; the distance h3 is 0.1 μm to 10 μm, and the distance h4 is 0.1 μm to 5 μm; the thickness T2 of the shielding dielectric layer is 50 Å to 2000 Å; the thickness T1 of the gate oxide layer is 10 Å to 1000 Å; and an oxide layer is formed along the sidewall surface of the trench on the upper part of the second control gate; the thickness T1 of the gate oxide layer is less than the thickness T2 of the shielding dielectric layer, which is less than the thickness T3 of the oxide layer.

[0012] A method for fabricating a common-source shielded gate trench power semiconductor device includes the following steps: Step S1, providing a substrate; Step S2, forming an epitaxial layer on the substrate; Step S3, forming alternating P-type pillars or N-type pillars in the epitaxial layer through multiple epitaxy and ion implantation, wherein the P-type pillars or N-type pillars extend longitudinally from the surface of the epitaxial layer to the upper surface of the substrate; Step S4, forming a doped region in the epitaxial layer; Step S5, forming a plurality of trenches in the doped region, wherein the trenches divide the doped region into alternating first doped region and second doped region; Step S6, growing a gate oxide layer on the surface of the lower sidewall of the trench; Step S7, forming a first control gate in the trench, located at the lower part of the trench and in contact with the gate oxide layer; Step S8: A shielding dielectric layer is formed on the sidewall surface of the trench above the first control gate; Step S9: A second control gate is formed above the first control gate in the trench, in contact with the shielding dielectric layer; Step S10: A first contact region is formed in the first doped region, and a second contact region is formed in the second doped region; Step S11: A cover dielectric layer is formed on the upper part of the epitaxial layer, and a plurality of contact holes are formed on the cover dielectric layer. The contact holes respectively form: a first contact electrode, which passes through the cover dielectric layer and connects to the first contact region; a second contact electrode, which passes through the cover dielectric layer and connects to the second contact region; and a first substrate electrode and a second substrate electrode, which pass through the cover dielectric layer and connect to the P-type pillar or N-type pillar.

[0013] The preparation method of the present invention includes step S3, which involves depositing a photoresist of a certain thickness on the epitaxial layer, photolithographically etching the window of the P-type pillar or N-type pillar, performing ion implantation from the window to form a floating island region, alternating multiple epitaxy and ion implantation processes along the longitudinal direction of the epitaxial layer to form multiple floating island regions, performing annealing activation, and causing the ions in the multiple floating island regions to diffuse and connect together longitudinally to form the P-type pillar or N-type pillar; step S4 includes forming a SiO2 layer on the surface of the epitaxial layer by thermal oxidation or chemical vapor deposition, and patterning the surface of the epitaxial layer by photolithography and etching processes to form an opening in a designated area; and using an ion implantation process with an implantation energy of 100–10000 keV and an implantation dose of 1×10⁻⁶. 12 ~1×10 15 cm -2 Under the specified process conditions, a doped region of P-well or N-well is formed in the epitaxial layer 2.

[0014] The fabrication method of the present invention includes step S5, which involves removing the SiO2 layer on the surface using a wet etching process; subsequently forming a barrier layer on the surface of the epitaxial layer by thermal oxidation or chemical vapor deposition; patterning the barrier layer by photolithography and etching processes, selectively removing certain areas to form the desired openings; and using the barrier layer as a mask to etch the exposed semiconductor regions to form multiple trenches, which divide the doped regions into alternating first and second doped regions. In step S6, an oxide layer is grown on the sidewalls of the trenches using a thermal oxidation process, the thickness of which is less than the thickness of the barrier layer; selective ion implantation is performed on the bottom of the multiple trenches to form channel regions in the epitaxial layer, which are in contact with both the first and second doped regions; a sacrificial oxide layer is grown on the surface of the trenches using a thermal oxidation process, and then the sacrificial oxide layer is selectively removed by a wet etching process to grow a gate oxide layer with a thickness of T1 on the surface of the trenches.

[0015] The preparation method of the present invention includes step S7, which involves using a deposition process to fill multiple trenches with polysilicon, using a chemical mechanical polishing process to remove the polysilicon outside the multiple trenches, and then using a dry etching process to etch back the polysilicon to form the first control gate, wherein the upper surface of the first control gate is at a distance h3 from the surface of the epitaxial layer; and step S9, which involves using a deposition process to fill multiple trenches with second polysilicon, using a chemical mechanical polishing process to remove the second polysilicon outside the multiple trenches, and then using a dry etching process to etch back the second polysilicon to form the second control gate, wherein the upper surface of the second control gate is at a distance h4 from the silicon surface.

[0016] The preparation method of the present invention includes step S10, which involves forming an oxide layer on the sidewall of the trench and the surface of the epitaxial layer using a chemical vapor deposition process, wherein the thickness of the oxide layer is T3; filling multiple trenches with third polysilicon using a deposition process; removing the third polysilicon outside the multiple trenches using a chemical mechanical polishing process; forming a first contact region in the first doped region and a second contact region in the second doped region using a photolithography mask by implantation and diffusion.

[0017] The preparation method of the present invention includes step S11, which comprises forming a cover dielectric layer by chemical vapor deposition, forming a plurality of contact holes on the cover dielectric layer by photolithography and etching, depositing a metal conductive layer on the surface of the cover dielectric layer and in the contact holes, the metal conductive layer covering and filling the contact holes, and patterning the metal conductive layer again by photolithography and etching to form a first contact electrode, a second contact electrode, a first substrate electrode and a second substrate electrode that are isolated from each other, wherein the first contact electrode and the second contact electrode serve as the source electrode and the drain electrode, respectively, and the spacing between the first substrate electrode and the second substrate electrode does not exceed 50 μm.

[0018] Beneficial effects: This invention provides a novel bidirectional power device that can achieve symmetrical high-voltage bidirectional blocking, low channel loss and excellent dynamic characteristics on a single chip, meeting the urgent needs of modern power electronic systems for high efficiency, high power density and high reliability. Attached Figure Description

[0019] Figure 1 This is a circuit diagram of a common-source shielded gate trench power semiconductor device according to the present invention; Figure 2 This is a circuit internal structure diagram of a common-source shielded gate trench power semiconductor device according to the present invention; Figures 3a to 3t This is a schematic diagram of a method for fabricating a common-source shielded gate trench power semiconductor device according to the present invention; Figure 4 This is a schematic diagram of a specific application circuit of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0022] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0023] Reference Figure 1 , Figure 2 A common-source shielded gate trench power semiconductor device includes: a substrate 1; an epitaxial layer 2 formed on the substrate 1; a plurality of alternately arranged P-type pillars or N-type pillars 5 extending longitudinally from the surface of the epitaxial layer 2 to the upper surface of the substrate 1; a doped region 7 formed in the epitaxial layer 2; a plurality of trenches 9 formed in the doped region 7, the trenches 9 dividing the doped region 7 into alternately arranged first doped region 7a and second doped region 7b; and a gate oxide layer 13. The following are the components of the trench: a first control gate 15 formed in the trench 9, located in the lower part of the trench 9, and in contact with the gate oxide layer 13; a shielding dielectric layer 16 formed on the sidewall surface of the trench 9 above the first control gate 15; a second control gate 18 formed in the trench 9, located above the first control gate 15, and in contact with the shielding dielectric layer 16; a first contact region 22a formed in the first doped region 7a; a second contact region 22b formed in the second doped region 7b; a cover dielectric layer 23 formed on the upper part of the epitaxial layer, with a plurality of contact holes formed on the cover dielectric layer 23, wherein the contact holes respectively form: a first contact electrode 24, which passes through the cover dielectric layer 23 and is connected to the first contact region 22a; a second contact electrode 25, which passes through the cover dielectric layer 23 and is connected to the second contact region 22b; and a first substrate electrode 26a and a second substrate electrode 26b, which pass through the cover dielectric layer 23 and are connected to a P-type pillar or an N-type pillar 5.

[0024] This invention provides a novel bidirectional power device with a common-source differential drain architecture on a single chip, achieving symmetrical high-voltage bidirectional blocking, low channel loss, and excellent dynamic characteristics, thus meeting the urgent needs of modern power electronic systems for high efficiency, high power density, and high reliability.

[0025] Combination Figure 1The equivalent circuit diagram of the present invention shows that the bidirectional power device includes a common source electrode located on the substrate Sub, and two drain electrodes Drain1 and Drain2 serving as output terminals, along with two parasitic body diodes. When the drain Drain2 is shorted to the substrate Sub (i.e., common source), applying a high level higher than the threshold voltage to the gate allows the bidirectional power device to conduct, and current flows from the output terminal Drain1 to Drain2. When the drain Drain1 is shorted to the substrate Sub, similarly, applying a high level to the gate allows current to flow from the output terminal Drain2 to Drain1. When the substrate Sub is grounded, if the voltage applied to the gate is lower than the threshold voltage, the bidirectional power device is in the off state. It can bidirectionally block current.

[0026] The common-source shielded gate trench power semiconductor device of the present invention includes a channel region 12 formed in an epitaxial layer at the bottom of a trench 9, the channel region 12 enclosing the bottom of the trench 9; the channel region 12 is in contact with a first doped region 7a and a second doped region 7b; the doping type of the channel region 12 is the same as that of the epitaxial layer 2.

[0027] In the common-source shielded gate trench power semiconductor device of the present invention, the distance between the first substrate electrode 26a and the second substrate electrode 26b is 10um~100um, and the depth of the multiple trenches 9 is 0.1μm~50μm; the substrate 1 of the present invention is a silicon substrate, and its doping type and concentration are selected according to the product characteristics, and can be N-type or P-type doped; the epitaxial layer 2 is also N-type or P-type, and has a specific resistivity and thickness h1, which can be 1μm~100μm. Taking the bidirectional power device type as an example: if the device is designed as NMOS, both the substrate 1 and the epitaxial layer 2 are doped to form P-type; if the device is PMOS, both are N-type doped.

[0028] The distance between adjacent P-type or N-type columns 5 is 10μm to 100μm.

[0029] In the common-source shielded gate trench power semiconductor device of the present invention, the distance h3 between the surface of the first control gate 15 and the surface of the epitaxial layer 2 is greater than the distance h4 between the surface of the second control gate 18 and the surface of the epitaxial layer 2; the distance h3 is 0.1 μm to 10 μm, and the distance h4 is 0.1 μm to 5 μm; the thickness T2 of the shielding dielectric layer 16 is 50 Å to 2000 Å; the thickness T1 of the gate oxide layer 13 is 10 Å to 1000 Å; including an oxide layer 19, formed along the sidewall surface of the trench 9 on the upper part of the second control gate 18; the thickness T1 of the gate oxide layer 13 is less than the thickness T2 of the shielding dielectric layer 16 and less than the thickness T3 of the oxide layer 19.

[0030] The present invention employs a thicker oxide layer 19 in the upper region of the second control gate 18, which can effectively withstand the high electric field intensity near the surface and ensure the reliability of the device under high voltage. At the same time, the corresponding epitaxial drift region can use a lower doping concentration to further optimize the electric field distribution and ensure sufficient depletion layer width.

[0031] Reference Figures 3a to 3t A method for fabricating a common-source shielded gate trench power semiconductor device includes the following steps: Step S1, providing a substrate 1; Step S2, forming an epitaxial layer 2 on the substrate 1; Step S3, forming alternating P-type pillars or N-type pillars 5 in the epitaxial layer 2 through multiple epitaxy and ion implantation, wherein the P-type pillars or N-type pillars 5 extend longitudinally from the surface of the epitaxial layer 2 to the upper surface of the substrate 1; Step S4, forming a doped region 7 in the epitaxial layer 2; Step S5, forming a plurality of trenches 9 in the doped region 7, wherein the trenches 9 divide the doped region 7 into alternating first doped region 7a and second doped region 7b; Step S7, growing a gate oxide layer 13 on the surface of the lower sidewall of the trench 9; Step S8, forming a first control gate 15 in the trench 9, located at the lower part of the trench 9 and in contact with the gate oxide layer 13; Step S9: A shielding dielectric layer 16 is formed on the sidewall surface of the trench above the first control gate 15. Step S10: A second control gate 18 is formed above the first control gate 15 in the trench 9, and contacts the shielding dielectric layer 16. Step S11: A first contact region 22a is formed in the first doped region 7a, and a second contact region 22b is formed in the second doped region 7b. Step S12: A cover dielectric layer 23 is formed on the upper part of the epitaxial layer 2, and a plurality of contact holes are formed on the cover dielectric layer 23. The contact holes respectively form: a first contact electrode 24, which passes through the cover dielectric layer 23 and is connected to the first contact region 22a; a second contact electrode 25, which passes through the cover dielectric layer 23 and is connected to the second contact region 22b; and a first substrate electrode 26a and a second substrate electrode 26b, which pass through the cover dielectric layer 23 and are connected to a P-type pillar or an N-type pillar 5.

[0032] Reference Figure 3b and Figure 3c Step S3 includes depositing a photoresist 3 of a certain thickness on the epitaxial layer 2, photolithographically etching windows of P-type or N-type pillars 5, and performing ion implantation from the windows to form floating island regions 4. The window distance is L, ranging from 10 to 100 μm. Multiple epitaxial and ion implantations are performed alternately along the longitudinal direction of the epitaxial layer to form multiple floating island regions 4. The total thickness of the epitaxial layer reaches h2, controlled within the range of 1 μm to 100 μm to meet the requirements of different voltage level devices for drift region thickness. When the bidirectional power device is an NMOS transistor, B+ ions are typically used for implantation; when the bidirectional power device is a PMOS transistor, As+ or P+ ions are typically used for implantation. (Refer to...) Figure 3dThe B+ or As+ injected into each layer is activated by annealing, and the ions in multiple floating island regions 4 diffuse, connect together in the longitudinal direction, and contact the substrate 1 to form P-type pillars or N-type pillars 5. The annealing temperature is 1000 degrees and the annealing time is 60 minutes.

[0033] Reference Figure 3e Step S4 includes forming a SiO2 layer 6 on the surface of the epitaxial layer 2 by thermal oxidation or chemical vapor deposition, patterning the surface of the epitaxial layer 2 by photolithography and etching processes to form openings in designated areas, and then using an ion implantation process with an implantation energy of 100–10000 keV and an implantation dose of 1×10⁻⁶. 12 ~1×10 15 cm -2 Under the specified process conditions, a doped region 7, consisting of a P-well or an N-well, is formed in the epitaxial layer 2. The doping type of the doped region 7 is opposite to that of the epitaxial layer 2: if the bidirectional power device is PMOS type, then the doped region 7 is P-type, and the dopant is usually B+; if it is an NMOS type device, then the doped region 7 is N-type, and As+ or P+ is usually used as the dopant impurity.

[0034] Reference Figure 3f Step S5 includes removing the SiO2 layer 6 on the surface using a wet etching process; subsequently, forming a barrier layer 8 on the surface of the epitaxial layer 2 by thermal oxidation or chemical vapor deposition; then patterning the barrier layer 8 using photolithography and etching processes, selectively removing certain areas to form the desired openings; and using the barrier layer 8 as a mask, etching the exposed semiconductor areas to form multiple trenches 9. The trenches 9 divide the doped region 7 into alternately arranged first doped regions 7a and second doped regions 7b, while the area covered by the barrier layer 8 is protected from etching. The conductivity type of the first doped region 7a and the second doped region 7b is opposite to that of the epitaxial layer 2. Taking the bidirectional power device as a PMOS transistor as an example, the doping type of the first doped region 7a and the second doped region 7b is P-type, and the doping impurity is preferably B+; if the device is an NMOS transistor, then the first doped region 7a and the second doped region 7b are N-type, and the doping impurity is preferably As+ or P+.

[0035] Reference Figure 3g In step S6, an oxide layer 10 is grown on the sidewall of the trench 9 using a thermal oxidation process. The oxide layer 10 is SiO2. The barrier layer 8 is retained. The thickness d2 of the oxide layer 10 is less than the thickness d1 of the barrier layer 8. The thickness of d1 ranges from 100 Å to 8000 Å, and the thickness of d2 ranges from 50 Å to 1000 Å.

[0036] Reference Figure 3hSelective ion implantation is performed on the bottom of multiple trenches 9 to form channel regions 12 in the epitaxial layer 2. Channel regions 12 are in contact with both the first doped region 7a and the second doped region 7b. Channel regions 12 are used to precisely adjust the threshold voltage of the device. The implantation process parameters are as follows: energy range of 100–10000 keV, implantation dose of 1 × 10⁻⁶ keV. 12 ~1×10 15 cm -2 The subsequent annealing temperature is controlled between 600 and 1200 degrees Celsius. The conductivity type of the channel region 12 is opposite to that of the first doped region 7a and the second doped region 7b. Specifically, if the bidirectional power device is PMOS type, then the channel region 12 is N-type, and As+ or P+ is usually used as the dopant; if it is an NMOS type device, then the channel region 12 is P-type, and B+ is usually used for doping.

[0037] Reference Figure 3i A sacrificial oxide layer is grown on the surface of trench 9 using a thermal oxidation process. This sacrificial oxide layer is mainly used to repair surface defects that may be caused during trench etching, resulting in a trench surface with a good interface condition. Then, a wet etching process is used to selectively remove the sacrificial oxide layer. Under the same or adjusted thermal oxidation conditions, a gate oxide layer 13 with a thickness of T1 is grown on the surface of trench 9. The thickness of T1 ranges from 10 to 1000 Å. The thickness of the gate oxide layer 13 should be considered in conjunction with the threshold voltage required by the product, the depth of the trench in the device structure, the doping concentration of the doped region, and the junction depth.

[0038] Reference Figure 3j Step S7 includes using a deposition process to fill multiple trenches 9 with polysilicon 14. Undoped polysilicon can be deposited first, followed by the implantation of doped impurities. For example, in the case of a PMOS transistor as the bidirectional power device, the doping type of polysilicon 14 is P-type; in the case of an NMOS transistor as the bidirectional power device, the doping type of polysilicon 14 is N-type. (Refer to...) Figure 3k The polysilicon 14 outside the multiple trenches 9 is removed by chemical mechanical polishing. Then, the polysilicon 14 is etched back to form the first control gate 15 by dry etching. The distance between the upper surface of the first control gate 15 and the surface of the epitaxial layer 2 is h3. The depth h3 needs to be matched with the epitaxial layer, voltage resistance, doping, gate oxide thickness and other factors of the product. The range of depth h3 includes 0.1 to 10 μm.

[0039] Reference Figure 3l Step S8 includes forming a shielding dielectric layer 16 using a chemical vapor deposition process. The thickness of the shielding dielectric layer 16 is T2, and the range of T2 includes 50~2000 Å.

[0040] Reference Figure 3mStep S9 includes using a deposition process to fill multiple trenches 9 with the second polysilicon 17. This can be achieved by first depositing undoped polysilicon and then implanting doped impurities. For example, when the bidirectional power device is a PMOS transistor, the doping type of the second polysilicon 17 is P-type; when the bidirectional power device is an NMOS transistor, the doping type of the second polysilicon 17 is N-type. (Refer to...) Figure 3n The second polysilicon 17 outside the multiple trenches 9 is removed by chemical mechanical polishing. Then, the second polysilicon 17 is etched back to form the second control gate 18 by dry etching, so that the distance between the upper surface of the second control gate 18 and the silicon surface is h4. The depth h4 needs to be matched with the epitaxial growth, voltage withstand, doping, gate oxide thickness and other factors of the product. The range of depth h4 includes 0.1 to 5 μm.

[0041] Reference Figure 3o The preparation method of the present invention includes step S10, which involves forming an oxide layer 19 on the sidewall of the trench 9 and the surface of the epitaxial layer 2 using a chemical vapor deposition process. The thickness of the oxide layer 19 is T3, and the range of T3 includes 1~100 Å. Under the same oxidation growth conditions, T3>T2>T1.

[0042] Reference Figure 3p A deposition process is used to fill multiple trenches 9 with the third polysilicon 20. Undoped polysilicon can be deposited first, followed by the implantation of doped silicon. For example, when the bidirectional power device is a PMOS transistor, the doping type of the third polysilicon 20 is P-type; when the bidirectional power device is an NMOS transistor, the doping type of the third polysilicon 20 is N-type. (Refer to...) Figure 3q and Figure 3r The third polysilicon 20 outside the multiple trenches 9 is removed by chemical mechanical polishing. Based on the remaining polysilicon 21 on the surface of the epitaxial layer, a first contact region 22a is formed in the first doped region 7a and a second contact region 22b is formed in the second doped region 7b by implantation and diffusion using a photolithography mask. The implantation energy of the doping process is 10-100 keV and the implantation dose is 1E12-1E15 cm⁻¹. 2 .

[0043] The doping type of the first contact region 22a and the second contact region 22b is the same as that of the first doped region 7a and the second doped region 7b. For example, if the bidirectional power device is a PMOS, the doping type of the first contact region 22a and the second contact region 22b is P-type; if the bidirectional power device is an NMOS, the doping type of the first contact region 22a and the second contact region 22b is N-type. Among them, the doping of the P-type contact region is usually B+ / BF2+, and the doping of the N-type contact region is usually As+ or P+.

[0044] Reference Figure 3sStep S11 includes forming a cover dielectric layer 23 using a chemical vapor deposition process. The cover dielectric layer 23 is composed of SiO2. Subsequently, the surface of the deposited dielectric layer is planarized by a chemical mechanical polishing process to obtain a uniform and flat cover dielectric layer 23 with a predetermined thickness, providing a good foundation for the subsequent formation of contact holes and metal interconnect structures.

[0045] Reference Figure 3t Multiple contact holes are formed on the cover dielectric layer 23 using photolithography and etching processes. A conductive metal layer is deposited on the surface of the cover dielectric layer 23 and within the contact holes, covering and filling the contact holes. The conductive metal layer is then patterned again using photolithography and etching processes to form mutually isolated first contact electrodes 24, second contact electrodes 25, first substrate electrodes 26a, and second substrate electrodes 26b. The conductive metal layer can be selected from metals such as Ti, W, Al, Cu, Ni, or combinations thereof. The patterning process can be achieved using wet etching, plasma etching, or a combination thereof.

[0046] The first contact electrode 24 is connected to the first contact area 22a, and the second contact electrode 25 is connected to the second contact area 22b; the first substrate electrode 26a and the second substrate electrode 26b are connected to the P-type pillar or the N-type pillar 5. The first contact electrode 24 and the second contact electrode 25 serve as the source electrode and drain electrode of the bidirectional power device, respectively, and are electrically interchangeable. The spacing between the first substrate electrode 26a and the second substrate electrode 26b does not exceed 50 μm. By connecting the first substrate electrode 26a and the second substrate electrode 26b to the P-type pillar or the N-type pillar, the bulk resistance of the device is effectively reduced, thereby improving the overall electrical performance.

[0047] As electronic products become increasingly feature-rich, many consumer electronics, such as tablets and laptops, incorporate bidirectional charging and discharging capabilities. Industrial power supplies and server power supplies also feature hot-swapping and redundancy control. A single MOSFET as a switch is no longer sufficient to prevent backflow and meet the requirements of redundancy control. Therefore, two MOSFETs are connected in series using a common-source or common-drain configuration to achieve bidirectional blocking. This common-source or common-drain design is widely used in lithium-ion battery active balancing circuits, where its core function is bidirectional blocking.

[0048] The common-source shielded gate trench power semiconductor device of this invention, due to its excellent bidirectional blocking characteristics, is highly suitable for circuits requiring precise control of bidirectional energy flow. A typical application is the active balancing circuit of a lithium battery pack. (Refer to...) Figure 4Each battery cell is connected to a common bus (e.g., 24VBUS) via a bidirectional blocking MOS switch constructed using the device of this invention. When the voltage of a battery cell (e.g., Cell2) is higher than that of other battery cells (Cell1, Cell3 to Cell9), the control chip activates the corresponding PWM signal (e.g., PWM_2, PWM_3, and PWMB), while keeping other PWM signals (e.g., PWM_1, PWM_4 to PWM_10, and PWM_A) off. This allows battery cell Cell2 to discharge excess charge to 24VBUS through a boost circuit (bidirectional ISO DC-DC PMP23580). At this time, the bidirectional blocking MOS switches of other battery cells are off and therefore do not participate in charge transfer, achieving isolation between cells. Conversely, when the voltage of battery cell Cell2 is lower than that of other cells, the control chip also activates the corresponding PWM signals PWM2, PWM3, and PWMB. In this case, 24VBUS charges battery cell Cell2 through a buck circuit, while other cells remain isolated due to their respective bidirectional blocking MOS switches being off. Therefore, bidirectional blocking MOSFETs are widely used in battery active balancing circuit structures. A single device can replace two MOSFETs to achieve bidirectional blocking functionality, simplifying customer solution design and meeting high power density requirements.

[0049] The description and accompanying drawings provide typical embodiments of specific structures for specific implementations. Other modifications are possible based on the spirit of the invention. While the above-described invention presents preferred embodiments, these are not intended to be limiting.

[0050] For those skilled in the art, various changes and modifications will undoubtedly be apparent after reading the above description. Therefore, the appended claims should be construed as covering all changes and modifications that encompass the true intent and scope of the invention. Any and all equivalent scope and content within the scope of the claims should be considered to remain within the intent and scope of the invention.

Claims

1. A common-source shielded gate trench power semiconductor device, comprising: a substrate (1); an epitaxial layer (2) formed on the substrate (1); a plurality of alternating P-type pillars or N-type pillars (5) extending longitudinally from the surface of the epitaxial layer (2) to the upper surface of the substrate (1); a doped region (7) formed in the epitaxial layer (2); a plurality of trenches (9) formed in the doped region (7), the trenches (9) dividing the doped region (7) into alternating first doped region (7a) and second doped region (7b); and a gate oxide layer (13). The surface of the lower sidewall of the trench (9) is formed; the first control gate (15) is formed in the trench (9), located in the lower part of the trench (9), and in contact with the gate oxide layer (13); the shielding dielectric layer (16) is formed on the sidewall surface of the trench (9) above the first control gate (15); the second control gate (18) is formed in the trench (9), located above the first control gate (15), and in contact with the shielding dielectric layer (16); the first contact region (22a) is formed in the first doped region (7a); the second contact region (22b) is formed in the trench (9). In the second doped region (7b); a cover dielectric layer (23) is formed on the upper part of the epitaxial layer (2), and a plurality of contact holes are formed on the cover dielectric layer (23). The contact holes respectively form: a first contact electrode (24) that passes through the cover dielectric layer (23) and is connected to the first contact region (22a); a second contact electrode (25) that passes through the cover dielectric layer (23) and is connected to the second contact region (22b); a first substrate electrode (26a) and a second substrate electrode (26b) that pass through the cover dielectric layer (23) and are connected to the P-type pillar or N-type pillar (5).

2. The common-source shielded gate trench power semiconductor device according to claim 1, characterized in that, The epitaxial layer includes a channel region (12) formed at the bottom of the trench (9), the channel region (12) enclosing the bottom of the trench (9); the channel region (12) is in contact with the first doped region (7a) and the second doped region (7b); the doping type of the channel region (12) is the same as that of the epitaxial layer (2).

3. The common-source shielded gate trench power semiconductor device according to claim 1, characterized in that, The distance between the first substrate electrode (26a) and the second substrate electrode (26b) is 10 μm to 100 μm, and the depth of the plurality of trenches (9) is 0.1 μm to 50 μm; the substrate (1) is a silicon substrate, the thickness h1 of the epitaxial layer (2) is 1 μm to 100 μm, and the distance between adjacent P-type pillars or N-type pillars (5) is 10 μm to 100 μm.

4. The common-source shielded gate trench power semiconductor device according to claim 1, characterized in that, The distance h3 between the surface of the first control gate (15) and the surface of the epitaxial layer (2) is greater than the distance h4 between the surface of the second control gate (18) and the surface of the epitaxial layer (2); the distance h3 is 0.1 μm to 10 μm, and the distance h4 is 0.1 μm to 5 μm; the thickness T2 of the shielding dielectric layer (16) is 50 Å to 2000 Å; the thickness T1 of the gate oxide layer (13) is 10 Å to 1000 Å; including an oxide layer (19), formed on the upper part of the second control gate (18) along the sidewall surface of the trench (9); the thickness T1 of the gate oxide layer (13) is less than the thickness T2 of the shielding dielectric layer (16) and less than the thickness T3 of the oxide layer (19).

5. A method for fabricating a common-source shielded gate trench power semiconductor device, characterized in that, Includes the following steps: Step S1, provide a substrate (1); Step S2, form an epitaxial layer (2) on the substrate (1); Step S3, form alternating P-type pillars or N-type pillars (5) in the epitaxial layer (2) by multiple epitaxy and ion implantation, the P-type pillars or N-type pillars (5) extending longitudinally from the surface of the epitaxial layer (2) to the upper surface of the substrate (1); Step S4, form a doped region (7) in the epitaxial layer (2); Step S5, form a plurality of trenches (9) in the doped region (7), the trenches (9) dividing the doped region (7) into alternating first doped region (7a) and second doped region (7b); Step S6, grow a gate oxide layer (13) on the surface of the lower sidewall of the trench (9); Step S7, form a first control gate (15) in the trench (9), located at the lower part of the trench (9) and in contact with the gate oxide layer (13); Step S8, a shielding dielectric layer (16) is formed on the sidewall surface of the trench above the first control gate (15); Step S9, a second control gate (18) is formed above the first control gate (15) in the trench (9) and contacts the shielding dielectric layer (16); Step S10, a first contact region (22a) is formed in the first doped region (7a). A second contact region (22b) is formed in the second doped region (7b); in step S11, a cover dielectric layer (23) is formed on the upper part of the epitaxial layer (2), and a plurality of contact holes are formed on the cover dielectric layer (23). The contact holes respectively form: a first contact electrode (24), which passes through the cover dielectric layer (23) and is connected to the first contact region (22a); a second contact electrode (25), which passes through the cover dielectric layer (23) and is connected to the second contact region (22b); a first substrate electrode (26a) and a second substrate electrode (26b), which pass through the cover dielectric layer (23) and are connected to the P-type pillar or N-type pillar (5).

6. The preparation method according to claim 5, characterized in that, Step S3 includes depositing photoresist (3) on the epitaxial layer (2), photolithographically etching the window of the P-type pillar or N-type pillar (5), performing ion implantation from the window to form a floating island region (4), alternating multiple epitaxy and ion implantation along the longitudinal direction of the epitaxial layer to form multiple floating island regions (4), performing annealing activation, and the ions in the multiple floating island regions (4) diffuse and connect together longitudinally to form the P-type pillar or N-type pillar (5); Step S4 includes forming a SiO2 layer on the surface of the epitaxial layer (2) by thermal oxidation or chemical vapor deposition, and patterning the surface of the epitaxial layer (2) by photolithography and etching processes to form an opening in a specified area; using an ion implantation process with an implantation energy of 100-10000 keV and an implantation dose of 1×10 12 ~1×10 15 cm -2 Under the process conditions, the doped region (7) of P well or N well is formed in the epitaxial layer (2).

7. The preparation method according to claim 6, characterized in that, Step S5 includes removing the SiO2 layer on the surface using a wet etching process; then forming a barrier layer (8) on the surface of the epitaxial layer (2) by thermal oxidation or chemical vapor deposition; and then patterning the barrier layer (8) by photolithography and etching processes, selectively removing some areas to form the required opening. Using the barrier layer (8) as a mask, the exposed semiconductor region is etched to form multiple trenches (9). The trenches (9) divide the doped region (7) into alternating first doped region (7a) and second doped region (7b). In step S6, an oxide layer (10) is grown on the sidewall of the trench (9) using a thermal oxidation process. The thickness of the oxide layer (10) is less than the thickness of the barrier layer (8). Selective ion implantation is performed on the bottom of the multiple trenches (9) to form a channel region (12) in the epitaxial layer (2). The channel region (12) is in contact with both the first doped region (7a) and the second doped region (7b). A sacrificial oxide layer is grown on the surface of the trench (9) using a thermal oxidation process. Then, the sacrificial oxide layer is selectively removed using a wet etching process. A gate oxide layer (13) with a thickness of T1 is grown on the surface of the trench (9).

8. The preparation method according to claim 5, characterized in that, Step S7 includes: using a deposition process to fill the multiple trenches (9) with polysilicon (14); using a chemical mechanical polishing process to remove the polysilicon (14) outside the multiple trenches (9); and then using a dry etching process to etch back the polysilicon (14) to form the first control gate (15), wherein the upper surface of the first control gate (15) is h3 away from the surface of the epitaxial layer (2); Step S9 The process includes using a deposition process to fill multiple trenches (9) with a second polysilicon (17), using a chemical mechanical polishing process to remove the second polysilicon (17) outside the multiple trenches (9), and then using a dry etching process to etch back the second polysilicon (17) to form the second control gate (18), such that the upper surface of the second control gate (18) is at a distance of h4 from the silicon surface.

9. The preparation method according to claim 5, characterized in that, Step S10 includes forming an oxide layer (19) on the sidewall of the trench (9) and the surface of the epitaxial layer (2) using a chemical vapor deposition process, wherein the thickness of the oxide layer (19) is T3; filling the trenches (9) with a third polysilicon (20) using a deposition process; removing the third polysilicon (20) outside the trenches (9) using a chemical mechanical polishing process; forming a first contact region (22a) in the first doped region (7a) and a second contact region (22b) in the second doped region (7b) using a photolithography mask by implantation and diffusion.

10. The preparation method according to claim 5, characterized in that, Step S11 includes forming a cover dielectric layer (23) using a chemical vapor deposition process, forming multiple contact holes on the cover dielectric layer (23) using photolithography and etching processes, depositing a metal conductive layer on the surface of the cover dielectric layer (23) and in the contact holes, the metal conductive layer covering and filling the contact holes, and patterning the metal conductive layer again using photolithography and etching processes to form a first contact electrode (24), a second contact electrode (25), a first substrate electrode (26a), and a second substrate electrode (26b) that are isolated from each other. The first contact electrode (24) and the second contact electrode (25) serve as the source electrode and the drain electrode, respectively, and the distance between the first substrate electrode (26a) and the second substrate electrode (26b) does not exceed 50 μm.

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