Semiconductor device and electronic apparatus

Abstract

The invention relates to the technical field of power devices, and discloses a semiconductor device and electronic equipment, and the semiconductor device comprises a packaging body, a lead frame, a semiconductor chip and a connecting clamping piece, the lead frame comprises a base island and a first pin, and the first pin is electrically connected with an external circuit; a first electrode on the first surface of the semiconductor chip is fixed on the surface of the base island through a first bonding layer and is electrically connected with the first pin through the base island; the connecting clamping piece is arranged on the second surface of the semiconductor chip through the second bonding layer and electrically connected with the electrode of the second surface, and at least part of the connecting clamping piece extends out of the edge of the lead frame to form a second pin electrically connected with an external circuit. The part of the surface, away from the semiconductor chip, of the base island is not wrapped by the packaging body and is exposed out of the packaging body, when the semiconductor device is fixed on the device bearing plate, the exposed surface of the base island is located on the side, away from the device bearing plate, of the semiconductor device, and the heat dissipation efficiency of the chip to the external environment is remarkably improved.

Description

Technical Field

[0001] This application relates to the field of power device technology, and more particularly to a semiconductor device electronic device. Background Technology

[0002] With the rapid development of power electronics technology, power devices are increasingly widely used in industrial control, new energy power generation, electric vehicles, and other fields. To meet the demands for high efficiency, high power density, and miniaturization, the operating current and switching frequency of power devices are constantly increasing, leading to a significant increase in heat generation. Traditional power devices typically employ a leadframe structure, with the leadframe located at the bottom of the device. Heat dissipation occurs through the leadframe, pins, and pads on the circuit board. This heat dissipation path is limited by material thermal resistance and contact area, resulting in low heat conduction efficiency. Especially in high-power, high-heat-generating applications, this can easily cause the device junction temperature to rise, affecting the device's reliability and lifespan. Summary of the Invention

[0003] In view of this, the present application provides a semiconductor device and electronic device that can effectively solve the problem that in the prior art, the lead frame is designed at the bottom of the device, and heat is dissipated through the lead frame, pins and pads on the circuit board, which can easily cause the junction temperature of the device to rise, affecting the reliability and service life of the device.

[0004] In a first aspect, embodiments of this application provide a semiconductor device, including: a package body and a lead frame, a semiconductor chip and a connector clip stacked together; The lead frame includes a base island and a first pin, the first pin being used for electrical connection with an external circuit; The semiconductor chip has a first surface and a second surface disposed opposite to each other. A first electrode on the first surface is fixed to the surface of the base island through a first bonding layer and is electrically connected to the first pin through the base island. The connecting clip is disposed on the second surface of the semiconductor chip through the second bonding layer, electrically connected to the electrodes of the second surface, and at least partially extends beyond the edge of the lead frame to form a second pin for electrical connection with the external circuit. The package encapsulates the semiconductor chip and part of the connector clips, and at least part of the base island facing away from the surface of the semiconductor chip is not encapsulated by the package and is exposed outside the package. Wherein, when the semiconductor device is fixed on the device carrier plate, the exposed base island surface is located on the side of the semiconductor device away from the device carrier plate.

[0005] In some embodiments, the connecting clip includes a first metal clip and a second metal clip that are isolated from each other; The first metal clip is electrically connected to the second electrode on the second surface of the semiconductor chip, and the second metal clip is electrically connected to the third electrode on the second surface.

[0006] In some embodiments, the first pin extends from the base island along the direction of the semiconductor chip and is exposed outside the package.

[0007] In some embodiments, the second pin is a gull-wing pin.

[0008] In some embodiments, the solder surfaces of the second pin and the first pin are coplanar.

[0009] In some embodiments, the surfaces of the first metal clip and / or the second metal clip facing away from the semiconductor chip have a recessed structure.

[0010] In some embodiments, the extension portion of the first metal clip and / or the second metal clip is provided with a trapezoidal groove.

[0011] In some embodiments, the lead frame has a groove structure on the surface facing the semiconductor chip.

[0012] In some embodiments, the groove structure includes a first groove disposed on the edge of the base island and a second groove disposed on the first pin.

[0013] Secondly, embodiments of this application provide an electronic device, which includes at least one semiconductor device as described in the first aspect above.

[0014] The embodiments of this application have the following beneficial effects: The semiconductor device of this application includes a package and a stacked lead frame, a semiconductor chip, and a connector clip. The lead frame includes a base island and a first pin, the first pin being used for electrical connection with an external circuit. The semiconductor chip has a first surface and a second surface disposed opposite to each other. A first electrode of the first surface is fixed to the surface of the base island through a first bonding layer and is electrically connected to the first pin through the base island. The connector clip is disposed on the second surface of the semiconductor chip through a second bonding layer, is electrically connected to the electrode of the second surface, and extends at least partially beyond the edge of the lead frame to form a second pin for electrical connection with an external circuit. The connector clip not only serves as a conductive path but also extends at least partially beyond the edge of the lead frame to directly form a second pin for external connection. The package encloses the semiconductor chip and part of the connector clip. At least a portion of the base island facing away from the semiconductor chip is not enclosed by the package and is exposed outside the package. When the semiconductor device is fixed on a device carrier plate, the exposed base island surface is located on the side of the semiconductor device away from the device carrier plate.

[0015] The semiconductor device of this application exposes at least a portion of the base island of the lead frame away from the surface of the semiconductor chip outside the package. After the semiconductor device is mounted on the device carrier plate, this exposed surface is located on the side away from the carrier plate, forming the top surface of the device, thereby achieving direct top heat dissipation. Since this top surface is not covered by the package, it can be directly exposed to the external environment or connected to a heat dissipation structure, allowing the heat generated during chip operation to be efficiently conducted upwards and dissipated via the base island. This avoids the problem of increased thermal resistance caused by circuit board obstruction in traditional bottom heat dissipation paths, significantly improving heat dissipation efficiency. Simultaneously, the connecting clip directly adheres to the second surface of the semiconductor chip and extends to form a second pin, eliminating the need for bonding wires or additional pin structures. This not only simplifies the process flow but also significantly reduces parasitic inductance and contact resistance, improving current transmission capability and high-frequency response performance. Furthermore, the connecting clip itself also constitutes part of the conductive path and heat dissipation path, further enhancing the heat conduction capability from the top of the chip outwards. The overall structure realizes the potential for double-sided heat dissipation while improving power density and thermal stability, which is beneficial for device miniaturization and high-reliability applications. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram of the structure of a semiconductor device according to an embodiment of this application is shown; Figure 2 A partial structural schematic diagram of a semiconductor device according to an embodiment of this application is shown; Figure 3 A partial structural side view of a semiconductor device according to an embodiment of this application is shown; Figure 4 A schematic diagram of the lead frame structure according to an embodiment of this application is shown; Figure 5 A schematic diagram of the structure of the connecting clip according to an embodiment of this application is shown; Figure 6 A schematic flowchart of a semiconductor device packaging method according to an embodiment of this application is shown.

[0018] Explanation of key component symbols: 10: Lead frame; 11: Base island; 111: First groove; 12: First pin; 121: Second groove; 20: Semiconductor chip; 30: Connecting clip; 31: First metal clip; 32: Second metal clip; 321: Second pin; 33: Recessed structure; 34: Trapezoidal groove; 40: Package; 50: First bonding layer; 60: Second bonding layer. Detailed Implementation

[0019] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0020] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0021] In the following text, the terms "comprising," "having," and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more combinations thereof. Furthermore, the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0022] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be construed as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.

[0023] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0024] With the exponential growth in AI computing power demand, global hyperscale data centers are placing higher demands on the energy efficiency and power density of power supply systems. For power semiconductors, the key breakthrough lies in achieving synergistic optimization of energy efficiency and thermal management capabilities, reducing device footprint and accelerating power density iteration, while improving system-level reliability in the face of more complex and demanding application environments.

[0025] The 5×6 mm² ultra-compact package is a leadless surface-mount package designed for low- to medium-voltage power devices, delivering high electrical performance within a limited package size. This package reduces PCB footprint by 62%, supports IBC module power densities exceeding 200 W / in³, meets the high integration requirements of AI servers for 48V-12V conversion layers, and saves 38% of wiring space for GPU cluster power supply. It is particularly suitable for applications requiring high power density and high reliability.

[0026] In terms of packaging structure, existing technologies typically use a combination of wires or ribbon connectors and copper clips to connect the chip electrodes to the leadframe pins. This multi-level interconnection method introduces additional on-resistance and parasitic inductance, leading to increased device switching losses and affecting overall energy efficiency.

[0027] In terms of heat dissipation performance, traditional structures rely on the lead frame 10, pins, and PCB pads at the bottom of the device for heat dissipation, resulting in concentrated heat being conducted from one side of the bottom. High-power, high-heat-generating devices are difficult to cool effectively under this unidirectional heat dissipation mode, which may lead to localized overheating and limit the device's ability to operate continuously under high load conditions.

[0028] In terms of reliability applications, the flat pin structure lacks a stress buffering mechanism, making it prone to solder joint fatigue under temperature cycling or mechanical vibration environments, resulting in decreased board-level connection reliability. This type of structure is unsuitable for harsh environments with high vibration, such as automotive electronics, and poses a risk of long-term operational failure.

[0029] In terms of production efficiency, existing processes require step-by-step assembly of strip-and-wire combinations, copper clip-and-wire combinations, or separate installation of gate and source copper clips. This complex process involves numerous steps, reducing production cycle time and increasing the risk of unstable process control, which is detrimental to large-scale, efficient manufacturing.

[0030] In terms of manufacturing costs, as power density increases, the chip size within a single device continues to grow. To accommodate larger chips, the stage area of ​​the lead frame needs to be expanded accordingly. Traditional stamping processes are limited by forming precision, often requiring the use of more expensive etching processes to achieve stage enlargement, resulting in a significant increase in material and processing costs.

[0031] This application addresses the aforementioned problems of existing 5×6 mm² power devices by providing a semiconductor device and electronic device. By optimizing the design of the lead frame 10 and the layout of the connecting clips 30, direct interconnection at the top of the chip is achieved, reducing intermediate connection links, thereby lowering on-resistance and parasitic inductance, effectively reducing switching losses, and improving electrical performance.

[0032] By exposing at least a portion of the surface of the base island 11 of the lead frame 10 away from the semiconductor chip 20 outside the package 40, after the semiconductor device is mounted on the device carrier board, this exposed surface is located on the side away from the carrier board, thus forming the top surface of the device, thereby achieving direct heat dissipation from the top. Since this top surface is not covered by the package, it can be directly exposed to the external environment or connected to a heat dissipation structure, allowing the heat generated during chip operation to be efficiently conducted upwards and dissipated via the base island. This avoids the problem of increased thermal resistance caused by circuit board obstruction in traditional bottom heat dissipation paths, significantly improving heat dissipation efficiency. This application not only reduces packaging costs at the manufacturing end but also is compatible with existing PCB layout designs, eliminating the need for users to redesign the board and reducing redesign costs during device replacement, facilitating rapid application. It is understood that the technical solution of this application is not limited to 5×6 mm² power devices but can also be extended to other power package sizes, demonstrating good versatility and industrialization prospects.

[0033] The semiconductor device will be described below with reference to some specific embodiments.

[0034] Figure 1 A schematic diagram of the structure of a semiconductor device according to an embodiment of this application is shown. Figure 2 A partial structural schematic diagram of a semiconductor device according to an embodiment of this application is shown. Figure 3 A partial side view of a semiconductor device according to an embodiment of this application is shown. Exemplarily, the semiconductor device includes a package 40 and a lead frame 10, a semiconductor chip 20, and a connecting clip 30 stacked together.

[0035] Exemplarily, the semiconductor chip 20 has a first surface and a second surface arranged opposite to each other. This semiconductor chip 20 is a power MOSFET chip, including three electrodes: a source, a gate, and a drain. The drain, as the first electrode, is located on the first surface, i.e., the bottom surface of the chip, while the source and gate are located on the second surface, i.e., the top surface of the chip, forming a double-sided electrode distribution structure. Optionally, a similar structure can be applied as long as the design logic of double-sided electrode distribution, top clip lead-out, bottom coplanar pins, and top heat dissipation channel is met. Therefore, this solution has good scalability and platform application potential, suitable for the advanced packaging needs of silicon-based MOSFETs, IGBTs, and wide-bandgap semiconductors such as SiC and GaN devices.

[0036] like Figure 4As shown, the lead frame 10 includes a base island 11 and a first pin 12, which is used for electrical connection with an external circuit. The lead frame 10 serves as the supporting structure for the semiconductor device, undertaking electrical conduction, mechanical load-bearing, and some heat dissipation functions. Exemplarily, the lead frame 10 is made of copper, which possesses excellent electrical and thermal conductivity.

[0037] The first pin 12 extends from the base island 11 along the direction of the semiconductor chip 20, i.e., perpendicular to the chip surface, and is exposed on the bottom surface of the semiconductor device. It is used for soldering to pads on the printed circuit board. This structure inherits the advantages of surface mount devices (SMD), is suitable for automated placement processes, and improves assembly efficiency. Since the first pin 12 and the base island 11 are integrally constructed from the same metal body, a low-impedance path can be formed without additional soldering or wire bonding, significantly reducing parasitic parameters introduced by traditional interconnect methods.

[0038] The first electrode on the first surface is fixed to the surface of the base island 11 via the first bonding layer 50, achieving both electrical conduction and mechanical support. The first bonding layer 50 is solder paste, and the drain of the semiconductor chip 20 is fixed to the surface of the base island 11 via the solder paste. The thickness of the solder paste can be controlled within 50 micrometers to ensure that the solder layer has good filling and thermal conductivity. The base island 11 serves as the conduction path for the drain current, directly transferring the current from the chip to the first pin 12, eliminating intermediate links such as gold wires or strip connectors, thereby significantly reducing on-resistance and parasitic inductance. This short and wide current path helps suppress voltage oscillations and electromagnetic interference during high-frequency switching, improving the stability and energy efficiency of the device under high-frequency operating conditions, making it particularly suitable for scenarios with high dynamic response requirements, such as AI server power modules.

[0039] The lead frame 10 has a groove structure on its surface facing the semiconductor chip 20 to enhance packaging reliability. This groove structure can be flexibly designed according to actual needs. Exemplarily, the groove structure includes a first groove 111 located at the edge of the base island 11 and a second groove 121 located on the surface of the first pin 12. The first groove 111 is a strip-shaped groove arranged around the base island 11, acting as a stop groove to prevent solder paste from overflowing to the outside of the base island 11 and contaminating the back surface area during placement, ensuring the cleanliness and solderability of the subsequent bottom heat dissipation path; it also locks in the encapsulating resin, making the encapsulating resin and lead frame 10 more firmly bonded, preventing delamination that could cause device failure.

[0040] The second groove 121 is a circular groove located on the surface of the first pin 12. During reflow soldering, it can accommodate more solder, enhancing the bonding strength of the solder joint and improving the connection reliability of the device under temperature cycling and mechanical vibration environments. This design is particularly suitable for high-vibration applications such as automotive electronics, effectively preventing solder joint detachment or fatigue cracking.

[0041] The connector clip 30 is disposed on the second surface of the semiconductor chip 20 through the second bonding layer 60, electrically connected to the source and gate electrodes of the second surface, and at least partially extends beyond the edge of the lead frame 10 to form a second pin 321 for electrical connection with external circuitry. This connector clip 30 not only serves as a conductive path but also extends the structure, eliminating the need for traditional bonding wires or additional pin structures, further reducing lead inductance and contact resistance, and minimizing switching losses.

[0042] Exemplary, such as Figure 5 As shown, the connecting clip 30 includes a first metal clip 31 and a second metal clip 32 that are isolated from each other. The first metal clip 31 is electrically connected to the gate electrode of the second surface of the semiconductor chip 20, and the second metal clip 32 is electrically connected to the source electrode of the third surface. The first metal clip 31 is the gate metal clip, and the second metal clip 32 is the source metal clip. The metal clip material can be any conductive metal; copper clips are exemplary because they have low resistivity and good processing performance, making them suitable for mass production. It is understood that the second pin 321 includes a gate pin and a source pin, with the extended portion of the first metal clip 31 being the gate pin and the extended portion of the second metal clip 32 being the source pin.

[0043] The first metal clip 31, or the second metal clip 32, or the surface of the first metal clip 31 and the second metal clip 32 facing away from the semiconductor chip 20, is provided with a recessed structure 33. Exemplarily, both the first metal clip 31 and the second metal clip 32 are provided with a recessed structure 33. During the molding process, the recessed structure 33 can be fully filled with the molding resin, forming a mechanical interlocking effect, enhancing the interfacial bonding force, and preventing delamination failure caused by moisture intrusion and temperature cycling. Simultaneously, the extended portions of the first metal clip 31 and the second metal clip 32 are provided with trapezoidal grooves 34, further locking the molding resin, improving the overall encapsulation strength, and meeting the stringent long-term reliability requirements of automotive applications.

[0044] The extension of the connecting clip 30 bends in the direction of the extension of the first pin 12, forming a second pin 321 with an arc transition or a right-angle transition, i.e., a gull-wing pin structure. This second pin 321 is coplanar with the first pin 12, both exposed on the bottom surface of the package, and can be soldered to PCB pads simultaneously. The gull-wing structure has a certain degree of elastic deformation capability, which can absorb stress caused by thermal expansion and contraction and mechanical vibration, enhancing the stability of board-level connections and improving the reliability of devices under complex operating conditions.

[0045] Understandably, the package 40 is a plastic-encapsulated structure formed by integrally molding the lead frame 10, semiconductor chip 20, and connecting clip 30 using molding resin, exposing only the back side of the base island 11, the first pin 12, and the second pin 321. The plastic-encapsulated structure at least encapsulates the semiconductor chip 20 and part of the connecting clip 30, wherein at least part of the surface of the base island 11 facing away from the semiconductor chip 20 is not encapsulated by the plastic-encapsulated structure and is exposed outside the plastic-encapsulated structure. When the semiconductor device is fixed on the device carrier plate, the exposed surface of the base island 11 is located on the side of the semiconductor device away from the device carrier plate, thus forming the top surface of the device, thereby achieving direct heat dissipation from the top. Understandably, the device carrier plate is a platform for supporting the semiconductor device. Exemplarily, the device carrier plate is a circuit board, and when the semiconductor device is soldered onto the circuit board, the base island 11 is positioned away from the surface of the semiconductor chip and away from the circuit board.

[0046] This application revolutionizes the traditional heat transfer path through structural innovation. Unlike conventional semiconductor devices that place the heat dissipation surface on the bottom and conduct heat through the circuit board via pads, this solution flips the back of the base island 11, which originally faced the circuit board, upwards, exposing it directly to the top of the device and allowing for close contact with an external heat sink. The heat generated by the chip during operation is dissipated upwards from the chip via the base island 11, no longer relying on the circuit board for heat dissipation. This effectively avoids the thermal bottleneck problem caused by the low thermal conductivity of the circuit board dielectric material, achieving functional decoupling between the signal path and the heat dissipation path.

[0047] Based on this, this application constructs a dual-channel heat dissipation path through the collaborative design of the base island 11 and the connecting clip 30: on the one hand, most of the heat generated by the semiconductor chip 20 is vertically conducted from the base island 11 to the top of the device through a low thermal resistance path, directly coupling with the external heat sink to achieve efficient top surface heat dissipation; on the other hand, some heat is laterally conducted to its exposed area through the connecting clip 30, and diffuses to the metal wiring or ground plane on the circuit board via the soldering area of ​​the second pin 321, forming an auxiliary heat dissipation branch. This dual-path design not only improves the overall heat conduction capability, but also helps to balance the internal thermal stress distribution of the device, reduce the formation of local hot spots, and improve the thermal stability and reliability of long-term operation.

[0048] Furthermore, the exposed top island structure supports various advanced cooling methods, including natural convection cooling, forced air cooling, liquid cooling, and phase change cooling, to meet the application requirements of different power levels. For example, in AI servers, a small air-cooled heatsink can be installed on top of the device or integrated into a liquid cooling plate system to achieve efficient thermal management and ensure the continuous high-load operation of the GPU cluster.

[0049] Furthermore, by flipping the main pins to the bottom and connecting them to the PCB, this design inherits the high-density mounting advantages of surface mount devices. It is compatible with existing automated surface mount processes and PCB layouts, allowing for system upgrades without additional modifications. Experimental data shows that, compared to traditional bottom-heat-dissipating semiconductor devices, this application reduces the junction-to-environment thermal resistance by approximately 15%, and the overall thermal impedance by up to 50%, significantly improving power handling capabilities and transient thermal response performance.

[0050] In summary, this application achieves more efficient thermal management, lower electrical losses, and stronger environmental adaptability through structural reconfiguration without increasing the package size, providing an optimized packaging solution for high power density and high reliability semiconductor devices.

[0051] Figure 6 A schematic flowchart of a semiconductor device packaging method according to an embodiment of this application is shown. Exemplarily, the packaging method includes S101-S104: S101: Provide a lead frame 10, the lead frame 10 including a base island 11 and a first pin 12, the first pin 12 being used for electrical connection with an external circuit.

[0052] Exemplary of this design, the lead frame 10 is made of copper and formed in one piece using a stamping process, offering advantages such as fast production cycle, high material utilization, and low processing costs. Compared to etching processes, which require complex masking and etching steps, the stamping process eliminates the need for wet processing, uses simpler materials, is environmentally friendly, and is suitable for large-scale mass production.

[0053] The stamped lead frame 10 has a strip-shaped groove on the edge of the base island 11 and a circular groove on the surface of the first pin 12. These structural features are formed during the manufacturing stage and require no further processing.

[0054] S102: Provide a semiconductor chip 20, which includes a first surface and a second surface disposed opposite to each other. A first electrode of the first surface is mounted on the surface of the base island 11 using a first bonding layer 50, so that the first electrode is electrically connected to the first pin 12 through the base island 11.

[0055] The first electrode is the drain, i.e., the power input terminal, and is mounted on the surface of the base island 11 of the lead frame 10 via a first bonding layer 50. This first bonding layer 50 is solder paste, applied to the base island 11 using an SMT printing process. The solder paste thickness is controlled at 50 micrometers to ensure good wettability, filling properties, and thermal stability of the solder layer. Subsequently, the semiconductor chip 20 is precisely mounted onto the solder paste-coated base island 11, and after alignment, proceeds to the next process.

[0056] S103: Provide a connecting clip 30, which extends at least partially beyond the edge of the lead frame 10 to form a second pin 321 for electrical connection with an external circuit.

[0057] The connecting clip 30 includes a source copper clip and a gate copper clip, which are electrically isolated from each other and correspond to the source and gate of the semiconductor chip 20, respectively. The extended portion of the clip forms an exposed pin, which can achieve external connection without additional pin structure or bonding wire, simplifying the packaging complexity.

[0058] S104: The connecting clip 30 is mounted on the corresponding electrode of the second surface of the semiconductor chip 20 using the second bonding layer 60.

[0059] The specific operation involves coating solder paste onto the source and gate surfaces of the semiconductor chip 20, and then simultaneously mounting the source copper clips and gate copper clips to their corresponding positions. Subsequently, a reflow soldering process is used to heat the solder paste, causing it to melt and solidify simultaneously, thus completing the dual electrical connection between the chip and the base island 11, and between the chip and the copper clips.

[0060] This integrated reflow soldering process achieves multi-point synchronous interconnection, replacing the complex traditional step-by-step process of combining strips with conductors or individually binding copper clips. This not only reduces the number of processes but also lowers the risk of alignment deviations and poor contact caused by multiple operations. Compared to existing technologies, this method can increase production efficiency by at least two times, which is beneficial for improving production line throughput and yield.

[0061] After the electrical connection is completed, plastic resin is used for molding and encapsulation to form a protective package 40. During the molding process, the molding compound fully fills the recessed structure 33 of the source and gate copper clips and the trapezoidal groove 34 of the extended portion, forming a mechanical anchoring effect, enhancing the interface bonding strength, preventing delamination failure caused by moisture penetration and temperature cycling, and meeting the long-term reliability requirements of automotive applications.

[0062] Subsequently, the exposed pins and back area of ​​the lead frame 10 can be electroplated. The plating material is pure tin, which complies with RoHS environmental standards and avoids lead pollution. The main function of the tin plating layer is to protect the underlying copper conductor from oxidation and corrosion, preventing functional failure due to open circuits. At the same time, as an excellent conductive medium, the tin layer can reduce contact resistance, improve signal transmission efficiency, and quickly fuse with solder during the subsequent THD process of plug-in installation, reducing the probability of soldering defects such as cold solder joints and poor solder joints.

[0063] Finally, product information, such as product model, production date, and batch number, is laser-marked on the back of the lead frame 10 to achieve unique identification and traceability management. This marking method is non-contact, highly precise, and highly permanent, making it suitable for integration into automated production lines and ensuring product quality control.

[0064] This packaging method has a clear overall logic, with each step interconnected, forming a complete causal chain from front-end material preparation to mid-stage mounting and soldering, and finally to back-end molding and electroplating. Through structural innovation and process integration, it achieves a balance between high performance, high reliability, and low-cost manufacturing. For example, in AI server power modules, this method supports efficient 48V to 12V conversion, meeting the high power density and energy efficiency requirements of GPU clusters, while remaining compatible with existing PCB layouts, eliminating the need for motherboard redesign and shortening product iteration cycles.

[0065] It is understood that the options in the above embodiments also apply to this embodiment, so they will not be described again here.

[0066] This application also provides an electronic device, exemplary of which includes the aforementioned semiconductor device.

[0067] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that, in alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0068] In addition, the functional modules or units in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0069] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application.

[0070] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A semiconductor device, characterized in that, include: The package and the stacked lead frame, semiconductor chip and connector clips; The lead frame includes a base island and a first pin, the first pin being used for electrical connection with an external circuit; The semiconductor chip has a first surface and a second surface disposed opposite to each other. A first electrode on the first surface is fixed to the surface of the base island through a first bonding layer and is electrically connected to the first pin through the base island. The connecting clip is disposed on the second surface of the semiconductor chip through the second bonding layer, electrically connected to the electrodes of the second surface, and at least partially extends beyond the edge of the lead frame to form a second pin for electrical connection with the external circuit. The package encapsulates the semiconductor chip and part of the connector clips, and at least part of the base island facing away from the surface of the semiconductor chip is not encapsulated by the package and is exposed outside the package. Wherein, when the semiconductor device is fixed on the device carrier plate, the exposed base island surface is located on the side of the semiconductor device away from the device carrier plate.

2. The semiconductor device according to claim 1, characterized in that, The connecting clip includes a first metal clip and a second metal clip that are isolated from each other; The first metal clip is electrically connected to the second electrode on the second surface of the semiconductor chip, and the second metal clip is electrically connected to the third electrode on the second surface.

3. The semiconductor device according to claim 1, characterized in that, The first pin extends from the base island along the direction of the semiconductor chip and is exposed outside the package.

4. The semiconductor device according to claim 1, characterized in that, The second pin is a gull-wing shaped pin.

5. The semiconductor device according to claim 1, characterized in that, The welding surfaces of the second pin and the first pin are coplanar.

6. The semiconductor device according to claim 2, characterized in that, The surfaces of the first metal clip and / or the second metal clip facing away from the semiconductor chip have a recessed structure.

7. The semiconductor device according to claim 2, characterized in that, The extension portion of the first metal clip and / or the second metal clip is provided with a trapezoidal groove.

8. The semiconductor device according to claim 1, characterized in that, The lead frame has a groove structure on its surface facing the semiconductor chip.

9. The semiconductor device according to claim 8, characterized in that, The groove structure includes a first groove disposed on the edge of the base island and a second groove disposed on the first pin.

10. An electronic device, characterized in that, The electronic device includes a semiconductor device as described in any one of claims 1-8.

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