Tracking instruction processing using opcode matching in processor-based device

Abstract

Tracking instruction processing using opcode matching in a processor-based device is disclosed herein. In some aspects, a processor-based device provides a processor device that includes an opcode match register, an accumulator register, and instruction processing circuitry. The instruction processing circuitry is configured to determine that an instruction of the plurality of instructions matches an opcode value stored in the opcode match register. The instruction processing circuitry is further configured to, in response to determining that the instruction matches the opcode value stored in the opcode match register, modify the value stored in the accumulator register without stopping or modifying the program control flow.

Description

[0001] Priority application

[0002] This application claims priority to U.S. Patent Application Serial No. 18 / 473,414, filed September 25, 2023, entitled “TRACKING INSTRUCTION HANDLINGUSING OPCODE MATCHING IN PROCESSOR-BASED DEVICES”, the entire contents of which are incorporated herein by reference. background

[0003] I. Technical Field

[0004] The techniques disclosed herein generally relate to debugging and profiling applications executed on processor-based devices, and particularly to opcode matching and trap functionality provided by processor-based devices.

[0005] II. Background Technology

[0006] Microprocessors (also referred to herein as “processors”) perform computational tasks for a wide variety of applications. To assist with application debugging, some processor devices provide a feature called “opcode matching and traps,” which allows debugging software to obtain additional information about the application being executed. The opcode matching and traps feature allows, for example, specifying an opcode corresponding to a specific instruction or an opcode mask corresponding to a set of instructions by writing a corresponding value to an opcode matching register and optionally to an opcode mask register. When an instruction that matches the opcode itself (or an opcode masked using an opcode mask) is encountered while the application is executing, the processor device can perform special processing for the instruction based on the value stored in the processor’s opcode matching control register. For example, the value stored in the opcode matching control register can cause the processor device to halt application execution and enter debug mode, or it can cause the processor device to transfer program control to an exception handler.

[0007] While standard opcode matching and trap functionality provide access to detailed data on the executing application, such functionality is often more useful in the context of debugging software than in analyzing or measuring application performance. Therefore, it may be desirable to provide access to additional data to facilitate application profiling and measurement while minimizing any negative impact on processor performance. Summary of the Invention

[0008] The aspects disclosed in the detailed description include using opcode matching to track instruction processing in processor-based devices. Related apparatus and methods are also disclosed. In this regard, in some exemplary aspects disclosed herein, the processor device includes instruction processing circuitry for processing (i.e., fetching, decoding, executing, and retiring) a plurality of instructions. The processor device also includes an opcode matching register and an accumulator register. The opcode matching register stores an opcode value, against which the instruction processing circuitry compares each of a plurality of instructions. If an instruction matches the opcode value stored in the opcode matching register, the instruction processing circuitry is configured to modify the value stored in the accumulator register (e.g., by incrementing or decrementing the value) without halting or modifying the program control flow. In this way, the opcode matching register and the accumulator register provide access to data that enables the execution of an application to be profiled and measured with minimal impact on processor performance.

[0009] Some aspects may provide that determining whether an instruction matches the opcode value stored in the opcode match register includes: determining whether the opcode of the instruction matches the opcode value stored in the opcode match register. In some such aspects, the processor device may also provide an opcode mask register that stores opcode masks. Such aspects may provide that determining whether the opcode of an instruction matches the opcode value stored in the opcode match register includes: determining whether the opcode of an instruction masked by the opcode mask matches the opcode value when the opcode mask is used. This enables instruction matching to be performed on multiple sets of instructions having opcodes that match the opcode mask.

[0010] Depending on some aspects of the processor device's operation in "instruction count mode," the value stored in the accumulator register represents the instruction occurrence count. In this aspect, the instruction processing circuitry modifies the value stored in the accumulator register to a value of one (1) (i.e., by incrementing or decrementing the value by one (1)). Some aspects of the processor device's operation in "total processing time mode" may provide that the value stored in the accumulator register represents the total time spent processing the occurrence of instructions. In this aspect, the instruction processing circuitry modifies the value stored in the accumulator register to a time value indicating the time interval between the occurrence of instruction fetch and end events (e.g., as a non-limiting example, a deactivation instruction, determining whether an instruction matches an opcode value, and / or marking an instruction as a result of the determination). In some aspects, the processor device may be configured to support both the instruction count mode and the total processing time mode described above. In this aspect, a mode indicator indicating either the instruction count mode or the total processing time mode may be provided to indicate how the instruction processing circuitry should modify the accumulator register.

[0011] Further aspects include: the processor device also includes an opcode matching control register that allows the functionality described above to be selectively enabled and disabled by an execution software process (such as an operating system (OS) or supermanager), which writes an enable value or a disable value to the opcode matching control register, respectively. According to such aspects, instruction processing circuitry can determine that an instruction matches an opcode value stored in the opcode matching register in response to determining that the value of the opcode matching control register is an enable value. In some aspects, the execution software process can also enable and disable the functionality described above depending on the current software context. Thus, the execution software process can set the value of the opcode matching control register to an enable value when executing in a first software context, and subsequently set the value of the opcode matching control register to a disable value when executing in a second software context (i.e., after a context switch). Further aspects include: the execution software process can read a value stored in an accumulator register, and / or can reset the value stored in the accumulator register (e.g., reset to a value of zero (0) or some other predefined reset value).

[0012] In another aspect, a processor device is disclosed. The processor device includes an opcode matching register and an accumulator register, as well as instruction processing circuitry. The instruction processing circuitry is configured to determine that one of a plurality of instructions matches an opcode value stored in the opcode matching register. The instruction processing circuitry is further configured to modify a value stored in the accumulator register in response to determining that an instruction matches an opcode value stored in the opcode matching register, without halting or modifying program control flow.

[0013] In another aspect, a processor device is disclosed. The processor device includes means for determining that an instruction among a plurality of instructions matches an opcode value stored in an opcode matching register of the processor device. The processor device also includes means for modifying a value stored in an accumulator register of the processor device in response to determining that the instruction matches the opcode value stored in the opcode matching register without halting or modifying the program control flow.

[0014] In another aspect, a method for tracking instruction processing using opcode matching in a processor-based device is disclosed. The method includes: determining, by instruction processing circuitry of the processor device, that an instruction among a plurality of instructions matches an opcode value stored in an opcode matching register of the processor device. The method further includes: in response to determining that an instruction matches an opcode value stored in the opcode matching register, modifying a value stored in an accumulator register of the processor device by the instruction processing circuitry without halting or modifying program control flow.

[0015] In another aspect, a non-transitory computer-readable medium is disclosed. The non-transitory computer-readable medium stores computer-executable instructions that, when executed, cause a processor device of a processor-based device to determine that one of a plurality of instructions matches an opcode value stored in an opcode matching register of the processor device. The computer-executable instructions further cause the processor device, in response to determining that the instruction matches the opcode value stored in the opcode matching register, to modify a value stored in an accumulator register of the processor device without halting or modifying the program control flow. Attached Figure Description

[0016] Figure 1 This is a block diagram of an exemplary processor-based device according to some aspects, the processor-based device including instruction processing circuitry configured to use opcode matching to track instruction processing; Figure 2 Examples are provided based on several aspects of using opcode matching to trace instruction processing. Figure 1 A flowchart illustrating an exemplary operation of the instruction processing circuit; Figures 3A to 3C Examples are provided based on several aspects of using opcode matching to trace instruction processing. Figure 1 A flowchart illustrating another exemplary operation of the instruction processing circuitry; and Figure 4 Yes, it can include Figure 1 A block diagram of an exemplary processor-based device for instruction processing circuitry. Detailed Implementation

[0017] Several exemplary aspects of this disclosure will now be described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or superior to other aspects. Unless otherwise indicated, the terms “first,” “second,” etc., as used herein are intended to distinguish similarly named elements and do not indicate an ordering relationship between such elements.

[0018] The aspects disclosed in the detailed description include using opcode matching to track instruction processing in processor-based devices. Related apparatus and methods are also disclosed. In this regard, in some exemplary aspects disclosed herein, the processor device includes instruction processing circuitry for processing (i.e., fetching, decoding, executing, and retiring) a plurality of instructions. The processor device also includes an opcode matching register and an accumulator register. The opcode matching register stores an opcode value, against which the instruction processing circuitry compares each of a plurality of instructions. If an instruction matches the opcode value stored in the opcode matching register, the instruction processing circuitry is configured to modify the value stored in the accumulator register (e.g., by incrementing or decrementing the value) without halting or modifying the program control flow. In this way, the opcode matching register and the accumulator register provide access to data that enables the execution of an application to be profiled and measured with minimal impact on processor performance.

[0019] Some aspects may provide that determining whether an instruction matches the opcode value stored in the opcode match register includes: determining whether the opcode of the instruction matches the opcode value stored in the opcode match register. In some such aspects, the processor device may also provide an opcode mask register that stores opcode masks. Such aspects may provide that determining whether the opcode of an instruction matches the opcode value stored in the opcode match register includes: determining whether the opcode of an instruction masked by the opcode mask matches the opcode value when the opcode mask is used. This enables instruction matching to be performed on multiple sets of instructions having opcodes that match the opcode mask.

[0020] Depending on some aspects of the processor device's operation in "instruction count mode," the value stored in the accumulator register represents the instruction occurrence count. In this aspect, the instruction processing circuitry modifies the value stored in the accumulator register to a value of one (1) (i.e., by incrementing or decrementing the value by one (1)). Some aspects of the processor device's operation in "total processing time mode" may provide that the value stored in the accumulator register represents the total time spent processing the occurrence of instructions. In this aspect, the instruction processing circuitry modifies the value stored in the accumulator register to a time value indicating the time interval between the occurrence of instruction fetch and end events (e.g., as a non-limiting example, a deactivation instruction, determining whether an instruction matches an opcode value, and / or marking an instruction as a result of the determination). In some aspects, the processor device may be configured to support both the instruction count mode and the total processing time mode described above. In this aspect, a mode indicator indicating either the instruction count mode or the total processing time mode may be provided to indicate how the instruction processing circuitry should modify the accumulator register.

[0021] Further aspects include: the processor device also includes an opcode matching control register that allows the functionality described above to be selectively enabled and disabled by an execution software process (such as an operating system (OS) or supermanager), which writes an enable value or a disable value to the opcode matching control register, respectively. According to such aspects, instruction processing circuitry can determine that an instruction matches an opcode value stored in the opcode matching register in response to determining that the value of the opcode matching control register is an enable value. In some aspects, the execution software process can also enable and disable the functionality described above depending on the current software context. Thus, the execution software process can set the value of the opcode matching control register to an enable value when executing in a first software context, and subsequently set the value of the opcode matching control register to a disable value when executing in a second software context (i.e., after a context switch). Further aspects include: the execution software process can read a value stored in an accumulator register, and / or can reset the value stored in the accumulator register (e.g., reset to a value of zero (0) or some other predefined reset value).

[0022] in this regard, Figure 1 This is a diagram of an exemplary processor-based device 100 including processor device 102. Processor device 102 (also referred to as a "processor core" or "central processing unit (CPU) core") may be an ordered or unordered processor (OoP) and / or may be one of a plurality of processor devices 102 provided by processor-based device 100. Figure 1 In the example, processor device 102 includes instruction processing circuitry 104, which includes one or more instruction pipelines I0 to I106 for processing a plurality of instructions 106. N These instructions are fetched from the instruction memory (in) by the fetch circuit 110. Figure 1 The instruction cache (labeled as "instruction memory") 108 is retrieved for execution. As a non-limiting example, the instruction memory 108 may be located in or be part of the system memory in the processor-based device 100. An instruction cache (in...) may also be located in the processor device 102. Figure 1 The instruction cache (112) is used to cache the instruction 106 retrieved from the instruction memory 108 to reduce the latency of the retrieval circuit 110.

[0023] exist Figure 1 In the example, the fetch circuit 110 is configured to provide instruction 106 as fetched instruction 106F to one or more instruction pipelines I0 to I1 in the instruction processing circuit 104. N In order to ensure that the extracted instruction 106F reaches the execution circuit (in Figure 1The instruction pipeline I0 to I14 (labeled "Execution Circuit") undergoes preprocessing before execution. N Different processing circuits or stages are set across instruction processing circuitry 104 to preprocess and process the fetched instruction 106F in a series of concurrently executable steps before the fetched instruction 106F is executed by execution circuitry 114, thereby improving throughput.

[0024] Continue to refer to Figure 1 The instruction processing circuit 104 includes a decoding circuit 118 configured to decode the extracted instruction 106F extracted by the extraction circuit 110 into a decoded instruction 106D to determine the instruction type and the required action. The instruction type and required operation encoded in the decoded instruction 106D can also be used to determine which instruction pipeline I0 to I10 should place the decoded instruction 106D in. N In this example, the decoding instruction 106D is placed in instruction pipelines I0 to I1. N In one or more instruction pipelines, the instruction is then provided to the renaming circuit 120 in the instruction processing circuit 104. The renaming circuit 120 is configured to determine whether any register names in the decoded instruction 106D should be renamed to decouple any register dependencies that would prevent parallel or out-of-order processing.

[0025] Figure 1 The instruction processing circuitry 104 in the processor device 102 also includes register access circuitry (in... Figure 1 The register access circuit 122 is labeled "Register Access Circuit". Register access circuit 122 is configured to access physical registers in the physical register file (PRF) (not shown) based on mapping entries of logical registers in the register map table (RMT) (not shown) that map to the source register operands of the decoded instruction 106D, in order to retrieve the produced value from the executed instruction 106E in the execution circuit 114. Register access circuit 122 is also configured to provide the produced value retrieved from the executed instruction 106E as the source register operand for the decoded instruction 106D to be executed.

[0026] Furthermore, in the instruction processing circuit 104, in the instruction pipeline I0 to I N A scheduler circuit is set up (in) Figure 1 The scheduler circuit 124 (labeled as "scheduler circuit") is configured to store the decoded instruction 106D in a reserved entry until all source register operands of the decoded instruction 106D are available. The scheduler circuit 124 issues the decoded instruction 106D ready for execution to the execution circuit 114. The instruction processing circuit 104 also provides a write circuit 126 to write back or commit the generated value from the executed instruction 106E to memory (such as PRF), cache memory, or system memory.

[0027] like Figure 1 As seen, processor-based device 100 provides a physical register file 128 including an opcode matching register 130. In normal use, the opcode matching register 130 can be used to provide "opcode matching and trap" functionality. To provide this functionality, the opcode matching register 130 stores an opcode value (not shown), which the instruction processing circuitry 104 can compare with one of a plurality of instructions 106. If the opcode of the instruction matches the opcode value, the instruction processing circuitry 104 can cause the processor device 102 to, for example, stop the execution of the application and enter a debug state, or transfer program control to an exception handler (not shown).

[0028] In some aspects, an opcode mask register 132 may also be provided, in which an opcode mask (not shown) may be stored. The opcode mask may include multiple bits, wherein bits set to a value of one (1) indicate the bits of interest to be used when comparing the opcode of an instruction with the opcode value stored in the opcode match register 130, while bits set to a value of zero (0) are ignored. In such aspects, the opcode mask is used to mask the opcode of an instruction (e.g., by performing a logical AND operation using the opcode of the instruction and the opcode mask). The opcode value stored in the opcode match register 130 is also masked using the opcode mask and subsequently compared with the masked opcode of the instruction. If the masked values ​​match, the instruction processing circuitry 104 may cause the processor device 102 to, for example, stop the execution of the application and enter a debug state, or transfer program control to an exception handler (not shown).

[0029] As mentioned above, such opcode matching and trap functionality may be useful in the context of debugging software, but may not prove useful for analyzing or measuring application performance. In this regard, instruction processing circuitry 104 may be configured to use opcode matching register 130 to trace instruction processing using opcode matching. In exemplary operation, instruction processing circuitry 104 (e.g., by determining that the opcode of instruction 134 matches the opcode value stored in opcode matching register 130) determines that instruction 134 of a plurality of instructions 106 matches the opcode value stored in opcode matching register 130 of processor device 102, wherein processor device 102 includes aspects of opcode mask register 132 that provide: instruction processing circuitry 104 determines that the opcode of instruction 134 matches the opcode value stored in opcode matching register 130 by determining that the opcode of instruction 134 masked using the opcode mask stored in opcode mask register 132 matches the opcode value masked using the opcode mask.

[0030] In response to determining that instruction 134 matches the opcode value stored in opcode match register 130, instruction processing circuitry 104 modifies the value stored in accumulator register 136 of processor device 102 without halting or modifying program control flow. As a non-limiting example, modifying the value stored in accumulator register 136 may include, for example, incrementing or decrementing the value. Where the value stored in accumulator register 136 represents aspects of the occurrence count of instruction 134 (i.e., "instruction count mode"), instruction processing circuitry 104 may modify the value stored in accumulator register 136 by modifying the value stored in accumulator register 136 to value one (1). Where the value stored in accumulator register 136 represents aspects of the total time spent processing the occurrence of instruction 134 (i.e., "total processing time mode"), instruction processing circuitry 104 may modify the value stored in accumulator register 136 by modifying the value stored in accumulator register 136 to a time value indicating the time interval between the fetch and end events of instruction 134. As a non-limiting example, an end event may include, for example, the termination of instruction 134, determining whether instruction 134 matches an opcode value, and / or marking instruction 134 as a result of the determination. The time interval in such aspects may be determined based on, for example, a tag or other instruction metadata (not shown) associated with instruction 134 and indicating the time when instruction 134 was retrieved and the time when the end event occurred.

[0031] In some aspects, processor device 102 can be configured to support both the instruction counting mode and the total processing time mode referenced above. In such aspects, instruction processing circuitry 104 includes a mode indicator (in... Figure 1 The mode indicator 138 (labeled as "mode indicator") can be set by software and indicates either instruction counting mode or total processing time mode. In this respect, the instruction processing circuitry 104 is configured to modify the accumulator register 136 in an appropriate manner based on the mode indicator 138.

[0032] In some aspects, processor device 102 also includes an opcode matching control register 140, which can be used by execution software process 142 (such as an operating system or super manager) to selectively enable or disable instruction processing tracing. Thus, for example, in such an aspect, instruction processing circuitry 104 can determine that the value of opcode matching control register 140 is an enabled value, and can subsequently determine, in response to determining that the value of opcode matching control register 140 is an enabled value, that instruction 134 matches the opcode value stored in opcode matching register 130.

[0033] Several aspects are available: the execution software process 142 can enable or disable instruction processing tracing in response to a software context change. Thus, in some such aspects, the execution software process 142 can set the value of the opcode matching control register 140 to an enabled value when executing in a first software context. Subsequently, in such aspects, the execution software process 142 can set the value of the opcode matching control register 140 to a disabled value when executing in a second software context. The execution software process 142 can also read the value stored in the accumulator register 136, and / or reset the value stored in the accumulator register 136 (e.g., by setting the accumulator register 136 to the value zero (0) or some other predefined reset value). In this way, the execution software process 142 can read and reset the value in the accumulator register 136 in response to, for example, a software context change, or can choose to maintain the value in the accumulator register 136 and monitor changes in the value in the accumulator register 136 over time.

[0034] Figure 2 This example illustrates how, when using opcode matching trace instructions, it can be handled by... Figure 1 The instruction processing circuit 104 performs an exemplary operation 200. For clarity, in the description Figure 2 Referenced at the time Figure 1 Components. In Figure 2 In this example, operation 200 begins with the opcode matching register 130 being set with the opcode value to be used for instruction matching (and optionally, the opcode mask register 132 being set with an opcode mask) (box 202). Additionally, the opcode matching control register 140 is set with a value to enable and indicate the action to be performed (i.e., regular debugging or trap functionality, or instruction processing tracking) (box 204). Software execution then continues (box 206). During instruction processing by the instruction processing circuitry 104, the instruction processing circuitry 104 determines whether instruction 134 matches the opcode value stored in the opcode matching register 130 (optionally, masked using the opcode mask stored in the opcode mask register 132) (box 208). If not, processing continues at box 206.

[0035] However, if instruction processing circuitry 104 determines at decision block 208 that instruction 134 matches the opcode value stored in opcode match register 130, then instruction processing circuitry 104 determines the appropriate action to be performed based on opcode match control register 140 (block 210). If the value stored in opcode match control register 140 indicates debug functionality, instruction processing circuitry 104 processes debug stop (e.g., by placing execution software procedure 142 into debug mode) (block 212). Processing then continues at block 206. If the value stored in opcode match control register 140 indicates trap functionality, instruction processing circuitry 104 processes traps (e.g., by transferring program control to an exception handler) (block 214). Processing then continues at block 206. Finally, if the value stored in opcode match control register 140 indicates counter functionality, instruction processing circuitry 104 modifies accumulator register 136 (block 216). Processing then continues at block 206.

[0036] To illustrate, based on some aspects, Figure 1 The instruction processing circuit 104 performs operations for tracking instruction processing using opcode matching. Figures 3A to 3C A flowchart illustrating exemplary operation 300 is provided. For clarity, in the description... Figures 3A to 3C Reference Figure 1 The components. It should be understood that some aspects can be provided: Figures 3A to 3C Some operations illustrated herein may be performed in a different order than those illustrated herein, and / or may be omitted.

[0037] In some respects, Figure 3A Operations begin in the instruction processing circuitry of the processor device (e.g., Figure 1 The instruction processing circuitry 104 of the processor device 102 determines the opcode matching control register (such as...) of the processor device 102. Figure 1 The value of the opcode matching control register 140 is the enabled value (box 302). The instruction processing circuit 104 determines the instruction among multiple instructions (such as...). Figure 1 Instruction 134 (one of the multiple instructions 106) matches the opcode matching register (e.g., stored in the processor device 102) stored in the processor device 102. Figure 1The opcode value in the opcode matching register 130 is matched (box 304). In some aspects, in response to determining that the value of the opcode matching control register 140 is an enabled value, the operation of box 304 for determining that instruction 134 matches the opcode value stored in the opcode matching register 130 is performed (box 306). According to some aspects, the operation of box 304 for determining that instruction 134 matches the opcode value stored in the opcode matching register 130 may include: determining that the opcode of instruction 134 matches the opcode value stored in the opcode matching register 130 (box 308). In some such aspects, the operation of box 308 for determining that the opcode of instruction 134 matches the opcode value stored in the opcode matching register 130 includes: determining that the opcode of instruction 134 matches the opcode value stored in the opcode matching register 130 is matched using the opcode mask register (e.g., opcode mask register stored in the processor device 102). Figure 1 The opcode of instruction 134, which is opcode masked in opcode mask register 132, is matched with the opcode value masked by the opcode mask (box 310). Exemplary operation 300 is then performed in... Figure 3B Continue at frame 312.

[0038] Now go to Figure 3B In response to determining that instruction 134 matches the opcode value stored in opcode match register 130, instruction processing circuitry 104 modifies the accumulator register stored in processor device 102 (e.g., Figure 1 The value stored in accumulator register 136) without stopping or modifying the program control flow (box 312). The value stored in accumulator register 136 represents aspects of the occurrence count of instruction 134. The operation of modifying the value stored in accumulator register 136 in box 312 may include: modifying the value stored in accumulator register 136 to value one (1) (box 314). The value stored in accumulator register 136, representing aspects of the total time spent processing instruction 134, may provide: the operation of modifying the value stored in accumulator register 136 in box 312 may include: modifying the value stored in accumulator register 136 to a time value indicating the time interval between the fetch and end events of instruction 134 (e.g., as a non-limiting example, withdrawing instruction 134, determining whether instruction 134 matches an opcode value, and / or marking instruction 134 as a result of the determination) (box 316). In some aspects, the operation of modifying the value stored in accumulator register 136 in box 312 may be based on a mode indicator (such as... Figure 1 The mode indicator 138 indicates one of the instruction counting mode and the total processing time mode of the instruction processing circuit 104 (box 318).

[0039] In some respects, the software process executed by the instruction processing circuit 104 (e.g., Figure 1 The execution of software procedure 142 may, when executed in a first software context, set the value of opcode matching control register 140 to an enabled value (box 320). Subsequently, in such an aspect, the execution of software procedure 142 may, when executed in a second software context, set the value of opcode matching control register 140 to a disabled value (box 322). In some aspects, exemplary operations may be performed in... Figure 3C Continue at frame 324.

[0040] Now for reference Figure 3C In some aspects, the execution of software procedure 142 may read the value stored in accumulator register 136 (box 324). In some aspects, the execution of software procedure 142 may reset the value stored in accumulator register 136 (e.g., reset it to the value zero (0) or some other predefined reset value) (box 326).

[0041] Based on the information disclosed in this article and referenced Figure 1 , Figure 2 as well as Figures 3A to 3C The instruction processing circuitry discussed in these aspects can be provided in or integrated into any processor-based device. Examples, without limitation, include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet computers, phablets, servers, computers, portable computers, mobile computing devices, laptop computers, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotor aircraft.

[0042] in this regard, Figure 4 An example of a processor-based device 400 is illustrated, which functionally corresponds to Figure 1Processor-based device 100. Processor-based device 400 includes processor device 402, which includes one or more CPUs 404 coupled to cache memory 406. CPU 404 is also coupled to system bus 408 and can be interactively coupled to devices included in processor-based device 400. As is well known, CPU 404 communicates with these other devices by exchanging address, control, and data information on system bus 408. For example, CPU 404 can communicate bus transaction requests to memory controller 410. Although in Figure 4 Not illustrated, but multiple system buses 408 may be provided, each of which constitutes a different structure.

[0043] Other devices can be connected to system bus 408. For example... Figure 4 As illustrated, these devices may include a memory system 412, one or more input devices 414, one or more output devices 416, one or more network interface devices 418, and one or more display controllers 420. Input devices 414 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output devices 416 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface devices 418 may be any device configured to allow data exchange to and from network 422. Network 422 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), and Bluetooth. ™ Networks and the Internet. Network interface device 418 can be configured to support any type of communication protocol desired. Memory system 412 may include a memory controller 410 coupled to one or more memory arrays 424.

[0044] CPU 404 can also be configured to access display controller 420 via system bus 408 to control information transmitted to one or more displays 426. Display controller 420 transmits information to be displayed to displays 426 via one or more video processors 428, which process the information to be displayed into a format suitable for displays 426. Displays 426 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc.

[0045] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithms described in conjunction with the aspects disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium, and executed by a processor device. As an example, the master and slave devices described herein can be employed in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, the functionality of the various exemplary components, blocks, modules, circuits, and steps has been generally described above. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0046] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using processor devices, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic components, discrete hardware components, or any combination thereof, designed to perform the functions described herein. The processor device may be a microprocessor, but in alternative embodiments, it may be any conventional processor device, controller, microcontroller, or state machine. The processor device may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0047] The aspects disclosed herein may be embodied in hardware and instructions stored in the hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor device, enabling the processor device to read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor device. The processor device and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor device and the storage medium may reside as discrete components in a remote station, base station, or server.

[0048] It should also be noted that the operational steps described in any of the exemplary aspects of this document are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flowcharts. Those skilled in the art will also understand that any of a variety of different techniques and arts can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0049] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0050] Specific implementation examples are described in the following numbered clauses: 1. A processor device, the processor device comprising: Opcode matching register; Accumulator register; and Instruction processing circuit, the instruction processing circuit being configured to: Determine that one of the multiple instructions matches the opcode value stored in the opcode matching register; and In response to determining that the instruction matches the opcode value stored in the opcode matching register, the value stored in the accumulator register is modified without stopping or modifying the program control flow.

[0051] 2. The processor device according to Clause 1, wherein the instruction processing circuitry is configured to determine that the instruction matches the opcode value stored in the opcode matching register by being configured to determine that the opcode of the instruction matches the opcode value stored in the opcode matching register.

[0052] 3. The processor device according to any one of clauses 1 to 2, wherein: The processor device further includes an opcode mask register for storing opcode masks; and The instruction processing circuit is configured to determine that the opcode of the instruction matches the opcode value stored in the opcode matching register by determining that the opcode of the instruction masked by the opcode mask matches the opcode value masked by the opcode mask.

[0053] 4. The processor device according to any one of clauses 1 to 3, wherein: The value stored in the accumulator register represents the occurrence count of the instruction; and The instruction processing circuit is configured to modify the value stored in the accumulator register by being configured to modify the value stored in the accumulator register to the value one (1).

[0054] 5. The processor device according to any one of clauses 1 to 3, wherein: The value stored in the accumulator register represents the total time spent processing the instruction; and The instruction processing circuit is configured to modify the value stored in the accumulator register by modifying the value stored in the accumulator register to a time value indicating the time interval between the occurrence of the instruction fetch and end events.

[0055] 6. The processor device according to Clause 5, wherein the termination event includes one of the following: termination of the instruction, determining whether the instruction matches the opcode value, and marking the instruction as a result of the determination.

[0056] 7. The processor device according to any one of clauses 1 to 6, wherein: The processor device further includes a mode indicator that indicates one of an instruction counting mode and a total processing time mode of the instruction processing circuit; and The instruction processing circuit is configured to modify the value stored in the accumulator register based on the mode indicator.

[0057] 8. The processor device according to any one of clauses 1 to 7, wherein: The processor device also includes an opcode matching control register; The instruction processing circuit is further configured to determine that the value of the opcode matching control register is an enabled value; and The instruction processing circuitry is configured to determine that the instruction matches the opcode value stored in the opcode matching register in response to determining that the value of the opcode matching control register is the enabled value.

[0058] 9. The processor device according to Clause 8, wherein the processor device is configured to: When executed in the first software context, the value of the opcode matching control register is set to the enabled value using the execution software procedure; and When executed in the second software context, the execution software procedure is used to set the value of the opcode matching control register to a disabled value.

[0059] 10. The processor device according to any one of clauses 1 to 9, wherein the instruction processing circuitry is further configured to read the value stored in the accumulator register.

[0060] 11. The processor device according to any one of clauses 1 to 10, wherein the instruction processing circuitry is further configured to reset the value stored in the accumulator register.

[0061] 12. The processor device according to any one of Clauses 1 to 11, wherein the processor device is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multirotor aircraft.

[0062] 13. A processor device, the processor device comprising: A component for determining whether an instruction among a plurality of instructions matches an opcode value stored in the opcode matching register of the processor device; and A component for modifying a value stored in an accumulator register of a processor device without stopping or modifying program control flow in response to determining that the instruction matches the opcode value stored in the opcode matching register.

[0063] 14. A method for tracking instruction processing using opcode matching, the method comprising: The instruction processing circuitry of the processor device determines that one of a plurality of instructions matches the opcode value stored in the opcode matching register of the processor device; and In response to determining that the instruction matches the opcode value stored in the opcode matching register, the instruction processing circuit modifies the value stored in the accumulator register of the processor device without stopping or modifying the program control flow.

[0064] 15. The method according to Clause 14, wherein

[0065] Determining that the instruction matches the opcode value stored in the opcode matching register includes: determining that the opcode of the instruction matches the opcode value stored in the opcode matching register.

[0066] 16. The method according to any one of Clauses 14 to 15, wherein determining that the opcode of the instruction matches the opcode value stored in the opcode matching register comprises: determining that the opcode of the instruction masked using an opcode mask stored in the opcode mask register of the processor device matches the opcode value masked using the opcode mask.

[0067] 17. The method according to any one of clauses 14 to 16, wherein: The value stored in the accumulator register represents the occurrence count of the instruction; and Modifying the value stored in the accumulator register includes: modifying the value stored in the accumulator register to value one (1).

[0068] 18. The method according to any one of clauses 14 to 16, wherein: The value stored in the accumulator register represents the total time spent processing the instruction; and Modifying the value stored in the accumulator register includes: changing the value stored in the accumulator register to a time value indicating the time interval between the occurrence of the instruction fetch and end events.

[0069] 19. The method according to Clause 18, wherein the termination event includes one of the following: termination of the instruction, determining whether the instruction matches the opcode value, and marking the instruction as a result of the determination.

[0070] 20. The method according to any one of clauses 14 to 19, wherein the modification of the value stored in the accumulator register is based on a mode indicator that indicates one of an instruction counting mode of the instruction processing circuit and a total processing time mode of the instruction processing circuit.

[0071] 21. The method according to any one of clauses 14 to 20, wherein: The processor device also includes an opcode matching control register; The method further includes determining that the value of the opcode matching control register is an enabled value; and Determining that the instruction matches the opcode value stored in the opcode matching register is in response to determining that the value of the opcode matching control register is the enabled value.

[0072] 22. The method according to Clause 21, further comprising: When executed in the first software context, the execution software procedure sets the value of the opcode matching control register to the enabled value; and When executed in the second software context, the execution software process sets the value of the opcode matching control register to a disabled value.

[0073] 23. The method according to any one of clauses 14 to 22, the method further comprising: reading the value stored in the accumulator register.

[0074] 24. The method according to any one of clauses 14 to 23, the method further comprising: resetting the value stored in the accumulator register.

[0075] 25. A non-transitory computer-readable medium having stored thereon computer-executable instructions, which, when executed, cause a processor device of a processor-based device to: Determine that one of a plurality of instructions matches an opcode value stored in the opcode matching register of the processor device; and In response to determining that the instruction matches the opcode value stored in the opcode matching register, the value stored in the accumulator register of the processor device is modified without stopping or modifying the program control flow.

[0076] 26. The non-transitory computer-readable medium according to Clause 25, wherein the computer-executable instructions cause the processor device to determine that the instruction matches the opcode value stored in the opcode matching register by causing the processor device to determine that the opcode of the instruction matches the opcode value stored in the opcode matching register.

[0077] 27. A non-transitory computer-readable medium according to any one of Clauses 25 to 26, wherein the computer-executable instructions cause the processor device to determine that the opcode of the instructions, which is masked using an opcode mask stored in an opcode mask register of the processor device, matches the opcode value masked using the opcode mask.

[0078] 28. A non-transitory computer-readable medium according to any one of clauses 25 to 27, wherein: The value stored in the accumulator register represents the occurrence count of the instruction; and The computer-executable instructions cause the processor device to modify the value stored in the accumulator register by causing the processor device to modify the value stored in the accumulator register to the value one (1).

[0079] 29. A non-transitory computer-readable medium according to any one of clauses 25 to 27, wherein: The value stored in the accumulator register represents the total time spent processing the instruction; and The computer-executable instruction causes the processor device to modify the value stored in the accumulator register by causing the processor device to modify the value stored in the accumulator register to a time value indicating the time interval between the occurrence of the fetch and end events of the instruction.

[0080] 30. A nontransitory computer-readable medium according to any one of clauses 25 to 29, wherein the computer-executable instructions cause the processor device to modify the value stored in the accumulator register based on a mode indicator, the mode indicator indicating one of an instruction counting mode of the instruction processing circuit and a total processing time mode of the instruction processing circuit.

Claims

1. A processor device, the processor device comprising: Opcode matching register; Accumulator register; and Instruction processing circuit, the instruction processing circuit being configured to: Determine that one of the multiple instructions matches the opcode value stored in the opcode matching register; and In response to determining that the instruction matches the opcode value stored in the opcode matching register, the value stored in the accumulator register is modified without stopping or modifying the program control flow.

2. The processor device of claim 1, wherein the instruction processing circuitry is configured to determine that the instruction matches the opcode value stored in the opcode matching register by being configured to determine that the opcode of the instruction matches the opcode value stored in the opcode matching register.

3. The processor device according to claim 2, wherein: The processor device further includes an opcode mask register for storing opcode masks; and The instruction processing circuit is configured to determine that the opcode of the instruction matches the opcode value stored in the opcode matching register by determining that the opcode of the instruction masked by the opcode mask matches the opcode value masked by the opcode mask.

4. The processor device according to claim 1, wherein: The value stored in the accumulator register represents the occurrence count of the instruction; and The instruction processing circuit is configured to modify the value stored in the accumulator register by modifying the value stored in the accumulator register to the value one (1).

5. The processor device according to claim 1, wherein: The value stored in the accumulator register represents the total time spent processing the instruction; and The instruction processing circuit is configured to modify the value stored in the accumulator register by modifying the value stored in the accumulator register to a time value indicating the time interval between the occurrence of the instruction fetch and end events.

6. The processor device of claim 5, wherein the termination event includes one of: instruction termination, determining whether the instruction matches the opcode value, and marking the instruction as a result of the determination.

7. The processor device according to claim 1, wherein: The processor device further includes a mode indicator that indicates one of an instruction counting mode and a total processing time mode of the instruction processing circuit; and The instruction processing circuitry is configured to modify the value stored in the accumulator register based on the mode indicator.

8. The processor device according to claim 1, wherein: The processor device also includes an opcode matching control register; The instruction processing circuit is further configured to determine that the value of the opcode matching control register is an enabled value; and The instruction processing circuitry is configured to determine that the instruction matches the opcode value stored in the opcode matching register in response to determining that the value of the opcode matching control register is the enabled value.

9. The processor device according to claim 8, wherein the processor device is configured to: When executed in the first software context, the value of the opcode matching control register is set to the enabled value using the execution software procedure; and When executed in the second software context, the execution software procedure is used to set the value of the opcode matching control register to a disabled value.

10. The processor device of claim 1, wherein the instruction processing circuitry is further configured to read the value stored in the accumulator register.

11. The processor device of claim 1, wherein the instruction processing circuitry is further configured to reset the value stored in the accumulator register.

12. The processor device of claim 1, wherein the processor device is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multirotor aircraft.

13. A processor device, the processor device comprising: A component for determining whether an instruction among a plurality of instructions matches an opcode value stored in the opcode matching register of the processor device; and A component for modifying a value stored in an accumulator register of a processor device without stopping or modifying program control flow in response to determining that the instruction matches the opcode value stored in the opcode matching register.

14. A method for tracking instruction processing using opcode matching, the method comprising: The instruction processing circuitry of the processor device determines that one of a plurality of instructions matches the opcode value stored in the opcode matching register of the processor device. as well as In response to determining that the instruction matches the opcode value stored in the opcode matching register, the instruction processing circuit modifies the value stored in the accumulator register of the processor device without stopping or modifying the program control flow.

15. The method of claim 14, wherein Determining that the instruction matches the opcode value stored in the opcode matching register includes: Determine that the opcode of the instruction matches the opcode value stored in the opcode matching register.

16. The method of claim 15, wherein determining that the opcode of the instruction matches the opcode value stored in the opcode matching register comprises: It is determined that the opcode of the instruction, which is masked using an opcode mask stored in the opcode mask register of the processor device, matches the opcode value masked using the opcode mask.

17. The method of claim 14, wherein: The value stored in the accumulator register represents the occurrence count of the instruction; and Modifying the value stored in the accumulator register includes: modifying the value stored in the accumulator register to value one (1).

18. The method of claim 14, wherein: The value stored in the accumulator register represents the total time spent processing the instruction; and Modifying the value stored in the accumulator register includes: modifying the value stored in the accumulator register to a time value indicating the time interval between the occurrence of the instruction fetch and end events.

19. The method of claim 18, wherein the termination event includes one of: withdrawing the instruction, determining whether the instruction matches the opcode value, and marking the instruction as a result of the determination.

20. The method of claim 14, wherein the modification of the value stored in the accumulator register is based on a mode indicator that indicates one of an instruction counting mode of the instruction processing circuit and a total processing time mode of the instruction processing circuit.

21. The method of claim 14, wherein: The processor device also includes an opcode matching control register; The method further includes determining that the value of the opcode matching control register is an enabled value; and Determining that the instruction matches the opcode value stored in the opcode matching register is in response to determining that the value of the opcode matching control register is the enabled value.

22. The method according to claim 21, further comprising: When executed in the first software context, the value of the opcode matching control register is set to the enabled value by the execution software procedure; as well as When executed in the second software context, the execution software process sets the value of the opcode matching control register to a disabled value.

23. The method according to claim 14, further comprising: Read the value stored in the accumulator register.

24. The method according to claim 14, further comprising: Reset the value stored in the accumulator register.

25. A non-transitory computer-readable medium having stored thereon computer-executable instructions, which, when executed, cause a processor device of a processor-based device to: Determine that one of a plurality of instructions matches an opcode value stored in the opcode matching register of the processor device; and In response to determining that the instruction matches the opcode value stored in the opcode matching register, the value stored in the accumulator register of the processor device is modified without stopping or modifying the program control flow.

26. The non-transitory computer-readable medium of claim 25, wherein the computer-executable instruction causes the processor device to determine that the instruction matches the opcode value stored in the opcode matching register by causing the processor device to determine that the opcode of the instruction matches the opcode value stored in the opcode matching register.

27. The non-transitory computer-readable medium of claim 26, wherein the computer-executable instruction causes the processor device to determine that the opcode of the instruction matches the opcode value stored in the opcode matching register by causing the processor device to determine that the opcode of the instruction, masked using an opcode mask stored in the processor device's opcode mask register, matches the opcode value masked using the opcode mask.

28. The non-transitory computer-readable medium according to claim 27, wherein: The value stored in the accumulator register represents the occurrence count of the instruction; and The computer-executable instructions cause the processor device to modify the value stored in the accumulator register by causing the processor device to modify the value stored in the accumulator register to the value one (1).

29. The non-transitory computer-readable medium according to claim 25, wherein: The value stored in the accumulator register represents the total time spent processing the instruction; and The computer-executable instruction causes the processor device to modify the value stored in the accumulator register by causing the processor device to modify the value stored in the accumulator register to a time value indicating the time interval between the occurrence of the fetch and end events of the instruction.

30. The non-transitory computer-readable medium of claim 25, wherein the computer-executable instructions cause the processor device to modify the value stored in the accumulator register based on a mode indicator, the mode indicator indicating one of an instruction counting mode of the instruction processing circuit and a total processing time mode of the instruction processing circuit.

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