FPGA-based nerve cell membrane potential detection method and related device

Abstract

The invention discloses an FPGA-based nerve cell membrane potential detection method and a related device, and the device comprises an input excitation module which is used for inputting an analog current signal to an FPGA core processing module; a model IP core is deployed in the FPGA core processing module, a pipeline design is adopted in the model IP core, the model IP core is obtained by mapping a Hodgkin-Here differential equation corresponding to the Purkinje cell electrophysiology model through high-level synthesis, the Purkinje cell membrane potential value at the current moment is calculated in real time according to an analog current signal, and the Purkinje cell membrane potential value is calculated in real time according to the calculated Purkinje cell membrane potential value. A digital voltage signal is obtained; the digital-to-analog conversion module is used for receiving the digital voltage signal output by the FPGA core processing module and converting the digital voltage signal into an analog voltage signal; and the display module is used for displaying the membrane potential waveform in real time according to the analog voltage signal. On the basis, the real-time high-speed calculation of the membrane potential change can be realized, and the occupation of hardware resources is effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of cell membrane potential detection, and in particular to a method and related apparatus for detecting neural cell membrane potential based on FPGA. Background Technology

[0002] The membrane potential changes of nerve cells (such as Purkinje cells) follow a complex nonlinear dynamic process, typically described by a set of differential equations, such as the Hodgkin-Huxley (HH) model. Traditional biomedical research and cardiac electrophysiology simulations primarily rely on software simulations using general-purpose computers (CPUs) or graphics processing units (GPUs). However, the serial computing approach based on the von Neumann architecture has inherent processing bottlenecks, making it difficult to break through nanosecond-level limitations in the real-time simulation step size of single-cell models, and also resulting in large hardware size and high power consumption. Furthermore, while existing artificial experimental measurement methods (such as glass microelectrodes) can directly observe potential changes, they suffer from drawbacks such as high invasiveness, uncontrollable conditions, and long experimental cycles, making rapid drug screening or reproducible validation difficult.

[0003] Existing neural cell simulation schemes based on general-purpose processors (CPUs) or traditional digital signal processors (DSPs) are limited by their von Neumann architecture and serial instruction execution mechanism. When dealing with scenarios like the Purkinje cell model, which involves numerous nonlinear differential equations and parallel computation of ion channels, they suffer from bottlenecks such as low computational parallelism and limited data throughput, making it difficult to achieve nanosecond-level real-time membrane potential evolution simulation. Furthermore, existing schemes struggle to effectively control hardware resource consumption while maintaining high floating-point arithmetic accuracy. This often results in large size, high power consumption, or difficulties in hardware timing convergence when implementing high-precision models, failing to meet the stringent requirements of miniaturization, low power consumption, and high real-time performance for portable medical devices or high-throughput drug screening equipment. Therefore, existing technologies suffer from low computational parallelism, high resource consumption, and insufficient real-time performance. Summary of the Invention

[0004] This invention provides a method and device for detecting the membrane potential of nerve cells based on FPGA, which can realize real-time high-speed calculation of membrane potential changes and effectively reduce the occupation of hardware resources.

[0005] In a first aspect, embodiments of the present invention provide an FPGA-based neural cell membrane potential detection device, comprising: The input excitation module is used to input analog current signals to the FPGA core processing module through the AXI Stream interface; The FPGA core processing module is built based on the Verilog hardware description language. The FPGA core processing module has a model IP core deployed inside. The model IP core adopts a pipelined design. The model IP core is obtained by mapping the Hodgkin-Huxley differential equation corresponding to the Purkinje cell electrophysiological model through high-level synthesis. The model IP core calculates the Purkinje cell membrane potential value at the current moment in real time and parallel based on the simulated current signal to obtain a digital voltage signal. In the calculation process, a nonlinear lookup table interpolation strategy is used to perform nonlinear operations. The digital-to-analog converter module is used to receive the digital voltage signal output by the FPGA core processing module via the SPI bus and convert the digital voltage signal into an analog voltage signal. The display module is used to display the membrane potential waveform in real time based on the analog voltage signal.

[0006] In one embodiment, the FPGA core processing module further includes a control logic module and an output driver module. The control logic module adopts a finite state machine design, and the driver module includes a floating-point to fixed-point conversion unit and an SPI host controller.

[0007] In one embodiment, the control logic module is used to parse external instructions, configure the total number of simulation steps, and start the calculation process; the drive module is used to convert the calculated 32-bit floating-point voltage value into a 12-bit integer required by the digital-to-analog converter module, and output it serially according to the MCP4921 communication protocol.

[0008] In one embodiment, the structure of the Purkinje cell electrophysiological model is designed using a data flow-driven approach, and the display module is an oscilloscope.

[0009] In one embodiment, the Purkinje cell electrophysiological model includes a lookup table module, a floating-point arithmetic unit, and an Euler integral module. The lookup table module is used to obtain the steady-state values ​​and time constants of the gating variables of each ion channel based on the linear interpolation of the current membrane potential. The floating-point arithmetic unit is used to calculate the ion currents in parallel, including sodium current and potassium current. The Euler integral module is used to update the membrane potential at the next time step.

[0010] In one embodiment, the lookup table module includes a linear interpolation module, which includes an address calculation unit, a system storage unit, and an interpolation operation unit. The address calculation unit calculates the corresponding ROM address and address offset based on the voltage range, reads two consecutive values ​​from the system storage unit, and performs a floating-point multiplication and addition in the interpolation operation unit with the offset to obtain a high-precision intermediate result.

[0011] In a second aspect, embodiments of the present invention provide an electronic device, including the FPGA-based neural cell membrane potential detection device as described in the first aspect.

[0012] Thirdly, embodiments of the present invention provide an FPGA-based method for detecting neural cell membrane potentials, applied to the FPGA-based neural cell membrane potential detection device as described in the first aspect, the method comprising: The input excitation module transmits the analog current signal to the FPGA core processing module through the AXI Stream interface; The FPGA core processing module calculates the current Purkinje cell membrane potential value in parallel based on the analog current signal, and sends the Purkinje cell membrane potential value to the digital-to-analog converter module via the SPI bus. The digital-to-analog converter module converts the digital voltage signal into an analog voltage signal; The display module displays the real-time curve of the Purkinje nerve cell membrane potential change based on the simulated voltage signal.

[0013] Fourthly, embodiments of the present invention provide an edge computing device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, when the processor executes the computer program, it implements the FPGA-based neural cell membrane potential detection method as described in the third aspect.

[0014] Fifthly, embodiments of the present invention provide a computer-readable storage medium storing computer-executable instructions for performing the FPGA-based neural cell membrane potential detection method as described in the third aspect.

[0015] This invention provides an FPGA-based method and apparatus for detecting neural cell membrane potential. The FPGA-based neural cell membrane potential detection apparatus includes an input excitation module, an FPGA core processing module, a digital-to-analog converter (DAC), and a display module. The input excitation module inputs an analog current signal to the FPGA core processing module via an AXI Stream interface. The FPGA core processing module is built using the Verilog hardware description language and internally deploys a model IP core. The model IP core employs a pipelined design and maps the Hodgkin-Huxley differential equation corresponding to the Purkinje cell electrophysiological model through high-level synthesis. The model IP core calculates the Purkinje cell membrane potential value at the current moment in parallel based on the analog current signal to obtain a digital voltage signal, employing a nonlinear lookup table interpolation strategy to perform nonlinear operations during the calculation process. The DAC module receives the digital voltage signal output by the FPGA core processing module via an SPI bus and converts the digital voltage signal into an analog voltage signal. The display module displays the membrane potential waveform in real time based on the analog voltage signal. This device utilizes the hardware parallelism and pipeline technology of FPGAs to map the differential equations of cell models into dedicated hardware circuits through high-level synthesis (HLS), significantly improving the parallel computing capabilities and data processing throughput of ion channel states. This enables nanosecond-level real-time calculation and simulation of membrane potential changes. Furthermore, by employing a nonlinear lookup table interpolation strategy, complex exponential function operations are transformed into efficient lookup table operations, avoiding the direct use of a large number of DSPs for floating-point exponentiation. This allows implementation with only a small amount of on-chip memory resources and logic gates, significantly reducing computational latency and making it ideal for neural simulation applications with extremely high real-time requirements. Based on this, the FPGA-based neural cell membrane potential detection device of this invention can achieve real-time, high-speed calculation of membrane potential changes while effectively reducing hardware resource consumption.

[0016] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0017] The accompanying drawings are provided to further understand the technical solutions of the present invention and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the technical solutions of the present invention, and do not constitute a limitation on the technical solutions of the present invention.

[0018] Figure 1 A schematic diagram of the overall structure of an FPGA-based neural cell membrane potential detection device provided in one embodiment of the present invention; Figure 2 This is a schematic diagram of the internal logic architecture of an FPGA core processing module provided in one embodiment of the present invention; Figure 3 A logical topology diagram of a Purkinje cell electrophysiological model provided in one embodiment of the present invention; Figure 4 A detailed circuit diagram of a linear interpolation module provided in one embodiment of the present invention; Figure 5 A graph showing the FPGA resource utilization of simple and complex spikes in cerebellar Purkinje neurons, provided as an embodiment of the present invention. Figure 6 An FPGA power consumption diagram of simple and complex spikes in cerebellar Purkinje neurons provided in one embodiment of the present invention; Figure 7 A flowchart illustrating an FPGA-based neural cell membrane potential detection method according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of an edge computing device provided in one embodiment of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0020] It should be understood that in the description of the embodiments of the present invention, "multiple" (or "amounts") means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. If "first," "second," etc., are used in the description, they are only for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0021] First, let's analyze some of the terms used in this invention: FPGA (Field-Programmable Gate Array): is an integrated chip that is mainly composed of digital circuits.

[0022] HLS (High-Level Synthesis): High-level synthesis addresses the traditional FPGA development challenge of drawing circuits in very low-level hardware languages ​​(Verilog), which is as difficult as writing code in machine language. HLS acts as a "translator," allowing algorithms to be written directly using the familiar C++ programming language, and the HLS tool automatically translates the C++ code into low-level hardware circuits.

[0023] Purkinje cells are special cardiomyocytes found in the heart's conduction system. They act as "highways" in the heart, responsible for transmitting electrical signals extremely quickly from the atria to the ventricles, ensuring the heart can pump blood efficiently and effectively.

[0024] The Hodgkin-Huxley Model (HH Model) is the gold standard in mathematics for describing how nerve cells (or cardiomyocytes) generate electrical signals. It is not a simple matter of addition, subtraction, multiplication, and division, but rather a complex set of nonlinear differential equations that simulate the membrane potential changes caused by the opening and closing of ion channels such as sodium and potassium.

[0025] To facilitate a more convenient description of the working principle of the embodiments of the present invention, the following introduction of relevant technical scenarios is given first.

[0026] The membrane potential changes of nerve cells (such as Purkinje cells) follow a complex nonlinear dynamic process, typically described by a set of differential equations, such as the Hodgkin-Huxley (HH) model. Traditional biomedical research and cardiac electrophysiology simulations primarily rely on software simulations using general-purpose computers (CPUs) or graphics processing units (GPUs). However, the serial computing approach based on the von Neumann architecture has inherent processing bottlenecks, making it difficult to break through nanosecond-level limitations in the real-time simulation step size of single-cell models, and also resulting in large hardware size and high power consumption. Furthermore, while existing artificial experimental measurement methods (such as glass microelectrodes) can directly observe potential changes, they suffer from drawbacks such as high invasiveness, uncontrollable conditions, and long experimental cycles, making rapid drug screening or reproducible validation difficult.

[0027] Existing neural cell simulation schemes based on general-purpose processors (CPUs) or traditional digital signal processors (DSPs) are limited by their von Neumann architecture and serial instruction execution mechanism. When dealing with scenarios like the Purkinje cell model, which involves numerous nonlinear differential equations and parallel computation of ion channels, they suffer from bottlenecks such as low computational parallelism and limited data throughput, making it difficult to achieve nanosecond-level real-time membrane potential evolution simulation. Furthermore, existing schemes struggle to effectively control hardware resource consumption while maintaining high floating-point arithmetic accuracy. This often results in large size, high power consumption, or difficulties in hardware timing convergence when implementing high-precision models, failing to meet the stringent requirements of miniaturization, low power consumption, and high real-time performance for portable medical devices or high-throughput drug screening equipment. Therefore, existing technologies suffer from low computational parallelism, high resource consumption, and insufficient real-time performance.

[0028] To address the aforementioned problems in the existing technology, this invention provides an FPGA-based method and device for detecting neural cell membrane potential. The FPGA-based neural cell membrane potential detection device includes an input excitation module, an FPGA core processing module, a digital-to-analog converter (DAC) module, and a display module. The input excitation module inputs an analog current signal to the FPGA core processing module via an AXIStream interface. The FPGA core processing module is built using the Verilog hardware description language and internally deploys a model IP core. The model IP core employs a pipelined design and is obtained by mapping the Hodgkin-Huxley differential equation corresponding to the Purkinje cell electrophysiological model through high-level synthesis. The model IP core calculates the Purkinje cell membrane potential value at the current moment in parallel based on the analog current signal to obtain a digital voltage signal, and uses a nonlinear lookup table interpolation strategy to perform nonlinear operations during the calculation process. The DAC module receives the digital voltage signal output by the FPGA core processing module via an SPI bus and converts the digital voltage signal into an analog voltage signal. The display module displays the membrane potential waveform in real time based on the analog voltage signal. This device utilizes the hardware parallelism and pipeline technology of FPGAs to map the differential equations of cell models into dedicated hardware circuits through high-level synthesis (HLS), significantly improving the parallel computing capabilities and data processing throughput of ion channel states. This enables nanosecond-level real-time calculation and simulation of membrane potential changes. Furthermore, by employing a nonlinear lookup table interpolation strategy, complex exponential function operations are transformed into efficient lookup table operations, avoiding the direct use of a large number of DSPs for floating-point exponentiation. This allows implementation with only a small amount of on-chip memory resources and logic gates, significantly reducing computational latency and making it ideal for neural simulation applications with extremely high real-time requirements. Based on this, the FPGA-based neural cell membrane potential detection device of this invention can achieve real-time, high-speed calculation of membrane potential changes while effectively reducing hardware resource consumption.

[0029] like Figure 1 As shown, an embodiment of the present invention provides an FPGA-based neural cell membrane potential detection device, which mainly includes: an input excitation module, an FPGA core processing module, a digital-to-analog converter (DAC) module, and a display module. The input excitation module is used to input an analog current signal to the FPGA core processing module via an AXI Stream interface. The FPGA core processing module is built based on the Verilog hardware description language and internally deploys a model IP core. The model IP core adopts a pipelined design and is obtained by mapping the Hodgkin-Huxley differential equation corresponding to the Purkinje cell electrophysiological model through high-level synthesis. The model IP core calculates the Purkinje cell membrane potential value at the current moment in real time and parallel based on the analog current signal to obtain a digital voltage signal, and uses a nonlinear lookup table interpolation strategy to perform nonlinear operations during the calculation process. The DAC module receives the digital voltage signal output by the FPGA and converts it into an analog voltage signal. The display module is used to display the converted membrane potential waveform in real time; the display module can be an oscilloscope. During operation, the input excitation module transmits current data to the FPGA via the AXI Stream interface. The FPGA core processing module calculates the cell membrane potential value at the current moment in parallel and sends the potential value to the DAC via the SPI bus. Finally, the real-time membrane potential change curve is displayed on the oscilloscope.

[0030] It is understood that the FPGA-based neural cell membrane potential detection device of the present invention utilizes high-level synthesis (HLS) technology to automatically map the complex Hodgkin-Huxley (HH) differential equation model of Purkinje neural cells into FPGA hardware circuits, and realizes parallel data processing through pipeline technology. This architecture breaks through the bottleneck of traditional serial computing based on CPU or DSP, enabling ion channel state updates, floating-point operations and interpolation queries to be executed in parallel on hardware, thereby reducing the latency of single-step simulation to the nanosecond level and realizing real-time high-speed calculation of membrane potential changes.

[0031] Understandably, the AXI Stream interface enables streaming interaction between external excitation signals and internal computing modules, and the calculated real-time membrane potential digital signal is directly transmitted to the digital-to-analog converter (DAC) module via the SPI bus. This system eliminates the delay in software-hardware interaction in traditional simulations, realizes end-to-end real-time physical feedback from current injection to voltage output, and can realistically reproduce the dynamic potential response of cells under different physiological or pathological conditions.

[0032] like Figure 2The diagram illustrates a specific embodiment of the internal logic architecture of the FPGA core processing module of this invention. This architecture mainly comprises three parts: control logic, computation logic, and output driving logic. The control logic employs a finite state machine (FSM) design, responsible for parsing external instructions, configuring the total number of simulation steps (total_steps), and initiating the computation process. The computation logic is the core of this invention; it synthesizes the Purkinje cell HH differential equation model into a dedicated hardware IP core using the Vitis HLS tool. This IP core employs a pipelined design, enabling parallel execution of current injection, ion channel updates, and potential calculations. The output driving logic includes a floating-point to fixed-point conversion unit and an SPI host controller, responsible for converting the calculated 32-bit floating-point voltage value into the 12-bit integer required by the DAC and serially outputting it according to the MCP4921 communication protocol.

[0033] like Figure 3 The diagram illustrates the logical topology of the Purkinje cell electrophysiology model within the FPGA core processing module of this invention. This structure employs a dataflow-driven design to simulate the dynamic processes of ion channels on the cell membrane. Specifically, the signal first passes through a lookup table (LUT) module, which linearly interpolates the current membrane potential V to obtain the steady-state values ​​(m_inf, h_inf, n_inf) and time constants (tau) of each ion channel gating variable. Subsequently, these values ​​enter the floating-point arithmetic unit to calculate each ion current (e.g., sodium current I_Na, potassium current I_K). Finally, the membrane potential V at the next time step is updated via an Euler integral module. This topology leverages the parallel capabilities of the FPGA, allowing the computational steps that were originally executed serially on the CPU to overlap in hardware, significantly improving computational efficiency.

[0034] like Figure 4 The diagram shows the specific circuit structure of the linear interpolation module in this embodiment of the invention. To implement complex nonlinear operations (such as exponential functions) with limited resources, this invention employs a lookup table (LUT) combined with a hardware implementation of linear interpolation. The circuit includes an address calculation unit, a system memory unit (ROM), and an interpolation unit. Upon receiving the current membrane potential V, the address calculation unit calculates the corresponding ROM address and address offset based on the voltage range. The system reads two consecutive values ​​from the ROM and performs a floating-point multiplication and addition in the interpolation unit using the offset, thereby obtaining a high-precision intermediate result. Compared to directly using a large number of DSPs for floating-point exponentiation, this structure consumes only a small amount of on-chip storage resources and logic gates, and requires only extremely low clock latency, making it very suitable for neural simulation applications with extremely high real-time requirements.

[0035] Understandably, this invention employs an optimized lookup table interpolation and resource allocation strategy: For nonlinear calculations in the cell model that heavily rely on voltage variables (such as the steady-state value of gated variables), a linear interpolation module based on field-programmable gate array on-chip storage resources (LUT-RAM / BRAM) is used. By transforming complex exponential function operations into efficient lookup table operations, computational latency is significantly reduced. Simultaneously, by flexibly configuring the number of instantiations of floating-point arithmetic units (FPU / DSIP) (such as limiting DSP reuse) and timing constraints (such as II=36), the utilization rate of logic resources (LUT) and dedicated arithmetic units (DSP) is effectively optimized while ensuring IEEE 754 floating-point calculation accuracy, thus solving the resource adaptation problem of high-precision models on miniaturized FPGA devices.

[0036] like Figure 5 As shown in the figure, this invention's FPGA-based neural cell membrane potential detection device achieves efficient biophysical computation through a highly optimized hardware architecture while maintaining low and reasonable logic resource consumption. Specifically, compared to the simple spike wave model of cerebellar Purkinje cells, the resource requirements of the complex spike wave model (LUT increases to 33%, FF increases to 19%, and DSP surges to 53%) are significantly higher, but still far below the device's resource limit (LUT < 35%), demonstrating the algorithm's good scalability and hardware adaptability. Crucially, this invention fully utilizes the heterogeneous computing advantages of FPGAs: although the LUT and FF (general logic and register) occupancy rates remain around 30%, they do not expand exponentially with model complexity, reflecting the efficient pipeline design effectively controlling logic resource overhead; the high DSP (digital signal processing unit) occupancy rates (36% and 53%) highlight the system's core advantages, indicating that the device successfully maps a large number of complex nonlinear differential equation calculations (such as ion current calculations in the HH model) to dedicated hardware acceleration units, rather than inefficient general logic. This resource distribution characteristic of "DSP as the main component and logic resources as the auxiliary component" ensures that high-precision real-time simulation at the nanosecond level can be achieved with limited hardware resources, reserving sufficient resource space for the subsequent integration of more neural networks or the implementation of more complex pathological models on the same FPGA.

[0037] like Figure 6As shown, the FPGA-based neural cell membrane potential detection device of this invention maintains extremely low power consumption despite significantly increasing model complexity, demonstrating excellent energy efficiency. Specifically, although the complex spike model utilizes more DSP resources (DSP power consumption increased from 18% to 24% to handle heavier floating-point operations), the total power consumption of the device did not increase linearly, but remained at a low level of ~0.122W. This is due to the efficient pipeline design effectively suppressing unnecessary consumption of signal switching and logic gates. It is worth noting that the total power consumption structure of the two models is highly similar, with approximately 58%-59% of the power consumption being PL Static, mainly due to the basic leakage current of the FPGA chip, which is an inherent attribute of the hardware platform. This means that the increased complexity of calculations only affects the Dynamic component, which accounts for about 41% of the total power consumption, and its value is controlled within 0.05W. This proves that the hardware acceleration solution of the present invention can achieve extremely low operating power consumption while ensuring high-precision real-time simulation, which is very suitable for the stringent low power consumption requirements of portable medical devices and edge computing devices.

[0038] Based on this, the present invention has significant advantages in computational efficiency and real-time performance compared to existing real-time simulation schemes based on DSPs or CPUs. Existing technologies, limited by the fixed instruction set architecture of processors, typically process the differential equations of ion channels serially, making it difficult to handle the intensive floating-point operations required in the Purkinje cell model. The present invention utilizes the hardware reconfigurability and parallel pipeline technology of FPGAs to map the complex HH model into dedicated hardware circuits, achieving nanosecond-level data throughput and parallel computing. This represents a speed improvement of several orders of magnitude compared to traditional software simulation, and the hardware timing is optimized through HLS, ensuring stable operation at high clock frequencies.

[0039] Furthermore, this invention demonstrates superior performance in terms of resource utilization and system integration. Existing solutions often consume significant amounts of general-purpose logic resources in pursuit of high precision, resulting in large device size, high power consumption, and difficulty in portability. In contrast, this invention employs a nonlinear lookup table interpolation strategy to replace complex exponential operations and, through flexible configuration of DSP reuse, significantly reduces the occupancy of FPGA logic resources (LUTs) and dedicated computing units (DSPs) while strictly maintaining IEEE 754 floating-point calculation accuracy. This enables the device to achieve high-precision real-time simulation on resource-constrained miniaturized FPGA devices and integrates a high-performance DA conversion interface, constructing a compact closed-loop system from biological simulation to physical signal output, greatly enhancing the device's application value in portable medical monitoring and in vitro drug screening.

[0040] In addition, an embodiment of the present invention also discloses an electronic device. Since the electronic device adopts the above-mentioned FPGA-based neural cell membrane potential detection device, the electronic device can achieve the same technical effect as the above-mentioned FPGA-based neural cell membrane potential detection device, which will not be described in detail here.

[0041] In addition, such as Figure 7 As shown, an embodiment of the present invention also discloses an FPGA-based method for detecting neural cell membrane potential, applied to the aforementioned FPGA-based neural cell membrane potential detection device. The method includes the following steps: Step S101: The input excitation module transmits the analog current signal to the FPGA core processing module through the AXI Stream interface; Step S102: The FPGA core processing module calculates the current Purkinje cell membrane potential value in parallel based on the analog current signal, and sends the Purkinje cell membrane potential value to the digital-to-analog converter module via the SPI bus. Step S103: The digital-to-analog converter module converts the digital voltage signal into an analog voltage signal; In step S104, the display module displays the real-time curve of the Purkinje nerve cell membrane potential change based on the analog voltage signal.

[0042] This method leverages the hardware parallelism and pipelined technology of FPGAs to map the differential equations of cell models into dedicated hardware circuits through High-Level Synthesis (HLS), significantly improving the parallel computing capabilities and data processing throughput of ion channel states. This enables nanosecond-level real-time calculation and simulation of membrane potential changes. Furthermore, by employing a nonlinear lookup table interpolation strategy, complex exponential function operations are transformed into efficient lookup operations, avoiding the direct use of a large number of DSPs for floating-point exponentiation. This allows implementation with minimal on-chip memory resources and logic gates, significantly reducing computational latency and making it highly suitable for real-time neural simulation applications. Therefore, the FPGA-based neural cell membrane potential detection method of this invention can achieve real-time, high-speed calculation of membrane potential changes while effectively reducing hardware resource consumption.

[0043] In addition, such as Figure 8 As shown, one embodiment of the present invention also discloses an edge computing device, including: at least one processor 210; at least one memory 220 for storing at least one program; when the at least one program is executed by at least one processor 210, it implements the FPGA-based neural cell membrane potential detection method as in any of the preceding embodiments.

[0044] In addition, one embodiment of the present invention discloses a computer-readable storage medium storing computer-executable instructions for performing the FPGA-based neural cell membrane potential detection method as described in any of the preceding embodiments.

[0045] The system architecture and application scenarios described in the embodiments of this invention are for the purpose of more clearly illustrating the technical solutions of the embodiments of this invention, and do not constitute a limitation on the technical solutions provided by the embodiments of this invention. As those skilled in the art will know, with the evolution of system architecture and the emergence of new application scenarios, the technical solutions provided by the embodiments of this invention are also applicable to similar technical problems.

[0046] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0047] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0048] The terms “unit,” “module,” “device,” etc., used in this specification are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process or execution thread, and components may be located on a single computer or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, or a network, such as the Internet interacting with other systems via signals).

[0049] The above provides a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of the present invention.

Claims

1. A neural cell membrane potential detection device based on FPGA, characterized in that, The device includes: The input excitation module is used to input analog current signals to the FPGA core processing module through the AXI Stream interface; The FPGA core processing module is built based on the Verilog hardware description language. The FPGA core processing module has a model IP core deployed inside. The model IP core adopts a pipelined design. The model IP core is obtained by mapping the Hodgkin-Huxley differential equation corresponding to the Purkinje cell electrophysiological model through high-level synthesis. The model IP core calculates the Purkinje cell membrane potential value at the current moment in real time and parallel based on the simulated current signal to obtain a digital voltage signal. In the calculation process, a nonlinear lookup table interpolation strategy is used to perform nonlinear operations. The digital-to-analog converter module is used to receive the digital voltage signal output by the FPGA core processing module via the SPI bus and convert the digital voltage signal into an analog voltage signal. The display module is used to display the membrane potential waveform in real time based on the analog voltage signal.

2. The FPGA-based neural cell membrane potential detection device according to claim 1, characterized in that, The FPGA core processing module also includes a control logic module and an output driver module. The control logic module adopts a finite state machine design, and the driver module includes a floating-point to fixed-point conversion unit and an SPI host controller.

3. The FPGA-based neural cell membrane potential detection device according to claim 2, characterized in that, The control logic module is used to parse external instructions, configure the total number of simulation steps, and start the calculation process; the drive module is used to convert the calculated 32-bit floating-point voltage value into a 12-bit integer required by the digital-to-analog converter module, and output it serially according to the MCP4921 communication protocol.

4. The FPGA-based neural cell membrane potential detection device according to claim 1, characterized in that, The structure of the Purkinje cell electrophysiological model is designed using a data flow-driven approach, and the display module is an oscilloscope.

5. The FPGA-based neural cell membrane potential detection device according to claim 1, characterized in that, The Purkinje cell electrophysiological model includes a lookup table module, a floating-point arithmetic unit, and an Euler integral module. The lookup table module is used to obtain the steady-state values ​​and time constants of the gating variables of each ion channel based on the linear interpolation of the current membrane potential. The floating-point arithmetic unit is used to calculate the ion currents in parallel, including sodium current and potassium current. The Euler integral module is used to update the membrane potential at the next time step.

6. The FPGA-based neural cell membrane potential detection device according to claim 5, characterized in that, The lookup table module includes a linear interpolation module, which includes an address calculation unit, a system storage unit, and an interpolation operation unit. The address calculation unit calculates the corresponding ROM address and address offset based on the voltage range, reads two consecutive values ​​from the system storage unit, and performs a floating-point multiplication and addition in the interpolation operation unit with the offset to obtain a high-precision intermediate result.

7. An electronic device comprising the FPGA-based neural cell membrane potential detection device as described in any one of claims 1 to 6.

8. A method for detecting neural cell membrane potential based on FPGA, characterized in that, The method, applied to the FPGA-based neural cell membrane potential detection device as described in any one of claims 1 to 6, comprises: The input excitation module transmits the analog current signal to the FPGA core processing module through the AXI Stream interface; The FPGA core processing module calculates the current Purkinje cell membrane potential value in parallel based on the analog current signal, and sends the Purkinje cell membrane potential value to the digital-to-analog converter module via the SPI bus. The digital-to-analog converter module converts the digital voltage signal into an analog voltage signal; The display module displays the real-time curve of the Purkinje nerve cell membrane potential change based on the simulated voltage signal.

9. An edge computing device, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, when the processor executes the computer program, it implements the FPGA-based neural cell membrane potential detection method as described in claim 8.

10. A computer-readable storage medium storing computer-executable instructions for performing the FPGA-based neural cell membrane potential detection method as described in claim 8.

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