Chip testing method and device and computer readable storage medium

Abstract

The embodiment of the invention provides a chip testing method and device and a computer readable storage medium, and the method comprises the steps: obtaining at least one eye pattern scanning result of at least one sample chip, each eye pattern scanning result being obtained by scanning mutually orthogonal judgment voltage and sampling time in a first scanning range, the judgment voltage is used for judging connectivity between crystal grains; based on the at least one eye pattern scanning result, a second scanning range formed by the eye pattern boundary of the at least one sample chip is determined, the second scanning range is smaller than the first scanning range, and the second scanning range belongs to a part of the first scanning range; and in the second scanning range, testing the connectivity between crystal grains of the target chip. Therefore, the number of test point positions for the target chip can be greatly reduced, so that the test time of the target chip is remarkably shortened, and the method is suitable for mass production test.

Description

Technical Field

[0001] This document relates to the field of network management technology, and in particular to a chip testing method, device, and computer-readable storage medium. Background Technology

[0002] As chip size continues to increase, the number of dies in chips using co-packaging technology also increases, making die-to-die (DTD) IP testing increasingly critical. After wafer fabrication is complete, but before dicing and packaging, chip probing (CP) is typically performed. If DTD IP testing can be completed at the CP stage, effectively identifying defective dies, test coverage will be significantly improved, and unnecessary cost waste due to poorly packaged dies will be avoided.

[0003] IP inner-loop testing is a commonly used DTD IP testing method during the CP (Content Processing) phase. This method has strict requirements on the timing of different planes between interconnect chips, which places high demands on the inner-loop link design of the IP. Furthermore, as the interface speed of DTD continues to increase, existing inner-loop link designs are no longer sufficient to meet the testing needs of high-speed DTD IP.

[0004] To overcome the shortcomings of IP inner-loop testing, the industry later proposed a new DTD IP testing method based on eye diagram scanning. However, the traditional DTD IP testing method based on eye diagram scanning suffers from long testing times, making it difficult to apply to mass production testing scenarios and requiring improvement. Summary of the Invention

[0005] This application provides a chip testing method, device, and computer-readable storage medium to solve the problem that existing chip testing methods have long testing times and are difficult to apply to mass production testing scenarios.

[0006] To solve the above-mentioned technical problems, the embodiments of this application are implemented as follows: Firstly, a chip testing method is provided, the method comprising: At least one eye diagram scan result of at least one sample chip is obtained, wherein each eye diagram scan result is obtained by scanning mutually orthogonal decision voltages and sampling times within a first scan range, the decision voltages being used to determine inter-crystal connectivity; Based on the at least one eye map scan result, a second scan range is determined to form the eye map boundary of the at least one sample chip, wherein the second scan range is smaller than the first scan range, and the second scan range is a part of the first scan range; Within the second scan range, the inter-die connectivity of the target chip is tested.

[0007] Secondly, a chip testing apparatus is provided, the apparatus comprising: The data acquisition module is used to acquire at least one eye diagram scan result of at least one sample chip, wherein each eye diagram scan result is obtained by scanning mutually orthogonal decision voltages and sampling times within a first scanning range, and the decision voltage is used to determine the inter-crystal connectivity. A scanning range determination module is used to determine a second scanning range formed by the eye map boundary of the at least one sample chip based on the at least one eye map scanning result, wherein the second scanning range is smaller than the first scanning range and the second scanning range is a part of the first scanning range; The first test module is used to test the inter-die connectivity of the target chip within the second scan range.

[0008] Thirdly, an electronic device is provided, comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to execute the instructions to implement the method as described in the first aspect.

[0009] Fourthly, a computer-readable storage medium is provided, wherein when instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the method described in the first aspect.

[0010] Fifthly, a computer program product including instructions is provided, characterized in that when a computer executes the instructions of the computer program product, the computer performs the method as described in the first aspect.

[0011] In this embodiment, by acquiring eye diagram scan results of at least one sample chip within a large first scan range, a relatively small second scan range is determined based on these results. The second scan range is formed by the eye diagram boundaries of the at least one sample chip. Subsequently, for the target chip to be tested, inter-die connectivity testing is performed within the second scan range. Because the scan range is reduced and covers possible eye diagram boundaries, this chip testing scheme can significantly reduce the number of test points for the target chip without sacrificing test accuracy and result reliability. This significantly shortens the test time for the target chip, making eye diagram-based testing methods suitable for mass production testing of chips. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic flowchart of a chip testing method provided in one embodiment of this application.

[0014] Figure 2 This is a schematic diagram of an eye diagram and its boundary provided in an embodiment of this application.

[0015] Figure 3 This is a schematic diagram showing the superimposed results of multiple eye diagram scans of a sample chip provided in an embodiment of this application.

[0016] Figure 4 This is a schematic flowchart of a chip testing method provided in another embodiment of this application.

[0017] Figure 5 This is a detailed flowchart illustrating a chip testing method provided in another embodiment of this application.

[0018] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0019] Figure 7 This is a schematic diagram of the structure of a chip testing device provided in one embodiment of this application.

[0020] Figure 8 This is a schematic diagram of the structure of a chip testing device provided in another embodiment of this application. Detailed Implementation

[0021] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in one or more embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the protection scope of this document.

[0022] The terms "first," "second," etc., used in this application and claims are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, in this application and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0023] As mentioned above, with the continuous increase in chip size, the number of dies in chips using co-packaging technology also increases, making the testing of die-to-die (DTD) IP increasingly critical. To overcome the shortcomings of traditional IP inner-loop testing, the industry has proposed a novel DTD IP testing method based on eye diagram scanning. This method scans a two-dimensional plane composed of decision voltage (Vref) and sampling time / sampling edge position (Digital Delay Locked Loop, DCDL), and depicts the boundaries and shape of the eye diagram based on the test results (pass / fail) of inter-die connectivity, thereby evaluating the performance of the DTD link. Typically, an eye diagram is a statistical graph resembling an eye, formed by segmenting and superimposing digital signals in time. Its opening degree intuitively reflects signal quality: a clearly open "eye" represents high-quality transmission, while a closed and blurry "eye" indicates a high risk of bit errors.

[0024] However, traditional DTD IP testing methods based on eye diagram scanning typically require dense two-dimensional scanning with fixed, small step sizes (e.g., step size 1) within a preset first scan range (i.e., a large range of decision voltage and sampling time) to accurately locate the eye diagram boundaries. While this "full-range, small-step" scanning strategy yields accurate results, it results in an extremely large number of test points, making the testing time for a single chip too long and failing to meet the stringent efficiency requirements of mass production testing scenarios.

[0025] The testing time for a chip depends primarily on two factors: the number of test points and the testing time for each test point. Since reducing the testing time for each test point (e.g., reducing data transmission and reception) introduces risks to the reliability of test results, reducing the total number of test points becomes the main direction for optimizing testing time.

[0026] In view of this, this application proposes a chip testing method, apparatus, and computer-readable storage medium. The method can be executed by an electronic device or software installed in an electronic device. The electronic device includes, but is not limited to, any one of the following smart devices: smartphones, personal computers (PCs), laptops, tablets, e-readers, smart TVs, wearable devices, etc.

[0027] The following description, in conjunction with the accompanying drawings, illustrates a chip testing method provided in an embodiment of this application.

[0028] One embodiment of this application provides a chip testing method that can be applied to testing equipment, such as... Figure 1 As shown, the method may include: Step 101: Obtain at least one eye diagram scan result of at least one sample chip, wherein each eye diagram scan result is obtained by scanning mutually orthogonal decision voltages and sampling times within a first scan range, the decision voltages being used to determine inter-crystal connectivity.

[0029] In this embodiment, the eye diagram scan of the chip refers to the process of scanning and testing the DTD connectivity of the chip within a set scanning range consisting of a decision voltage and a sampling time, using a preset step size. The test result is the eye diagram scan result of the chip. Plotting the eye diagram scan result on a two-dimensional plane corresponding to the scanning range yields the eye diagram of the chip.

[0030] Before optimizing the number of test points on the chip, it's essential to first understand the overall eye diagram of the chip using a small number of chips. To achieve this, during the early engineering debugging phase, a small number of chips can be selected as sample chips. Within the existing scan range and step size, these sample chips can undergo two-dimensional eye diagram scans at the decision voltage (Vref) and sampling time (DCDL), obtaining at least one eye diagram scan result for at least one sample chip. In the chip's eye diagram scan results, the inter-die connectivity test results are typically represented as "Pass" or "Fail," used to depict the shape of the eye diagram.

[0031] The original scanning range is the first scanning range. This first scanning range can be a pre-defined, large scanning range that covers all possible eye diagram boundaries to ensure that the complete eye diagram of the sample chip can be captured. The first scanning range is a relatively larger scanning range before optimizing the number of test points.

[0032] In some embodiments, to ensure that the second scan range selected later is suitable for all chips as much as possible, eye diagram scans can be performed on sample chips at different process corners within the first scan range to obtain a complete view of the eye diagrams of sample chips under various processes. In this case, in step 101, obtaining at least one eye diagram scan result of at least one sample chip may include: obtaining eye diagram scan results of at least one sample chip at at least one process corner to obtain at least one eye diagram scan result.

[0033] In some embodiments, to further ensure that the second scan range selected later is suitable for all chips as much as possible, the number of sample chips at each process angle can be multiple, for example, 2-3 chips.

[0034] In some embodiments, process corners may include, but are not limited to, extreme cases of semiconductor manufacturing processes such as typical (TT), fast (FF), and slow (SS).

[0035] It is understandable that by performing a complete two-dimensional eye diagram scan on multiple sample chips (e.g., 2-3 chips at each process angle) under various process angles, representative data reflecting chip performance fluctuations can be collected.

[0036] Step 102: Based on the at least one eye map scan result, determine a second scan range formed by the eye map boundary of the at least one sample chip, wherein the second scan range is smaller than the first scan range and the second scan range is a part of the first scan range.

[0037] The eye diagram boundary is the boundary of the open area of ​​the eye diagram; it is the dividing line between the "error-free region" and the "error-prone region".

[0038] In some embodiments, an eye diagram typically has two eye diagram boundaries: an upper boundary and a lower boundary. Sometimes an eye diagram contains four eye diagram boundaries: an upper boundary, a lower boundary, a left boundary, and a right boundary. Connecting all the eye diagram boundaries in an eye diagram defines a closed eye opening region. The eye opening region is the connected region formed on a two-dimensional plane by all points with a test result of "Pass," and its boundary is formed by the intersection of "Pass" and "Fail."

[0039] For example, such as Figure 2 The eye diagram shown has the boundary line between the red and green squares. The green-filled squares inside the eye diagram boundary represent the eye opening area, which are the test points that pass. The red-filled squares outside the eye diagram boundary represent the test points that fail.

[0040] It is understandable that after obtaining the eye diagram scan results of the sample chips, the test points corresponding to the eye diagram boundaries in the eye diagram scan results of each sample chip are statistically analyzed to obtain the second scan range formed by the eye diagram boundaries of the sample chips.

[0041] In some embodiments, step 102 may include: Determine the boundary of the eye opening region in each of the at least one eye map scan results of the at least one sample chip to obtain the eye map boundary in each of the eye map scan results; The scanning ranges corresponding to the eye map boundaries in each of the eye map scanning results are merged to obtain a second scanning range formed by the eye map boundaries of the at least one sample chip.

[0042] In some embodiments, merging the scanning ranges corresponding to the eye map boundaries in each eye map scan result to obtain a second scanning range formed by the eye map boundaries of the at least one sample chip may include: taking the test point located outside the boundary point of each eye map boundary (such as upper, lower, left, and right) in each eye map scan result as the reference boundary point, and then appropriately expanding a certain number of test points outward based on this reference to jointly form a safe and reliable second scanning range.

[0043] As an example, after obtaining eye diagram scan results for some sample chips at different process angles, eye diagrams for these sample chips are drawn based on these scan results, and the eye diagrams of these sample chips are superimposed. The superimposed result can be referenced. Figure 3 .exist Figure 3 In the diagram, the test points corresponding to the red squares are the test points where all sample chips failed, the test points corresponding to the green squares are the test points where all sample chips passed, and the test points corresponding to the white squares are the test points where some sample chips passed but others failed. The approximate range of the eye diagram boundary of all sample chips can be found by referring to the test points corresponding to the white squares.

[0044] As a concrete example, such as Figure 3 As shown, taking the left boundary of the eye diagram as an example, the scanning range that can ensure all chips can be scanned includes the scanning points with horizontal coordinate 8 and vertical coordinates 13 to 15. However, to ensure the reliability and accuracy of the test results, a wider scanning range is generally reserved as the boundary scanning range, for example, using vertical coordinates 13 to 15 and horizontal coordinates 7 to 9 as the boundary scanning range. It can be understood that an eye diagram has four boundaries: top, bottom, left, and right. Therefore, by finding the four boundary scanning ranges and merging them, a second scanning range that can be used for mass production testing can be obtained.

[0045] It is easy to understand that the second scanning range determined by the above method is much smaller than the first scanning range, and the second scanning range is sufficient to cover the eye diagram boundaries of all sample chips. Therefore, if the inter-die connectivity of the target chip is tested within the second scanning range, the number of test points for the target chip can be greatly reduced without sacrificing test accuracy and result reliability, thereby significantly shortening the test time of the target chip. This allows the eye diagram-based testing method to be used as a formal testing method in mass production testing.

[0046] Step 103: Within the second scanning range, test the inter-die connectivity of the target chip.

[0047] In some embodiments, the target chip may be a chip undergoing mass production testing, and the number of target chips may be multiple.

[0048] In some embodiments, step 103 may include: scanning the decision voltage and sampling time within the second scanning range at a fixed scanning step size to obtain the eye diagram boundary scan result of the target chip. The scanning step sizes corresponding to the decision voltage and sampling time may be the same or different.

[0049] In some embodiments, during actual testing, due to variations in chip manufacturing processes, the range of eye diagram boundaries often varies significantly between different chips. Therefore, even if the number of scan points is reduced by adjusting the eye diagram boundary range, the actual testing time may still be too long. In view of this, the number of test points can be further reduced by optimizing the scan step size. At this point, step 103 may include: For the target chip, within the second scanning range, the decision voltage and sampling time are scanned in a step-by-step scanning manner to obtain the eye diagram boundary scan result of the target chip. The step-by-step scanning includes scanning the decision voltage and sampling time using at least two different scan step sizes, with the scan step size used in the next scan being less than or equal to the scan step size used in the previous scan, and the minimum scan step size being no less than 1.

[0050] As an example, within the second scanning range, scanning the decision voltage and sampling time in a step-by-step scanning manner to obtain the eye diagram boundary scan result of the target chip may include: First scan: Within the second scan range, a sparser two-dimensional scan is performed using a larger scan step size (e.g., a step size of 5) to quickly locate the approximate area of ​​the eye diagram boundary.

[0051] Second scan: Within the approximate boundary area found in the first scan, a fine scan is performed using a medium scan step size (e.g., a step size of 3 or 2) to further narrow down the location range of the eye diagram boundary.

[0052] Third scan: Within the smaller area determined by the second scan, a finer scan is performed using a smaller scan step size (e.g., a step size of 1) to finally find the precise eye diagram boundary.

[0053] Understandably, this step-by-step scanning strategy, which proceeds from coarse to fine, can eliminate a large number of irrelevant test points in the internal "Pass" area and the external "Fail" area compared to performing a full scan with a smaller scan step size directly in the second scan range. This greatly reduces the total number of test points while ensuring the accuracy of the final boundary positioning.

[0054] In some embodiments, the chip testing method proposed in this application may further include: Step 104: Based on the eye diagram boundary scan results of the target chip, determine whether the inter-die connectivity test of the target chip has passed.

[0055] In one implementation, step 104 may include: Based on the eye diagram boundary scan results of the target chip, determine whether all eye diagram boundaries of the target chip can be obtained; Once all eye diagram boundaries of the target chip are obtained, the inter-die connectivity test of the target chip is confirmed to be passed. At this point, the testing process for the target chip can be terminated.

[0056] In another implementation, step 104 may include: Based on the eye diagram boundary scan results, determine whether all eye diagram boundaries of the target chip can be obtained; If all eye diagram boundaries of the target chip are available, the bit error rate of the target chip is tested based on all eye diagram boundaries of the target chip. If the bit error rate of the target chip meets a first preset condition, the inter-die connectivity test of the target chip is deemed to have passed. The first preset condition can be lower than a preset first threshold.

[0057] As an example, testing the bit error rate of a target chip based on all eye diagram boundaries can include: Based on all eye diagram boundaries of the target chip, determine the eye diagram center information of the target chip, where the eye diagram center information includes the decision voltage and sampling time corresponding to the eye diagram center; The eye diagram center information is written into the target chip, and the bit error rate of the target chip is tested after writing to obtain the bit error rate of the target chip.

[0058] For example, the midpoint of the upper and lower boundaries of the eye diagram of the target chip can be taken as the center decision voltage, and the midpoint of the left and right boundaries can be taken as the center sampling time. Then, the eye diagram center information is written into the corresponding configuration register of the target chip, and the bit error rate is tested on the target chip after the configuration is completed to obtain the bit error rate of the target chip.

[0059] Furthermore, considering that process variations may cause the eye diagram boundaries of individual target chips to fall outside the preset second scanning range, or that the target chip itself is a defective chip (without an eye diagram), the method also needs to include an anomaly handling process: based on the eye diagram boundary scanning results, determine whether all eye diagram boundaries of the target chip can be obtained; if not all eye diagram boundaries of the target chip are obtained, it indicates that all eye diagram boundaries of the target chip were not successfully scanned within the second scanning range. In this case, as a supplementary testing measure, such as... Figure 4 As shown, in the event that not all eye diagram boundaries of the target chip can be obtained, the chip testing method proposed in this application embodiment may further include: Step 105: Perform an eye diagram scan on the target chip within the first scanning range to obtain the eye diagram scan result of the target chip.

[0060] Step 106: Based on the eye diagram scan results of the target chip, determine whether the eye opening region in the eye diagram of the target chip meets the second preset condition. If it does, proceed to step 107; otherwise, proceed to step 109.

[0061] The second preset condition can be used to determine whether the target chip test passes. For example, the first preset condition may include, but is not limited to, at least one of the following: Does the target chip's eye diagram contain an open eye region? Is the area of ​​the eye diagram opening region of the target chip greater than the preset area? Is the distance between the upper and lower boundaries of the eye diagram of the target chip greater than the first distance? Is the distance between the left and right boundaries of the eye diagram of the target chip greater than the second distance? Whether the eye diagram shape of the target chip is regular, etc.

[0062] Step 107: Confirm that the inter-die connectivity test of the target chip has passed.

[0063] Step 109: Determine that the target chip is a faulty chip (bad chip).

[0064] In some embodiments, such as Figure 4 As shown, after step 107, the chip testing method proposed in this application embodiment may further include: Step 108: Add the eye diagram scan result of the target chip to the eye diagram scan result of the at least one sample chip to update the second scan range so that it can better adapt to actual process fluctuations.

[0065] In this embodiment, by acquiring eye diagram scan results of at least one sample chip within a large first scan range, a relatively small second scan range is determined based on these results. The second scan range is formed by the eye diagram boundaries of the at least one sample chip. Subsequently, for the target chip to be tested, inter-die connectivity testing is performed within the second scan range. Because the scan range is reduced and covers possible eye diagram boundaries, this chip testing scheme can significantly reduce the number of test points for the target chip without sacrificing test accuracy and result reliability. This significantly shortens the test time for the target chip, making eye diagram-based testing methods applicable to mass production testing of chips and improving mass production testing efficiency.

[0066] The following is combined with Figure 5 A chip testing method proposed in this application will be described in detail through an example.

[0067] like Figure 5 As shown in the embodiments of this application, a chip testing method may include the following detailed process: Phase 1: Data Collection and Scope Learning Step 501: During the engineering debugging phase, select multiple sample chips covering various process angles.

[0068] For example, select 2-3 chips as sample chips for each process corner.

[0069] Step 502: Perform a complete two-dimensional eye diagram scan on each sample chip within the first scanning range, record the test results of each test point, and obtain the eye diagram scan results of each sample chip.

[0070] Step 503: Based on the eye diagram scan results of each sample chip, determine the second scan range formed by the eye diagram boundary of the sample chip.

[0071] For example, for each eye map boundary (such as top, bottom, left, right) in the eye map scan results of each sample chip, take the test point located outside the boundary as the reference boundary point, and then appropriately expand a certain number of test points outward based on this as the reference to form the second scan range.

[0072] Phase Two: Testing of the Target Chip for Mass Production Step 504: For the target chip, within the second scanning range, the decision voltage and sampling time are scanned in a step-by-step scanning manner to obtain the eye diagram boundary scan result of the target chip.

[0073] The step-by-step scanning includes scanning the decision voltage and the sampling time using at least two different scanning step sizes, and the scanning step size used in the next scan is less than or equal to the scanning step size used in the previous scan, with the minimum scanning step size not less than 1.

[0074] Step 505: Based on the eye diagram boundary scan results of the target chip, determine whether all eye diagram boundaries of the target chip can be obtained. If yes, proceed to step 506; otherwise, proceed to step 508.

[0075] Step 506: Test the bit error rate of the target chip based on all eye diagram boundaries of the target chip.

[0076] Step 507: If the bit error rate of the target chip meets the first preset condition, determine that the inter-die connectivity test of the target chip has passed.

[0077] Step 508: Perform an eye diagram scan on the target chip within the first scanning range to obtain the eye diagram scan result of the target chip.

[0078] Step 509: Based on the eye diagram scan results of the target chip, determine whether the eye opening region in the eye diagram of the target chip meets the second preset condition. If it does, proceed to step 510; otherwise, proceed to step 511.

[0079] Step 510 confirms that the inter-die connectivity test of the target chip has passed. Then proceed to step 512.

[0080] Step 511: Determine that the target chip is a faulty chip (bad chip).

[0081] Step 512: Add the eye diagram scan result of the target chip to the eye diagram scan result of the at least one sample chip to update the second scan range.

[0082] This application proposes a chip testing method that utilizes eye diagram scan results from sample chips under multiple process angles collected during the early engineering debugging phase to determine a second scan range that is much smaller than the original scan range and has a high probability of covering the eye diagram boundary. Then, within this second scan range, a step-by-step scanning strategy from coarse to fine is employed to test the target chip for mass production. This approach works synergistically from two dimensions: "reducing the scan range" and "optimizing the scan step size." Without sacrificing test results, it significantly reduces the number of test points, thereby significantly shortening the test time for the target chip and improving test efficiency. This makes high-precision DTD IP testing based on eye diagram scanning applicable to mass production testing scenarios.

[0083] The foregoing has described specific embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0084] Figure 6 This is a schematic diagram of the structure of an electronic device provided in one embodiment of this application. Please refer to it. Figure 6 At the hardware level, the electronic device includes a processor, and optionally also includes an internal bus, a network interface, and memory. The memory may include main memory, such as high-speed random-access memory (RAM), or non-volatile memory, such as at least one disk drive. Of course, the electronic device may also include other hardware required for other business operations.

[0085] The processor, network interface, and memory can be interconnected via an internal bus, which can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. This bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 6 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0086] Memory is used to store programs. Specifically, programs may include program code, which includes computer operation instructions. Memory may include main memory and non-volatile memory, and provides instructions and data to the processor.

[0087] The processor reads the corresponding computer program from non-volatile memory into memory and then executes it, forming a chip testing device at the logical level. The processor is configured to execute the instructions to implement the chip testing method described above.

[0088] The above is as stated in this application. Figure 6 The method executed by the chip testing apparatus disclosed in the illustrated embodiments can be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software module can reside in a mature storage medium in the field, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0089] The electronic device can also perform Figure 1 The method, and the implementation of the chip testing device in Figure 1 The functions described in the illustrated embodiments will not be repeated here.

[0090] Of course, in addition to software implementation, the electronic device of this application does not exclude other implementation methods, such as logic devices or a combination of hardware and software, etc. In other words, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0091] This application also proposes a computer-readable storage medium, which, when the instructions in the storage medium are executed by the processor of an electronic device, enables the electronic device to perform the chip testing method described above.

[0092] This application also proposes a computer program product including instructions, characterized in that when a computer runs the instructions of the computer program product, the computer executes the chip testing method as described above.

[0093] Figure 7 This is a schematic diagram of the structure of a chip testing apparatus 700 according to an embodiment of this application. Please refer to it. Figure 7 In one software implementation, the chip testing device 700 may include: a data acquisition module 701, a scanning range determination module 702, and a first testing module 703.

[0094] The data acquisition module 701 is used to acquire at least one eye diagram scan result of at least one sample chip, wherein each eye diagram scan result is obtained by scanning mutually orthogonal decision voltages and sampling times within a first scan range, and the decision voltage is used to determine the inter-crystal connectivity.

[0095] In this embodiment, the eye diagram scan of the chip refers to the process of scanning and testing the DTD connectivity of the chip within a set scanning range consisting of a decision voltage and a sampling time, using a preset step size. The test result is the eye diagram scan result of the chip. Plotting the eye diagram scan result on a two-dimensional plane corresponding to the scanning range yields the eye diagram of the chip.

[0096] Before optimizing the number of test points on the chip, it's essential to first understand the overall eye diagram of the chip using a small number of chips. To achieve this, during the early engineering debugging phase, a small number of chips can be selected as sample chips. Within the existing scan range and step size, these sample chips can undergo two-dimensional eye diagram scans at the decision voltage (Vref) and sampling time (DCDL), obtaining at least one eye diagram scan result for at least one sample chip. In the chip's eye diagram scan results, the inter-die connectivity test results are typically represented as "Pass" or "Fail," used to depict the shape of the eye diagram.

[0097] The original scanning range is the first scanning range. This first scanning range can be a pre-defined, large scanning range that covers all possible eye diagram boundaries to ensure that the complete eye diagram of the sample chip can be captured. The first scanning range is a relatively larger scanning range before optimizing the number of test points.

[0098] In some embodiments, to ensure that the second scan range selected later is suitable for all chips as much as possible, eye diagram scans can be performed on sample chips at different process corners within the first scan range to obtain a complete view of the eye diagrams of sample chips under various processes. In this case, the data acquisition module 701 can be specifically used to acquire the eye diagram scan results of at least one sample chip at at least one process corner.

[0099] In some embodiments, to further ensure that the second scan range selected later is suitable for all chips as much as possible, the number of sample chips at each process angle can be multiple, for example, 2-3 chips.

[0100] In some embodiments, process corners may include, but are not limited to, extreme cases of semiconductor manufacturing processes such as typical (TT), fast (FF), and slow (SS).

[0101] It is understandable that by performing a complete two-dimensional eye diagram scan on multiple sample chips (e.g., 2-3 chips at each process angle) under various process angles, representative data reflecting chip performance fluctuations can be collected.

[0102] The scanning range determination module 702 can be used to determine a second scanning range formed by the eye map boundary of the at least one sample chip based on the at least one eye map scanning result, wherein the second scanning range is smaller than the first scanning range and the second scanning range is a part of the first scanning range.

[0103] The eye diagram boundary is the boundary of the open area of ​​the eye diagram; it is the dividing line between the "error-free region" and the "error-prone region".

[0104] In some embodiments, an eye diagram typically has two eye diagram boundaries: an upper boundary and a lower boundary. Sometimes an eye diagram contains four eye diagram boundaries: an upper boundary, a lower boundary, a left boundary, and a right boundary. Connecting all the eye diagram boundaries in an eye diagram defines a closed eye opening region. The eye opening region is the connected region formed on a two-dimensional plane by all points with a test result of "Pass," and its boundary is formed by the intersection of "Pass" and "Fail."

[0105] In some embodiments, the scanning range determination module 702 can be used to: determine the boundary of the eye opening region in each eye scan result; and merge the scanning ranges corresponding to the eye map boundaries in each eye scan result to obtain the second scanning range.

[0106] In some embodiments, merging the scanning ranges corresponding to the eye map boundaries in each eye map scan result to obtain a second scanning range formed by the eye map boundaries of the at least one sample chip may include: taking the test point located outside the boundary point of each eye map boundary (such as upper, lower, left, and right) in each eye map scan result as the reference boundary point, and then appropriately expanding a certain number of test points outward based on this reference to jointly form a safe and reliable second scanning range.

[0107] It is easy to understand that the second scanning range determined by the above method is much smaller than the first scanning range, and the second scanning range is sufficient to cover the eye diagram boundaries of all sample chips. Therefore, if the inter-die connectivity of the target chip is tested within the second scanning range, the number of test points for the target chip can be greatly reduced without sacrificing test accuracy and result reliability, thereby significantly shortening the test time of the target chip. This allows the eye diagram-based testing method to be used as a formal testing method in mass production testing.

[0108] The first test module 703 can be used to test the inter-die connectivity of the target chip within the second scan range.

[0109] In some embodiments, the target chip may be a chip undergoing mass production testing, and the number of target chips may be multiple.

[0110] In some embodiments, the first test module 703 can be used to: scan the decision voltage and sampling time within a second scan range at a fixed scan step size to obtain the eye diagram boundary scan result of the target chip. The scan step sizes corresponding to the decision voltage and sampling time can be the same or different.

[0111] In some embodiments, during actual testing, due to variations in chip manufacturing processes, the range of eye diagram boundaries often fluctuates significantly between different chips. Therefore, even if the number of scan points is reduced by adjusting the eye diagram boundary range, the actual testing time may still be too long. In view of this, the number of test points can be further reduced by optimizing the scan step size. In this case, the first test module 703 can be used to: scan the decision voltage and sampling time within the second scan range for the target chip using a step-by-step scanning method to obtain the eye diagram boundary scan result of the target chip. The step-by-step scanning includes scanning the decision voltage and sampling time using at least two different scan step sizes, with the scan step size used in the next scan being less than or equal to the scan step size used in the previous scan, and the minimum scan step size being not less than 1.

[0112] In some embodiments, such as Figure 8 As shown in the embodiments of this application, a chip testing device 700 may further include: a first judgment module 704, used to determine whether the inter-die connectivity test of the target chip has passed based on the eye diagram boundary scan results of the target chip.

[0113] As one implementation method, the first determination module 704 can be used for: Based on the eye diagram boundary scan results of the target chip, determine whether all eye diagram boundaries of the target chip can be obtained; If all eye diagram boundaries of the target chip are available, the inter-die connectivity test of the target chip is confirmed to be passed.

[0114] As one implementation method, the first determination module 704 can be used for: Based on the eye diagram boundary scan results, determine whether all eye diagram boundaries of the target chip can be obtained; If all eye diagram boundaries of the target chip are available, the bit error rate of the target chip is tested based on all eye diagram boundaries of the target chip. If the bit error rate of the target chip meets a first preset condition, the inter-die connectivity test of the target chip is deemed to have passed. The first preset condition can be lower than a preset first threshold.

[0115] As an example, testing the bit error rate of a target chip based on all eye diagram boundaries can include: Based on all eye diagram boundaries of the target chip, determine the eye diagram center information of the target chip, where the eye diagram center information includes the decision voltage and sampling time corresponding to the eye diagram center; The eye diagram center information is written into the target chip, and the bit error rate of the target chip is tested after writing to obtain the bit error rate of the target chip.

[0116] For example, the midpoint of the upper and lower boundaries of the eye diagram of the target chip can be taken as the center decision voltage, and the midpoint of the left and right boundaries can be taken as the center sampling time. Then, the eye diagram center information is written into the corresponding configuration register of the target chip, and the bit error rate is tested on the target chip after the configuration is completed to obtain the bit error rate of the target chip.

[0117] Furthermore, considering that process variations may cause the eye diagram boundaries of individual target chips to fall outside the preset second scanning range, or that the target chip itself is a defective chip (without an eye diagram), the method also needs to include an anomaly handling process: based on the eye diagram boundary scanning results, determine whether all eye diagram boundaries of the target chip can be obtained; if not all eye diagram boundaries of the target chip are obtained, it indicates that all eye diagram boundaries of the target chip were not successfully scanned within the second scanning range. In this case, as a supplementary testing measure, such as... Figure 8 As shown in the embodiments of this application, a chip testing apparatus 700 may further include: The second test module 705 is used to perform an eye diagram scan on the target chip within the first scan range when not all eye diagram boundaries of the target chip are obtained, so as to obtain the eye diagram scan result of the target chip.

[0118] The second determination module 706 is used to determine whether the eye opening region in the eye diagram of the target chip meets the second preset condition based on the eye diagram scanning result of the target chip. If it meets the condition, the first determination module 707 can be triggered; otherwise, the second determination module 708 can be triggered.

[0119] The second preset condition can be used to determine whether the target chip test passes. For example, the first preset condition may include, but is not limited to, at least one of the following: Does the target chip's eye diagram contain an open eye region? Is the area of ​​the eye diagram opening region of the target chip greater than the preset area? Is the distance between the upper and lower boundaries of the eye diagram of the target chip greater than the first distance? Is the distance between the left and right boundaries of the eye diagram of the target chip greater than the second distance? Whether the eye diagram shape of the target chip is regular, etc.

[0120] The first determining module 707 is used to determine whether the inter-die connectivity test of the target chip has passed.

[0121] The second determination module 708 is used to determine that the target chip is a faulty chip (bad chip).

[0122] In some embodiments, such as Figure 8As shown in the embodiments of this application, a chip testing apparatus 700 may further include: an update module 709, used to add the eye diagram scan result of the target chip to the eye diagram scan result of the at least one sample chip, so as to update the second scan range and make it better adapt to actual process fluctuations.

[0123] In this embodiment, by acquiring eye diagram scan results of at least one sample chip within a large first scan range, a relatively small second scan range is determined based on these results. The second scan range is formed by the eye diagram boundaries of the at least one sample chip. Subsequently, for the target chip to be tested, inter-die connectivity testing is performed within the second scan range. Because the scan range is reduced and covers possible eye diagram boundaries, this chip testing scheme can significantly reduce the number of test points for the target chip without sacrificing test accuracy and result reliability. This significantly shortens the test time for the target chip, making eye diagram-based testing methods applicable to mass production testing of chips and improving mass production testing efficiency.

[0124] The chip testing device 700 provided in this application embodiment can also perform... Figure 1 The method, and implementation Figure 1 The embodiments shown in this application have the same functions and achieve the same technical effects, and will not be described in detail here.

[0125] In summary, the above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

[0126] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0127] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0128] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0129] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

Claims

1. A chip testing method, characterized in that, The method includes: At least one eye diagram scan result of at least one sample chip is obtained, wherein each eye diagram scan result is obtained by scanning mutually orthogonal decision voltages and sampling times within a first scan range, the decision voltages being used to determine inter-crystal connectivity; Based on the at least one eye map scan result, a second scan range is determined to form the eye map boundary of the at least one sample chip, wherein the second scan range is smaller than the first scan range, and the second scan range is a part of the first scan range; Within the second scan range, the inter-die connectivity of the target chip is tested.

2. The method according to claim 1, characterized in that, The acquisition of at least one eye diagram scan result of at least one sample chip includes: Obtain eye diagram scan results of at least one sample chip at at least one process angle to obtain at least one eye diagram scan result.

3. The method according to claim 1, characterized in that, The step of determining the second scanning range formed by the eye map boundary of the at least one sample chip based on the at least one eye map scan result includes: Determine the boundary of the eye opening region in each of the at least one eye map scan results to obtain the eye map boundary in each eye map scan result; The scanning ranges corresponding to the eye map boundaries in each of the eye map scanning results are merged to obtain a second scanning range formed by the eye map boundaries of the at least one sample chip.

4. The method according to claim 1, characterized in that, The step of testing the inter-die connectivity of the target chip within the second scanning range includes: For the target chip, within the second scanning range, the decision voltage and sampling time are scanned in a step-by-step scanning manner to obtain the eye diagram boundary scanning result of the target chip. The step-by-step scanning includes scanning the decision voltage and sampling time using at least two different scanning step sizes, and the scanning step size used in the next scan is less than or equal to the scanning step size used in the previous scan, with the minimum scanning step size not less than 1.

5. The method according to claim 4, characterized in that, The method further includes: Based on the eye diagram boundary scan results, it is determined whether the inter-die connectivity test of the target chip has passed.

6. The method according to claim 5, characterized in that, The step of determining whether the inter-die connectivity test of the target chip passes based on the eye diagram boundary scan results includes: Based on the eye diagram boundary scan results, determine whether all eye diagram boundaries of the target chip can be obtained; If all eye diagram boundaries of the target chip can be obtained, the inter-die connectivity test of the target chip is deemed to have passed.

7. The method according to claim 5, characterized in that, The step of determining whether the inter-die connectivity test of the target chip passes based on the eye diagram boundary scan results includes: Based on the eye diagram boundary scan results, determine whether all eye diagram boundaries of the target chip can be obtained; If all eye diagram boundaries of the target chip are available, the bit error rate of the target chip is tested based on all eye diagram boundaries. If the bit error rate of the target chip meets the first preset condition, the inter-chip connectivity test of the target chip is determined to be passed.

8. The method according to claim 7, characterized in that, The step of testing the bit error rate of the target chip based on all eye diagram boundaries includes: Based on all the eye diagram boundaries, the eye diagram center information of the target chip is determined, wherein the eye diagram center information includes the decision voltage and the sampling time corresponding to the eye diagram center; The eye diagram center information is written into the target chip, and the bit error rate of the target chip is tested after writing to obtain the bit error rate of the target chip.

9. The method according to claim 4, characterized in that, The step of determining whether the inter-die connectivity test of the target chip passes based on the eye diagram boundary scan results includes: Based on the eye diagram boundary scan results, determine whether all eye diagram boundaries of the target chip can be obtained; If not all eye diagram boundaries of the target chip are obtained, an eye diagram scan is performed on the target chip within the first scan range to obtain the eye diagram scan result of the target chip; Based on the eye diagram scanning results of the target chip, determine whether the eye opening region in the eye diagram of the target chip meets the second preset condition; If the eye opening region in the eye diagram of the target chip meets the second preset condition, the inter-die connectivity test of the target chip is determined to be passed.

10. The method according to claim 9, characterized in that, The method further includes: If the eye opening region in the eye diagram of the target chip meets the second preset condition, the eye diagram scan result of the target chip is added to the eye diagram scan result of the at least one sample chip to update the second scan range.

11. The method according to claim 9, characterized in that, The method further includes: If the eye opening area in the eye diagram of the target chip does not meet the second preset condition, the target chip is determined to be a failed chip.

12. An electronic device, characterized in that, include: processor; Memory used to store the processor's executable instructions; The processor is configured to execute the instructions to implement the method as described in any one of claims 1 to 11.

13. A computer-readable storage medium, characterized in that, When the instructions in the storage medium are executed by the processor of the electronic device, the electronic device is able to perform the method as described in any one of claims 1 to 11.

14. A computer program product comprising instructions, characterized in that, When the computer executes the instructions of the computer program product, the computer performs the method as described in any one of claims 1 to 11.

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