Shared cache management method and device

Abstract

The invention relates to a shared cache management method and device. The method comprises the following steps: obtaining throughput data of each transmission queue in a shared cache; the shared cache comprises ports used for data reading and writing, the number of the ports is equal to that of the queues, and each transmission queue independently has a port with the highest reading and writing priority; receiving a read-write operation instruction, and if the throughput data represents that the throughput of each transmission queue is balanced, performing equal queue data read-write by adopting the port with the highest read-write priority; if the throughput data represents that the throughput of each transmission queue is unbalanced, queue sequence information is obtained; and performing data read-write on the shared cache according to the queue sequence information, the read-write operation instruction and the port. By adopting the method, the utilization rate of the cache space can be improved, a higher queue transmission bandwidth upper limit is obtained, and the high utilization rate of the total transmission upper limit bandwidth is ensured.

Description

Technical Field

[0001] This application relates to the field of data communication technology, and in particular to a shared cache management method and apparatus. Background Technology

[0002] The continuous increase in processor speed and storage capacity in computers has laid the foundation for high-performance computing. However, with the ongoing pursuit of high-performance and cost / power-efficient processor designs, the rhythm between computing, storage, and interconnect has become unbalanced: after processor and storage capacity soared according to Moore's Law, the I / O rate between processor and storage quickly became a bottleneck. How to provide data transfer performance under appropriate hardware and power budget has become an important issue.

[0003] Currently, existing shared cache scheduling schemes manage the cache uniformly and dynamically allocate cache space based on the current cache requirements of each queue. However, due to their lack of flexibility in multi-queue bandwidth management, they can only provide the maximum transmission bandwidth of their own cache to each queue in practical scenarios. This fails to address situations with uneven data volume or high bursts of data, where some queues have idle cache space while other queues still have to use their own cache queues, resulting in a constant maximum transmission bandwidth for each queue. This can lead to a decrease in total effective bandwidth / insufficient space, resulting in performance degradation and a reduction in the overall system's utilization of cache resources. Furthermore, the temporal and spatial locality of task generation and processing in applications / CPUs leads to uneven data transmission between tasks. Summary of the Invention

[0004] Therefore, it is necessary to provide a shared cache management method and apparatus that can dynamically provide high-bandwidth temporary data storage access for multiple queues in any data transmission path that requires data caching, in order to address the above-mentioned technical problems.

[0005] Firstly, this application provides a shared cache management method, including:

[0006] Obtain throughput data for each transmission queue in the shared cache; the shared cache contains a number of ports for data reading and writing equal to the number of queues, and each transmission queue independently has a port with the highest read / write priority;

[0007] Upon receiving read / write operation instructions, if the throughput data indicates that the throughput of each transmission queue is balanced, then the port with the highest read / write priority is used to perform equal queue data read / write.

[0008] If the throughput data indicates that the throughput of each transmission queue is uneven, then the queue order information is obtained.

[0009] Data is read and written to the shared cache according to the queue order information, the read and write operation instructions, and the port.

[0010] In one embodiment, the step of using the port with the highest read / write priority for equal queue data read / write includes:

[0011] When the bandwidth speedup ratio of each of the transmission queues is the same, data read and write operations are performed on the shared cache according to the port with the highest read / write priority corresponding to each of the transmission queues and the read / write operation instructions.

[0012] In one embodiment, obtaining the queue order information includes:

[0013] Get queue status information and queue head and tail address information;

[0014] The queue order information is determined based on the queue status information and the queue head and tail address information.

[0015] In one embodiment, the step of reading and writing data to the shared cache according to the queue order information, the read / write operation instructions, and the port includes:

[0016] Select target port data from the port according to the queue order information and the read / write operation instructions;

[0017] The shared cache is read and written according to the target port data and the read / write operation instructions.

[0018] In one embodiment, both the port and the shared buffer can be shared by any transmission channel, and the method further includes:

[0019] If there is an idle queue in the transmission queue, the port corresponding to the idle queue is set to a shared state; wherein the port in the shared state can be used by other queues.

[0020] In one embodiment, the method further includes:

[0021] Obtain the cache usage status of each of the transmission queues in the shared cache;

[0022] Based on the cache usage, bubble settings are applied to each of the transmission queues to obtain queue bubbles;

[0023] Flow control is performed on each of the transmission queues based on the queue bubble; wherein each queue bubble cannot be shared by other queues.

[0024] Secondly, this application also provides a shared cache management device, comprising:

[0025] The first acquisition module is used to acquire throughput data of each transmission queue in the shared cache; the shared cache contains a number of ports for data reading and writing equal to the number of queues, and each transmission queue independently has a port with the highest read and write priority;

[0026] The balanced read / write module is used to receive read / write operation instructions. If the throughput data indicates that the throughput of each transmission queue is balanced, then the port with the highest read / write priority is used to perform equal queue data read / write.

[0027] The second acquisition module is used to acquire queue order information if the throughput data indicates that the throughput of each transmission queue is unbalanced.

[0028] An unbalanced read / write module is used to read and write data to the shared cache according to the queue order information, the read / write operation instructions, and the port.

[0029] In one embodiment, the balanced read / write module is further configured to perform data read / write on the shared cache according to the port with the highest read / write priority corresponding to each of the transmission queues and the read / write operation instruction, provided that the bandwidth speedup ratio of each of the transmission queues is the same.

[0030] In one embodiment, the second acquisition module is further configured to acquire queue status information and queue head and tail address information; and determine the queue order information based on the queue status information and the queue head and tail address information.

[0031] In one embodiment, the unbalanced read / write module is further configured to select target port data from the ports according to the queue order information and the read / write operation instructions; and to perform data read / write on the shared cache according to the target port data and the read / write operation instructions.

[0032] In one embodiment, the port and the shared buffer can be shared by any transmission channel, and the device further includes: a port sharing module, used to set the port corresponding to the idle queue to a shared state when there is an idle queue in the transmission queue; wherein the port in the shared state can be used by other queues.

[0033] In one embodiment, the apparatus further includes: a bubble flow control module, configured to acquire the cache usage status of each of the transmission queues in the shared cache; set bubbles for each of the transmission queues according to the cache usage status to obtain queue bubbles; and perform flow control on each of the transmission queues according to the queue bubbles; wherein each queue bubble cannot be shared by other queues.

[0034] The aforementioned shared cache management method and apparatus acquire throughput data for each transmission queue in the shared cache. The shared cache contains a number of ports for data reading and writing equal to the number of queues, with each transmission queue independently possessing a port with the highest read / write priority. It receives read / write operation instructions; if the throughput data indicates balanced throughput across transmission queues, it uses the port with the highest read / write priority for equal queue data reading and writing; if the throughput data indicates uneven throughput across transmission queues, it acquires queue order information. Data reading and writing are performed on the shared cache based on the queue order information, read / write operation instructions, and ports. Therefore, by using a shared cache, all queues dynamically share the cache space. In balanced scenarios, equal queue data reading and writing can be achieved based on independent port priority settings. Furthermore, port sharing allows queues to transmit data from the same queue through multiple shared ports in non-uniform scenarios, achieving a higher upper limit for queue transmission bandwidth, ensuring high utilization of the total upper limit bandwidth, and providing a more efficient data transmission method by uniformly managing all ports and cache space. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a diagram illustrating the application environment of a shared cache management method in one embodiment.

[0037] Figure 2 This is a flowchart illustrating a shared cache management method in one embodiment;

[0038] Figure 3 This is a schematic diagram of the bubble flow control process of the shared cache management method in one embodiment;

[0039] Figure 4 This is a schematic diagram of the global address association table of the shared cache management method in another embodiment;

[0040] Figure 5 This is a flowchart illustrating the multi-queue parallel read / write process of the shared cache management method in another embodiment;

[0041] Figure 6 This is a flowchart illustrating the shared cache management method in another embodiment, performing single-queue parallel write and single-queue parallel read operations without port interleaving.

[0042] Figure 7This is a flowchart illustrating the process of performing single-queue parallel write and single-queue parallel read in a shared cache management method under port interleaving conditions, as described in another embodiment.

[0043] Figure 8 This is a flowchart illustrating the single-queue parallel write and single-queue serial read processes of the shared cache management method in another embodiment.

[0044] Figure 9 This is a flowchart illustrating the single-queue serial write and single-queue parallel read processes of the shared cache management method in another embodiment.

[0045] Figure 10 This is a structural block diagram of a shared cache management device in one embodiment. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0047] The shared cache management method provided in this application embodiment can be applied to, for example, Figure 1 In the application environment shown, terminal 102 communicates with server 104 via a network. A data storage system can store the data that server 104 needs to process. The data storage system can be integrated onto server 104 or placed on a cloud or other network server. Server 104 obtains throughput data for each transmission queue in a shared cache; the shared cache contains ports for data reading and writing equal to the number of queues, with each transmission queue independently having a port with the highest read / write priority; it receives read / write operation instructions. If the throughput data indicates that the throughput of each transmission queue is balanced, then the port with the highest read / write priority is used for equal queue data reading and writing; if the throughput data indicates that the throughput of each transmission queue is unbalanced, then the queue order information is obtained; and data is read and written to the shared cache according to the queue order information, read / write operation instructions, and ports. Terminal 102 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices. IoT devices can be smart speakers, smart TVs, smart air conditioners, smart in-vehicle devices, projection devices, etc. Portable wearable devices can be smartwatches, smart bracelets, head-mounted devices, etc. Headset devices can be virtual reality (VR) devices, augmented reality (AR) devices, smart glasses, etc. Server 104 can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud computing services.

[0048] In one exemplary embodiment, such as Figure 2 As shown, a shared cache management method is provided, which is applied to... Figure 1 Taking server 104 as an example, the explanation includes the following steps 202 to 208. Wherein:

[0049] Step 202: Obtain the throughput data of each transmission queue in the shared cache; the shared cache contains a number of ports for data reading and writing equal to the number of queues, and each transmission queue independently has a port with the highest read and write priority.

[0050] The throughput data can be protocol-level data, such as input / output operations per second (IOPS) and bandwidth, or latency data to reflect the effective throughput of the queue, such as average latency, tail latency / percentile latency, CPU utilization, packet loss rate and retransmission rate, and is not limited to these.

[0051] In this shared cache, all cache space can be used by any queue or any port. In subsequent embodiments, the shared cache is implemented in terms of logical structure as N physically contiguous and logically independent caches (N is related to the number of queues). Each transmission queue has an effective cache count in the shared cache. Externally, parallel read operations on the same queue can be initiated based on the value of the effective cache count.

[0052] In some embodiments, it should be noted that the shared cache uses a global cache space status record table and a global address contact table for recording. The global cache space status record table records the status information of which parts of all cache spaces are cached / uncached data. The status of each data cache space is recorded using a 1-bit value, where 1 indicates uncached and 0 indicates cached (or 1 indicates cached and 0 indicates uncached). When a queue writes data to this invention, it selects a space from the uncached cache spaces using the global cache space status record table for temporary data storage and changes the status of this space to cached. When a queue reads data from this invention, the status of the cache space containing the read data is changed to uncached.

[0053] In some embodiments, it is necessary to further explain that, such as Figure 4 As shown, Figure 4The diagram illustrates the storage of a global address-relationship table, which records the subsequent data addresses for each cache address. The location of data in any queue within the shared cache space may be discrete (non-contiguous). A global address-relationship table records the location of the next data entry for a given address space within the shared cache. When a queue writes data to this embodiment, if the previous data entry for that queue is cached within this invention and has not yet been read, the cache address of the current data storage is recorded in the address-relationship table corresponding to the cache address of the previous data entry. Figure 4 In this context, Qm-n represents the nth data item in the mth queue.

[0054] In some embodiments, throughput data of each transmission queue in the shared cache can be obtained based on the record data of the global cache space status record table and the global address association table, or other third-party software tools can be used to obtain throughput data of each transmission queue in the shared cache, and is not limited thereto.

[0055] In some embodiments, both the port and the shared buffer can be shared by any transmission channel. The method further includes setting the port corresponding to the idle queue to a shared state if there is an idle queue in the transmission queue; wherein the port in the shared state can be used by other queues.

[0056] In some embodiments, each input / output port and all buffers of the shared buffer can be shared by any transmission channel; if there is data transmission in each transmission queue, the corresponding read / write port will not be in a shared state; if there is no data transmission in a queue, that is, if there is an idle queue in the transmission queue, the read / write port corresponding to the idle queue is set to a shared state and can be used by other queues.

[0057] In this embodiment, through the design of shared cache and port, all cache space in the shared cache is dynamically shared by all queues, which greatly improves the utilization rate of cache space.

[0058] Step 204: Receive read / write operation instructions. If the throughput data indicates that the throughput of each transmission queue is balanced, then the port with the highest read / write priority is used to perform equal queue data read / write.

[0059] Among them, equal queue data read and write refers to a scenario in which all queues of the cache transmit data evenly, with all queues transmitting the same amount of data. Each queue performs data read / write operations in parallel and independently through its own highest priority port. Read and write operation instructions refer to the instructions that the queue initiates read and write operations to the cache. Read and write operation instructions can be generated based on the actual application scenario requirements, and are not limited to this.

[0060] In some embodiments, using the port with the highest read / write priority for equal queue data read / write includes: when the bandwidth speedup ratio of each transmission queue is the same, performing data read / write on the shared cache according to the port with the highest read / write priority and the read / write operation instruction corresponding to each transmission queue.

[0061] In some embodiments, such as As shown, Figure 5 This diagram illustrates a scenario where all queues (Q1, Q2, Q3, and Q4 in the diagram) transmit the same amount of data in a uniform manner. Each queue performs data read / write operations in parallel and independently through its highest-priority port. In this scenario, each queue and port utilizes the cache space corresponding to its highest read / write priority port equally. At this point, each queue effectively uses the bandwidth on its highest-priority port, resulting in a 1:1 bandwidth speedup ratio for all queues.

[0062] Step 206: If the throughput data indicates that the throughput of each transmission queue is unbalanced, then obtain the queue order information.

[0063] In cases where throughput data represents uneven throughput across transmission queues, i.e., in non-uniform traffic scenarios, a queue can use multiple ports to perform read and write operations in parallel according to actual conditions, providing greater transmission bandwidth and thus achieving a data transmission speedup ratio greater than 1.

[0064] In some embodiments, obtaining queue order information includes: obtaining queue status information and queue head and tail address information; and determining queue order information based on queue status information and queue head and tail address information.

[0065] The queue status information record records the queue status information in this embodiment. Queue status information refers to the presence or absence of data in each queue; 1 indicates presence, and 0 indicates absence. The queue head / tail address record records the head and tail address information of each queue. The head record indicates the position of the first piece of data still cached within this invention in the order of writing to each queue, and the tail record indicates the position of the last piece of data still cached within this embodiment in the order of writing to each queue. When a queue writes data to this invention, its tail record is updated synchronously; when a queue reads data from this invention, its head record is updated synchronously.

[0066] In some embodiments, queue order information, which includes a queue ID and an intra-queue sequence ID (i.e., a sequence ID used independently by each queue), is determined based on queue status information and queue head and tail address information to support the inconsistency between queue data write ports and read ports.

[0067] Step 208: Perform data read and write operations on the shared cache based on the queue order information, read and write operation instructions, and port.

[0068] The queue order information includes a queue ID and an intra-queue sequence ID. If a queue initiates a write operation to the cache, the order of the data being written is communicated by carrying the queue ID and the intra-queue sequence ID (i.e., the sequence ID used independently by each queue). This ID information allows for different queue data write and read ports.

[0069] In some embodiments, performing data read / write operations on a shared cache based on queue order information, read / write operation instructions, and a port includes: selecting target port data from the ports based on queue order information and read / write operation instructions; and performing data read / write operations on the shared cache based on the target port data and read / write operation instructions.

[0070] In some embodiments, such as As shown, This demonstrates that when read / write operation commands are single-queue parallel write and single-queue parallel read, the transmission order of selected ports can be kept consistent based on the queue ID and the sequence ID within the queue.

[0071] In some embodiments, such as As shown, This demonstrates that when read / write operation commands are single-queue parallel write and single-queue parallel read, the port transmission order can be selected differently based on the queue ID and the sequence ID within the queue.

[0072] In some embodiments, such as As shown, This demonstrates that when the read / write operation commands are single-queue parallel write and single-queue serial read, the transmission order of the selected port can be kept consistent based on the queue ID and the sequence ID within the queue.

[0073] In some embodiments, such as As shown, This demonstrates that when the read / write operation commands are single-queue serial write and single-queue parallel read, the transmission order of the selected port can be kept consistent based on the queue ID and the sequence ID within the queue.

[0074] In this embodiment, by selecting target port data from the port according to the queue order information and read / write operation instructions, and performing data read / write on the shared cache according to the target port data and read / write operation instructions, the effect of maintaining the order of data transmission in the same queue can be achieved under any read / write behavior.

[0075] In the aforementioned shared cache management method, the throughput data of each transmission queue in the shared cache is obtained. The shared cache contains a number of ports for data reading and writing equal to the number of queues, with each transmission queue independently having a port with the highest read / write priority. Read / write operation instructions are received. If the throughput data indicates that the throughput of each transmission queue is balanced, the port with the highest read / write priority is used for equal queue data reading and writing. If the throughput data indicates that the throughput of each transmission queue is uneven, queue order information is obtained. Data reading and writing are performed on the shared cache according to the queue order information, read / write operation instructions, and ports. Therefore, by using a shared cache, all queues can dynamically share the cache space. In balanced scenarios, equal queue data reading and writing can be achieved based on independent port priority settings. Furthermore, based on port sharing, in uneven scenarios, queues can transmit data from the same queue through multiple shared ports, obtaining a higher upper limit of queue transmission bandwidth, ensuring high utilization of the total upper limit of transmission bandwidth, and providing a more efficient data transmission method by uniformly managing all ports and cache space.

[0076] In one exemplary embodiment, such as Figure 3 As shown, the bubble flow control steps include steps 302 to 306. Wherein:

[0077] Step 302: Obtain the cache usage of each transmission queue in the shared cache.

[0078] In some embodiments, the cache usage of each transmission queue in the shared cache can be obtained at regular intervals by monitoring events or querying mechanisms, but this is not limited to these.

[0079] Step 304: Set bubbles for each transmission queue according to the cache usage to obtain queue bubbles.

[0080] Bubble setting refers to reserving bubble space for data transmission.

[0081] In some embodiments, if the cache usage indicates that a certain queue is consistently using a large amount of cache space, then the shared cache is bubble-set. This will always reserve bubble space for queues that do not have valid data in the cache, thus obtaining queue bubbles and effectively preventing a single queue from occupying the entire cache space.

[0082] Step 306: Perform flow control on each transmission queue according to the queue bubble; wherein, each queue bubble cannot be shared by other queues.

[0083] Among them, flow control is a resource scheduling method in the data transmission process.

[0084] In some embodiments, flow control is performed on each transmission queue based on queue bubbles. Each queue in the shared buffer is flow controlled based on the corresponding queue bubble. Inside the multi-input port, a scheduling module distributes data to different queue buffers. If a queue writes data to the buffer, the scheduling module will prioritize allocating buffer space for it.

[0085] In some embodiments, if the shared cache identifies that some ports are idle (no read / write operations), the scheduling logic can also ensure that the head of each queue is located in a different cache. By scheduling the data of each queue to be evenly distributed in each cache, this cache can support serial writing and parallel reading.

[0086] In this embodiment, by obtaining the cache usage of each transmission queue in the shared cache, bubble settings are made for each transmission queue based on the cache usage to obtain queue bubbles, and flow control is performed on each transmission queue based on the queue bubbles. Based on the bubble-based flow control scheme, the minimum data transmission space is reserved for each queue.

[0087] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0088] Based on the same inventive concept, this application also provides a shared cache management device for implementing the shared cache management method described above. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more shared cache management device embodiments provided below can be found in the limitations of the shared cache management method described above, and will not be repeated here.

[0089] In one exemplary embodiment, such as Figure 10As shown, a shared cache management device is provided, including: a first acquisition module 1001, a balanced read / write module 1002, a second acquisition module 1003, and an unbalanced read / write module 1004, wherein:

[0090] The first acquisition module 1001 is used to acquire throughput data of each transmission queue in the shared cache; the shared cache contains a number of ports for data reading and writing equal to the number of queues, and each transmission queue independently has a port with the highest read and write priority;

[0091] The balanced read / write module 1002 is used to receive read / write operation instructions. If the throughput data indicates that the throughput of each transmission queue is balanced, then the port with the highest read / write priority is used to perform equal queue data read / write.

[0092] The second acquisition module 1003 is used to acquire queue order information if the throughput data indicates that the throughput of each transmission queue is unbalanced.

[0093] The unbalanced read / write module 1004 is used to read and write data to the shared cache based on queue order information, read / write operation instructions, and port.

[0094] In some embodiments, the balanced read / write module 1002 is further configured to perform data read / write on the shared cache according to the port with the highest read / write priority and the read / write operation instruction corresponding to each of the transmission queues, provided that the bandwidth speedup ratio of each transmission queue is the same.

[0095] In some embodiments, the second acquisition module 1003 is further configured to acquire queue status information and queue head and tail address information; and determine queue order information based on the queue status information and queue head and tail address information.

[0096] In some embodiments, the unbalanced read / write module 1004 is further configured to select target port data from the ports according to queue order information and read / write operation instructions; and to perform data read / write on the shared cache according to the target port data and read / write operation instructions.

[0097] In some embodiments, both the port and the shared buffer can be shared by any transmission channel. The device further includes a port sharing module, which sets the port corresponding to the idle queue to a shared state when there is an idle queue in the transmission queue; wherein the port in the shared state can be used by other queues.

[0098] In some embodiments, the apparatus further includes: a bubble flow control module, configured to acquire the cache usage of each transmission queue in the shared cache; set bubbles for each transmission queue according to the cache usage to obtain queue bubbles; and perform flow control on each transmission queue according to the queue bubbles; wherein each queue bubble cannot be shared by other queues.

[0099] In the aforementioned shared cache management device, throughput data of each transmission queue in the shared cache is obtained. The shared cache contains a number of ports for data reading and writing equal to the number of queues, with each transmission queue independently having a port with the highest read / write priority. Read / write operation instructions are received. If the throughput data indicates that the throughput of each transmission queue is balanced, the port with the highest read / write priority is used for equal queue data reading and writing. If the throughput data indicates that the throughput of each transmission queue is uneven, queue order information is obtained. Data reading and writing are performed on the shared cache according to the queue order information, read / write operation instructions, and ports. Therefore, by using a shared cache, all queues can dynamically share the cache space. In balanced scenarios, equal queue data reading and writing can be achieved based on independent port priority settings. Furthermore, based on port sharing, in non-uniform scenarios, queues can transmit data of the same queue through multiple shared ports, obtaining a higher upper limit of queue transmission bandwidth, ensuring high utilization of the total upper limit of transmission bandwidth, and providing a more efficient data transmission method by uniformly managing all ports and cache space.

[0100] Each module in the aforementioned shared cache management device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0101] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0102] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0103] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0104] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A shared cache management method, characterized in that, The method includes: Obtain throughput data for each transmission queue in the shared cache; the shared cache contains a number of ports for data reading and writing equal to the number of queues, and each transmission queue independently has a port with the highest read / write priority; Upon receiving read / write operation instructions, if the throughput data indicates that the throughput of each transmission queue is balanced, then the port with the highest read / write priority is used to perform equal queue data read / write. If the throughput data indicates that the throughput of each transmission queue is uneven, then the queue order information is obtained. Data is read and written to the shared cache according to the queue order information, the read and write operation instructions, and the port.

2. The method according to claim 1, characterized in that, The step of using the port with the highest read / write priority for equal queue data read / write includes: When the bandwidth speedup ratio of each of the transmission queues is the same, data read and write operations are performed on the shared cache according to the port with the highest read / write priority corresponding to each of the transmission queues and the read / write operation instructions.

3. The method according to claim 1, characterized in that, The process of obtaining queue order information includes: Get queue status information and queue head and tail address information; The queue order information is determined based on the queue status information and the queue head and tail address information.

4. The method according to claim 1, characterized in that, The step of reading and writing data to the shared cache according to the queue order information, the read / write operation instructions, and the port includes: Select target port data from the port according to the queue order information and the read / write operation instructions; The shared cache is read and written according to the target port data and the read / write operation instructions.

5. The method according to claim 1, characterized in that, Both the port and the shared buffer can be shared by any transmission channel, and the method further includes: If there is an idle queue in the transmission queue, the port corresponding to the idle queue is set to a shared state; wherein the port in the shared state can be used by other queues.

6. The method according to claim 1, characterized in that, The method further includes: Obtain the cache usage status of each of the transmission queues in the shared cache; Based on the cache usage, bubble settings are applied to each of the transmission queues to obtain queue bubbles; Flow control is performed on each of the transmission queues based on the queue bubble; wherein each queue bubble cannot be shared by other queues.

7. A shared cache management device, characterized in that, The device includes: The first acquisition module is used to acquire throughput data of each transmission queue in the shared cache; the shared cache contains a number of ports for data reading and writing equal to the number of queues, and each transmission queue independently has a port with the highest read and write priority; The balanced read / write module is used to receive read / write operation instructions. If the throughput data indicates that the throughput of each transmission queue is balanced, then the port with the highest read / write priority is used to perform equal queue data read / write. The second acquisition module is used to acquire queue order information if the throughput data indicates that the throughput of each transmission queue is unbalanced. An unbalanced read / write module is used to read and write data to the shared cache according to the queue order information, the read / write operation instructions, and the port.

8. The apparatus according to claim 7, characterized in that, The balanced read / write module is further configured to perform data read / write operations on the shared cache based on the port with the highest read / write priority corresponding to each of the transmission queues and the read / write operation instructions, provided that the bandwidth speedup ratios of each transmission queue are the same.

9. The apparatus according to claim 7, characterized in that, The second acquisition module is further configured to acquire queue status information and queue head and tail address information; and determine the queue order information based on the queue status information and the queue head and tail address information.

10. The apparatus according to claim 7, characterized in that, The unbalanced read / write module is further configured to select target port data from the ports according to the queue order information and the read / write operation instructions; and to perform data read / write on the shared cache according to the target port data and the read / write operation instructions.

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