Instruction execution method, related device and medium
By decoupling loading instructions from matrix multiplication and addition instructions in the graphics processor, asynchronous execution and data preloading are achieved, solving the problem of data loading latency in ultra-large tensor kernels and improving computational efficiency and throughput.
Patent Information
- Application Number
- CN202610113456.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-27
- Publication Date
- 2026-04-17
AI Technical Summary
In existing technologies, data loading of ultra-large tensor kernels is bundled with matrix multiplication and addition operations, which causes data loading delays to be exposed on critical computation paths, limiting the effective utilization of high computing power and restricting the overall instruction throughput.
By decoupling the loading instruction from the matrix multiplication and addition instruction and supporting asynchronous execution, the matrix data is preloaded into a dedicated matrix data buffer by issuing independent loading instructions through the scheduling unit, and the matrix multiplication and addition operations are executed asynchronously, thus hiding the data loading delay.
It improves the computational efficiency and hardware resource utilization of the tensor processing unit, increases the overall instruction throughput, and effectively solves the data supply bottleneck problem.