Recovery method and device for ADC exception, electronic equipment and storage medium
By monitoring the ADC conversion time and state machine interaction signals, and combining a multi-level reset strategy and a timeout threshold, the problems of long recovery time and complexity in ADC state machine anomaly handling are solved, achieving fast and accurate anomaly recovery and improving the stability and adaptability of the system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NATIONZ TECH INC
- Filing Date
- 2025-12-01
- Publication Date
- 2026-04-17
AI Technical Summary
In existing technologies, ADC state machine anomaly handling has long recovery time and complex operation, is prone to causing new errors, and has a significant impact on system stability, making it particularly unsuitable for high-reliability systems.
By monitoring the ADC conversion time and state machine interaction signals, anomalies are identified and control signals are output for rapid reset. A multi-level reset strategy and a configurable timeout threshold are adopted to avoid power-on and register reconfiguration.
It enables rapid and accurate anomaly recovery, shortens fault handling time, reduces the impact on other system devices, and improves system stability and reliability, making it suitable for high-reliability scenarios.
Smart Images
Figure CN121880091A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic equipment fault handling technology, and more specifically, to a method and apparatus for recovering from ADC anomalies, an electronic device, and a storage medium. Background Technology
[0002] In modern electronic systems, analog-to-digital converters (ADCs), as key interface devices between analog and digital signals, are widely used in various electronic devices. With the increasing complexity of application scenarios, ADCs typically include multiple state machines to collaboratively achieve signal conversion. However, under complex operating conditions, the coordinated operation of these multiple state machines may be affected by external interference, signal anomalies, or other factors, leading to state machine malfunctions, which in turn cause ADC conversion errors and affect the normal operation of the system.
[0003] Existing technologies for handling ADC state machine anomalies have significant drawbacks: when an anomaly occurs, the ADC typically requires a power-on reset. This process not only leads to the loss of configuration parameters but also necessitates tedious register reconfiguration, making the operation complex and time-consuming (usually requiring tens or even hundreds of milliseconds). Furthermore, power-on may impact other related devices in the system, causing data loss or device initialization errors, severely affecting the system's real-time performance and stability. This makes it particularly unsuitable for fields with extremely high reliability requirements, such as aerospace and medical equipment.
[0004] Existing technologies detect anomalies and perform overall resets by monitoring the extreme values of ADC output results. However, this approach can only identify specific types of anomalies, and the reset process still relies on power cycling. This approach cannot solve the problems of long recovery time and complex operation, and it is difficult to meet the requirements of high-reliability systems. Summary of the Invention
[0005] To address at least one of the aforementioned problems, this application proposes a method, apparatus, electronic device, and storage medium for ADC anomaly recovery, overcoming the shortcomings of existing ADC state machine anomaly handling, such as long recovery time, complex operation, easy induction of new errors, and significant impact on system stability. This achieves fast, accurate, and low-interference anomaly recovery, ensuring continuous and stable system operation.
[0006] According to a first aspect of this application, at least one embodiment of this application provides a method for recovering an ADC anomaly, comprising: monitoring the conversion time of the ADC and the interaction signal between the ADC's state machine; determining whether the conversion time is consistent with a first preset time; determining whether the interaction signal is received within a second preset time; generating an anomaly signal if the conversion time is inconsistent with the first preset time and / or the interaction signal is not received within the second preset time; and outputting a control signal according to the anomaly signal to cause the ADC's state machine to perform a reset operation and recover the ADC's state machine.
[0007] For example, in some embodiments of this application, the interaction signals between the ADC state machines include: state transition signals and / or state hold signals.
[0008] For example, in some embodiments of this application, it further includes: monitoring the dwell time of the ADC state machine in a set state; determining whether the dwell time of the ADC state machine in the set state exceeds a third set time; and generating an abnormal signal if the dwell time of any state machine of the ADC in the set state exceeds the third set time.
[0009] For example, in some embodiments of this application, the method further includes: monitoring whether the state machine of the ADC returns to a set state signal and / or flag bit when the state machine of the ADC performs a reset operation; determining that the state machine reset of the ADC has failed when the state machine of the ADC does not return to the set state signal and the flag bit; and outputting a control signal to restart the ADC and / or perform warning measures when the state machine reset of the ADC has failed.
[0010] According to a second aspect of this application, at least one embodiment of this application provides a recovery apparatus for an ADC anomaly, used to perform the recovery method as described in any one of the first aspects, the recovery apparatus comprising: a state monitoring component, used to monitor the conversion time of the ADC and the interaction signal between the ADC's state machine, and generate a first monitoring result; an anomaly judgment component, used to determine, based on the first monitoring result, whether the conversion time is consistent with a first set time and whether the interaction signal is received within a second set time, and, if the conversion time is inconsistent with the first set time and / or the interaction signal is not received within the second set time, used to generate an anomaly signal; and a reset control component, used to output a control signal based on the anomaly signal to cause the ADC's state machine to perform a reset operation, thereby restoring the ADC's state machine.
[0011] For example, in some embodiments of this application, the state monitoring component is further configured to monitor the dwell time of the ADC's state machine in a set state; the anomaly judgment component is further configured to determine whether the dwell time of the ADC's state machine in the set state exceeds a third set time, and to generate an anomaly signal if any state machine of the ADC dwells in the set state for more than the third set time.
[0012] For example, in some embodiments of this application, the state monitoring component is further configured to monitor whether the state machine of the ADC returns to a set state signal when the state machine of the ADC performs a reset operation, and generate a second monitoring result; the anomaly judgment component is further configured to determine whether the state machine of the ADC has been successfully reset based on the second monitoring result; the reset control component is further configured to output a control signal to restart the ADC and / or execute warning measures when the state machine of the ADC fails to reset.
[0013] For example, in some embodiments of this application, it further includes: a configuration component connected to the anomaly detection component, used to configure the first set time and the second set time.
[0014] According to a third aspect of this application, at least one embodiment of this application provides an electronic device, comprising: one or more processors; a memory for storing one or more programs; and, when the one or more programs are executed by the one or more processors, causing the one or more processors to perform the method as described in any one aspect of the first application.
[0015] According to a fourth aspect of this application, at least one embodiment of this application provides a computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the method as described in any one of the first aspects.
[0016] Through the above exemplary embodiments, the method, apparatus, electronic device, and storage medium for recovering ADC anomalies provided in this application have at least one of the following beneficial effects: Highly efficient and fast recovery: The reset process takes only a few microseconds to tens of microseconds, without the need for power-on and register configuration, which greatly shortens the fault recovery time and meets the stringent real-time requirements of high-reliability systems.
[0017] Low interference and high stability: Avoid the impact of power-on on other devices in the system, reduce the risk of data loss and device initialization errors, reduce system resource consumption, and improve overall stability.
[0018] Precisely adaptable to high-reliability scenarios: Through multi-level reset strategies and configurable timeout thresholds, it can be flexibly adjusted to meet the special needs of aerospace, medical equipment and other fields. The first anomaly only resets the state machine to reduce the impact, while continuous anomalies trigger high-level processing, balancing recovery efficiency and system security.
[0019] Easy to operate and highly scalable: The software configuration function simplifies the parameter adjustment process, making it easier for engineers to respond quickly to faults; the components are highly versatile and easy to integrate into electronic systems with different ADC models, and the performance can be further improved by upgrading the monitoring algorithm and optimizing the reset logic.
[0020] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description
[0021] The above and other objects, features, and advantages of this application will become more apparent from the detailed description of exemplary embodiments with reference to the accompanying drawings. The drawings described below are merely some embodiments of this application and are not intended to limit the scope of this application.
[0022] Figure 1 A flowchart illustrating an exemplary embodiment of a method for recovering from ADC anomalies is provided. Figure 2 A schematic diagram of an exemplary embodiment of a recovery device for ADC anomalies is shown; Figure 3 This diagram illustrates the structure of an electronic device provided in this application. Detailed Implementation
[0023] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this application will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.
[0024] The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of these specific details, or other methods, components, materials, devices, etc. In these cases, well-known structures, methods, devices, implementations, materials, or operations will not be shown or described in detail.
[0025] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.
[0026] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.
[0027] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of exemplary embodiments, and the modules or processes in the drawings are not necessarily essential for implementing this application, and therefore cannot be used to limit the scope of protection of this application.
[0028] Figure 1 A flowchart illustrating an exemplary embodiment of a method for recovering from ADC anomalies is shown.
[0029] like Figure 1 As shown, the method for recovering from ADC anomalies includes steps S101-S104.
[0030] In step S101, the conversion time of the ADC and the interaction signals between the ADC state machines are monitored.
[0031] According to the example embodiment, the interaction signals between ADC state machines include: state transition signals and / or state hold signals.
[0032] According to an example embodiment, step S101 further includes monitoring the dwell time of the ADC's state machine in the set state.
[0033] In step S102, it is determined whether the conversion time is consistent with the first set time, and whether an interaction signal is received within the second set time.
[0034] According to the example embodiment, step S102 further includes determining whether the dwell time of the ADC state machine in the set state exceeds a third set time.
[0035] The first, second, and third set times can be set by the user, and this application is not limited to them.
[0036] In step S103, an abnormal signal is generated if the conversion time is inconsistent with the first set time and / or if an interaction signal is not received within the second set time.
[0037] According to the example embodiment, step S103 further includes: generating an abnormal signal if any state machine of the ADC stays in a set state for a period of time exceeding a third set time.
[0038] In step S104, a control signal is output according to the abnormal signal to cause the ADC state machine to perform a reset operation and restore the ADC state machine.
[0039] According to the example embodiment, after the ADC state machine performs a reset operation, the recovery method further includes steps S105-S107.
[0040] In step S105, if the ADC state machine performs a reset operation, it is monitored whether the ADC state machine returns to the set state signal and / or flag bit.
[0041] In step S106, if the ADC state machine does not return the set state signal and flag bit, it is determined that the ADC state machine reset has failed.
[0042] In step S107, if the ADC state machine reset fails, a control signal is output to restart the ADC and / or execute a warning measure.
[0043] According to some embodiments, in the event of an ADC state machine reset failure, a corresponding control signal can be output to enable the ADC restart operation and / or the execution of warning measures. The triggering methods for both are highly flexible and can be set by the user according to actual application requirements.
[0044] Specifically, users can configure the software or set parameters to choose to only perform the ADC restart operation, that is, drive the ADC to reinitialize through control signals to attempt to restore normal operation; they can also choose to only perform warning measures, such as triggering an audible alarm, light prompts, or sending an alarm signal containing abnormal information to a preset terminal so that staff can intervene in time; in addition, it can be set to trigger both restart and warning measures at the same time, that is, issue a warning while starting the ADC restart process, both attempting to restore through automatic operation and simultaneously informing relevant personnel through warning information, thereby adapting to the different fault handling needs of different systems, and is especially suitable for scenarios with extremely high requirements for reliability and fault response flexibility, such as aerospace and medical equipment.
[0045] The warning measures include: sending an alarm command to the system, activating the audible and visual alarm device, and recording an anomaly log, which includes the time of the anomaly, the type of anomaly, and the number of resets. This application uses this as an example only, but is not limited to it.
[0046] Figure 2 A schematic diagram of an exemplary embodiment of a recovery device for ADC anomalies is shown.
[0047] like Figure 2 As shown, the recovery device for ADC anomalies includes: a status monitoring component 201, an anomaly judgment component 202, and a reset control component 203.
[0048] The status monitoring component 201 is used to monitor the conversion time of the ADC and the interaction signals between the ADC's state machines, and generate the first monitoring result.
[0049] According to some embodiments, the interaction signals between ADC state machines include: state transition signals and / or state hold signals.
[0050] According to some embodiments, the status monitoring component 201 collects data at a set monitoring frequency to ensure real-time capture of abnormal states.
[0051] According to an example embodiment, the state monitoring component 201 is also used to monitor the dwell time of the ADC's state machine in a set state.
[0052] The anomaly detection component 202 is connected to the state monitoring component 201. The anomaly detection component 202 has preset normal state rules (including preset transition time, fixed signal monitoring time, and state dwell time range) based on the ADC model and system requirements. When the anomaly detection component 202 receives the monitoring result from the state monitoring component 201, it outputs an anomaly signal if it determines that any of the following situations exist: the transition time does not match the preset time; the state machine does not detect the relevant interaction signal within the fixed time; the state machine's dwell time in a certain state exceeds the normal range.
[0053] Specifically, the anomaly detection component 202 is used to determine whether the conversion time is consistent with the first set time based on the first monitoring result, and also to determine whether an interaction signal is received within a second set time. Furthermore, if the conversion time is inconsistent with the first set time, and / or if an interaction signal is not received within the second set time, the anomaly detection component 202 generates an anomaly signal.
[0054] The anomaly detection component 202 is also used to determine whether the dwell time of the ADC state machine in the set state exceeds the third set time, and to generate an anomaly signal if the dwell time of any state machine of the ADC in the set state exceeds the third set time.
[0055] The reset control component 203 is connected to the fault detection component 202 and is used to perform a reset operation after receiving a fault signal, and adopts a multi-level reset strategy: Upon initial detection of an anomaly, the reset control component 203 outputs a control signal based on the anomaly signal to cause the ADC state machine to perform a reset operation, restoring the ADC state machine. That is, the initial reset operation only resets the ADC state machine; the reset process does not involve power-on or register configuration, and takes a few microseconds to tens of microseconds.
[0056] The status monitoring component 201 is also used to monitor whether the ADC state machine returns to a set status signal when the ADC state machine performs a reset operation, and generate a second monitoring result. The anomaly judgment component 202 is also used to determine whether the ADC state machine has been successfully reset based on the second monitoring result. The reset control component 203 is also used to output a control signal to restart the ADC and / or execute warning measures when the ADC state machine reset fails. That is, when an anomaly is detected consecutively (e.g., 2 or more times), the reset control component 203 triggers a system alarm or a system-level reset.
[0057] According to an example embodiment, the recovery device further includes a configuration component 204.
[0058] Configuration component 204 is connected to anomaly judgment component 202 and is used to configure the first set time, the second set time and the third set time. This allows users to dynamically configure the timeout threshold (including fixed time, preset time and state dwell time range) in the anomaly judgment module through software to adapt to the needs of different high-reliability scenarios such as real-time data acquisition of aerospace equipment and vital sign monitoring of medical equipment.
[0059] This application provides a method and apparatus for recovering from ADC anomalies. It utilizes a status monitoring component to monitor ADC conversion time and state machine interaction signals in real time, combined with an anomaly detection component to quickly identify anomalies. This eliminates the need for cumbersome problem localization operations, enabling precise triggering of processing and effectively solving the problems of delayed anomaly detection and complex localization in existing technologies. A reset control component performs targeted resets, eliminating the need for power-on and register reconfiguration. Recovery is completed in a few microseconds to tens of microseconds, significantly shortening fault handling time and adapting to scenarios with stringent real-time requirements, such as high-speed communication and real-time monitoring. A multi-level reset strategy is introduced (the first anomaly only resets the state machine; continuous anomalies trigger system alarms or resets) and a software-configurable timeout threshold, flexibly adapting to systems with extremely high reliability requirements, such as aerospace and medical equipment, balancing fault handling efficiency and system security. It avoids the impact of power-on on other system devices, reducing the risk of data loss and device initialization errors, lowering system resource consumption, and improving overall stability. The modules are highly versatile and easily integrated into electronic systems with different ADC models. Furthermore, the monitoring algorithm can be upgraded and the reset logic optimized to expand functionality. Operation is convenient; parameters can be adjusted via software without system downtime, significantly reducing maintenance difficulty.
[0060] The recovery method and recovery apparatus provided in this application can be used in high-reliability systems that require rapid recovery from ADC state machine anomalies: For example, the recovery method and recovery device provided in this application can be used for abnormal recovery of ADC state machines in aerospace equipment. In a certain aerospace data acquisition system, the ADC needs to convert sensor analog signals in real time, which places extremely high demands on reliability and real-time performance.
[0061] The status monitoring component collects the ADC conversion time and the interaction signals (including state transition commands and state hold flags) of the three internal state machines in real time at a frequency 20 times the maximum conversion frequency of the ADC. The anomaly detection component is preset with the normal conversion time range (5μs-8μs), state machine signal monitoring interval (≤10μs), and maximum dwell time of a single state (≤20μs) for this ADC model. When a state machine dwell time reaches 25μs, it is determined to be abnormal and an abnormal signal is immediately sent to the reset control component. After receiving the first abnormal signal, the reset control component performs a reset operation only on that state machine (taking 6μs) and confirms the reset success by checking the "normal initialization" flag returned by the state machine. If three abnormal signals are received consecutively within 1 second, a system alarm is triggered (an alarm command is sent and an audible and visual alarm is activated), and an abnormal log is recorded (including the time of the abnormality, the state machine number, and the number of resets). Engineers configured components to adjust the normal range of state dwell time to ≤15μs and ≤20μs respectively, depending on the flight phase (such as takeoff and cruise phase), in order to adapt to the signal conversion requirements of different phases.
[0062] For example, the recovery method and device provided in this application can also be used for abnormal recovery of the ADC state machine in medical devices. In a certain vital signs monitor, the ADC is used to convert electrocardiogram signals, and it is necessary to ensure that the data is continuous and uninterrupted.
[0063] The status monitoring component monitors the ADC conversion time and state machine interaction signals in real time. When the state machine transition signal is lost due to electromagnetic interference (not received for more than 12μs of the fixed monitoring time), the anomaly judgment component outputs an anomaly signal. The reset control component performs the first state machine reset (takes 5μs); if the reset fails, a restart operation is initiated. If two consecutive resets fail, a system-level reset is triggered. During a system-level reset, enhanced warning measures are activated, including sending alarm information to the nurse station terminal, displaying the anomaly code locally on the device, and saving the original signal data for 10 seconds before and after the anomaly for subsequent fault analysis.
[0064] The recovery method and device provided in this application effectively solve the problem of rapid recovery from ADC state machine anomalies in high-reliability systems through precise monitoring, hierarchical processing, and flexible configuration, significantly improving system stability and security, and possessing broad application value. This application only uses applications in aerospace and medical equipment as examples, but is not limited thereto.
[0065] Figure 3 This diagram illustrates the structure of an electronic device provided in this application.
[0066] See Figure 3 , Figure 3 An electronic device is provided, including a processor and a memory. The memory stores computer instructions, which, when executed by the processor, cause the processor to perform the computer instructions to achieve the following: Figure 1 The method and its detailed scheme are shown.
[0067] It should be understood that the above-described device embodiments are merely illustrative, and the device disclosed in this application can also be implemented in other ways. For example, the division of units / modules in the above embodiments is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units, modules, or components may be combined, or integrated into another system, or some features may be ignored or not executed.
[0068] Furthermore, unless otherwise specified, the functional units / modules in the various embodiments of this application can be integrated into one unit / module, or each unit / module can exist physically separately, or two or more units / modules can be integrated together. The integrated units / modules described above can be implemented in hardware or as software program modules.
[0069] When an integrated unit / module is implemented in hardware, the hardware can be digital circuits, analog circuits, etc. The physical implementation of the hardware structure includes, but is not limited to, transistors, memristors, etc. Unless otherwise specified, the processor or chip can be any suitable hardware processor, such as a CPU, GPU, FPGA, DSP, and ASIC, etc. Unless otherwise specified, on-chip cache, off-chip memory, and storage can be any suitable magnetic or magneto-optical storage medium, such as Resistive Random Access Memory (RRAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Enhanced Dynamic Random Access Memory (EDRAM), High-Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), etc.
[0070] If the integrated unit / module is implemented as a software program module and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments disclosed herein. The aforementioned memory includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.
[0071] This application also provides a non-transitory computer storage medium storing a computer program, which, when executed by multiple processors, causes the processors to perform actions such as... Figure 1 The method and its detailed scheme are shown.
[0072] It should be clearly understood that this application describes how specific examples are formed and used, but this application is not limited to any details of these examples. Rather, based on the teachings of the disclosure of this application, these principles can be applied to many other embodiments.
[0073] Furthermore, it should be noted that the above figures are merely illustrative representations of the processes included in the method according to exemplary embodiments of this application, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.
[0074] Exemplary embodiments of this application have been specifically shown and described above. It should be understood that this application is not limited to the detailed structures, arrangements, or implementation methods described herein; rather, this application is intended to cover various modifications and equivalent arrangements that fall within the objectives and scope of the appended claims.
Claims
1. A method for recovering from ADC anomalies, characterized in that, include: Monitor the conversion time of the ADC and the interaction signals between the ADC's state machine; Determine whether the conversion time is consistent with the first set time; Determine whether the interaction signal is received within a second set time period; An abnormal signal is generated if the conversion time is inconsistent with the first set time and / or the interaction signal is not received within the second set time. Based on the abnormal signal, a control signal is output to cause the ADC state machine to perform a reset operation and restore the ADC state machine.
2. The recovery method as described in claim 1, characterized in that, The interaction signals between the ADC state machines include: state transition signals and / or state hold signals.
3. The recovery method as described in claim 1, characterized in that, Also includes: Monitor the dwell time of the ADC's state machine in the set state; Determine whether the dwell time of the ADC state machine in the set state exceeds a third set time; If any state machine of the ADC stays in the set state for a period of time exceeding the third set time, an abnormal signal is generated.
4. The recovery method as described in claim 1, characterized in that, Also includes: When the ADC state machine performs a reset operation, monitor whether the ADC state machine returns to the set state signal and / or flag bit; If the ADC state machine does not return the set state signal and the flag bit, it is determined that the ADC state machine reset has failed. In the event that the state machine of the ADC fails to reset, a control signal is output to restart the ADC and / or to execute a warning measure.
5. A recovery device for ADC anomalies, characterized in that, For performing the recovery method as described in any one of claims 1-4, the recovery apparatus comprises: A status monitoring component is used to monitor the conversion time of the ADC and the interaction signals between the state machines of the ADC, and generate a first monitoring result; An anomaly detection component is used to determine whether the conversion time is consistent with a first set time and whether the interaction signal is received within a second set time based on the first monitoring result, and to generate an anomaly signal if the conversion time is inconsistent with the first set time and / or the interaction signal is not received within the second set time. A reset control component is used to output a control signal based on the abnormal signal, so as to cause the state machine of the ADC to perform a reset operation and restore the state machine of the ADC.
6. The recovery device as described in claim 5, characterized in that, The state monitoring component is also used to monitor the dwell time of the ADC's state machine in a set state; The anomaly detection component is also used to determine whether the dwell time of the ADC's state machine in the set state exceeds a third set time, and to generate an anomaly signal if the dwell time of any state machine of the ADC in the set state exceeds the third set time.
7. The recovery device as described in claim 5, characterized in that, The state monitoring component is also used to monitor whether the ADC state machine returns to a set state signal when the ADC state machine performs a reset operation, and generate a second monitoring result; The anomaly detection component is also used to determine whether the state machine of the ADC has been successfully reset based on the second monitoring result; The reset control component is also used to output a control signal to restart the ADC and / or execute warning measures in the event that the state machine reset of the ADC fails.
8. The recovery device as described in claim 5, characterized in that, Also includes: A configuration component, connected to the exception detection component, is used to configure the first set time and the second set time.
9. An electronic device, characterized in that, include: One or more processors; Memory, used to store one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors perform the method as described in any one of claims 1-4.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1-4.