Memory access error reproduction method, memory controller and computing system

Abstract

The embodiment of the invention provides a memory access error reproduction method, a memory controller and a computing system, and the scheme comprises the following steps: backing up memory access records of a plurality of memory access requests in a mirror image queue according to the plurality of memory access requests to be sent to a memory chip; when the memory access error is detected, extracting a memory access record from the mirror image queue; generating a target memory access sequence according to the memory access record; and sending the target memory access sequence to a storage chip, and reproducing a memory access error. According to the technical scheme provided by the invention, the memory access record when the memory access error occurs is backed up through the mirror image queue, so that the target memory access sequence can be regenerated according to the memory access record, and the memory access error scene can be reproduced, and therefore, no matter how long the time is consumed by the test program, the key scene inducing the error can be quickly reproduced, and the test efficiency is improved. A test program does not need to be completely and repeatedly run, so that an error root cause can be quickly found, and the effectiveness of improvement measures can be verified.

Description

Technical Field

[0001] This application relates to the field of computing system technology, and more specifically, to a method for reproducing memory access errors, a memory controller, and a computing system. Background Technology

[0002] Artificial intelligence systems such as deep learning models and large language models typically rely on high-performance computing systems for training. High-performance computing systems often integrate processors (CPUs, GPUs) and high-bandwidth, high-capacity memory chips (DRAM, such as DDR5, GDDR6, HBM). With the rapid development and widespread application of artificial intelligence and autonomous driving, the scale of models is becoming increasingly large, and the communication rate and data throughput between processors and memory chips are growing explosively. The capacity of memory chips is also increasing rapidly, which leads to a sharp increase in the probability of memory access errors.

[0003] Processor memory access errors can occur on the high-speed link between the processor and the memory chip, or on the memory cells within the memory chip itself. Link errors involve inter-symbol interference and inter-line interference of specific code patterns, while memory cell errors may involve coupling faults (CF) induced by specific memory access sequences and neighborhood pattern sensitive faults (NPSF). Therefore, locating the root cause of memory access errors requires eliminating many factors. To quickly identify key influencing factors and verify the effectiveness of improvement measures, memory access errors should be easily reproducible. However, training large models often involves multiple GPUs and multiple iterations, typically taking days or even months. If large model applications are used to reproduce memory access errors, root cause localization and verification of improvement measures will be an impossible task.

[0004] How to quickly reproduce memory access errors that occur when running large models in high-performance computing systems is an urgent problem to be solved. Summary of the Invention

[0005] The purpose of this application is to provide a method for reproducing memory access errors, a memory controller, and a computing system, so as to solve the problem of the difficulty in reproducing memory access errors in the prior art.

[0006] This application provides a method for reproducing memory access errors. The method includes: backing up memory access records of multiple memory access requests to be sent to a memory chip in a mirror queue; when a memory access error is detected, extracting the memory access records from the mirror queue; generating a target memory access sequence based on the memory access records; and sending the target memory access sequence to the memory chip to reproduce the memory access error.

[0007] The solution provided in the above embodiments backs up the memory access records when a memory access error occurs through a mirror queue. Then, the target memory access sequence can be generated based on the memory access records to reproduce the memory access error scenario. Thus, no matter how long the test program takes, the key scenario that caused the error can be quickly reproduced without having to run the entire test program. This makes it easy to quickly find the root cause of the error and verify the effectiveness of the improvement measures.

[0008] In one embodiment, backing up the memory access records of the multiple memory access requests to be sent to the memory chip in a mirror queue includes: sequentially caching the multiple memory access requests to be sent in an instruction queue; sequentially sending the memory access requests in the instruction queue to the memory chip; and backing up the memory access records of the multiple memory access requests in a mirror queue according to the memory access requests in the instruction queue.

[0009] The solution provided in the above embodiments can save memory access records in a timely manner when memory access errors occur by backing up memory access requests in the instruction queue.

[0010] In one embodiment, backing up the memory access records of the multiple memory access requests to be sent to the memory chip in a mirror queue includes: obtaining the time interval between two adjacent memory access requests; and caching the request type, request address, request data, and time interval of each memory access request in the mirror queue according to the request type, request address, and request data of each memory access request, thereby obtaining the memory access record.

[0011] The solution provided in the above embodiments can record the memory access data mode, address association mode and timing constraint information when a memory access error occurs in the memory access record in a timely manner, so as to facilitate the rapid reconstruction of the error scenario based on the recorded information.

[0012] In one embodiment, the step of caching the request type, request address, request data, and time interval of each memory access request in a mirror queue to obtain the memory access record includes: when the memory access request is a read request, first caching the request type, request address, and time interval of the read request in the mirror queue; when the request data corresponding to the read request is received, inserting the request data into the position of the read request in the mirror queue.

[0013] The solution provided in the above embodiments can record complete request data in the memory access record when the memory access request is a read request, which facilitates the complete reconstruction of the error scenario based on the recorded information.

[0014] In one embodiment, backing up the memory access records of the multiple memory access requests to be sent to the memory chip in a mirror queue includes: when the mirror queue is full, deleting the oldest memory access request record at the head of the queue according to the first-in-first-out principle, and adding the latest memory access request record at the tail of the queue.

[0015] The solution provided in the above embodiments can always back up the latest memory access records in the mirror queue by using the first-in-first-out principle, thereby avoiding excessively long memory access records that affect the efficiency of memory access error reproduction.

[0016] In one embodiment, generating a target memory access sequence based on the memory access records includes: analyzing whether the memory access records contain the following condition: "there is a read request record for any specified address, but no write request record for the specified address"; if the condition exists, generating a write request for the specified address; and generating the target memory access sequence based on the write request and the memory access records.

[0017] The solution provided in the above embodiments generates a write request for a certain address when there is only a read request and no write request in the memory access record. This can make the memory access record more complete and facilitate the smooth reproduction of subsequent memory access errors.

[0018] In one embodiment, generating the target memory access sequence based on the write request and the memory access record includes: injecting the write request into the instruction queue first; generating the target memory access sequence based on the request type, request address, and request data of each memory access request cached in the memory access record; and sequentially injecting the target memory access sequence into the instruction queue according to the time interval of each memory access request cached in the memory access record.

[0019] The solution provided in the above embodiments can initialize the stored data by injecting the write request into the instruction queue in advance, so that subsequent read requests at the same address can read back the real original data, thereby ensuring the authenticity and accuracy of the reproduced scenario.

[0020] In one embodiment, sending the target memory access sequence to the memory chip to reproduce the memory access error includes: performing an access operation on the memory chip according to the target memory access sequence cached in the instruction queue.

[0021] In one embodiment, before generating the target memory access sequence based on the memory access record, the method further includes: saving the memory access record locally when idle; and loading the locally saved memory access record into the mirror queue when entering debug mode.

[0022] The solution provided in the above embodiments can store memory access records for a long time, and retrieve the memory access records at any time when debugging is needed. The memory access records can be used repeatedly, and memory access records for multiple error scenarios can also be recorded.

[0023] In one embodiment, the method further includes: repeatedly generating the target memory access sequence and sending it to the memory chip until the memory access error is reproduced or the number of repetitions reaches a threshold.

[0024] The solution provided in the above embodiments can repeatedly generate target memory access sequences for debugging until the error scenario is reproduced or the storage system stability meets the standard after the verification measures are introduced.

[0025] The solution provided in the above embodiments can be applied to the reproduction of memory access errors during the operation of upper-layer applications (such as large model programs). Since the mathematical operations of large models are complex and time-consuming, the method provided in this application can quickly reproduce memory access error scenarios that occur during the operation of upper-layer applications.

[0026] This application embodiment also provides a memory controller, the memory controller comprising: a mirror queue module, used to back up memory access records of multiple memory access requests to be sent to the memory chip in a mirror queue; an error detection module, connected to the mirror queue module and the memory chip, used to detect whether a memory access error has occurred in the memory chip, and when a memory access error is detected, to send an error notification to the mirror queue module, triggering the mirror queue module to extract the memory access record from the mirror queue; and a sequence generation module, connected to the mirror queue module, used to generate a target memory access sequence based on the memory access record in the mirror queue module; the target memory access sequence is used to send to the memory chip to reproduce the memory access error.

[0027] In one embodiment, the memory controller includes an instruction queue module for sequentially caching the multiple memory access requests to be sent to the memory chip in an instruction queue.

[0028] In one embodiment, the sequence generation module includes a preprocessing module and a sequence generator. The preprocessing module, connected to the mirror queue module and the instruction queue module, is used to analyze whether the memory access record contains the following condition: "There is a read request record for any specified address, but no write request record for the specified address"; if the condition exists, a write request for the specified address is generated based on the request address and request data contained in the read request record; the write request is injected into the instruction queue first. The sequence generator, connected to the mirror queue module and the instruction queue module, is used to generate a target memory access sequence based on the request type, request address, and request data of each memory access request cached in the memory access record; the target memory access sequence is injected into the instruction queue sequentially according to the time interval of each memory access request cached in the memory access record.

[0029] This application also provides a computing system, including: a processor and a memory chip; the processor includes a processor core and a memory controller; the processor core is used to issue a memory access request; the memory controller is connected to the processor core and the memory chip; the memory controller is used to receive the memory access request, execute the method described in the above embodiments, and perform a memory access operation on the memory chip.

[0030] The memory controller and computing system provided in the above embodiments back up memory access records when memory access errors occur through a mirror queue. Subsequently, the target memory access sequence can be generated based on the memory access records to reproduce the memory access error scenario. Thus, no matter how long the test program takes, the key scenario that caused the error can be quickly reproduced without having to run the entire test program. This facilitates the rapid identification of the root cause of the error and the verification of the effectiveness of the improvement measures. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is an architectural block diagram of a computing system provided in an embodiment of this application; Figure 2 A flowchart illustrating the method for reproducing memory access errors provided in this application embodiment; Figure 3 A schematic diagram illustrating the logic of mirror queue updating and extraction provided in an embodiment of this application; Figure 4 yes Figure 2Detailed flowchart of step S230 in the corresponding embodiment; Figure 5 This is a schematic diagram illustrating the principle of preprocessing the target memory access sequence based on memory access records, provided in an embodiment of this application. Detailed Implementation

[0033] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0034] To reproduce memory access errors, the conventional approach is to directly run the benchmark program corresponding to the faulty model and reproduce the error through repeated testing. Taking a large-scale benchmark program as an example, it calls the computing units of a high-performance computing system to perform complex mathematical operations. A single execution typically takes minutes or even tens of minutes. From a micro-timing perspective, its execution process generates a massive sequence of memory access requests. However, the critical sequences that cause memory access errors due to inter-symbol interference, inter-line interference, and memory cell coupling failures often only appear within a few clock cycles of the memory chip, on the order of nanoseconds. Obviously, the critical sequences that actually induce memory access errors account for a very small percentage of the total memory access sequences, and memory access error reproduction still suffers from inefficiency.

[0035] This application provides a method for reproducing memory access errors to improve the efficiency of memory access error reproduction. This method can be executed by a processor. Figure 1 This is an architectural block diagram of a computing system provided in one embodiment of this application. The method provided in this application can be... Figure 1 The processor of the computing system shown executes the operation. This processor may include a processor core 110 (such as a CPU core or GPU core) and a memory controller 120 (such as a memory controller). The memory controller 120 can communicate with the memory chip 130 via signal lines such as DQ / DQS, and the memory chip 130 may be DRAM (Dynamic Random Access Memory). The processor core 110 can run upper-level applications (such as benchmark programs corresponding to large models), generating access requests, which constitute a memory access request sequence. The processor core 110 can send the memory access request sequence sequentially to the memory controller 120. The memory controller 120 receives the aforementioned memory access requests and executes the method provided in the following embodiments of this application to perform memory access operations on the memory chip 130.

[0036] The memory controller 120 includes a mirror queue module, a sequence generation module, and an error detection module. The error detection module may be an ECC (Error Correcting Code) module. The mirror queue module is used to back up the memory access records of multiple memory access requests to be sent to the memory chip 130 in a mirror queue. The error detection module is connected to the mirror queue module and the memory chip. The error detection module is used to detect whether a memory access error has occurred in the memory chip. When a memory access error is detected, an error notification is sent to the mirror queue module, triggering the mirror queue module to retrieve the memory access record from the mirror queue. The sequence generation module is connected to the mirror queue module. The sequence generation module is used to generate a target memory access sequence based on the memory access records in the mirror queue module. The target memory access sequence is sent to the memory chip to reproduce the memory access error.

[0037] In one embodiment, the memory controller 120 may further include an instruction queue module for sequentially caching the multiple memory access requests to be sent to the memory chip in the instruction queue. That is, memory access requests sent from the processor core 110 to the memory controller 120 can be added to the instruction queue first, and then sent to the memory chip 130 in sequence.

[0038] The mirror queue module can perform backups based on memory access requests from the instruction queue, the output of the arbitrator in the memory controller 120, or the output of the final execution unit of the memory controller 120. The arbitrator can determine the order in which requests are sent based on the DRAM timing. The final execution unit of the memory controller 120 can translate the ordered requests into specific DRAM access commands.

[0039] The error detection module can be used to detect whether a memory access error has occurred. Memory access errors can be of various types, including UE (Uncorrected Error), CE (Corrected Error), Parity error, and CRC (Cyclic Redundancy Check) error. UE and CE generally indicate that the content stored in the memory chip 130 has been corrupted, while Parity and CRC errors generally indicate errors occurring on the transmission link between the memory controller 120 and the memory chip 130.

[0040] The sequence generation module can generate a target memory access sequence based on the memory access record and add the target memory access sequence to the instruction queue. Then, the memory controller 120 can send the target memory access requests in the instruction queue to the memory chip 130 in sequence. The sequence generation module can include a sequence generator and a preprocessing module. The preprocessing module can perform preprocessing based on the memory access record. The preprocessing process can check if there is a scenario in the memory access record where "a memory access request for a certain address has no write operation before the read operation". If so, a write operation for that address is generated based on the request data recorded in the memory access record and injected into the instruction queue of the memory controller 120 to complete the initialization of the stored data, ensuring consistency with the data in the read request in the memory access record.

[0041] The sequence generator can generate a real target memory access sequence based on the request type, request address, and request data recorded in the memory access record, and inject it into the instruction queue of the memory controller 120 according to the recorded time intervals. The memory controller 120 then reproduces the real scenario that caused the memory access error based on the instruction queue. The sequence generator can repeatedly execute the target sequence generation operation as needed, thereby accelerating the reproduction of memory access errors and verifying the effectiveness of improvement measures. The sequence generator can be an independent module in the memory controller 120, or it can be implemented based on other driver engines in the memory controller 120, such as the BIST (Built-In Self-Test) module. The method for reproducing memory access errors provided in this application will be described in detail below.

[0042] Figure 2 This is a flowchart illustrating the method for reproducing memory access errors provided in an embodiment of this application. Figure 2 As shown, the method includes the following steps S210-S240.

[0043] S210: Based on the multiple memory access requests to be sent to the memory chip, back up the memory access records of the multiple memory access requests in the mirror queue.

[0044] Memory access requests can be generated by the processor core 110 after running upper-layer applications (such as benchmark programs corresponding to large models), and then transmitted to the instruction queue inside the memory controller 120 via data routing or transmission links. The memory controller 120 can first cache multiple memory access requests to be sent in the instruction queue, and then the arbitrator of the memory controller 120 sorts the memory access requests according to the timing status of the DRAM chip. Finally, the end execution unit of the memory controller 120 translates the memory access requests into access commands, and then sends them to the DRAM chip in sequence via signal lines such as CA / DQ / DQS.

[0045] The memory controller 120's mirror queue module can back up the memory access records of multiple memory access requests in the mirror queue based on multiple memory access requests from the instruction queue, or based on multiple memory access requests output by the arbitrator, or based on multiple memory access requests output by the final execution unit of the memory controller 120.

[0046] A memory access request can include a request type and a request address. The request type can be a write request or a read request. The request address can be a specific memory address within the memory chip. When the memory access request is a write request, it can also include request data, which refers to the data to be written to the memory chip.

[0047] The memory access record is used to record the request type, request address, request data, and time interval of each memory access request. To distinguish different memory access requests, the memory access record may also include a request sequence number. The time interval refers to the interval between the timestamp of the current memory access request and the timestamp of the previous memory access request. The timestamp of the memory access request can be obtained from a clock counter. In one embodiment, the time when the memory access request enters the instruction queue can be used as the timestamp of the memory access request, or the time when the computing unit issues the memory access request can be used as the timestamp of the memory access request. In another embodiment, the time when the arbitrator or the final execution unit in the memory controller 120 outputs the memory access request can also be used as the timestamp of the memory access request. In one embodiment, when the memory access request is a read request, since the read request does not contain request data, the request type, request address, and time interval of the read request can be cached in the mirror queue first; then, when the request data corresponding to the read request is received, the request data is inserted into the position of the read request in the mirror queue. Thus, the memory access record can cache the request type, request address, request data, and time interval corresponding to each memory access request.

[0048] In one embodiment, the mirror queue module of the memory controller 120 can first synchronize multiple memory access requests from the instruction queue to the mirror queue; then obtain the time interval between two adjacent memory access requests from the time counter and store it in the mirror queue; then update the request data returned by the read request to the position of the read request in the mirror queue. Thus, the mirror queue caches the request type, request address, request data and time interval of each memory access request, i.e., the memory access record.

[0049] In one embodiment, when the mirror queue is full, the mirror queue module deletes the oldest memory access request record at the head of the queue according to the first-in-first-out principle and adds the newest memory access request record to the tail of the queue.

[0050] like Figure 3As shown, a memory access request record can include the request sequence number, request type, request address, request data, and time interval. The mirror queue caches the memory access request record for each request in the order they were requested. Figure 3 As can be seen, when the memory controller 120 receives memory access request 1, the mirror queue module caches the memory access request record corresponding to memory access request 1, namely Req1, Write, Addr A, DataA, ΔT1. When the memory controller 120 receives memory access request 2, the mirror queue module caches the memory access request record corresponding to memory access request 2, namely Req2, Write, Addr B, DataB, ΔT2. And so on. Taking a mirror queue with a depth of 3 as an example, when the memory access request record corresponding to memory access request 3 is cached, the mirror queue is full. When the memory controller 120 receives memory access request 4, according to the first-in-first-out principle, that is, the memory access request record that entered the mirror queue first is deleted first. Therefore, the earliest memory access request record corresponding to memory access request 1 at the head of the queue (Req1, Write, Addr A, DataA, ΔT1) is deleted. The memory access request record corresponding to memory access request 4 (Req2, Write, Addr D, DataD, ΔT4) is added to the tail of the queue.

[0051] S220: When a memory access error is detected, the memory access record is retrieved from the mirror queue.

[0052] Specifically, the ECC module of the memory controller 120 reads back data and checksum from the DRAM, calculates the checksum of the data using the corresponding algorithm, and compares the read-back checksum with the calculated checksum to detect erroneous bits.

[0053] by Figure 3 For example, assuming that when the memory access request record corresponding to memory access request 4 is cached in the mirror queue, the ECC module detects a memory access error. The processor can stop caching memory access request records in the mirror queue and archive the current cached memory access records. The archived memory access records can be considered to record the specific code pattern that triggered the memory access error and the specific timing characteristics between the memory access requests. Specifically, the processor can save the memory access records in the mirror queue locally when idle. Of course, if no memory access error occurs, it can continue caching the memory access request record corresponding to memory access request 5, delete the memory access request record corresponding to memory access request 2, and so on. S230: Generate the target memory access sequence based on the memory access records.

[0054] When it is necessary to reproduce a memory access error or when the computing system enters debug mode, and after an improvement measure has been implemented based on the cause of the memory access error, the processor can load the locally stored memory access records into the image queue to verify the effectiveness of the measure.

[0055] The target memory access sequence refers to a sequence of memory access requests regenerated based on the memory access records.

[0056] In one embodiment, such as Figure 4 As shown, the above S230 specifically includes the following steps S231-S233.

[0057] S231: Analyze whether the memory access record contains the following condition: "There is a read request record for any specified address, but there is no write request record for the specified address".

[0058] The specified address can be any request address, and the read request record can include the request sequence number, request type (Read), request data, request address, and time interval.

[0059] It's important to note that in a memory access request sequence, if there's only a read request for a specific address and no preceding write request for that address, the read request will not retrieve any data. Therefore, to ensure successful testing and maintain the consistency of the target sequence data, we can first determine whether there is a read request record for a specific address in the memory access logs, and whether there is a write request record for that address.

[0060] S232: If the above situation exists, generate a write request for the specified address based on the request address and request data contained in the read request record.

[0061] If there is a situation where an address only has read requests and no write requests, a write request can be generated before the read request to initialize the stored data.

[0062] For example, suppose the memory access record is as follows: Figure 5 As shown on the left, request type Req4 is Read, request address is Addr A, and request data is Data A; however, there is no Write request corresponding to Addr A in the memory access record, therefore... Figure 5 As shown on the right, the preprocessing module can perform preprocessing to generate a write request of type Write, with the request address and request data being consistent with those of Req4.

[0063] S233: Generate the target memory access sequence based on the write request and the memory access record.

[0064] The target memory access sequence includes a series of regenerated memory access requests. The series of memory access requests may include write requests and read requests. Write requests include request type, request address and request data, and read requests may include request type and request address.

[0065] In one embodiment, the preprocessing module can first inject the preprocessed write requests into the instruction queue; then the sequence generator generates the target memory access sequence according to the request type, request address and request data of each memory access request in the memory access record cache; then, according to the time interval of each memory access request in the memory access record cache, the target memory access sequence is injected into the instruction queue in sequence.

[0066] Specifically, based on the request type, request address, and request data of each memory access request recorded in the memory access record, a corresponding write request or read request can be generated. Then, according to the time interval between adjacent memory access requests recorded in the memory access record, the generated read requests or write requests are sequentially injected into the instruction queue of the memory controller.

[0067] S240: Send the target memory access sequence to the memory chip to reproduce the memory access error.

[0068] Specifically, the target memory access sequence can be injected into the instruction queue. The memory controller 120 can then perform access operations on the memory chip 130 based on the target memory access sequence cached in the instruction queue. The access operation can be a write operation or a read operation, depending on the memory access request in the target memory access sequence.

[0069] Since the memory access record is a record of access requests saved when a memory access error occurs, it records the request sequence number, request data, request address, time interval, etc. that triggered the memory access error. Therefore, the target memory access sequence can be regenerated based on the memory access record to perform the memory access operation, accurately restore the scenario in which the error occurred, and significantly improve the efficiency of memory access error reproduction.

[0070] In one embodiment, the target memory access sequence can be generated and sent to the memory chip multiple times until the memory access error recurs or the number of repetitions reaches a threshold. The threshold can be adjusted according to the stability requirements of the computing system, for example, it could be 10,000 times, 100,000 times, or 1 million times. After an improvement measure is implemented, to verify its effectiveness and avoid accidental occurrences, the target memory access sequence can be generated multiple times for verification, thus accurately confirming the effectiveness of the improvement measure.

[0071] This application captures memory access records that induce memory access errors during the actual operation of the application from the memory controller 120. It is not constrained by the processor core 110 and the type of upper-level application, and has universal applicability to memory access error scenarios in high-performance computing systems.

[0072] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0073] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0074] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0075] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0076] In this article, "multiple" refers to two or more.

[0077] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for reproducing memory access errors, characterized in that, The method includes: Based on the multiple memory access requests to be sent to the memory chip, the memory access records of the multiple memory access requests are backed up in the mirror queue; When a memory access error is detected, the memory access record is retrieved from the mirror queue; Based on the memory access records, generate the target memory access sequence; The target memory access sequence is sent to the memory chip to reproduce the memory access error.

2. The method according to claim 1, characterized in that, The step of backing up the memory access records of multiple memory access requests to be sent to the memory chip in the mirror queue includes: The multiple memory access requests to be sent are cached sequentially in the instruction queue; The memory access requests in the instruction queue are sent to the memory chip in sequence; Based on the memory access requests in the instruction queue, the memory access records of the multiple memory access requests are backed up in the mirror queue.

3. The method according to claim 1, characterized in that, The step of backing up the memory access records of multiple memory access requests to be sent to the memory chip in the mirror queue includes: Get the time interval between two adjacent memory access requests; Based on the request type, request address, and request data of each memory access request, the request type, request address, request data, and time interval of each memory access request are cached in the mirror queue to obtain the memory access record.

4. The method according to claim 3, characterized in that, The process of caching the request type, request address, request data, and time interval of each memory access request in the mirror queue based on the request type, request address, and request data of each memory access request to obtain the memory access record includes: When the memory access request is a read request, the request type, request address, and time interval of the read request are first cached in the mirror queue; When the request data corresponding to the read request is received, the request data is inserted into the position of the read request in the mirror queue.

5. The method according to claim 1, characterized in that, The step of generating the target memory access sequence based on the memory access record includes: Analyze whether the memory access records contain the following condition: "There is a read request record for any specified address, but no write request record for the specified address"; If the above situation exists, a write request for the specified address is generated based on the request address and request data contained in the read request record; The target memory access sequence is generated based on the write request and the memory access record.

6. The method according to claim 5, characterized in that, The step of generating the target memory access sequence based on the write request and the memory access record includes: The write request is first injected into the instruction queue; Based on the request type, request address, and request data of each memory access request in the memory access record cache, a target memory access sequence is generated; According to the time interval of each memory access request in the memory access record cache, the target memory access sequence is sequentially injected into the instruction queue.

7. The method according to claim 6, characterized in that, Sending the target memory access sequence to the memory chip to reproduce the memory access error includes: The memory chip is accessed according to the target memory access sequence cached in the instruction queue.

8. The method according to claim 1, characterized in that, Before generating the target memory access sequence based on the memory access record, the method further includes: The memory access records are saved locally when the system is idle. When entering debug mode, the locally saved memory access records are loaded into the mirror queue.

9. The method according to claim 1, characterized in that, The method further includes: The target memory access sequence is repeatedly generated and sent to the memory chip until the memory access error is reproduced or the number of repetitions reaches a threshold.

10. A memory controller, characterized in that, The memory controller includes: The mirror queue module is used to back up the memory access records of multiple memory access requests to be sent to the memory chip in the mirror queue. An error detection module, connected to the mirror queue module and the storage chip, is used to detect whether a memory access error has occurred on the storage chip. When a memory access error is detected, an error notification is sent to the mirror queue module, triggering the mirror queue module to extract the memory access record from the mirror queue. A sequence generation module, connected to the mirror queue module, is used to generate a target memory access sequence based on the memory access records of the mirror queue module; the target memory access sequence is used to send to the memory chip to reproduce the memory access error.

11. The memory controller according to claim 10, characterized in that, The memory controller includes an instruction queue module, used to cache the multiple memory access requests to be sent to the memory chip in the instruction queue in sequence.

12. The memory controller according to claim 11, characterized in that, The sequence generation module includes a preprocessing module and a sequence generator; The preprocessing module, connected to the mirror queue module and the instruction queue module, is used to analyze whether the memory access record contains the following condition: "There is a read request record for any specified address, but no write request record for the specified address"; if the condition exists, a write request for the specified address is generated based on the request address and request data contained in the read request record; and the write request is injected into the instruction queue in advance. A sequence generator, connecting the mirror queue module and the instruction queue module, is used to generate a target memory access sequence based on the request type, request address, and request data of each memory access request in the memory access record cache; and to sequentially inject the target memory access sequence into the instruction queue according to the time interval of each memory access request in the memory access record cache.

13. A computing system, characterized in that, include: Processors and memory chips; The processor includes a processor core and a memory controller; The processor core is used to issue memory access requests; The memory controller is connected to the processor core and the memory chip; The memory controller is used to receive the memory access request and execute the method according to any one of claims 1-9 to perform a memory access operation on the memory chip.

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