Pixel circuit and driving method thereof, display panel, display module and electronic equipment

Abstract

The embodiment of the invention discloses a pixel circuit and a driving method thereof, a display panel, a display module and electronic equipment, and relates to the technical field of display. The pixel circuit comprises a driving control circuit and a reset circuit. And the driving control circuit is electrically connected with the anode of the light-emitting device and is configured to provide a driving signal for the anode of the light-emitting device so as to drive the light-emitting device to emit light. And the reset circuit is electrically connected with the reset signal end, the initial signal end and the anode of the light-emitting device, and is configured to be switched on in response to a reset signal transmitted by the reset signal end, and transmit the first initial signal and the second initial signal from the initial signal end to the anode of the light-emitting device in a time-sharing manner. The voltage values of the first initial signal and the second initial signal are different. One of the first initial signal and the second initial signal can reset the anode of the light-emitting device, and the other one can fill up internal defects or charge vacancies of materials of the light-emitting device, so that the problems of smear and the like are effectively solved, and the display effect is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a pixel circuit and its driving method, a display panel, a display module, and an electronic device. Background Technology

[0002] OLED (organic light emitting diode) displays are gaining increasing attention from users due to their self-illuminating, high contrast, low power consumption, wide viewing angle, fast response speed, and wide operating temperature range, making them a hot trend in current display products.

[0003] However, when the grayscale of the image displayed on an OLED screen changes, display anomalies are prone to occur, such as ghosting and color shift. Summary of the Invention

[0004] This application provides a pixel circuit and its driving method, a display panel, a display module, and an electronic device to improve display effects.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, a pixel circuit is provided, comprising a drive control circuit and a reset circuit. The drive control circuit is electrically connected to the anode of a light-emitting device (LED), and is configured to provide a drive signal to the anode of the LED to drive the LED to emit light. The reset circuit is electrically connected to a reset signal terminal, an initial signal terminal, and the anode of the LED, and is configured to conduct in response to a reset signal transmitted from the reset signal terminal, transmitting a first initial signal and a second initial signal from the initial signal terminal to the anode of the LED in a time-division multiplexing manner. The voltage values ​​of the first initial signal and the second initial signal are different.

[0007] The pixel circuits provided in some embodiments of this application, by setting a reset circuit, can initialize the light-emitting device before the driving control circuit drives the light-emitting device to emit light. Moreover, by splitting the initial signal transmitted from the reset circuit to the anode of the light-emitting device into a first initial signal and a second initial signal with different voltage values, and transmitting the first initial signal and the second initial signal to the anode of the light-emitting device at different times, it is possible to both reset the anode of the light-emitting device and fill internal defects or charge vacancies in the material of the light-emitting device.

[0008] This reduces the amount of charge captured by the light-emitting device during its light emission process, and also reduces the current loss in the driving signal (e.g., driving current) used to fill internal defects or charge vacancies in the material of the light-emitting device. This increases the proportion of the current in the driving signal used to drive the light-emitting device to emit light, so that most or even all of the driving signal can be used for the light emission of the light-emitting device, thereby reducing the impact of internal defects or charge vacancies in the material of the light-emitting device on the brightness of the light-emitting device.

[0009] When the brightness (or grayscale) of the light-emitting device changes, the start-up speed of the light-emitting device can be increased, so that the brightness (or grayscale) of the light-emitting device in different frames approaches or reaches the target brightness (or target grayscale), thereby improving image display anomalies, reducing the impact of problems such as ghosting and color shift, and improving display effect.

[0010] In a possible design in the first aspect, the reset circuit includes a first reset unit and a second reset unit, a reset signal terminal including a first reset signal terminal and a second reset signal terminal, and an initial signal terminal including a first initial signal terminal and a second initial signal terminal. The first reset unit is electrically connected to the first reset signal terminal, the first initial signal terminal, and the anode of the light-emitting device; the first reset unit is configured to conduct in response to a first reset signal transmitted from the first reset signal terminal, transmitting a first initial signal from the first initial signal terminal to the anode of the light-emitting device. The second reset unit is electrically connected to the second reset signal terminal, the second initial signal terminal, and the anode of the light-emitting device; the second reset unit is configured to conduct in response to a second reset signal transmitted from the second reset signal terminal, transmitting a second initial signal from the second initial signal terminal to the anode of the light-emitting device. The timing of the transmission of the first reset signal to the first reset unit and the timing of the transmission of the second reset signal to the second reset unit are different. This allows for independent control of the first reset unit and the second reset unit, facilitating the independent transmission of the first initial signal and the second initial signal to the anode of the light-emitting device. When the above-mentioned pixel circuit is applied to a display panel, it is convenient to selectively control the first reset unit and the second reset unit in the pixel circuit, improve the accuracy of the transmission of the first initial signal and the second initial signal to the anode of the light-emitting device, and effectively improve display abnormalities such as ghosting.

[0011] In one possible design approach, the voltage value of the second initial signal is greater than the voltage value of the first initial signal. Thus, the first initial signal can reset (or initialize) the light-emitting device; the second initial signal can increase the voltage difference between the anode and cathode of the light-emitting device and fill internal defects or charge vacancies in the material of the light-emitting device.

[0012] In one possible design approach, the first reset unit includes a first transistor, and the second reset unit includes a second transistor. The control electrode of the first transistor is electrically connected to a first reset signal terminal, the first electrode of the first transistor is electrically connected to a first initial signal terminal, and the second electrode of the first transistor is electrically connected to the anode of the light-emitting device. The control electrode of the second transistor is electrically connected to a second reset signal terminal, the first electrode of the second transistor is electrically connected to a second initial signal terminal, and the second electrode of the second transistor is electrically connected to the anode of the light-emitting device. This design allows for time-division multiplexing of the first and second initial signals while maintaining a relatively simple structure for both the first and second reset units, avoiding a significant increase in the area occupied by the pixel circuitry and preventing any impact on the pixel density of the display panel.

[0013] In one possible design aspect, the drive control circuit includes: a data writing unit, a drive unit, a compensation unit, and a light-emitting control unit. The data writing unit is electrically connected to a scan signal terminal, a data signal terminal, and the drive unit; the compensation unit is electrically connected to the scan signal terminal and the drive unit. The data writing unit and the compensation unit are configured to conduct in response to a scan signal transmitted from the scan signal terminal, transmitting a data signal from the data signal terminal to the drive unit. The light-emitting control unit is electrically connected to an enable signal terminal, a first voltage signal terminal, the drive unit, and the anode of the light-emitting device; the light-emitting control unit is configured to conduct in response to an enable signal transmitted from the enable signal terminal, connecting the path between the first voltage signal terminal and the anode of the light-emitting device. The timing of the first reset signal transmission to the first reset unit is earlier than the timing of the data signal transmission to the drive unit; the timing of the second reset signal transmission to the second reset unit is earlier or later than the timing of the first reset signal transmission to the first reset unit. The timing of the second reset signal transmission to the second reset unit has multiple options, which can enhance the flexibility and practicality of the pixel circuit.

[0014] In a possible design in the first aspect, the data writing unit includes a third transistor, the driving unit includes a fourth transistor and a capacitor, the compensation unit includes a fifth transistor, and the light-emitting control unit includes a sixth and a seventh transistor. The control electrode of the third transistor is electrically connected to the scan signal terminal, the first electrode of the third transistor is electrically connected to the data signal terminal, and the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor. The control electrode of the fourth transistor is electrically connected to the second electrode of the fifth transistor, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor. The control electrode of the fifth transistor is electrically connected to the scan signal terminal. The control electrode of the sixth transistor is electrically connected to the enable signal terminal, the first electrode of the sixth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the sixth transistor is electrically connected to the first electrode of the fourth transistor. The control electrode of the seventh transistor is electrically connected to the enable signal terminal, the first electrode of the seventh transistor is electrically connected to the second electrode of the fourth transistor, and the second electrode of the seventh transistor is electrically connected to the anode of the light-emitting device. The first electrode of the capacitor is electrically connected to the control electrode of the fourth transistor, and the second electrode of the capacitor is electrically connected to the first voltage signal terminal.

[0015] In one possible design approach in the first aspect, the drive control circuit further includes a third reset unit. The third reset unit is electrically connected to the first reset signal terminal, the third initial signal terminal, and the drive unit; the third reset unit is configured to be turned on in response to the first reset signal, transmitting a third initial signal from the third initial signal terminal to the drive unit.

[0016] In one possible design of the first aspect, the third reset unit includes an eighth transistor. The control terminal of the eighth transistor is electrically connected to the first reset signal terminal, the first terminal of the eighth transistor is electrically connected to the third initial signal terminal, and the second terminal of the eighth transistor is electrically connected to the drive unit.

[0017] In a second aspect, a display panel is provided, the display panel including a plurality of sub-pixels. Each sub-pixel includes a pixel circuit and a light-emitting device, the pixel circuit being electrically connected to the anode of the light-emitting device. The pixel circuit includes the pixel circuit described in any embodiment of the first aspect.

[0018] In a possible design in the second aspect, the pixel circuit's reset circuit includes a first reset unit and a second reset unit. The display panel also includes: a first reset signal line, a second reset signal line, a first initial signal line, and a second initial signal line. The first reset unit is electrically connected to the first reset signal line via a first reset signal terminal and to the first initial signal line via a first initial signal terminal. The second reset unit is electrically connected to the second reset signal line via a second reset signal terminal and to the second initial signal line via a second initial signal terminal.

[0019] In a possible design approach in the second aspect, the display panel further includes scan signal lines; the driving control circuit of the pixel circuit includes a data writing unit, which is electrically connected to the scan signal lines via a scan signal terminal. Multiple sub-pixels are arranged in multiple rows. The first reset signal line electrically connected to the first reset unit of the m-th row sub-pixel is electrically connected to the scan signal line electrically connected to the data writing unit of the n-th row sub-pixel. The second reset signal line electrically connected to the second reset unit of the m-th row sub-pixel is electrically connected to the scan signal line electrically connected to the data writing unit of the nj-th row sub-pixel; where m and n are both positive integers, j is an integer, and m ≠ n. This avoids the need for a separate circuit structure to generate the first reset signal, simplifying the structure of the display panel.

[0020] In a possible design approach in the second aspect, multiple sub-pixels are arranged in multiple columns. The driving control circuit of the pixel circuit includes a third reset unit; the display panel also includes multiple third initial signal lines extending along the column direction; the multiple third initial signal lines are electrically connected to the third reset units of the multiple columns of sub-pixels respectively. At least two third initial signal lines transmit third initial signals with different voltage values, and the sub-pixels connected to the third initial signal lines transmitting third initial signals with different voltage values ​​emit different colors.

[0021] In this way, the voltage values ​​of the third initial signals transmitted by at least two third initial signal lines are different, and the sub-pixels connected to the third initial signal lines that transmit third initial signals with different voltage values ​​emit different colors. The initial state of the control electrode of the fourth transistor of the sub-pixel that emits different colors of light can be changed by using the third reset unit to adjust the magnitude of the subsequently generated driving current. This makes the turn-on time of the light-emitting devices used to emit different colors of light more consistent, improves the low grayscale color shift problem caused by the different capacitance and threshold voltage of the light-emitting devices used to emit different colors of light, and improves the display effect of the display panel.

[0022] In a possible design approach in the second aspect, the multiple columns of sub-pixels include a first sub-pixel column and a second sub-pixel column. The emission color of each sub-pixel in the first sub-pixel column is different from the emission color of each sub-pixel in the second sub-pixel column. Multiple third initial signal lines include a third sub-signal line and a fourth sub-signal line. The third sub-signal line is electrically connected to each third reset unit in the first sub-pixel column, and the fourth sub-signal line is electrically connected to each third reset unit in the second sub-pixel column. The voltage values ​​of the third initial signals transmitted by the third sub-signal line and the fourth sub-signal line are different.

[0023] In a possible design in the second aspect, the first sub-pixel column includes a plurality of first color sub-pixels, and the second sub-pixel column includes a plurality of second color sub-pixels and third color sub-pixels alternately arranged along the column direction.

[0024] In a possible design approach in the second aspect, the multiple sub-pixel columns also include a third sub-pixel column, and the multiple third initial signal lines also include a fifth sub-signal line, which is electrically connected to each third reset unit in the third sub-pixel column. The first sub-pixel column includes multiple first-color sub-pixels, the second sub-pixel column includes multiple second-color sub-pixels, and the third sub-pixel column includes multiple third-color sub-pixels.

[0025] In the second possible design, the voltage values ​​of the third initial signal transmitted by the third sub-signal line, the fourth sub-signal line, and the fifth sub-signal line are all different.

[0026] In the second possible design, the voltage values ​​of the third initial signal transmitted by the fifth sub-signal line and the fourth sub-signal line are the same.

[0027] In a second possible design approach, the display panel also includes multiple auxiliary signal lines extending along the row direction. These auxiliary signal lines are electrically connected to multiple third initial signal lines that transmit the same third initial signal value.

[0028] Thirdly, a display panel is provided, comprising: a plurality of sub-pixels and a plurality of initial signal lines. The plurality of sub-pixels are arranged in multiple rows; each sub-pixel includes a pixel circuit and a light-emitting device. The pixel circuit includes a drive control circuit and a reset circuit. The drive control circuit is electrically connected to the anode of the light-emitting device. The drive control circuit is configured to provide a drive signal to the anode of the light-emitting device to drive the light-emitting device to emit light. The reset circuit is electrically connected to a reset signal terminal, an initial signal terminal, and the anode of the light-emitting device. The reset circuit is configured to conduct in response to a reset signal transmitted from the reset signal terminal, and to transmit an initial signal from the initial signal terminal to the anode of the light-emitting device in a time-division multiplexing manner. The voltage value of the initial signal received by the anode of the light-emitting device is different at different times. The plurality of initial signal lines extend along the row direction. The plurality of initial signal lines are electrically connected to the reset circuits of the multiple rows of sub-pixels respectively through the initial signal terminals. The plurality of initial signal lines include at least: a plurality of first sub-signal lines and a plurality of second sub-signal lines alternately arranged along the column direction, the plurality of first sub-signal lines being electrically connected, and the plurality of second sub-signal lines being electrically connected.

[0029] Fourthly, a display module is provided, comprising: a display panel as described in any embodiment of the second or third aspect, and a display driver integrated circuit. The display driver integrated circuit is electrically connected to the display panel.

[0030] Fifthly, an electronic device is provided, comprising: a display module as described in any embodiment of the fourth aspect, and a drive controller. The drive controller is coupled to the display panel.

[0031] Sixthly, a driving method for a pixel circuit is provided. The pixel circuit includes a driving control circuit and a reset circuit. The driving control circuit is electrically connected to the anode of the light-emitting device, and the reset circuit is electrically connected to a reset signal terminal, an initial signal terminal, and the anode of the light-emitting device. The display stage of a frame of image includes a light-emitting stage and a non-light-emitting stage. In the light-emitting stage, the driving control circuit provides a driving signal to the anode of the light-emitting device to drive the light-emitting device to emit light; in the non-light-emitting stage, the reset circuit is turned on in response to the reset signal transmitted from the reset signal terminal, and transmits a first initial signal and a second initial signal from the initial signal terminal to the anode of the light-emitting device in a time-division manner. The voltage values ​​of the first initial signal and the second initial signal are different.

[0032] In a possible design in the sixth aspect, the reset circuit includes a first reset unit and a second reset unit, a reset signal terminal including a first reset signal terminal and a second reset signal terminal, and an initial signal terminal including a first initial signal terminal and a second initial signal terminal. The first reset unit is electrically connected to the first reset signal terminal, the first initial signal terminal, and the anode of the light-emitting device; the second reset unit is electrically connected to the second reset signal terminal, the second initial signal terminal, and the anode of the light-emitting device.

[0033] During the non-light-emitting phase, the reset circuit is turned on in response to the reset signal transmitted from the reset signal terminal, and transmits the first initial signal and the second initial signal from the initial signal terminal to the anode of the light-emitting device in a time-division manner. This includes: a first reset unit being turned on in response to the first reset signal transmitted from the first reset signal terminal, and transmitting the first initial signal from the first initial signal terminal to the anode of the light-emitting device; and a second reset unit being turned on in response to the second reset signal transmitted from the second reset signal terminal, and transmitting the second initial signal from the second initial signal terminal to the anode of the light-emitting device; wherein the timing of the transmission of the first reset signal to the first reset unit and the timing of the transmission of the second reset signal to the second reset unit are different.

[0034] In a possible design in the sixth aspect, the drive control circuit includes: a data writing unit, a drive unit, a compensation unit, and a light-emitting control unit. The data writing unit is electrically connected to the scan signal terminal, the data signal terminal, and the drive unit; the compensation unit is electrically connected to the scan signal terminal and the drive unit; and the light-emitting control unit is electrically connected to the enable signal terminal, the first voltage signal terminal, the drive unit, and the anode of the light-emitting device.

[0035] During the light-emitting stage, the driving control circuit provides a driving signal to the anode of the light-emitting device to drive the light-emitting device to emit light, including: the light-emitting control unit turns on in response to the enable signal transmitted by the enable signal terminal, connecting the path between the first voltage signal terminal and the anode of the light-emitting device.

[0036] During the non-light-emitting phase, the reset circuit is turned on in response to the reset signal transmitted from the reset signal terminal, and transmits the first initial signal and the second initial signal from the initial signal terminal to the anode of the light-emitting device in a time-division manner. It also includes a data writing unit and a compensation unit that are turned on in response to the scan signal transmitted from the scan signal terminal, and transmit the data signal from the data signal terminal to the driving unit. The first reset signal is transmitted to the first reset unit earlier than the data signal is transmitted to the driving unit. The second reset signal is transmitted to the second reset unit earlier or later than the first reset signal is transmitted to the first reset unit.

[0037] The technical effects of any of the design methods in the second, fourth, fifth, and sixth aspects can be found in the technical effects of the different design methods in the first aspect, and will not be repeated here.

[0038] In a seventh aspect, a driving method for a pixel circuit is provided. The pixel circuit includes a driving control circuit and a reset circuit. The driving control circuit is electrically connected to the anode of the light-emitting device, and the reset circuit is electrically connected to a reset signal terminal, an initial signal terminal, and the anode of the light-emitting device. The display stage of a frame of image includes a light-emitting stage and a non-light-emitting stage; in the light-emitting stage, the driving control circuit provides a driving signal to the anode of the light-emitting device to drive the light-emitting device to emit light. In the non-light-emitting stage, the reset circuit is turned on in response to the reset signal transmitted from the reset signal terminal, transmitting the initial signal from the initial signal terminal to the anode of the light-emitting device; wherein the voltage value of the initial signal received by the anode of the light-emitting device is different at different times.

[0039] The pixel circuit driving method provided in some embodiments of this application fills the internal defects or charge vacancies of the material of the light-emitting device using the higher voltage portion of the initial signal before the light-emitting stage. In this way, during the light-emitting stage, when the driving control circuit transmits the driving signal to the anode of the light-emitting device, the amount of charge captured by the light-emitting device can be reduced, the current loss in the driving signal used to fill the internal defects or charge vacancies of the material of the light-emitting device can be reduced, and the proportion of the current used to drive the light-emitting device to emit light can be increased. This allows most or even all of the driving signal to be used for the light-emitting device to emit light, thereby reducing the impact of the internal defects or charge vacancies of the material of the light-emitting device on the brightness of the light-emitting device.

[0040] In this way, when the brightness (or grayscale) presented by the light-emitting device changes, the turn-on speed of the light-emitting device can be increased, so that the brightness (or grayscale) presented by the light-emitting device in different frames approaches or reaches the target brightness (or target grayscale), thereby improving display abnormalities, reducing the impact of problems such as ghosting and color shift, and improving display effect.

[0041] The technical effects of any of the design methods in the third, fourth, and fifth aspects can be found in the technical effects of different design methods in the seventh aspect, which will not be repeated here. Attached Figure Description

[0042] Figure 1 A structural diagram of an electronic device provided in an embodiment of this application;

[0043] Figure 2 A partial structural diagram of an electronic device provided in an embodiment of this application;

[0044] Figure 3 An equivalent circuit diagram of a pixel circuit and a light-emitting device provided for an embodiment of this application;

[0045] Figure 4 A method corresponding to the embodiments of this application is provided. Figure 3 The timing diagram of the pixel circuit is shown.

[0046] Figure 5 A schematic diagram of a motion blur phenomenon provided in an embodiment of this application;

[0047] Figure 6 A brightness curve of a light-emitting device in different frames after switching from a dark screen to a light screen, provided as an embodiment of this application;

[0048] Figure 7 This application provides a normalized curve of the luminance of different color sub-pixels after switching from a dark screen to a light screen.

[0049] Figure 8 An architectural diagram of a pixel circuit and a light-emitting device provided for an embodiment of this application;

[0050] Figure 9 A method corresponding to the embodiments of this application is provided. Figure 8 The timing diagram of the pixel circuit is shown.

[0051] Figure 10 A structural diagram of a display panel provided in an embodiment of this application;

[0052] Figure 11 This is a structural diagram of another display panel provided in an embodiment of this application;

[0053] Figure 12 Another pixel circuit and light-emitting device architecture diagram provided for an embodiment of this application;

[0054] Figure 13 This is an architectural diagram of another pixel circuit and light-emitting device provided in an embodiment of this application;

[0055] Figure 14An equivalent circuit diagram of another pixel circuit and light-emitting device provided for an embodiment of this application;

[0056] Figure 15a A method corresponding to the embodiments of this application is provided. Figure 12 , Figure 13 and Figure 14 The timing diagram of the pixel circuit is shown.

[0057] Figure 15b Another corresponding embodiment provided for this application Figure 12 , Figure 13 and Figure 14 The timing diagram of the pixel circuit is shown.

[0058] Figure 15c Another embodiment corresponding to the present application Figure 12 , Figure 13 and Figure 14 The timing diagram of the pixel circuit is shown.

[0059] Figure 16 This is a structural diagram of another display panel provided in an embodiment of this application;

[0060] Figure 17 This is a structural diagram of another display panel provided in an embodiment of this application;

[0061] Figure 18 This is a structural diagram of another display panel provided in an embodiment of this application;

[0062] Figure 19 This is a structural diagram of another display panel provided in an embodiment of this application;

[0063] Figure 20 This is a structural diagram of another display panel provided in an embodiment of this application;

[0064] Figure 21 This is a structural diagram of another display panel provided in an embodiment of this application;

[0065] Figure 22 This is a structural diagram of another display panel provided in an embodiment of this application;

[0066] Figure 23 This is a structural diagram of another display panel provided in an embodiment of this application. Detailed Implementation

[0067] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0068] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more. "At least one item" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items.

[0069] Furthermore, to facilitate a clear description of the technical solutions in the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that "first" and "second" are not necessarily different. Meanwhile, in the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is being used as an example, illustration, or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of terms such as "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding.

[0070] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "coupled" may indicate, for example, that two or more components have direct physical or electrical contact, or it may mean that two or more components do not have direct contact but still cooperate or interact with each other. The term "connected" should be interpreted broadly; for example, "connected" can mean directly linked or indirectly linked through an intermediate medium. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. Furthermore, the use of "based on" implies openness and inclusiveness, because processes, steps, calculations, or other actions "based on" one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0071] In this application embodiment, "upper," "lower," "left," and "right" are not limited to the orientation of the components schematically placed in the accompanying drawings. It should be understood that these directional terms can be relative concepts used for description and clarification, and can vary accordingly depending on the orientation of the components in the accompanying drawings. In the drawings, for clarity, the thickness of layers and regions is exaggerated, and the dimensional proportions between the parts in the illustrations do not reflect actual dimensional proportions. Therefore, variations in shape relative to the drawings are conceivable due to, for example, manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as being limited to the shapes of the areas shown in this application, but rather include shape deviations caused, for example, by manufacturing. For example, an etched area shown as rectangular would typically have a curved feature. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0072] Furthermore, the architecture and scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of architecture and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0073] In some embodiments of this application, the circuit structures (e.g., pixel circuits) used can be thin-film transistors (TFTs), metal-oxide-semiconductor (MOS) transistors, or other switching devices with the same characteristics. Further, the first electrode of each transistor is one of the source and drain, and the second electrode of each transistor is the other of the source and drain. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable; that is, the first and second electrodes of the transistors in some embodiments of this application can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first electrode is the source and the second electrode is the drain; or, when the transistor is an N-type transistor, the first electrode is the drain and the second electrode is the source.

[0074] The transistors included in the circuit structures (e.g., pixel circuits) provided in some embodiments of this application can all be N-type transistors or all be P-type transistors. Alternatively, some of the transistors in the circuit structure (e.g., pixel circuit) may be N-type transistors, and others may be P-type transistors. "Active level" refers to the level that enables each unit or transistor in the pixel circuit to conduct.

[0075] The accompanying drawings in this application embodiment are illustrated using an example where all transistors included in the pixel circuit are P-type transistors. Accordingly, "effective level" refers to a low level.

[0076] In some embodiments of this application, the circuit structures (e.g., pixel circuits) provided do not represent actual components, but rather represent the junctions of related couplings in the circuit diagram. In other words, these nodes are equivalent to the junctions of related couplings in the circuit diagram.

[0077] Some embodiments of this application provide an electronic device. This electronic device can be, for example, a consumer electronics product, a home electronics product, an in-vehicle electronics product, or a financial terminal product. Consumer electronics products can be mobile phones, tablets, desktop computers, laptops, handheld computers, personal computers (PCs), netbooks, cellular phones, personal digital assistants (PDAs), augmented reality (AR) devices, virtual reality (VR) devices, artificial intelligence (AI) devices, and smart wearable devices (e.g., smartwatches, smart bracelets), etc. This application does not impose any special limitations on the specific type of this electronic device. Home electronics products can be smart door locks, televisions, remote controls, refrigerators, and rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), etc. In-vehicle electronics products can be in-vehicle navigation systems, in-vehicle DVDs, etc. Financial terminal products can be ATMs, self-service terminals, etc. This application does not impose any special limitations on the specific form of the above-mentioned electronic devices.

[0078] For ease of explanation, the following explanation uses a mobile phone as an example of an electronic device. This should not be considered a specific limitation on the structural form of electronic devices. Figure 1 This is a structural diagram of an electronic device provided in an embodiment of this application. Figure 2 This is a partial structural diagram of an electronic device provided in an embodiment of this application. Those skilled in the art will understand that... Figure 1 and Figure 2 The architecture of the electronic device shown does not constitute a limitation on the electronic device, which may include, for example... Figure 1 and Figure 2 The components shown may have more or fewer components, or may be combined as follows: Figure 1 and Figure 2 Some of the components shown, or those that can be used with, for example Figure 1and Figure 2 The component arrangements shown are different.

[0079] In some embodiments, such as Figure 1 As shown, the electronic device 1000 mainly includes: a display module 100, a middle frame 200, a housing 300, and a cover plate 400.

[0080] The housing 300 is located on the backlight side of the display module 100. The mid-frame 200 is located between the display module 100 and the housing 300. The surface of the mid-frame 200 away from the display module 100 (i.e., the surface facing the housing 300) is used to mount internal components such as batteries, circuit boards, cameras, and antennas. The cover plate 400 is located on the side of the display module 100 away from the mid-frame 200. The cover plate 400 can be, for example, a cover glass, which may have a certain degree of toughness. The display module 100 has a light-emitting side capable of displaying images and a backlight side disposed opposite to the light-emitting side. The mid-frame 200 is located on the backlight side of the display module 100, and the cover plate 400 is located on the light-emitting side of the display module 100.

[0081] In some examples, such as Figure 2 As shown, the electronic device 1000 also includes a drive controller 500, which is coupled to the display module 100. The drive controller 500 can receive image signals RGB and control signals CTRL, and output image data signals DATA that match the interface specifications of the display module 100 according to the image signal RGB. The drive controller 500 can also output data control signals DCS. The drive controller 500 may include, for example, a system-on-chip (SOC).

[0082] The aforementioned display module 100 includes, for example, a display panel 10 and a display driver integrated circuit (DDIC) 20. The DDIC 20 is coupled to, for example, a drive controller 500, receives signals output by the drive controller 500, and provides display signals to the display panel 10. Of course, the display module 100 may also include structures such as flexible circuit boards.

[0083] For example, the display driver integrated circuit 20 receives a data control signal DCS and an image data signal DATA from the driver controller 500. The display driver integrated circuit 20 converts the image data signal DATA into a data signal and outputs the data signal to multiple data signal lines DL in the display panel 10. The data signal is an analog voltage corresponding to the grayscale value of the image data signal DATA. The display driver integrated circuit 20 can also output scan control signals SCS (such as clock signal CLK, initial input signal STV, reset signal RST, etc.) required for display to the display panel 10.

[0084] In some examples, the display panel 10 described above can be a self-emissive display panel such as an organic light-emitting diode (OLED) display panel, an active-matrix organic light-emitting diode (AMOLED) display panel, a mini organic light-emitting diode (Mini-OLED) display panel, a micro light-emitting diode (Micro-LED) display panel, a micro organic light-emitting diode (Micro-OLED) display panel, or a quantum dot light-emitting diode (QLED) display panel. In this case, the display panel 10 can be a rigid display panel or a flexible display panel.

[0085] For any of the above-described display panels 10, the display panel 10 includes an active display area (AA) and a non-display area BB located around the active display area AA. The active display area AA is used to display images. For example... Figure 2 As shown, the display panel 10 includes a plurality of sub-pixels P disposed within the effective display area AA. In some embodiments of this application, the sub-pixels P are illustrated by arranging them in a matrix form. Sub-pixels P arranged in a row along the row direction (or horizontal direction) X are called sub-pixels in the same row, and sub-pixels P arranged in a row along the column direction (or vertical direction) Y are called sub-pixels in the same column.

[0086] Figure 3 An equivalent circuit diagram of a sub-pixel is provided for an embodiment of this application. For example... Figure 3 As shown, a sub-pixel P includes a pixel circuit 1 and a light-emitting device 2 electrically connected to the pixel circuit 1. The light-emitting device 2 is, for example, an OLED. The pixel circuit 1 generates a driving signal and transmits the driving signal to the light-emitting device 2 electrically connected to it, driving the light-emitting device 2 to emit light. The light emitted by the light-emitting devices 2 of multiple sub-pixels P cooperates to enable the electronic device 1000 to display an image.

[0087] The aforementioned plurality of sub-pixels P may include sub-pixels of various colors. For example, the plurality of sub-pixels P may include: red sub-pixels, green sub-pixels, and blue sub-pixels. The light-emitting device 2 of the red sub-pixel emits red light, the light-emitting device 2 of the green sub-pixel emits green light, and the light-emitting device 2 of the blue sub-pixel emits blue light. Of course, the plurality of sub-pixels P may also include sub-pixels of other colors. When the plurality of sub-pixels P includes red, green, and blue sub-pixels, these three colors of sub-pixels can be arranged in a horizontal, vertical, or triangular pattern. This application embodiment does not limit this arrangement.

[0088] Continue reading Figure 2 The display panel 10 also includes a driving circuit 3, multiple scan signal lines GL, multiple reset signal lines RL, and multiple enable signal lines EL.

[0089] The aforementioned driving circuit 3 receives the scan control signal SCS from the display driver integrated circuit 20. In response to the scan control signal SCS, the driving circuit 3 can output scan signals to the multiple scan signal lines GL, reset signals to the multiple reset signal lines RL, and enable signals to the multiple enable signal lines EL.

[0090] For example, the driving circuit 3 is, for instance, a gate driver on array (GOA) and / or an emission circuit on array (EOA). The EOA is configured to output enable signals to the plurality of enable signal lines EL respectively; the GOA is configured to output scan signals to the plurality of scan signal lines GL respectively, and to output reset signals to the plurality of reset signal lines RL respectively.

[0091] In addition, the display panel 10 also includes, for example, multiple initial signal lines VL, multiple first voltage signal lines, and multiple second voltage signal lines. These multiple initial signal lines VL, multiple first voltage signal lines, and multiple second voltage signal lines are electrically connected, for example, to a voltage generator in an electronic device; the voltage generator can output initial signals to the multiple initial signal lines VL respectively, output first voltage signals to the multiple first voltage signal lines respectively, and output second voltage signals to the second voltage signal lines.

[0092] like Figure 3 As shown, pixel circuit 1, for example, has a scan signal terminal SS, a data signal terminal SD, a reset signal terminal SR, an enable signal terminal EM, an initial signal terminal Vinit, a first voltage signal terminal ELVDD, and a second voltage signal terminal ELVSS. Combined with... Figure 2 and Figure 3Each pixel circuit 1 in the same row of sub-pixels P is electrically connected to the scan signal line GL via the scan signal terminal SS. Each pixel circuit 1 in the same row of sub-pixels P is electrically connected to the reset signal line RL via the reset signal terminal SR. Each pixel circuit 1 in the same row of sub-pixels P is electrically connected to the enable signal line EL via the enable signal terminal EM. Each pixel circuit 1 in the same column of sub-pixels P is electrically connected to the data signal line DL via the data signal terminal SD.

[0093] Furthermore, the pixel circuit 1 in each sub-pixel P is electrically connected to the initial signal line VL via the initial signal terminal Vinit, the pixel circuit 1 in each sub-pixel P is electrically connected to the first voltage signal line via the first voltage signal terminal ELVDD, and the light-emitting device 2 in each sub-pixel P is electrically connected to the second voltage signal line via the second voltage signal terminal ELVSS.

[0094] The number of scan signal lines GL, reset signal lines RL, and initial signal lines VL electrically connected to each pixel circuit 1 are related to the specific structure of the pixel circuit 1. If the specific structure of the pixel circuit 1 changes, the number of scan signal lines GL, reset signal lines RL, and initial signal lines VL electrically connected to each pixel circuit 1 may also change. This application does not limit this aspect.

[0095] by Figure 3 The structure of pixel circuit 1 shown is an example. Figure 3 The pixel circuit 1 shown is electrically connected, for example, to a scan signal line GL, a reset signal line RL, and two initial signal lines.

[0096] For example, such as Figure 3 As shown, pixel circuit 1 includes a first reset transistor T1, a write transistor T3, a drive transistor T4, a compensation transistor T5, a first light-emitting control transistor T6, a second light-emitting control transistor T7, a second reset transistor T8, and a capacitor C. The first reset transistor T1, write transistor T3, drive transistor T4, compensation transistor T5, first light-emitting control transistor T6, second light-emitting control transistor T7, and second reset transistor T8 are, for example, P-type transistors.

[0097] The control electrode (also known as the gate) of the first reset transistor T1 is electrically connected to the reset signal terminal SR, and is also electrically connected to the reset signal line RL through the reset signal terminal SR. The first electrode of the first reset transistor T1 is electrically connected to the initial signal terminal Vinit (e.g., the first initial signal terminal Vinit1), and is also electrically connected to the initial signal line (e.g., the first initial signal line) through the first initial signal terminal Vinit1. The second electrode of the first reset transistor T1 is electrically connected to the first node N1; in other words, the second electrode of the first reset transistor T1 is electrically connected to the anode of the light-emitting device 2. The cathode of the light-emitting device 2 is electrically connected to the second voltage signal terminal ELVSS.

[0098] The control terminal of the write transistor T3 is electrically connected to the scan signal terminal SS, and is also electrically connected to the scan signal line GL through the scan signal terminal SS; the first terminal of the write transistor T3 is electrically connected to the data signal terminal SD, and is also electrically connected to the data signal line DL through the data signal terminal SD; the second terminal of the write transistor T3 is electrically connected to the second node N2.

[0099] The control electrode of the driving transistor T4 is electrically connected to the third node N3, the first electrode of the driving transistor T4 is electrically connected to the second node N2, and the second electrode of the driving transistor T4 is electrically connected to the fourth node N4.

[0100] The control terminal of the compensation transistor T5 is electrically connected to the scan signal terminal SS, and is also electrically connected to the scan signal line GL through the scan signal terminal SS; the first terminal of the compensation transistor T5 is electrically connected to the fourth node N4; and the second terminal of the compensation transistor T5 is electrically connected to the third node N3.

[0101] The control electrode of the first light-emitting control transistor T6 is electrically connected to the enable signal terminal EM, and is electrically connected to the enable signal line EL through the enable signal terminal EM; the first electrode of the first light-emitting control transistor T6 is electrically connected to the first voltage signal terminal ELVDD, and is electrically connected to the first voltage signal line through the first voltage signal terminal ELVDD; the second electrode of the first light-emitting control transistor T6 is electrically connected to the second node N2.

[0102] The control electrode of the second light-emitting control transistor T7 is electrically connected to the enable signal terminal EM, and is electrically connected to the enable signal line EL through the enable signal terminal EM; the first electrode of the second light-emitting control transistor T7 is electrically connected to the fourth node N4, and the second electrode of the second light-emitting control transistor T7 is electrically connected to the first node N1.

[0103] The control terminal of the second reset transistor T8 is electrically connected to the reset signal terminal SR, and is electrically connected to the reset signal line RL through the reset signal terminal SR; the first terminal of the second reset transistor T8 is electrically connected to the initial signal terminal Vinit (e.g., the third initial signal terminal Vinit3), and is electrically connected to the initial signal line (e.g., the third initial signal line) through the third initial signal terminal Vinit3; the second terminal of the second reset transistor T8 is electrically connected to the third node N3.

[0104] Figure 4 A method corresponding to the embodiments of this application is provided. Figure 3 The timing diagram of the pixel circuit is shown. Figure 4 In the diagram, EM represents the enable signal received by pixel circuit 1, SR represents the reset signal received by pixel circuit 1, SS represents the scan signal received by pixel circuit 1, and L represents the change in the brightness of light-emitting device 2 when the grayscale presented by light-emitting device 2 switches from low grayscale to high grayscale.

[0105] Below, in conjunction with Figure 3 and Figure 4 The working process of pixel circuit 1 is illustrated schematically. For example... Figure 4 As shown, the working process of pixel circuit 1 includes: reset stage S1, data writing and compensation stage S2, and light emission stage S3.

[0106] During the reset phase S1, both the first reset transistor T1 and the second reset transistor T8 are turned on in response to the reset signal. The first reset transistor T1 transmits a first initial signal to the first node N1 to reset the anode of the light-emitting device 2 and reset the electron-hole state within the material of the light-emitting device 2. The second reset transistor T8 transmits a third initial signal to the third node N3 to reset the third node N3. The light-emitting device 2 includes, but is not limited to, an anode, a cathode, and film layers such as a light-emitting layer, an electron transport layer, and a hole transport layer located between the anode and cathode. The material of the light-emitting device 2 includes, but is not limited to, the materials of the film layers such as the anode, cathode, light-emitting layer, electron transport layer, and hole transport layer.

[0107] During the data writing and compensation stage S2, both the writing transistor T3 and the compensation transistor T5 are turned on in response to the scan signal. The data signal is transmitted to the third node N3 in sequence through the writing transistor T3, the driving transistor T4 and the compensation transistor T5, thereby realizing the writing of the data signal and the compensation of the threshold voltage of the driving transistor T4.

[0108] During the light-emitting stage S3, both the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are turned on in response to the enable signal, thus opening the path between the first voltage signal terminal ELVDD and the light-emitting device 2. The driving signal (e.g., driving current) generated based on the data signal and the first voltage signal is transmitted to the light-emitting device 2 to drive the light-emitting device 2 to emit light.

[0109] Here, during the reset phase S1, the reset of the first node N1 by the first reset transistor T1 helps to reduce the brightness of the black screen displayed on the display panel 10 and improve the contrast. However, when the grayscale of the light-emitting device 2 switches from a low grayscale (e.g., black) to a high grayscale (e.g., white), a portion of the aforementioned driving signal is used to fill the internal defects or charge vacancies in the material of the light-emitting device, making it difficult for the driving signal to be fully used for the light emission of the light-emitting device 2. This results in a slower start-up speed for the light-emitting device 2, making it difficult to reach the target brightness during the current frame's image display phase. Consequently, this can lead to display abnormalities on the display panel 10, such as ghosting and color shift.

[0110] Furthermore, the voltage value of the first initial signal is usually lower than that of the second voltage signal, and the voltage difference between the two is relatively large, in order to avoid the light-emitting device 2 emitting light during the reset phase S1. However, this results in a large degree of reverse bias on the light-emitting device 2, making it difficult to reset the electron-hole state within the material of the light-emitting device 2. When the grayscale displayed by the light-emitting device 2 switches from a low grayscale to a high grayscale, it also affects the start-up speed and display brightness of the light-emitting device 2, thus affecting the display effect of the display panel 10.

[0111] Specifically, Figure 5 (a) illustrates an image against a dark mode background, where the background has low brightness (or grayscale) and the image contains patterns with high brightness (or grayscale), such as text or images. For example, the light-emitting device in area A1 displays a low grayscale, and the light-emitting device in area A2 displays a high grayscale.

[0112] Figure 5 (b) in the middle indicates Figure 5 The image shown in (a) has changed. For example, when an electronic device is swiped upwards, the image displayed on the electronic device changes. The grayscale of the light-emitting device in area A11, which is closer to area A2 in area A1, changes from a low grayscale (e.g., black) to a high grayscale (e.g., white). The grayscale of the light-emitting device in area A21, which is closer to area A1 in area A2, changes from a high grayscale (e.g., white) to a low grayscale (e.g., black).

[0113] Within region A11, due to the driving signal generated by the pixel circuit, it is necessary to pre-fill the internal defects or charge vacancies in the material of the light-emitting device. Figure 5 The screen shown in (a) switches to Figure 5 In the case of the image shown in (b), as Figure 6 As shown, the brightness of the light-emitting device in the first frame is difficult to match the brightness in the second frame, and even the brightness in the second and third frames is difficult to match the brightness in subsequent frames. Figure 5 As shown in (b), the light-emitting device in area A11 did not reach the target brightness (or target gray level), resulting in a ghosting phenomenon in the image (for example, when dragging the image up and down, the edges of the text or pictures in the image are discolored, blurry, or have colored shadows on the edges), affecting the display effect.

[0114] For example, if the brightness variation curves of red, green, and blue subpixels are different, the brightness ratio of these subpixels in the first frame will be inconsistent compared to the brightness ratio in the second frame, and even the brightness ratio in the second and third frames will be inconsistent compared to the brightness ratio in subsequent frames. This will result in an inconsistency in the color matching of red, green, and blue light, leading to color difference and creating colored ghosting. Figure 7 The data shown is normalized and does not mean that the brightness ratio of red, green and blue subpixels in the second, third and subsequent frames is the same as that in the first frame, nor does it mean that the absolute brightness of red, green and blue light is the same.

[0115] In some possible implementations, the ghosting phenomenon can be improved by reducing the voltage value of the data signal corresponding to the black state display (VGMP). However, the adjustment range of VGMP is limited, making it difficult to adjust it at every gray level (or brightness).

[0116] In some other possible implementations, the ghosting phenomenon can be improved by adjusting the voltage value of the first initial signal to be greater than that of the second voltage signal and increasing the voltage difference between the first initial signal and the second voltage signal. However, this results in insufficient black levels on the display panel 10, reducing contrast.

[0117] Based on this, some embodiments of this application provide a driving method for a pixel circuit, which is applied to the pixel circuit. This pixel circuit is, for example, the pixel circuit 1 in the aforementioned display panel 10.

[0118] In some examples, such as Figure 8As shown, the pixel circuit 1 used in the above driving method includes a driving control circuit 11 and a reset circuit 12. The driving control circuit 11 is electrically connected to the anode of the light-emitting device 2. The reset circuit 12 is electrically connected to the reset signal terminal SR, the initial signal terminal Vinit, and the anode of the light-emitting device 2.

[0119] Figure 9 (a) and Figure 9 (b) in the text represents a corresponding embodiment provided in this application. Figure 8 The timing diagram of the pixel circuit is shown. Figure 9 In this context, EM represents the enable signal received by the drive control circuit 11, SR represents the reset signal received by the reset circuit 12, SS represents the scan signal received by the drive control circuit 11, and Vinit represents the initial signal received by the reset circuit 12.

[0120] like Figure 9 As shown, the display stages of an image frame include a non-luminous stage SN and a luminous stage S3.

[0121] During the non-light-emitting phase SN, the aforementioned reset circuit 12 is turned on in response to the reset signal transmitted by the reset signal terminal SR, transmitting the initial signal from the initial signal terminal Vinit to the anode of the light-emitting device 2. The voltage value of the initial signal received by the anode of the light-emitting device 2 varies at different times.

[0122] For example, during the non-light-emitting phase SN, the level of the reset signal repeatedly transitions to the operating level. The reset circuit 12 is able to conduct each time the level of the reset signal transitions to the operating level, thereby transmitting the initial signal to the anode of the light-emitting device 2 in a time-division multiple manner. The initial signal is, for example, a non-constant voltage signal, and its voltage value is variable, differing at different times. The level of the reset signal can be adaptively adjusted for each grayscale (or brightness).

[0123] by Figure 9 (a) and Figure 9 Taking the timing diagram shown in (b) as an example, during the non-light-emitting phase SN, the reset signal level jumps to the operating level at times t1 and t2, respectively. Correspondingly, the reset circuit 12 transmits the initial signal to the anode of the light-emitting device 2 at times t1 and t2, respectively. The voltage values ​​of the initial signal are different at times t1 and t2. For example, in... Figure 9 In (a), the voltage value V1 of the initial signal at time t1 is greater than the voltage value V2 of the initial signal at time t2. Alternatively, in Figure 9 In (b), the voltage value V1 of the initial signal at time t1 is less than the voltage value V2 of the initial signal at time t2.

[0124] The initial signal with a lower voltage value is used to reset the light-emitting device 2. The initial signal with a higher voltage value is used to fill internal defects or charge vacancies in the material of the light-emitting device 2.

[0125] During the light-emitting stage S3, the aforementioned drive control circuit 11 provides a drive signal to the anode of the light-emitting device 2 to drive the light-emitting device 2 to emit light.

[0126] Continue reading Figure 8 The drive control circuit 11 is also electrically connected to the scan signal terminal SS, the data signal terminal SD, the enable signal terminal EM, and the first voltage signal terminal ELVDD. The drive control circuit 11 can receive the scan signal from the scan signal terminal SS, the data signal from the data signal terminal SD, the enable signal from the enable signal terminal EM, and the first voltage signal from the first voltage signal terminal ELVDD. Under the coordination of the scan signal, data signal, enable signal, and first voltage signal, it generates a drive signal and transmits the drive signal to the anode of the light-emitting device 2. Of course, the drive control circuit 11 can also be electrically connected to other signal terminals.

[0127] It is understandable that before the light-emitting stage S3, the initial signal with a higher voltage value has already filled the internal defects or charge vacancies in the material of the light-emitting device 2. Thus, during the light-emitting stage S3, when the drive control circuit 11 transmits the drive signal to the anode of the light-emitting device 2, the amount of charge captured by the light-emitting device 2 can be reduced, the current loss in the drive signal used to fill the internal defects or charge vacancies in the material of the light-emitting device 2 can be reduced, and the proportion of the current used to drive the light-emitting device 2 to emit light can be increased. This allows most or even all of the drive signal to be used for the light-emitting device to emit light, thereby reducing the impact of the internal defects or charge vacancies in the material of the light-emitting device 2 on the brightness of the light-emitting device 2.

[0128] In this way, when the brightness (or grayscale) presented by the light-emitting device 2 changes, the turn-on speed of the light-emitting device 2 can be increased, so that the brightness (or grayscale) presented by the light-emitting device 2 in different frames approaches or reaches the target brightness (or target grayscale), thereby improving display abnormalities, reducing the impact of problems such as ghosting and color shift, and improving display effect.

[0129] Optionally, with Figure 9 Taking (a) as an example, in the above-mentioned non-light-emitting stage SN, the voltage value V1 of the initial signal and the difference between the voltage value V1 of the initial signal and the voltage value of the second voltage signal can be selected and set according to actual needs, as long as it can improve the abnormal display phenomenon and avoid affecting the contrast. This application embodiment does not limit this.

[0130] The structures of the aforementioned drive control circuit 11 and reset circuit 12 include various types, and can be selected and configured according to actual needs.

[0131] In some embodiments, combined with Figure 3 and Figure 8 The drive control circuit 11 includes a write transistor T3, a drive transistor T4, a compensation transistor T5, a first light-emitting control transistor T6, a second light-emitting control transistor T7, and a capacitor C. The reset circuit 12 includes a first reset transistor T1.

[0132] Furthermore, the drive control circuit 11 may also include a second reset transistor T8. In this case, the initial signal terminal Vinit to which the reset circuit 12 is connected may also be referred to as the first initial signal terminal Vinit1.

[0133] For the connection relationship and working process of the first reset transistor T1, write transistor T3, drive transistor T4, compensation transistor T5, first light-emitting control transistor T6, second light-emitting control transistor T7, second reset transistor T8 and capacitor C, please refer to the relevant explanation above, which will not be repeated here.

[0134] More transistors can be incorporated into the drive control circuit 11 and the reset circuit 12, but this application embodiment does not limit this.

[0135] Based on the aforementioned pixel circuit driving method, some embodiments of this application also provide a display panel, which is applied to the aforementioned display module or electronic device. In some examples, the display panel can serve as... Figure 2 The display panel in the middle.

[0136] Figure 10 and Figure 11 These are structural diagrams of a display panel provided in embodiments of this application. In some examples, such as... Figure 10 and Figure 11 As shown, the display panel 10 includes multiple sub-pixels P and multiple initial signal lines VL.

[0137] The aforementioned multiple sub-pixels P are arranged in an array, specifically, in multiple rows and columns. Each row of sub-pixels P includes multiple sub-pixels P spaced apart along the row direction X, and each column of sub-pixels P includes multiple sub-pixels P spaced apart along the column direction Y. Of course, the arrangement of these multiple sub-pixels P is not limited to... Figure 10 and Figure 11 The arrangement shown is as described. The structure of sub-pixels P includes various methods; optionally, sub-pixels P adopt... Figure 8 The structure shown. For example, combined with... Figure 8 and Figure 10Sub-pixel P includes a pixel circuit 1 and a light-emitting device 2 connected together. Pixel circuit 1 includes a drive control circuit 11 and a reset circuit 12. The drive control circuit 11 is electrically connected to the anode of the light-emitting device 2. The drive control circuit 11 is configured to provide a drive signal to the anode of the light-emitting device 2 to drive the light-emitting device 2 to emit light. The reset circuit 12 is electrically connected to a reset signal terminal SR, an initial signal terminal Vinit, and the anode of the light-emitting device 2. The reset circuit 12 is configured to turn on in response to a reset signal transmitted from the reset signal terminal SR, and to transmit the initial signal from the initial signal terminal Vinit to the anode of the light-emitting device 2 in a time-division multiplexing manner. The voltage value of the initial signal received by the anode of the light-emitting device 2 is different at different times.

[0138] For the structure of pixel circuit 1 and its driving method, please refer to the relevant description above, which will not be repeated here.

[0139] Continue reading Figure 10 and Figure 11 The aforementioned multiple initial signal lines VL extend along the row direction X and are spaced apart along the column direction Y. Each of these initial signal lines VL is electrically connected to the reset circuit 12 of a multiple row of sub-pixels P via an initial signal terminal Vinit. For example, each initial signal line VL corresponds one-to-one with a multiple row of sub-pixels P, and one initial signal line VL is electrically connected to the reset circuit 12 of the sub-pixel P located in the same row. Combined with... Figure 8 and Figure 3 When the reset circuit 12 includes a first reset transistor T1 and the drive control circuit 11 includes a second reset transistor T8, the initial signal line VL is electrically connected to the first reset transistor T1 of the sub-pixel P located in the same row through the first initial signal terminal Vinit1, and the second reset transistor T8 is electrically connected to another signal line, for example.

[0140] The aforementioned multiple initial signal lines VL include at least: multiple first sub-signal lines VL11 and multiple second sub-signal lines VL12 alternately arranged along the column direction Y.

[0141] Optionally, such as Figure 10 As shown, the aforementioned multiple initial signal lines VL include multiple first sub-signal lines VL11 and multiple second sub-signal lines VL12, and the multiple first sub-signal lines VL11 and multiple second sub-signal lines VL12 are alternately arranged along the column direction Y. That is, a second sub-signal line VL12 is arranged between two adjacent first sub-signal lines VL11, and a first sub-signal line VL11 is arranged between two adjacent second sub-signal lines VL12. For example, the multiple first sub-signal lines VL11 are electrically connected to the reset circuit 12 of the sub-pixel P in the odd-numbered rows (or 2i-1 rows), and the multiple second sub-signal lines VL12 are electrically connected to the reset circuit 12 of the sub-pixel P in the even-numbered rows (or 2i rows), where i is a positive integer.

[0142] The aforementioned multiple first sub-signal lines VL11 are electrically connected. These multiple first sub-signal lines VL11 are capable of receiving the same initial signal and transmitting the same initial signal to the reset circuit 12 of each sub-pixel P in the odd-numbered rows. Multiple second sub-signal lines VL12 are electrically connected. These multiple second sub-signal lines VL12 are capable of receiving the same initial signal and transmitting the same initial signal to the reset circuit 12 of each sub-pixel P in the even-numbered rows. At the same time, the voltage values ​​of the initial signals received by the first sub-signal lines VL11 and VL12 are different. For example, at the same time, the voltage value of the initial signal received by the first sub-signal line VL11 is greater than or less than the voltage value of the initial signal received by the second sub-signal line VL12.

[0143] Optionally, such as Figure 11 As shown, the aforementioned multiple initial signal lines VL include multiple first sub-signal lines VL11, multiple second sub-signal lines VL12, and multiple third sub-signal lines VL13, and these multiple first sub-signal lines VL11, VL12, and VL13 are periodically arranged along the column direction Y. For example, the multiple first sub-signal lines VL11 are electrically connected to the reset circuit 12 of the sub-pixel P in row 3i-2, the multiple second sub-signal lines VL12 are electrically connected to the reset circuit 12 of the sub-pixel P in row 3i-1, and the multiple third sub-signal lines VL13 are electrically connected to the reset circuit 12 of the sub-pixel P in row 3i, where i is a positive integer.

[0144] The aforementioned multiple first sub-signal lines VL11 are electrically connected. These multiple first sub-signal lines VL11 can receive the same initial signal and transmit the same initial signal to the reset circuit 12 of each sub-pixel P in row 3i-2. Multiple second sub-signal lines VL12 are electrically connected. These multiple second sub-signal lines VL12 can receive the same initial signal and transmit the same initial signal to the reset circuit 12 of each sub-pixel P in row 3i-1. Multiple third sub-signal lines VL13 are electrically connected. These multiple third sub-signal lines VL13 can receive the same initial signal and transmit the same initial signal to the reset circuit 12 of each sub-pixel P in row 3i. At the same time, the voltage values ​​of the initial signals received by the first sub-signal lines VL11, second sub-signal lines VL12, and third sub-signal lines VL13 are different.

[0145] Of course, the aforementioned initial signal lines VL can also be configured in other ways, and can be selectively set according to the design of the display panel.

[0146] The display panel 10 provided in some embodiments of this application can transmit an initial signal to the reset circuit 12 of the row of sub-pixels P connected to it by setting an initial signal line VL. This makes the voltage value of the initial signal received by the anode of the light-emitting device 2 of this row of sub-pixels P different at different times. This can not only reset the light-emitting device 2, but also fill the internal defects or charge vacancies in the material of the light-emitting device 2, reduce the influence of the internal defects or charge vacancies in the material of the light-emitting device 2 on the light-emitting brightness of the light-emitting device 2, and improve display abnormalities.

[0147] Furthermore, by dividing the multiple initial signal lines VL into at least two groups, the sub-signal lines within different groups can transmit initial signals with different voltage values ​​at the same time. By configuring the arrangement of the sub-signal lines within the at least two groups, the reset circuits 12 of adjacent rows of sub-pixels P can be electrically connected to different sub-signal lines, thereby allowing the reset circuits 12 of the two rows of sub-pixels P to receive initial signals with different voltage values ​​at the same time. This avoids the level (or voltage value) of multiple initial signal lines VL or two adjacent initial signal lines VL from changing at the same time, thus preventing the problem of untimely response.

[0148] In some examples, such as Figure 10 and Figure 11 As shown, the display panel 10 also includes multiple auxiliary signal lines FL extending along the column direction Y. The auxiliary signal lines FL are used to connect sub-signal lines that transmit the same initial signal.

[0149] For example, such as Figure 10 As shown, when the multiple initial signal lines VL in the display panel 10 include multiple first sub-signal lines VL11 and multiple second sub-signal lines VL12, the aforementioned multiple auxiliary signal lines FL include a first auxiliary signal line FL1 and a second auxiliary signal line FL2. The first auxiliary signal line FL1 is connected to the multiple first sub-signal lines VL11, and the second auxiliary signal line FL2 is connected to the multiple second sub-signal lines VL12.

[0150] For example, such as Figure 11 As shown, when the multiple initial signal lines VL in the display panel 10 include multiple first sub-signal lines VL11, multiple second sub-signal lines VL12, and multiple third sub-signal lines VL13, the aforementioned multiple auxiliary signal lines FL include a first auxiliary signal line FL1, a second auxiliary signal line FL2, and a third auxiliary signal line FL3. The first auxiliary signal line FL1 is connected to the multiple first sub-signal lines VL11, the second auxiliary signal line FL2 is connected to the multiple second sub-signal lines VL12, and the third auxiliary signal line FL3 is connected to the multiple third sub-signal lines VL13.

[0151] In this way, the voltage generator in the electronic device can transmit the same initial signal to multiple sub-signal lines connected to the auxiliary signal line FL through each auxiliary signal line FL, which helps to simplify the connection between the voltage generator and multiple initial signal lines VL.

[0152] Some embodiments of this application also provide a pixel circuit, which is applied, for example, to... Figure 2 The display panel 10 shown is, as Figure 2 The pixel circuit 1 in the display panel 10 shown. Wherein, Figure 12 , Figure 13 and Figure 14 The architectures of a pixel circuit and a light-emitting device are illustrated respectively.

[0153] In some examples, such as Figure 12 , Figure 13 and Figure 14 As shown, the pixel circuit 1 includes a drive control circuit 11 and a reset circuit 12. The drive control circuit 11 is electrically connected to the anode of the light-emitting device 2. The reset circuit 12 is electrically connected to the reset signal terminal SR, the initial signal terminal Vinit, and the anode of the light-emitting device 2.

[0154] The aforementioned drive control circuit 11 is configured to provide a drive signal to the anode of the light-emitting device 2 to drive the light-emitting device 2 to emit light.

[0155] For example, such as Figure 12 , Figure 13 and Figure 14 As shown, the drive control circuit 11 is also electrically connected to the scan signal terminal SS, the data signal terminal SD, the enable signal terminal EM, and the first voltage signal terminal ELVDD. The drive control circuit 11 can receive the scan signal from the scan signal terminal SS, the data signal from the data signal terminal SD, the enable signal from the enable signal terminal EM, and the first voltage signal from the first voltage signal terminal ELVDD. Under the coordination of the scan signal, data signal, enable signal, and first voltage signal, it generates a drive signal (e.g., a drive current) and transmits the drive signal to the anode of the light-emitting device 2. Of course, the drive control circuit 11 can also be electrically connected to other signal terminals.

[0156] The magnitude of the driving signal received by the light-emitting device 2 affects its luminous brightness (or grayscale). For example, a smaller driving signal results in a lower luminous brightness (or grayscale). Conversely, a larger driving signal results in a higher luminous brightness (or grayscale).

[0157] The aforementioned reset circuit 12 is configured to turn on in response to the reset signal transmitted by the reset signal terminal SR, and to transmit the first initial signal and the second initial signal from the initial signal terminal Vinit to the anode of the light-emitting device 2 in a time-division manner.

[0158] In other words, when the reset circuit 12 is turned on, the anode of the light-emitting device 2 can receive the first initial signal and the second initial signal at different times. For example, the reset circuit 12 can be turned on at the first time and the second time in response to the reset signal; at the first time, the reset circuit 12 can receive the first initial signal and transmit the first initial signal to the anode of the light-emitting device 2; at the second time, the reset circuit 12 can receive the second initial signal and transmit the second initial signal to the anode of the light-emitting device 2.

[0159] The voltage values ​​of the first initial signal and the second initial signal are different. That is, the voltage value of one of the first initial signal and the second initial signal is greater than the voltage value of the other.

[0160] Optionally, of the first initial signal and the second initial signal, the one with the lower voltage value is used to reset (or initialize) the light-emitting device 2; the other with the higher voltage value is used to increase the voltage difference between the anode and cathode of the light-emitting device 2 and fill the internal defects or charge vacancies in the material of the light-emitting device 2.

[0161] Thus, the pixel circuit 1 provided in some embodiments of this application, by setting a reset circuit 12 and setting the reset circuit 12 to transmit first and second initial signals with different voltage values ​​to the anode of the light-emitting device 2 at different times, can fill the internal defects or charge vacancies of the material of the light-emitting device 2 before the driving control circuit 11 drives the light-emitting device 2 to emit light, based on resetting the anode of the light-emitting device 2. Furthermore, the amount of charge captured by the light-emitting device 2 during its light emission process can be reduced, and the current loss in the driving signal (e.g., driving current) used to fill the internal defects or charge vacancies of the material of the light-emitting device 2 can be reduced, increasing the proportion of the current in the driving signal used to drive the light-emitting device 2 to emit light, so that most or even all of the driving signal can be used for the light emission of the light-emitting device 2, thereby reducing the influence of the internal defects or charge vacancies of the material of the light-emitting device 2 on the brightness of the light-emitting device 2.

[0162] When the brightness (or grayscale) presented by the light-emitting device 2 changes, the start-up speed of the light-emitting device 2 can be increased, so that the brightness (or grayscale) presented by the light-emitting device 2 in different frames approaches or reaches the target brightness (or target grayscale), thereby improving image display abnormalities, reducing the impact of problems such as ghosting and color shift, and improving the display effect.

[0163] Optionally, the difference between the voltage value of the higher voltage value of the first initial signal and the voltage value of the second voltage signal can be selected and set according to actual needs, as long as it can improve the display abnormality and avoid affecting the contrast. This application embodiment does not limit this.

[0164] The structure of the reset circuit 12 described above includes various types. The structure of the reset circuit 12 is illustrated below with reference to the accompanying drawings, but the structure of the reset circuit 12 is not limited to this.

[0165] In some examples, such as Figure 12 and Figure 13 As shown, the reset circuit 12 includes a first reset unit 121 and a second reset unit 122. Further, the reset signal terminal SR includes a first reset signal terminal SR1 and a second reset signal terminal SR2, and the initial signal terminal Vinit includes a first initial signal terminal Vinit1 and a second initial signal terminal Vinit2.

[0166] Continue reading Figure 12 and Figure 13 The first reset unit 121 is electrically connected to the first reset signal terminal SR1, the first initial signal terminal Vinit1, and the anode of the light-emitting device 2. The first reset unit 121 is configured to turn on in response to the first reset signal transmitted by the first reset signal terminal SR1, and transmit the first initial signal from the first initial signal terminal Vinit1 to the anode of the light-emitting device 2.

[0167] For example, when the level of the first reset signal jumps to an active level, the first reset unit 121 can be turned on under the control of the first reset signal, receive the first initial signal, and transmit the first initial signal to the anode of the light-emitting device 2.

[0168] Continue reading Figure 12 and Figure 13 The second reset unit 122 is electrically connected to the second reset signal terminal SR2, the second initial signal terminal Vinit2, and the anode of the light-emitting device 2. The second reset unit 122 is configured to turn on in response to the second reset signal transmitted from the second reset signal terminal SR2, transmitting the second initial signal from the second initial signal terminal Vinit2 to the anode of the light-emitting device 2.

[0169] For example, when the level of the second reset signal jumps to an active level, the second reset unit 122 can be turned on under the control of the second reset signal, receive the second initial signal, and transmit the second initial signal to the anode of the light-emitting device 2.

[0170] Specifically, the timing of the transmission of the first reset signal to the first reset unit 121 and the timing of the transmission of the second reset signal to the second reset unit 122 are different. Specifically, the timing of the first reset signal level transitioning to an active level is different from the timing of the second reset signal level transitioning to an active level; the timing of the first reset unit 121 and the second reset unit 122 being turned on are different; and the timing of the first reset unit 121 transmitting the first initial signal to the anode of the light-emitting device 2 is different from the timing of the second reset unit 122 transmitting the second initial signal to the anode of the light-emitting device 2.

[0171] By including a first reset unit 121 and a second reset unit 122 in the reset circuit 12, the first reset unit 121 and the second reset unit 122 can be independently controlled, facilitating the independent transmission of the first initial signal and the second initial signal to the anode of the light-emitting device 2. When the pixel circuit 1 described above is applied to the display panel 10, it facilitates selective control of the first reset unit 121 and the second reset unit 122 in the pixel circuit 1, improving the accuracy of the transmission of the first initial signal and the second initial signal to the anode of the light-emitting device 2, and effectively reducing display anomalies such as ghosting.

[0172] For example, the voltage value of the second initial signal is greater than the voltage value of the first initial signal. In this way, the first initial signal can reset (or initialize) the light-emitting device 2; the second initial signal can increase the voltage difference between the anode and cathode of the light-emitting device 2 and fill the internal defects or charge vacancies in the material of the light-emitting device 2.

[0173] The structures of the first reset unit 121 and the second reset unit 122 described above include various types. The structures of the first reset unit 121 and the second reset unit 122 are illustrated below with reference to the accompanying drawings, but the structures of the first reset unit 121 and the second reset unit 122 are not limited to these.

[0174] In some examples, such as Figure 13 As shown, the first reset unit 121 includes a first transistor M1, and the second reset unit 122 includes a second transistor M2. Of course, more transistors can be provided in the first reset unit 121 and the second reset unit 122 according to actual needs.

[0175] Continue reading Figure 13 The control electrode of the first transistor M1 is electrically connected to the first reset signal terminal SR1, the first electrode of the first transistor M1 is electrically connected to the first initial signal terminal Vinit1, and the second electrode of the first transistor M1 is electrically connected to the anode (or the first node N1) of the light-emitting device 2.

[0176] For example, when the level of the first reset signal is an effective level, the first transistor M1 can be turned on under the control of the first reset signal to receive and transmit the first initial signal to the anode of the light-emitting device 2.

[0177] Continue reading Figure 13 The control electrode of the second transistor M2 is electrically connected to the second reset signal terminal SR2, the first electrode of the second transistor M2 is electrically connected to the second initial signal terminal Vinit2, and the second electrode of the second transistor M2 is electrically connected to the anode of the light-emitting device 2.

[0178] For example, when the level of the second reset signal is an active level, the second transistor M2 can be turned on under the control of the second reset signal to receive and transmit the second initial signal to the anode of the light-emitting device 2.

[0179] By setting the first reset unit 121 to include the first transistor M1 and the second reset unit 122 to include the second transistor M2, time-division transmission of the first initial signal and the second initial signal can be realized, and the structure of the first reset unit 121 and the second reset unit 122 can be made simpler, avoiding a significant increase in the area occupied by the pixel circuit 1 and avoiding affecting the pixel density of the display panel 10.

[0180] The structure of the drive control circuit 11 described above includes various types. The structure of the drive control circuit 11 will be schematically described below with reference to the accompanying drawings, but the structure of the drive control circuit 11 is not limited to this.

[0181] In some examples, such as Figure 14 As shown, the drive control circuit 11 includes: a data writing unit 111, a drive unit 112, a compensation unit 113, and a light-emitting control unit 114.

[0182] Continue reading Figure 14 The data writing unit 111 is electrically connected to the scan signal terminal SS, the data signal terminal SD, and the drive unit 112, and the compensation unit 113 is electrically connected to the scan signal terminal SS and the drive unit 112. The data writing unit 111 and the compensation unit 113 are configured to turn on in response to the scan signal transmitted by the scan signal terminal SS, and to transmit the data signal from the data signal terminal SD to the drive unit 112.

[0183] For example, when the scanning signal level transitions to an active level, the data writing unit 111 and the compensation unit 113 can be turned on under the control of the scanning signal. The data writing unit 111 can receive the data signal and transmit it to the driving unit 112 via the compensation unit 113 to compensate the threshold voltage of the driving unit 112. This can eliminate the influence of the threshold voltage of the driving unit 112 on the driving signal.

[0184] Continue reading Figure 14 The light-emitting control unit 114 is electrically connected to the enable signal terminal EM, the first voltage signal terminal ELVDD, the driving unit 112, and the anode of the light-emitting device 2. The light-emitting control unit 114 is configured to turn on in response to the enable signal transmitted by the enable signal terminal EM, thereby connecting the path between the first voltage signal terminal ELVDD and the anode of the light-emitting device 2.

[0185] For example, when the level of the enable signal jumps to an active level, the light-emitting control unit 114 can be turned on under the control of the enable signal, so that the path between the first voltage signal terminal ELVDD and the anode of the light-emitting device 2 is turned on, thereby enabling the drive signal to be transmitted to the anode of the light-emitting device 2.

[0186] Optionally, during the display phase of a frame image, the moment the first reset signal is transmitted to the first reset unit 121 is earlier than the moment the data signal is transmitted to the drive unit 112. Specifically, the moment the level of the first reset signal jumps to an active level is earlier than the moment the level of the scan signal jumps to an active level; the moment the first reset unit 121 is turned on is earlier than the moment the data writing unit 111 and the compensation unit 113 are turned on; the moment the first reset unit 121 transmits the first initial signal to the anode of the light-emitting device 2 is earlier than the moment the data writing unit 111 and the compensation unit 113 transmit the data signal to the drive unit 112.

[0187] Furthermore, during the display phase of a single frame image, the timing of the transmission of the second reset signal to the second reset unit 122 is earlier or later than the timing of the transmission of the first reset signal to the first reset unit 121.

[0188] For example, the second reset signal is transmitted to the second reset unit 122 earlier than the first reset signal is transmitted to the first reset unit 121. Specifically, the level of the second reset signal transitions to an active level earlier than the level of the first reset signal transitions to an active level; the second reset unit 122 is turned on earlier than the first reset unit 122 is turned on; and the second reset unit 122 transmits the second initial signal to the anode of the light-emitting device 2 earlier than the first reset unit 121 transmits the first initial signal to the anode of the light-emitting device 2. In this case, internal defects or charge vacancies in the material of the light-emitting device 2 can be filled first, and then the light-emitting device 2 can be reset (or initialized).

[0189] For example, the second reset signal is transmitted to the second reset unit 122 later than the first reset signal is transmitted to the first reset unit 121. Specifically, the level of the second reset signal transitions to an active level later than the level of the first reset signal transitions to an active level; the second reset unit 122 is turned on later than the second reset unit 122 is turned on; and the second reset unit 122 transmits the second initial signal to the anode of the light-emitting device 2 later than the first reset unit 121 transmits the first initial signal to the anode of the light-emitting device 2. In this case, the light-emitting device 2 can be reset (or initialized) first, and then the internal defects or charge vacancies in the material of the light-emitting device 2 can be filled.

[0190] Here, during the display phase of a single frame image, if the timing of the second reset signal transmission to the second reset unit 122 is later than the timing of the first reset signal transmission to the first reset unit 121, the timing of the second reset signal transmission to the second reset unit 122 can be earlier or later than the timing of the data signal transmission to the data writing unit 111. Of course, the timing of the second reset signal transmission to the second reset unit 122 can also be the same as the timing of the data signal transmission to the data writing unit 111; in this case, the second reset signal terminal SR2 is, for example, electrically connected to the scan signal terminal SS.

[0191] The structures of the data writing unit 111, driving unit 112, compensation unit 113, and light-emitting control unit 114 described above include various types. The structures of the data writing unit 111, driving unit 112, compensation unit 113, and light-emitting control unit 114 are illustrated below with reference to the accompanying drawings. However, the structures of the data writing unit 111, driving unit 112, compensation unit 113, and light-emitting control unit 114 are not limited to these.

[0192] In some examples, such as Figure 14 As shown, the data writing unit 111 includes a third transistor M3, the driving unit 112 includes a fourth transistor M4 and a capacitor C, the compensation unit 113 includes a fifth transistor M5, and the light-emitting control unit 114 includes a sixth transistor M6 and a seventh transistor M7.

[0193] Continue reading Figure 14 The control electrode of the third transistor M3 is electrically connected to the scan signal terminal SS, the first electrode of the third transistor M3 is electrically connected to the data signal terminal SD, and the second electrode of the third transistor M3 is electrically connected to the first electrode (or the second node N2) of the fourth transistor M4.

[0194] For example, when the scan signal level is active, the third transistor M3 can be turned on under the control of the scan signal to receive and transmit the scan signal to the second node N2.

[0195] Continue reading Figure 14 The control terminal of the fourth transistor M4 is electrically connected to the second terminal (or third node N3) of the fifth transistor M5, and the second terminal of the fourth transistor M4 is electrically connected to the first terminal (or fourth node N4) of the fifth transistor M5.

[0196] For example, when the potential of the third node N3 is an effective potential, the fourth transistor M4 can be turned on under the control of the potential of the third node N3 to transmit the electrical signal (e.g., data signal) at the second node N2 to the fourth node N4.

[0197] Continue reading Figure 14 The first terminal of capacitor C is electrically connected to the control terminal (or the third node N3) of the fourth transistor M4, and the second terminal of capacitor V is electrically connected to the first voltage signal terminal ELVDD.

[0198] For example, capacitor C has a storage function, which can store the electrical signal transmitted to the third node N3 and maintain the potential of the third node N3.

[0199] Continue reading Figure 14 The control electrode of the fifth transistor M5 is electrically connected to the scan signal terminal SS.

[0200] For example, when the scan signal level is active, the fifth transistor M5 can be turned on under the control of the scan signal to transmit the electrical signal (e.g., data signal) at the fourth node N4 to the third node N3.

[0201] Continue reading Figure 14 The control electrode of the sixth transistor M6 is electrically connected to the enable signal terminal EM, the first electrode of the sixth transistor M6 is electrically connected to the first voltage signal terminal ELVDD, and the second electrode of the sixth transistor M6 is electrically connected to the first electrode (or the second node N2) of the fourth transistor M4. The control electrode of the seventh transistor M7 is electrically connected to the enable signal terminal EM, the first electrode of the seventh transistor M7 is electrically connected to the second electrode (or the fourth node N4) of the fourth transistor M4, and the second electrode of the seventh transistor M7 is electrically connected to the anode (or the first node N1) of the light-emitting device 2.

[0202] For example, when the enable signal level is active, the sixth transistor M6 and the seventh transistor M7 can be turned on under the control of the enable signal, connecting the path between the first voltage signal terminal ELVDD and the first node N1.

[0203] In some examples, such as Figure 14 As shown, the drive control circuit 11 also includes a third reset unit 115.

[0204] The third reset unit 115 is electrically connected to the first reset signal terminal SR1, the third initial signal terminal Vinit3, and the drive unit 112 (or the second node N2). The third reset unit 115 is configured to turn on in response to the first reset signal and transmit the third initial signal from the third initial signal terminal Vinit3 to the drive unit 112.

[0205] For example, when the level of the first reset signal transitions to an active level, the third reset unit 115 can be turned on under the control of the first reset signal, receive the third initial signal, and transmit the third initial signal to the drive unit 112 to reset the second node N2. The third initial signal transmitted by the third initial signal terminal Vinit3 is, for example, a DC low-level signal.

[0206] By setting the third reset unit 115, a reference voltage can be provided to the third node N3 to eliminate the residual charge during the display of the previous frame image and improve the controllability of the pixel circuit 1.

[0207] Here, the third reset unit 115 and the first reset unit 121 are both connected to the first reset signal terminal SR1. The third reset unit 115 and the first reset unit 121 can be turned on synchronously and reset the third node N3 and the first node N1 synchronously. This helps to simplify the connection relationship and driving process of the pixel circuit 1 and simplify the structure of the display panel 10.

[0208] The structure of the third reset unit 115 described above includes various types. The structure of the third reset unit 115 will be schematically described below with reference to the accompanying drawings, but the structure of the third reset unit 115 is not limited to this.

[0209] For example, such as Figure 14 As shown, the third reset unit 115 includes an eighth transistor M8. The control terminal of the eighth transistor M8 is electrically connected to the first reset signal terminal SR1, the first terminal of the eighth transistor M8 is electrically connected to the third initial signal terminal Vinit3, and the second terminal of the eighth transistor M8 is electrically connected to the drive unit 112.

[0210] For example, when the level of the first reset signal is active, the eighth transistor M8 can be turned on under the control of the first reset signal to receive and transmit the third initial signal to the third node N3 in order to reset the third node N3.

[0211] The third reset unit 115 has a simple structure and is easy to manufacture.

[0212] Some embodiments of this application also provide a driving method for a pixel circuit, which is applied to the pixel circuit. This pixel circuit is, for example, the pixel circuit 1 in the display panel 10 described above.

[0213] In some examples, the pixel circuit used in the above driving method includes a driving control circuit and a reset circuit. The driving control circuit is electrically connected to the anode of the light-emitting device. The reset circuit is electrically connected to the reset signal terminal, the initial signal terminal, and the anode of the light-emitting device. Further, the pixel circuit used in the above driving method is, for example,... Figure 12 , Figure 13 and Figure 14 The pixel circuit 1 shown.

[0214] Figure 15a , Figure 15b and Figure 15c Each of the embodiments provided in this application corresponds to Figure 12 , Figure 13 and Figure 14 The timing diagram of the pixel circuit is shown.

[0215] like Figure 15a , Figure 15b and Figure 15c As shown, the display stages of an image frame include a non-luminous stage SN and a luminous stage S3.

[0216] During the non-light-emitting phase SN, the reset circuit 12 is turned on in response to the reset signal transmitted from the reset signal terminal SR, and transmits the first initial signal and the second initial signal from the initial signal terminal Vinit to the anode of the light-emitting device 2 in a time-division manner. The voltage values ​​of the first initial signal and the second initial signal are different. That is, the voltage value of one of the first initial signal and the second initial signal is greater than the voltage value of the other.

[0217] For example, when the reset circuit 12 is turned on, the anode of the light-emitting device 2 can receive a first initial signal and a second initial signal at different times. For instance, the reset circuit 12 can be turned on at a first time and a second time in response to a reset signal; at the first time, the reset circuit 12 can receive the first initial signal and transmit the first initial signal to the anode of the light-emitting device 2; at the second time, the reset circuit 12 can receive the second initial signal and transmit the second initial signal to the anode of the light-emitting device 2.

[0218] Optionally, of the first initial signal and the second initial signal, the one with the lower voltage value is used to reset (or initialize) the light-emitting device 2; the other with the higher voltage value is used to increase the voltage difference between the anode and cathode of the light-emitting device 2 and fill the internal defects or charge vacancies in the material of the light-emitting device 2.

[0219] During the light-emitting stage S3, the drive control circuit 11 provides a drive signal to the anode of the light-emitting device 2 to drive the light-emitting device 2 to emit light.

[0220] For example, such as Figure 12 , Figure 13 and Figure 14 As shown, the drive control circuit 11 is also electrically connected to the scan signal terminal SS, the data signal terminal SD, the enable signal terminal EM, and the first voltage signal terminal ELVDD. The drive control circuit 11 can receive the scan signal from the scan signal terminal SS, the data signal from the data signal terminal SD, the enable signal from the enable signal terminal EM, and the first voltage signal from the first voltage signal terminal ELVDD. Under the coordination of the scan signal, data signal, enable signal, and first voltage signal, it generates a drive signal and transmits the drive signal to the anode of the light-emitting device 2. Of course, the drive control circuit 11 can also be electrically connected to other signal terminals.

[0221] It is understandable that before the light emission stage S3, the higher voltage value of the first initial signal and the second initial signal has already filled the internal defects or charge vacancies in the material of the light-emitting device 2. Thus, during the light emission stage S3, when the drive control circuit 11 transmits the drive signal to the anode of the light-emitting device 2, the amount of charge captured by the light-emitting device 2 can be reduced, the current loss in the drive signal used to fill the internal defects or charge vacancies in the material of the light-emitting device 2 can be reduced, and the proportion of the current used to drive the light-emitting device 2 to emit light can be increased. This allows most or even all of the drive signal to be used for the light emission of the light-emitting device, thereby reducing the influence of the internal defects or charge vacancies in the material of the light-emitting device 2 on the brightness of the light emission of the light-emitting device 2.

[0222] In this way, when the brightness (or grayscale) presented by the light-emitting device 2 changes, the turn-on speed of the light-emitting device 2 can be increased, so that the brightness (or grayscale) presented by the light-emitting device 2 in different frames approaches or reaches the target brightness (or target grayscale), thereby improving display abnormalities, reducing the impact of problems such as ghosting and color shift, and improving display effect.

[0223] In some examples, such as Figure 12 , Figure 13 and Figure 14 As shown, the reset circuit 12 includes a first reset unit 121 and a second reset unit 122. The reset signal terminal SR includes a first reset signal terminal SR1 and a second reset signal terminal SR2, and the initial signal terminal Vinit includes a first initial signal terminal and a second initial signal terminal Vinit2. The first reset unit 121 is electrically connected to the first reset signal terminal SR1, the first initial signal terminal Vinit1, and the anode of the light-emitting device 2. The second reset unit 122 is electrically connected to the second reset signal terminal SR2, the second initial signal terminal Vinit2, and the anode of the light-emitting device 2.

[0224] During the non-light-emitting phase SN, the reset circuit 12 is turned on in response to the reset signal transmitted by the reset signal terminal SR, and transmits the first initial signal and the second initial signal from the initial signal terminal Vinit to the anode of the light-emitting device 2 in a time-division manner. This includes: the first reset unit 121 being turned on in response to the first reset signal transmitted by the first reset signal terminal SR1, and transmitting the first initial signal from the first initial signal terminal Vinit1 to the anode of the light-emitting device 2; and the second reset unit 122 being turned on in response to the second reset signal transmitted by the second reset signal terminal SR2, and transmitting the second initial signal from the second initial signal terminal Vinit2 to the anode of the light-emitting device 2.

[0225] Specifically, the timing of the transmission of the first reset signal to the first reset unit 121 and the timing of the transmission of the second reset signal to the second reset unit 122 are different. The timing when the level of the first reset signal transitions to an active level is different from the timing when the level of the second reset signal transitions to an active level; the timing when the first reset unit 121 and the second reset unit 122 are turned on are different; and the timing when the first reset unit 121 transmits the first initial signal to the anode of the light-emitting device 2 is different from the timing when the second reset unit 122 transmits the second initial signal to the anode of the light-emitting device 2.

[0226] For example, the second reset signal is transmitted to the second reset unit 122 at a time earlier or later than the first reset signal is transmitted to the first reset unit 121.

[0227] Below, we take the example where the voltage value of the second initial signal is greater than the voltage value of the first initial signal. In this case, the first initial signal can reset (or initialize) the light-emitting device 2; the second initial signal can increase the voltage difference between the anode and cathode of the light-emitting device 2 and fill the internal defects or charge vacancies in the material of the light-emitting device 2.

[0228] For example, such as Figure 15a , Figure 15b and Figure 15c As shown, in the non-light-emitting stage SN, the first reset unit 121 transmits the first initial signal to the anode of the light-emitting device 2, for example, the reset stage S11; the second reset unit 122 transmits the second initial signal to the anode of the light-emitting device 2, for example, the filling stage S12. Figure 15a , Figure 15b and Figure 15c In the diagram, SR1 represents the first reset signal received by the first reset unit 121, and SR2 represents the second reset signal received by the second reset unit 122.

[0229] Optionally, such as Figure 15a and Figure 15cAs shown, the reset stage S11 is located before the filling stage S12. The first reset signal is transmitted to the first reset unit 121 earlier than the second reset signal is transmitted to the second reset unit 122. At this time, the light-emitting device 2 can be reset (or initialized) first, and then the internal defects or charge vacancies in the material of the light-emitting device 2 can be filled.

[0230] Optionally, such as Figure 15b As shown, the filling stage S12 is located before the reset stage S11. The second reset signal is transmitted to the second reset unit 122 earlier than the first reset signal is transmitted to the first reset unit 121. At this time, the internal defects or charge vacancies of the material of the light-emitting device 2 can be filled first, and then the light-emitting device 2 can be reset (or initialized).

[0231] In some examples, such as Figure 14 As shown, the drive control circuit 11 includes a data writing unit 111, a drive unit 112, a compensation unit 113, and a light-emitting control unit 114. The data writing unit 111 is electrically connected to the scan signal terminal SS, the data signal terminal SD, and the drive unit 112. The compensation unit 113 is electrically connected to the scan signal terminal SS and the drive unit 112. The light-emitting control unit 114 is electrically connected to the enable signal terminal EM, the first voltage signal terminal ELVDD, the drive unit 112, and the anode of the light-emitting device 2.

[0232] During the light-emitting stage S3, the drive control circuit 11 provides a drive signal to the anode of the light-emitting device 2 to drive the light-emitting device 2 to emit light. This includes: the light-emitting control unit 114 being turned on in response to the enable signal transmitted by the enable signal terminal EM, connecting the path between the first voltage signal terminal ELVDD and the anode of the light-emitting device 2.

[0233] During the non-light-emitting phase SN, the reset circuit 12 is turned on in response to the reset signal transmitted by the reset signal terminal SR, and transmits the first initial signal and the second initial signal from the initial signal terminal Vinit to the anode of the light-emitting device 2 in a time-division manner. It also includes a data writing unit 111 and a compensation unit 113, which are turned on in response to the scan signal transmitted by the scan signal terminal SS, and transmit the data signal from the data signal terminal SD to the driving unit 112. The first reset signal is transmitted to the first reset unit 121 earlier than the data signal is transmitted to the driving unit 112.

[0234] For example, in Figure 15a , Figure 15b and Figure 15cIn this context, EM represents the enable signal received by the light-emitting control unit 114, and SS represents the scan signal received by the data writing unit 111 and the compensation unit 113. During the non-light-emitting stage SN, the data writing unit 111 and the compensation unit 113 transmit data signals to the driving unit 112, for example, the data writing and compensation stage S2.

[0235] The first reset signal is transmitted to the first reset unit 121 earlier than the data signal is transmitted to the drive unit 112. That is, the reset stage S11 is located in the data writing and compensation stage S2. At this time, the light-emitting device 2 can be reset (or initialized) first, and then the drive unit 112 can be used for data writing and threshold voltage compensation.

[0236] Here, if the reset phase S11 is prior to the filling phase S12, as follows: Figure 15a As shown, the filling stage S12 can be located before the data writing and compensation stage S2; or, as... Figure 15c As shown, the filling stage S12 can be located after the data writing and compensation stage S2. Of course, the filling stage S12 and the data writing and compensation stage S2 can also be performed simultaneously.

[0237] Some embodiments of this application also provide a display panel 10, which is applied to the aforementioned display module or electronic device. In some examples, the display panel can serve as... Figure 2 The display panel in the middle.

[0238] Figure 16 and Figure 17 These are structural diagrams of a display panel provided in embodiments of this application. In some examples, such as... Figure 16 and Figure 17 As shown, the display panel 10 includes a plurality of sub-pixels P.

[0239] The aforementioned multiple sub-pixels P are arranged in an array, specifically, in multiple rows and columns. Each row of sub-pixels P includes multiple sub-pixels P spaced apart along the row direction X, and each column of sub-pixels P includes multiple sub-pixels P spaced apart along the column direction Y. Of course, the arrangement of these multiple sub-pixels P is not limited to... Figure 16 and Figure 17 The arrangement shown is as shown.

[0240] The structure of subpixel P includes various types; optionally, subpixel P adopts... Figure 12 , Figure 13 and Figure 14 The structure shown. For example, combined with... Figure 12 and Figure 16 The sub-pixel P includes a pixel circuit 1 and a light-emitting device 2, and the pixel circuit 1 is electrically connected to the anode of the light-emitting device 2.

[0241] The beneficial effects that the display panel 10 provided in this embodiment can achieve are the same as the beneficial effects that the pixel circuit 1 in some of the above embodiments can achieve, and will not be repeated here.

[0242] In some embodiments, such as Figure 16 As shown, the display panel 10 further includes: a first reset signal line RL1, a second reset signal line RL2, a first initial signal line VL1, and a second initial signal line VL2. The first reset signal line RL1 is used to transmit a first reset signal, the second reset signal line RL2 is used to transmit a second reset signal, the first initial signal line VL1 is used to transmit a first initial signal, and the second initial signal line VL2 is used to transmit a second initial signal.

[0243] Combination Figure 16 and Figure 12 In pixel circuit 1, the first reset unit 121 is electrically connected to the first reset signal line RL1 via the first reset signal terminal SR1, and electrically connected to the first initial signal line VL1 via the first initial signal terminal Vinit1. Thus, the first reset unit 121 can receive the first reset signal from the first reset signal line RL1 via the first reset signal terminal SR1, and can receive the first initial signal from the first initial signal line VL1 via the first initial signal terminal Vinit1.

[0244] The second reset unit 122 in pixel circuit 1 is electrically connected to the second reset signal line RL2 via the second reset signal terminal SR2, and electrically connected to the second initial signal line VL2 via the second initial signal terminal Vinit2. Thus, the second reset unit 122 can receive the second reset signal from the second reset signal line RL2 via the second reset signal terminal SR2, and can receive the second initial signal from the second initial signal line VL2 via the second initial signal terminal Vinit2.

[0245] For example, such as Figure 16 As shown, there are multiple first reset signal lines RL1, second reset signal lines RL2, first initial signal lines VL1, and second initial signal lines VL2. These multiple first reset signal lines RL1, multiple second reset signal lines RL2, multiple first initial signal lines VL1, and multiple second initial signal lines VL2 all extend along the row direction X and are arranged sequentially at intervals along the column direction Y.

[0246] The aforementioned multiple first reset signal lines RL1 correspond one-to-one with multiple rows of sub-pixels P, and one first reset signal line RL1 is electrically connected to the first reset unit 121 of the sub-pixels P located in the same row. Similarly, the aforementioned multiple first initial signal lines VL1 correspond one-to-one with multiple rows of sub-pixels P, and one first initial signal line VL1 is electrically connected to the first reset unit 121 of the sub-pixels P located in the same row. This allows the first reset units 121 of multiple sub-pixels P located in the same row to be controlled synchronously to be turned on or off via a single first reset signal line RL1. Furthermore, when the first reset units 121 of multiple sub-pixels P located in the same row are synchronously turned on, they can synchronously receive the first initial signal, for example, synchronously resetting the anodes of the light-emitting devices 2 of the multiple sub-pixels P located in the same row.

[0247] The aforementioned multiple second reset signal lines RL2 correspond one-to-one with multiple rows of sub-pixels P, and one second reset signal line RL2 is electrically connected to the second reset unit 122 of the sub-pixels P located in the same row. Similarly, the aforementioned multiple second initial signal lines VL2 correspond one-to-one with multiple rows of sub-pixels P, and one second initial signal line VL2 is electrically connected to the second reset unit 122 of the sub-pixels P located in the same row. This allows the second reset units 122 of multiple sub-pixels P located in the same row to be controlled to be synchronously turned on or off via a single second reset signal line RL2. Furthermore, when the second reset units 122 of multiple sub-pixels P located in the same row are synchronously turned on, they can synchronously receive second initial signals, for example, to synchronously fill internal defects or charge vacancies in the material of the light-emitting device 2 of the multiple sub-pixels P located in the same row.

[0248] This improves the efficiency of resetting the anode of the light-emitting device 2 and the efficiency of filling internal defects or charge vacancies in the material of the light-emitting device 2. Furthermore, in localized areas of the display panel 10 (e.g., Figure 5 When the grayscale of the display in region A11 needs to change from low grayscale to high grayscale, the internal defects or charge vacancies of the material of the light-emitting device 2 located in the local area can be filled in a targeted manner through the second reset signal line RL2 and the second initial signal line VL2 located in the local area, so as to avoid significantly increasing the power consumption of the display panel 10.

[0249] In some embodiments, such as Figure 17 As shown, the display panel 10 also includes a scan signal line GL. The scan signal line GL is used to transmit scan signals.

[0250] Combination Figure 17 and Figure 14In pixel circuit 1, both the data writing unit 111 and the compensation unit 113 of the drive control circuit 11 are electrically connected to the scan signal line GL via the scan signal terminal SS. For example, the data writing unit 111 and the compensation unit 113 of the same drive control circuit 11 are electrically connected to the same scan signal line GL. Thus, the data writing unit 111 and the compensation unit 113 of the same drive control circuit 11 can synchronously receive the scan signal from the scan signal line GL via the scan signal terminal SS.

[0251] For example, such as Figure 17 As shown, there are multiple scan signal lines GL. These multiple scan signal lines GL extend along the row direction X and are arranged sequentially at intervals along the column direction Y. For example, each scan signal line GL corresponds one-to-one with a row of sub-pixels P. Each scan signal line GL is electrically connected to the data writing unit 111 and the compensation unit 113 of the sub-pixel P located in the same row.

[0252] In some examples, the first reset signal line RL1, electrically connected to the first reset unit 121 of the m-th row sub-pixel P, is electrically connected to the scan signal line GL, electrically connected to the data writing unit 111 of the n-th row sub-pixel P. Here, m and n are both positive integers, and m ≠ n. In other words, the scan signal received by the n-th row sub-pixel P can be multiplexed as the first reset signal and received by the m-th row sub-pixel P.

[0253] For example, n is less than m. Alternatively, n = m - 1. That is, as... Figure 17 As shown, the first reset signal line RL1, which is electrically connected to the first reset unit 121 of the m-th row sub-pixel P, is electrically connected to the scan signal line GL, which is electrically connected to the data writing unit 111 of the (m-1)-th row sub-pixel P. The scan signal received by the (m-1)-th row sub-pixel P can be multiplexed as the first reset signal and received by the m-th row sub-pixel P.

[0254] This avoids the need for a separate circuit structure to generate the first reset signal, which helps to simplify the structure of the display panel 10.

[0255] In some examples, the second reset signal can be a separately configured electrical signal or a multiplexed scan signal.

[0256] When the second reset signal is a separately configured electrical signal, the second reset signal line RL2 and the scan signal line are not electrically connected. For example, a circuit structure for generating the second reset signal is provided in the display panel 10.

[0257] When the second reset signal is multiplexed with the scan signal, the second reset signal line RL2, electrically connected to the second reset unit 122 of the m-th row sub-pixel P, is electrically connected to the scan signal line GL, electrically connected to the data writing unit 111 of the nj-th row sub-pixel P. In other words, the scan signal received by the nj-th row sub-pixel P can be multiplexed as the second reset signal and received by the m-th row sub-pixel P. Here, j is an integer. Optionally, j can be a positive integer, a negative integer, or 0.

[0258] For example, n = m - 1, and j = -1. That is to say, as... Figure 17 As shown, the second reset signal line RL2, which is electrically connected to the second reset unit 122 of the m-th row sub-pixel P, is electrically connected to the scan signal line GL, which is electrically connected to the data writing unit 111 of the m-th row sub-pixel P. The scan signal received by the m-th row sub-pixel P can be multiplexed into a second reset signal and received by the m-th row sub-pixel P.

[0259] This avoids the need for a separate circuit structure to generate the second reset signal, which helps to simplify the structure of the display panel 10.

[0260] Some embodiments of this application also provide a display panel 10, which is applied to the aforementioned display module or electronic device. In some examples, the display panel can serve as... Figure 2 The display panel in the middle. Figures 18-22 These are structural diagrams of a display panel provided in an embodiment of this application.

[0261] In some examples, such as Figure 18 As shown, the display panel 10 includes a plurality of sub-pixels P. These sub-pixels P are arranged, for example, in an array. Specifically, the plurality of sub-pixels P are arranged in multiple rows and columns, with each row including a plurality of sub-pixels P spaced apart along the row direction X, and each column including a plurality of sub-pixels P spaced apart along the column direction Y. Of course, the arrangement of these sub-pixels P is not limited to... Figure 18 The arrangement shown is as shown.

[0262] The structure of subpixel P includes various types; for example, subpixel P adopts... Figure 3 and Figure 8 The structure shown; for example, sub-pixel P adopts Figure 12 , Figure 13 and Figure 14 The structure shown is below. The sub-pixel P is used... Figure 12 , Figure 13 and Figure 14 The structure shown is illustrated as an example. In this case, the configuration of the third initial signal line in this embodiment can be combined with the configuration of the second reset signal line RL2 and the second initial signal line VL2 in some of the above embodiments.

[0263] In some embodiments, continue reading Figure 18 The display panel 10 includes a third initial signal line VL3. The third initial signal line VL3 is used to transmit a third initial signal.

[0264] Combination Figure 18 and Figure 14 In pixel circuit 1, the third reset unit 115 of drive control circuit 11 is electrically connected to the third initial signal line VL3 through the third initial signal terminal Vinit3. In this way, the third reset unit 115 can receive the third initial signal from the third initial signal line VL3 through the third initial signal terminal Vinit3.

[0265] For example, such as Figure 18 As shown, there are multiple third initial signal lines VL3. These multiple third initial signal lines VL3 extend, for example, along the column direction Y and are arranged alternately along the row direction X. The multiple third initial signal lines VL3 are electrically connected to the third reset units 115 of multiple columns of sub-pixels P. For example, the multiple third initial signal lines VL3 correspond one-to-one with multiple columns of sub-pixels P, and one third initial signal line VL3 is electrically connected to the third reset unit 115 of the sub-pixel P located in the same column.

[0266] Among them, at least two third initial signal lines VL3 transmit third initial signals with different voltage values, and the sub-pixels P connected to the third initial signal lines VL3 that transmit third initial signals with different voltage values ​​emit different colors.

[0267] For example, the multiple sub-pixels P in the display panel 10 include multiple first color sub-pixels, multiple second color sub-pixels, and multiple third color sub-pixels. The light-emitting device 2 in the first color sub-pixel emits first color light, the light-emitting device 2 in the second color sub-pixel emits second color light, and the light-emitting device 2 in the third color sub-pixel emits third color light. The third reset units 115 in the first and second color sub-pixels are respectively connected to different third initial signal lines VL3, and in the third reset units 115 of the first and second color sub-pixels, one receives a higher voltage value of the third initial signal, while the other receives a lower voltage value of the third initial signal.

[0268] like Figure 14As shown, when the third reset unit 115 is turned on, it transmits the third initial signal to the third node N3 to reset the control electrode of the fourth transistor M4, providing a reference voltage for the control electrode of the fourth transistor M4. After data writing and threshold voltage compensation, the potential of the control electrode of the fourth transistor M4 affects the magnitude of the drive signal. For example, if the potential of the control electrode of the fourth transistor M4 is low, the conduction degree of the fourth transistor M4 is large, and the drive signal is large; conversely, if the potential of the control electrode of the fourth transistor M4 is high, the conduction degree of the fourth transistor M4 is small, and the drive signal is small.

[0269] Understandably, the light-emitting devices 2 used to emit different colors of light have different capacitances (cap) and threshold voltages. Consequently, the turn-on speeds of these devices differ. For example, when transmitting the same driving signal to the light-emitting devices 2, some devices will turn on more slowly, while others will turn on more quickly. This can easily cause color shift problems during image display on the display panel 10 (especially low grayscale display), affecting the display effect of the display panel 10.

[0270] In some embodiments of this application, by setting the voltage values ​​of the third initial signals transmitted by different third initial signal lines VL3, the voltage values ​​of the third initial signals transmitted by at least two third initial signal lines VL3 are different, and the sub-pixels P connected to the third initial signal lines VL3 transmitting third initial signals with different voltage values ​​emit different colors. The initial state of the control electrode of the fourth transistor M4 of the sub-pixel P emitting different colors of light can be changed by the third reset unit 115 to adjust the magnitude of the subsequently generated driving current. This makes the turn-on time of the light-emitting devices 2 used to emit different colors of light more consistent, improves the low grayscale color shift problem caused by the different capacitance (cap) and threshold voltage of the light-emitting devices 2 used to emit different colors of light, and improves the display effect of the display panel 10.

[0271] Here, for light-emitting devices 2 that emit the same color of light, changes in the material of light-emitting device 2 may also change the turn-on speed of light-emitting device 2. Therefore, the voltage value of the third initial signal received by sub-pixels P with different emitted colors can be selectively set according to actual design requirements.

[0272] There are several ways to set the third initial signal line VL3 and the sub-pixel P, which are illustrated below with reference to the accompanying drawings.

[0273] In some examples, such as Figure 19 and Figure 20As shown, the multiple columns of subpixels P in the display panel 10 include multiple first subpixel columns PC1 and multiple second subpixel columns PC2. For example, the first subpixel columns PC1 and the second subpixel columns PC2 are arranged alternately along the row direction X.

[0274] The emission color of each sub-pixel P in the first sub-pixel column PC1 is different from the emission color of each sub-pixel P in the second sub-pixel column PC2. For example, as shown... Figure 19 and Figure 20 As shown, the first sub-pixel column PC1 includes multiple first-color sub-pixels P1, and the second sub-pixel column PC2 includes multiple second-color sub-pixels P2 and third-color sub-pixels P3 alternately arranged along the column direction Y. Optionally, the first-color sub-pixels P1 are used to emit green light, and the first-color sub-pixels P1 can also be called green sub-pixels; the second-color sub-pixels P2 are used to emit red light, and the second-color sub-pixels P2 can also be called red sub-pixels; the third-color sub-pixels P3 are used to emit blue light, and the third-color sub-pixels P3 can also be called blue sub-pixels.

[0275] Continue to refer to Figure 19 and Figure 20 The aforementioned multiple third initial signal lines VL3 include multiple third sub-signal lines VL31 and multiple fourth sub-signal lines VL32, which are arranged alternately, for example, along the row direction X. The third sub-signal lines VL3 are electrically connected to each third reset unit 115 in the first sub-pixel column PC1, and the fourth sub-signal lines VL32 are electrically connected to each third reset unit 115 in the second sub-pixel column PC2. The voltage values ​​of the third initial signals transmitted by the third sub-signal lines VL31 and VL32 are different.

[0276] For example, the difference in the lighting speed of the light-emitting device 2 in the second color sub-pixel P2 and the third color sub-pixel P3 is small, and the second color sub-pixel P2 and the third color sub-pixel P3 can receive the same third initial signal through the fourth sub-signal line VL32; while the difference in the lighting speed of the light-emitting device 2 in the first color sub-pixel P1 is large compared with that of the light-emitting device 2 in the second color sub-pixel P2 and the third color sub-pixel P3, and the first color sub-pixel P1 and the second color sub-pixel P2 respectively receive third initial signals with different voltage values.

[0277] This allows for the adaptive adjustment of the voltage value of the third initial signal transmitted by the third sub-signal line VL31 based on the turn-on speed of the light-emitting device 2 in the first color sub-pixel P1; it also allows for the adaptive adjustment of the voltage value of the third initial signal transmitted by the third sub-signal line VL31 based on the turn-on speed of the light-emitting devices 2 in the second color sub-pixel P2 and the third color sub-pixel P3, thereby improving the low grayscale color shift problem caused by the different capacitance (cap) and threshold voltage of the light-emitting devices 2 used to emit different colors of light, and improving the display effect of the display panel 10.

[0278] In other examples, such as Figure 21 and Figure 22 As shown, the multiple columns of sub-pixels P in the display panel 10 include multiple first sub-pixel columns PC1, multiple second sub-pixel columns PC2, and multiple third sub-pixel columns PC3. For example, the first sub-pixel columns PC1, second sub-pixel columns PC2, and third sub-pixel columns PC3 are arranged periodically along the row direction X.

[0279] The emission colors of each sub-pixel P in the first sub-pixel column PC1, the second sub-pixel column PC2, and the third sub-pixel column PC3 are different. For example, as shown... Figure 21 and Figure 22 As shown, the first sub-pixel column PC1 includes a plurality of first-color sub-pixels P1 arranged along the column direction Y, the second sub-pixel column PC2 includes a plurality of second-color sub-pixels P2 arranged along the column direction Y, and the third sub-pixel column PC3 includes a plurality of third-color sub-pixels P3 arranged along the column direction Y. Optionally, the first-color sub-pixels P1 are used to emit green light, the second-color sub-pixels P2 are used to emit red light, and the third-color sub-pixels P3 are used to emit blue light.

[0280] Continue to refer to Figure 21 and Figure 22 The aforementioned multiple third initial signal lines VL3 include multiple third sub-signal lines VL31, multiple fourth sub-signal lines VL32, and multiple fifth sub-signal lines VL33. The third sub-signal lines VL31, fourth sub-signal lines VL32, and fifth sub-signal lines VL33 are arranged periodically, for example, along the row direction X. Specifically, the third sub-signal lines VL3 are electrically connected to each third reset unit 115 in the first sub-pixel column PC1, the fourth sub-signal lines VL32 are electrically connected to each third reset unit 115 in the second sub-pixel column PC2, and the fifth sub-signal lines VL33 are electrically connected to each third reset unit 115 in the third sub-pixel column PC3.

[0281] In this way, the first color sub-pixel P1 can receive the third initial signal through the third sub-signal line VL31, the second color sub-pixel P2 can receive the third initial signal through the fourth sub-signal line VL32, and the third color sub-pixel P3 can receive the third initial signal through the fifth sub-signal line VL33. The voltage values ​​of the third initial signal transmitted by the third sub-signal line VL31, the fourth sub-signal line VL32, and the fifth sub-signal line VL33 can be selectively set according to the design needs of the first color sub-pixel P1, the second color sub-pixel P2, and the third color sub-pixel P3, enhancing flexibility and practicality.

[0282] Optionally, the voltage values ​​of the third initial signal transmitted by the third sub-signal line VL31, the fourth sub-signal line VL32, and the fifth sub-signal line VL33 are all different. For example... Figure 21 As shown, in this case, the third sub-signal line VL31, the fourth sub-signal line VL32, and the fifth sub-signal line VL33 are set independently.

[0283] In this way, based on the capacitance (cap) and threshold voltage of the light-emitting device 2 in the first color sub-pixel P1, the light-emitting device 2 in the second color sub-pixel P2, and the light-emitting device 2 in the third color sub-pixel P3, the voltage value of the third initial signal transmitted by the third sub-signal line VL31, the fourth sub-signal line VL32, and the fifth sub-signal line VL33 can be adapted to effectively address the low grayscale color shift problem caused by the different capacitance (cap) and threshold voltage of the light-emitting devices 2 used to emit different colors of light, thereby improving the display effect of the display panel 10.

[0284] Optionally, the voltage values ​​of the third initial signal transmitted on the fifth sub-signal line VL33 and the fourth sub-signal line VL32 are the same. For example... Figure 22 As shown, in this case, the fifth sub-signal line VL33 and the fourth sub-signal line VL32 are electrically connected, and the fifth sub-signal line VL33 and the fourth sub-signal line VL32 are used to transmit the same third initial signal.

[0285] In this way, the design complexity of the third initial signal can be reduced while improving the low grayscale color shift problem and the display effect of the display panel 10.

[0286] In some embodiments, such as Figure 20 , Figure 21 and Figure 22 As shown, the display panel 10 also includes multiple auxiliary signal lines FL extending along the row direction X. These multiple auxiliary signal lines FL are arranged at intervals, for example, along the column direction Y. The auxiliary signal lines FL are electrically connected to multiple third initial signal lines VL3 transmitting the same third initial signal value. The multiple auxiliary signal lines FL and the multiple third initial signal lines VL3 can form a mesh structure.

[0287] This helps to reduce the resistance of multiple third initial signal lines VL3 with the same voltage value, and improves the uniformity of the voltage value of the third initial signal at different positions of the third initial signal line VL3.

[0288] Since the extension direction of the auxiliary signal line FL intersects the extension direction of the third initial signal line VL3, multiple auxiliary signal lines FL and multiple third initial signal lines VL3 can be located in different conductive film layers (e.g., metal film layers). The connected auxiliary signal lines FL and third initial signal lines VL3 are electrically connected through vias.

[0289] In some examples, such as Figure 20 As shown, in the case where the multiple columns of sub-pixels P in the display panel 10 include the first sub-pixel column PC1 and the second sub-pixel column PC2, and the multiple third initial signal lines VL3 include the third sub-signal line VL31 and the fourth sub-signal line VL32, the aforementioned multiple auxiliary signal lines FL include, for example, multiple first auxiliary signal lines FL1 and multiple second auxiliary signal lines FL2.

[0290] Each first auxiliary signal line FL1 is electrically connected to multiple third sub-signal lines VL31, and each second auxiliary signal line FL2 is electrically connected to multiple fourth sub-signal lines VL32.

[0291] In some examples, such as Figure 21 and Figure 22 As shown, in the case where the multiple sub-pixel columns P in the display panel 10 include a first sub-pixel column PC1, a second sub-pixel column PC2 and a third sub-pixel column PC3, and the multiple third initial signal lines VL3 include a third sub-signal line VL31, a fourth sub-signal line VL32 and a fifth sub-signal line VL33, the aforementioned multiple auxiliary signal lines FL may include, for example, multiple first auxiliary signal lines FL1, multiple second auxiliary signal lines FL2 and multiple third auxiliary signal lines FL3.

[0292] For example, such as Figure 21 As shown, the voltage values ​​of the third initial signal transmitted by the third sub-signal line VL31, the fourth sub-signal line VL32, and the fifth sub-signal line VL33 are all different. Correspondingly, each first auxiliary signal line FL1 is electrically connected to multiple third sub-signal lines VL31, each second auxiliary signal line FL2 is electrically connected to multiple fourth sub-signal lines VL32, and each third auxiliary signal line FL3 is electrically connected to multiple fifth sub-signal lines VL33.

[0293] For example, such as Figure 22As shown, the voltage values ​​of the third initial signal transmitted by the fifth sub-signal line VL33 and the fourth sub-signal line VL32 are the same. Correspondingly, each first auxiliary signal line FL1 is electrically connected to, for example, multiple third sub-signal lines VL31, each second auxiliary signal line FL2 is electrically connected to, for example, multiple fourth sub-signal lines VL32 and multiple fifth sub-signal lines VL33, and each third auxiliary signal line FL3 is electrically connected to, for example, multiple fourth sub-signal lines VL32 and multiple fifth sub-signal lines VL33.

[0294] Some embodiments of this application also provide a display panel 10, which is applied to the aforementioned display module or electronic device. In some examples, the display panel can serve as... Figure 2 The display panel in the middle. Figure 23 This is a structural diagram of a display panel provided in an embodiment of this application.

[0295] In some examples, such as Figure 23 As shown, the display panel 10 includes a plurality of sub-pixels. These sub-pixels are arranged, for example, in an array; specifically, they are arranged in multiple rows and columns, with each row including multiple sub-pixels spaced apart along the row direction X, and each column including multiple sub-pixels spaced apart along the column direction Y. Of course, the arrangement of these sub-pixels is not limited to this. Figure 23 The arrangement shown is as described. Subpixel structures include various methods; for example, subpixels employ... Figure 3 and Figure 8 The structure shown is below. The sub-pixel P is used... Figure 8 The structure shown is used as an example for illustrative purposes.

[0296] In some embodiments, such as Figure 23 As shown, the display panel 10 includes: an initial signal line VL, which is used to transmit an initial signal. Combined with... Figure 23 and Figure 8 The reset circuit 12 in pixel circuit 1 is electrically connected to the initial signal line VL through the initial signal terminal Vinit.

[0297] For example, such as Figure 23 As shown, there are multiple initial signal lines VL. These multiple initial signal lines VL extend, for example, along the column direction Y and are arranged alternately along the row direction X. The multiple initial signal lines VL are electrically connected to the reset circuit 12 of multiple columns of sub-pixels P. For example, the multiple initial signal lines VL correspond one-to-one with the multiple columns of sub-pixels P, and one initial signal line VL is electrically connected to the reset circuit 12 of the sub-pixel P located in the same column.

[0298] Combination Figure 8When the reset circuit 12 is turned on, the reset circuit 12 transmits the initial signal from the initial signal line VL to the anode of the light-emitting device 2 to reset the light-emitting device 2.

[0299] Among them, at least two initial signal lines VL transmit initial signals with different voltage values, and the sub-pixels P connected to the initial signal lines VL that transmit initial signals with different voltage values ​​emit different colors.

[0300] For example, such as Figure 23 As shown, the multiple sub-pixels P in the display panel 10 include multiple first-color sub-pixels P1, multiple second-color sub-pixels P2, and multiple third-color sub-pixels P3. The light-emitting device 2 in the first-color sub-pixel P1 is used to emit first-color light, the light-emitting device 2 in the second-color sub-pixel P2 is used to emit second-color light, and the light-emitting device 2 in the third-color sub-pixel P3 is used to emit third-color light.

[0301] It is understandable that the light-emitting devices 2 used to emit different colors of light have different turn-on speeds. As a result, when the grayscale of the image displayed on the display panel 10 changes, it is easy to produce a ghosting problem, which affects the display effect of the display panel 10.

[0302] In some embodiments of this application, by using initial signals with different voltage values, the light-emitting devices 2 of sub-pixels P with different light-emitting colors are reset, so that there are different voltage differences between the anode and cathode of the light-emitting devices 2 that emit different colors of light. This allows the lighting state of the materials of the light-emitting devices 2 that emit different colors of light to be adjusted, so that the lighting speed of the light-emitting devices 2 that emit different colors of light tends to be consistent. This can effectively improve the ghosting problem and improve the display effect of the display panel 10.

[0303] There are several ways to set the initial signal line VL and sub-pixel P, which are illustrated below with reference to the accompanying drawings.

[0304] In some examples, the multiple columns of subpixels P in the display panel 10 include multiple first subpixel columns and multiple second subpixel columns. For example, the first and second subpixel columns are arranged alternately along the row direction X.

[0305] The emission color of each sub-pixel in the first sub-pixel column is different from the emission color of each sub-pixel in the second sub-pixel column. For example, the first sub-pixel column includes multiple first-color sub-pixels P1, and the second sub-pixel column includes multiple second-color sub-pixels P2 and third-color sub-pixels P3 alternately arranged along the column direction Y. Optionally, the first-color sub-pixels P1 emit green light, the second-color sub-pixels P2 emit red light, and the third-color sub-pixels P3 emit blue light.

[0306] The aforementioned multiple initial signal lines VL include multiple sixth sub-signal lines and multiple seventh sub-signal lines, which are arranged alternately, for example, along the row direction X. The sixth sub-signal lines are electrically connected to each reset circuit 12 in the first sub-pixel column, and the seventh sub-signal lines are electrically connected to each reset circuit 12 in the second sub-pixel column. The voltage values ​​of the initial signals transmitted by the sixth and seventh sub-signal lines are different.

[0307] In other examples, such as Figure 23 As shown, the multiple columns of sub-pixels P in the display panel 10 include multiple first sub-pixel columns PC1, multiple second sub-pixel columns PC2, and multiple third sub-pixel columns PC3. For example, the first sub-pixel columns PC1, second sub-pixel columns PC2, and third sub-pixel columns PC3 are arranged periodically along the row direction X.

[0308] The emission colors of each sub-pixel P in the first sub-pixel column PC1, the second sub-pixel column PC2, and the third sub-pixel column PC3 are different. For example, as shown... Figure 23 As shown, the first sub-pixel column PC1 includes a plurality of first-color sub-pixels P1 arranged along the column direction Y, the second sub-pixel column PC2 includes a plurality of second-color sub-pixels P2 arranged along the column direction Y, and the third sub-pixel column PC3 includes a plurality of third-color sub-pixels P3 arranged along the column direction Y. Optionally, the first-color sub-pixels P1 are used to emit green light, the second-color sub-pixels P2 are used to emit red light, and the third-color sub-pixels P3 are used to emit blue light.

[0309] Continue to refer to Figure 23 The aforementioned multiple initial signal lines VL include multiple sixth sub-signal lines VL13, multiple seventh sub-signal lines VL14, and multiple eighth sub-signal lines VL15. The sixth sub-signal lines VL13, VL14, and VL15 are arranged periodically, for example, along the row direction X. Specifically, the sixth sub-signal line VL13 is electrically connected to each reset circuit 12 in the first sub-pixel column PC1, the seventh sub-signal line VL14 is electrically connected to each reset circuit 12 in the second sub-pixel column PC2, and the eighth sub-signal line VL15 is electrically connected to each reset circuit 12 in the third sub-pixel column PC3.

[0310] Optionally, the voltage values ​​of the initial signals transmitted on the sixth sub-signal line VL13, the seventh sub-signal line VL14, and the eighth sub-signal line VL15 are all different. For example... Figure 23 As shown, in this case, the sixth sub-signal line VL13, the seventh sub-signal line VL14, and the eighth sub-signal line VL15 are set independently.

[0311] Optionally, the voltage values ​​of the initial signals transmitted by the seventh sub-signal line VL14 and the eighth sub-signal line VL15 are the same. In this case, the seventh sub-signal line VL14 and the eighth sub-signal line VL15 are electrically connected, and the seventh sub-signal line VL14 and the eighth sub-signal line VL15 are used to transmit the same third initial signal.

[0312] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A pixel circuit, characterized in that, The pixel circuit includes: A drive control circuit is electrically connected to the anode of the light-emitting device; the drive control circuit is configured to provide a drive signal to the anode of the light-emitting device to drive the light-emitting device to emit light. A reset circuit is electrically connected to a reset signal terminal, an initial signal terminal, and the anode of the light-emitting device; the reset circuit is configured to turn on in response to a reset signal transmitted from the reset signal terminal, and to transmit a first initial signal and a second initial signal from the initial signal terminal to the anode of the light-emitting device in a time-division manner; wherein the voltage values ​​of the first initial signal and the second initial signal are different.

2. The pixel circuit according to claim 1, characterized in that, The reset circuit includes a first reset unit and a second reset unit, the reset signal terminal includes a first reset signal terminal and a second reset signal terminal, and the initial signal terminal includes a first initial signal terminal and a second initial signal terminal. The first reset unit is electrically connected to the first reset signal terminal, the first initial signal terminal, and the anode of the light-emitting device; the first reset unit is configured to be turned on in response to a first reset signal transmitted from the first reset signal terminal, and to transmit a first initial signal from the first initial signal terminal to the anode of the light-emitting device; The second reset unit is electrically connected to the second reset signal terminal, the second initial signal terminal, and the anode of the light-emitting device; the second reset unit is configured to be turned on in response to the second reset signal transmitted by the second reset signal terminal, and to transmit the second initial signal from the second initial signal terminal to the anode of the light-emitting device; The timing at which the first reset signal is transmitted to the first reset unit is different from the timing at which the second reset signal is transmitted to the second reset unit.

3. The pixel circuit according to claim 2, characterized in that, The voltage value of the second initial signal is greater than the voltage value of the first initial signal.

4. The pixel circuit according to claim 2 or 3, characterized in that, The first reset unit includes a first transistor, and the second reset unit includes a second transistor; The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the first initial signal terminal, and the second electrode of the first transistor is electrically connected to the anode of the light-emitting device. The control electrode of the second transistor is electrically connected to the second reset signal terminal, the first electrode of the second transistor is electrically connected to the second initial signal terminal, and the second electrode of the second transistor is electrically connected to the anode of the light-emitting device.

5. The pixel circuit according to any one of claims 2-4, characterized in that, The drive control circuit includes: a data writing unit, a drive unit, a compensation unit, and a light-emitting control unit; The data writing unit is electrically connected to the scan signal terminal, the data signal terminal, and the driving unit; the compensation unit is electrically connected to the scan signal terminal and the driving unit. The data writing unit and the compensation unit are configured to be turned on in response to the scan signal transmitted by the scan signal terminal, and to transmit the data signal from the data signal terminal to the driving unit; The light-emitting control unit is electrically connected to an enable signal terminal, a first voltage signal terminal, the driving unit, and the anode of the light-emitting device; the light-emitting control unit is configured to be turned on in response to an enable signal transmitted by the enable signal terminal, thereby connecting the path between the first voltage signal terminal and the anode of the light-emitting device. Wherein, the moment when the first reset signal is transmitted to the first reset unit is earlier than the moment when the data signal is transmitted to the drive unit; The timing at which the second reset signal is transmitted to the second reset unit is earlier or later than the timing at which the first reset signal is transmitted to the first reset unit.

6. The pixel circuit according to claim 5, characterized in that, The data writing unit includes a third transistor, the driving unit includes a fourth transistor and a capacitor, the compensation unit includes a fifth transistor, and the light-emitting control unit includes a sixth transistor and a seventh transistor. The control electrode of the third transistor is electrically connected to the scan signal terminal, the first electrode of the third transistor is electrically connected to the data signal terminal, and the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor. The control electrode of the fourth transistor is electrically connected to the second electrode of the fifth transistor, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor; The control electrode of the fifth transistor is electrically connected to the scanning signal terminal; The control electrode of the sixth transistor is electrically connected to the enable signal terminal, the first electrode of the sixth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the sixth transistor is electrically connected to the first electrode of the fourth transistor. The control electrode of the seventh transistor is electrically connected to the enable signal terminal, the first electrode of the seventh transistor is electrically connected to the second electrode of the fourth transistor, and the second electrode of the seventh transistor is electrically connected to the anode of the light-emitting device. The first terminal of the capacitor is electrically connected to the control terminal of the fourth transistor, and the second terminal of the capacitor is electrically connected to the first voltage signal terminal.

7. The pixel circuit according to claim 5 or 6, characterized in that, The drive control circuit further includes: a third reset unit; The third reset unit is electrically connected to the first reset signal terminal, the third initial signal terminal, and the driving unit; the third reset unit is configured to be turned on in response to the first reset signal and transmit the third initial signal from the third initial signal terminal to the driving unit.

8. The pixel circuit according to claim 7, characterized in that, The third reset unit includes an eighth transistor; The control electrode of the eighth transistor is electrically connected to the first reset signal terminal, the first electrode of the eighth transistor is electrically connected to the third initial signal terminal, and the second electrode of the eighth transistor is electrically connected to the driving unit.

9. A display panel, characterized in that, The display panel includes multiple sub-pixels; The sub-pixel includes a pixel circuit and a light-emitting device, wherein the pixel circuit is electrically connected to the anode of the light-emitting device; the pixel circuit includes the pixel circuit as described in any one of claims 1-8.

10. The display panel according to claim 9, characterized in that, The reset circuit of the pixel circuit includes a first reset unit and a second reset unit; The display panel further includes: a first reset signal line, a second reset signal line, a first initial signal line, and a second initial signal line; The first reset unit is electrically connected to the first reset signal line via a first reset signal terminal, and is also electrically connected to the first initial signal line via a first initial signal terminal; The second reset unit is electrically connected to the second reset signal line via the second reset signal terminal, and is also electrically connected to the second initial signal line via the second initial signal terminal.

11. The display panel according to claim 10, characterized in that, The display panel further includes a scan signal line; the driving control circuit of the pixel circuit includes a data writing unit, which is electrically connected to the scan signal line through a scan signal terminal; The multiple sub-pixels are arranged in multiple rows; The first reset signal line electrically connected to the first reset unit of the m-th row sub-pixel is electrically connected to the scan signal line electrically connected to the data writing unit of the n-th row sub-pixel. The second reset signal line electrically connected to the second reset unit of the m-th row sub-pixel is electrically connected to the scan signal line electrically connected to the data writing unit of the nj-th row sub-pixel; where m and n are both positive integers, j is an integer, and m≠n.

12. The display panel according to any one of claims 9-11, characterized in that, The multiple sub-pixels are arranged in multiple columns; The driving control circuit of the pixel circuit includes a third reset unit; the display panel also includes multiple third initial signal lines extending along the column direction; the multiple third initial signal lines are electrically connected to the third reset units of multiple columns of the sub-pixels respectively; Among them, at least two of the third initial signal lines transmit third initial signals with different voltage values, and the sub-pixels connected to the third initial signal lines that transmit third initial signals with different voltage values ​​emit different colors.

13. The display panel according to claim 12, characterized in that, The multiple columns of sub-pixels include a first sub-pixel column and a second sub-pixel column, wherein the emission color of each sub-pixel in the first sub-pixel column is different from the emission color of each sub-pixel in the second sub-pixel column; the multiple third initial signal lines include a third sub-signal line and a fourth sub-signal line; The third sub-signal line is electrically connected to each of the third reset units in the first sub-pixel column, and the fourth sub-signal line is electrically connected to each of the third reset units in the second sub-pixel column; The voltage values ​​of the third initial signal transmitted by the third sub-signal line and the fourth sub-signal line are different.

14. The display panel according to claim 13, characterized in that, The first sub-pixel column includes a plurality of first color sub-pixels, and the second sub-pixel column includes a plurality of second color sub-pixels and third color sub-pixels alternately arranged along the column direction.

15. The display panel according to claim 13, characterized in that, The multiple columns of sub-pixels also include a third sub-pixel column, and the multiple third initial signal lines also include a fifth sub-signal line, which is electrically connected to each of the third reset units in the third sub-pixel column; The first sub-pixel column includes multiple first-color sub-pixels, the second sub-pixel column includes multiple second-color sub-pixels, and the third sub-pixel column includes multiple third-color sub-pixels.

16. The display panel according to claim 15, characterized in that, The voltage values ​​of the third initial signal transmitted by the third sub-signal line, the fourth sub-signal line, and the fifth sub-signal line are all different.

17. The display panel according to claim 15, characterized in that, The voltage values ​​of the third initial signal transmitted by the fifth sub-signal line and the fourth sub-signal line are the same.

18. The display panel according to any one of claims 12-17, characterized in that, The display panel also includes multiple auxiliary signal lines extending along the row direction; The auxiliary signal line is electrically connected to multiple third initial signal lines that transmit the same voltage value as the third initial signal.

19. A display panel, characterized in that, The display panel includes: Multiple sub-pixels are arranged in multiple rows; each sub-pixel includes a pixel circuit and a light-emitting device; the pixel circuit includes a driving control circuit and a reset circuit; the driving control circuit is electrically connected to the anode of the light-emitting device; the driving control circuit is configured to provide a driving signal to the anode of the light-emitting device to drive the light-emitting device to emit light; the reset circuit is electrically connected to a reset signal terminal, an initial signal terminal, and the anode of the light-emitting device; the reset circuit is configured to turn on in response to a reset signal transmitted from the reset signal terminal, and to transmit an initial signal from the initial signal terminal to the anode of the light-emitting device in a time-division multiplexing manner; the voltage value of the initial signal received by the anode of the light-emitting device is different at different times; Multiple initial signal lines extend along the row direction; the multiple initial signal lines are electrically connected to the reset circuits of the multiple rows of sub-pixels through the initial signal terminals respectively; The plurality of initial signal lines include at least: a plurality of first sub-signal lines and a plurality of second sub-signal lines alternately arranged along the column direction, wherein the plurality of first sub-signal lines are electrically connected and the plurality of second sub-signal lines are electrically connected.

20. A display module, characterized in that, The display module includes: The display panel as described in any one of claims 9-19; The display driver integrated circuit is electrically connected to the display panel.

21. An electronic device, characterized in that, The electronic device includes: The display module as described in claim 20; A drive controller is coupled to the display module.

22. A driving method for a pixel circuit, characterized in that, The pixel circuit includes a drive control circuit and a reset circuit; the drive control circuit is electrically connected to the anode of the light-emitting device, and the reset circuit is electrically connected to the reset signal terminal, the initial signal terminal, and the anode of the light-emitting device. The display of a single frame of an image includes a light-emitting phase and a non-light-emitting phase. During the light-emitting stage, the driving control circuit provides a driving signal to the anode of the light-emitting device to drive the light-emitting device to emit light; During the non-light-emitting phase, the reset circuit is turned on in response to the reset signal transmitted from the reset signal terminal, and transmits the first initial signal and the second initial signal from the initial signal terminal to the anode of the light-emitting device in a time-division manner; wherein the voltage values ​​of the first initial signal and the second initial signal are different.

23. The driving method according to claim 22, characterized in that, The reset circuit includes a first reset unit and a second reset unit; the reset signal terminal includes a first reset signal terminal and a second reset signal terminal; the initial signal terminal includes a first initial signal terminal and a second initial signal terminal; the first reset unit is electrically connected to the first reset signal terminal, the first initial signal terminal, and the anode of the light-emitting device; the second reset unit is electrically connected to the second reset signal terminal, the second initial signal terminal, and the anode of the light-emitting device. During the non-light-emitting phase, the reset circuit is turned on in response to the reset signal transmitted from the reset signal terminal, and transmits the first initial signal and the second initial signal from the initial signal terminal to the anode of the light-emitting device in a time-division manner, including: The first reset unit is turned on in response to the first reset signal transmitted from the first reset signal terminal, and transmits the first initial signal from the first initial signal terminal to the anode of the light-emitting device; the second reset unit is turned on in response to the second reset signal transmitted from the second reset signal terminal, and transmits the second initial signal from the second initial signal terminal to the anode of the light-emitting device; wherein the timing of the first reset signal being transmitted to the first reset unit and the timing of the second reset signal being transmitted to the second reset unit are different.

24. The driving method according to claim 23, characterized in that, The drive control circuit includes: a data writing unit, a drive unit, a compensation unit, and a light-emitting control unit; the data writing unit is electrically connected to the scan signal terminal, the data signal terminal, and the drive unit; the compensation unit is electrically connected to the scan signal terminal and the drive unit; the light-emitting control unit is electrically connected to the enable signal terminal, the first voltage signal terminal, the drive unit, and the anode of the light-emitting device. During the light-emitting stage, the driving control circuit provides a driving signal to the anode of the light-emitting device to drive the light-emitting device to emit light, including: The light-emitting control unit is turned on in response to the enable signal transmitted by the enable signal terminal, connecting the path between the first voltage signal terminal and the anode of the light-emitting device; During the non-light-emitting phase, the reset circuit is turned on in response to the reset signal transmitted from the reset signal terminal, and transmits the first initial signal and the second initial signal from the initial signal terminal to the anode of the light-emitting device in a time-division manner, further comprising: The data writing unit and the compensation unit are turned on in response to the scan signal transmitted by the scan signal terminal, and transmit the data signal from the data signal terminal to the driving unit; wherein, the time when the first reset signal is transmitted to the first reset unit is earlier than the time when the data signal is transmitted to the driving unit; the time when the second reset signal is transmitted to the second reset unit is earlier or later than the time when the first reset signal is transmitted to the first reset unit.

25. A driving method for a pixel circuit, characterized in that, The pixel circuit includes a drive control circuit and a reset circuit; the drive control circuit is electrically connected to the anode of the light-emitting device, and the reset circuit is electrically connected to the reset signal terminal, the initial signal terminal, and the anode of the light-emitting device. The display of a single frame of an image includes a light-emitting phase and a non-light-emitting phase. During the light-emitting stage, the driving control circuit provides a driving signal to the anode of the light-emitting device to drive the light-emitting device to emit light; During the non-light-emitting phase, the reset circuit is turned on in response to the reset signal transmitted by the reset signal terminal, and transmits the initial signal from the initial signal terminal to the anode of the light-emitting device; wherein the voltage value of the initial signal received by the anode of the light-emitting device is different at different times.

Images