System and method for reducing electrical stress of a switching device

Abstract

The invention relates to a system and method for reducing electrical stress of a switching device. Methods, systems, and devices are provided for techniques for a switching device that controllably couples a first conductive line to a second conductive line or decouples the first conductive line from the second conductive line. The switching device includes a branch of a primary transistor and a branch of a circuit. At least one of the one or more branches of the primary transistor includes a plurality of primary transistors connected in series. The control terminals of the plurality of primary transistors are connected together and receive a primary control signal, and the plurality of primary transistors are controllably switched to couple the first conductive line to the second conductive line or to decouple the first conductive line from the second conductive line. A plurality of circuits are configured to provide a gradient voltage level between the first conductive line and the second conductive line such that drain-source voltages of the plurality of primary transistors are limited to a maximum allowable value.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 707,720 and U.S. Non-Provisional Application No. 19 / 327,768, both filed October 15, 2024, entitled "Systems and methods for reducing electrical stress of switching devices." The contents of both applications are incorporated herein by reference in their entirety for all purposes. Technical Field

[0003] This disclosure relates to one or more memory devices, and more particularly, to techniques for using multi-gate transistors to reduce electrical stress on switching devices. Background Technology

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access stored information, the memory device can read (e.g., sense, detect, retrieve, determine) the state from the memory cell. To store information, the memory device can write (e.g., program, set, assign) states to the memory cell. Information can also be erased from the memory cell, and new information can be stored in the memory cell.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), self-select memory, chalcogenide memory technology, NOR and NAND memory devices, and others. Memory cells can be described according to volatile or non-volatile configurations. Memory cells configured as non-volatile can maintain their stored logic state for a long time, even without external power. Memory cells configured as volatile will lose their stored state when disconnected from external power. Summary of the Invention

[0006] On one hand, this disclosure provides a switching device for controllably coupling a first conductive line to a second conductive line or decoupling the first conductive line from the second conductive line, the switching device comprising: one or more branches of a primary transistor, wherein at least one of the one or more branches of the primary transistor comprises a plurality of primary transistors connected in series, the control terminals of the plurality of primary transistors being connected together and receiving a primary control signal, and the plurality of primary transistors being controllably switched based on the primary control signal to couple the first conductive line to the second conductive line or decouple the first conductive line from the second conductive line; and one or more branches of a circuit, wherein at least one of the one or more branches of the circuit comprises a plurality of circuit elements connected in series, and each of the plurality of circuit elements being connected in parallel to a corresponding primary transistor, and the plurality of circuit elements being configured to provide a gradient voltage level between the first conductive line and the second conductive line, such that the drain-source voltage of the plurality of primary transistors is limited to a maximum permissible value.

[0007] On the other hand, this disclosure provides a switching device for controllably connecting a first conductive line to a second conductive line or decoupling the first conductive line from the second conductive line. The switching device includes a plurality of branches of a primary transistor, wherein: each of the plurality of branches of the primary transistor includes a plurality of primary transistors connected in series; corresponding primary transistors across the plurality of branches of the primary transistor are connected in parallel to form a plurality of groups of corresponding primary transistors; and control terminals of the plurality of groups of primary transistors are configured to receive gradient control signals such that the drain-source voltage of the plurality of primary transistors in each branch is limited to a maximum allowable value. Attached Figure Description

[0008] Figure 1 This is a block diagram of a memory device communicating with a memory system controller of a memory system, based on the examples disclosed herein.

[0009] Figures 2A to 2C This is an illustrative schematic diagram of a portion of a memory cell array in a memory device based on the examples disclosed herein.

[0010] Figures 3A and 3B are circuit diagrams of prior art switching devices containing a single transistor or multiple transistors connected in series.

[0011] Figure 3C is a circuit diagram of a prior art switching device with multiple transistors connected in series.

[0012] Figure 3D is a voltage curve of the internal node of the prior art switching device during the global word line ramp-up.

[0013] Figure 4This is a block diagram of an example switching device whose internal node electrical stress has been reduced, based on the examples disclosed in this article.

[0014] Figure 5A This is a circuit diagram of an example switching device with a capacitor bridge based on the examples disclosed herein.

[0015] Figure 5B It is based on the examples disclosed in this article. Figure 5A The example switch device shown in the image has a voltage curve of its internal nodes during the global word line ramp-up.

[0016] Figure 5C It is based on the examples disclosed in this article. Figure 5A The graph shows the drain-source voltage of the transistor in the switching device.

[0017] Figures 6A to 6C It is a circuit diagram of an example switching device having one or more secondary transistor branches, based on the examples disclosed herein.

[0018] Figure 6D It is based on the examples disclosed in this article. Figures 6A to 6C The example switch device shown in the image has a voltage curve of its internal nodes during the global word line ramp-up.

[0019] Figure 6E It is based on the examples disclosed in this article. Figures 6A to 6C The example switching device is shown in the figure with voltage curves of the internal nodes and control terminals of the primary transistor during programming, programming verification and read operations.

[0020] Figure 6F It is based on the examples disclosed in this article. Figures 6A to 6C The example switching device shown in the image has voltage curves of the internal nodes and control terminals of the primary transistor during the erase operation.

[0021] Figure 7A This is a circuit diagram of an example switching device with gradient control signals based on the examples disclosed herein.

[0022] Figure 7B It is based on the examples disclosed in this article. Figure 7A The example switch device shown in the image has a voltage curve of its internal nodes during the global word line ramp-up.

[0023] Figure 7C It is based on the examples disclosed in this article. Figure 7A The example switching device is shown in the figure with voltage curves of the internal nodes and control terminals of the primary transistor during programming, programming verification and read operations.

[0024] Figure 7DIt is based on the examples disclosed in this article. Figure 7B The example switching device shown in the image has voltage curves of the internal nodes and control terminals of the primary transistor during the erase operation.

[0025] Figure 8 This is a block diagram illustrating an example gradient control signal generation circuit based on the examples disclosed herein. Detailed Implementation

[0026] A memory device may comprise an array of memory cells, also known as a memory array. A memory array may comprise a plurality of memory blocks. Each memory block may have a plurality of memory cells and associated word lines for accessing those memory cells. Multiple memory blocks may be connected to a global word line. In various operations of the memory device (e.g., read, program, erase), one memory block is selected from a plurality of memory blocks, while the others are not selected. To select a memory block, a plurality of switching devices are typically used. Each of the plurality of switching devices is connected between the global word line and the corresponding memory block. Thus, one end of the switching device is connected to the global word line and the other end of the switching device is connected to one or more local word lines within the memory block. When a memory block is selected for an operation, the switching device is turned on to electrically connect the global word line and the local word line. If the memory block is not selected, the switching device is turned off. This switching device is sometimes also called a serial driver.

[0027] In existing technologies, switching devices can be implemented using a single transistor (e.g., an NMOS transistor). When the memory block is not selected, a single-transistor switching device may experience high electrical stress. For example, the global word line may have a voltage of 25V, while a local word line within the memory block may have a voltage of 0V. Therefore, a single-transistor switching device may experience high voltage at the semiconductor junction (e.g., the pn junction between the channel and the doped drain or source region of the transistor). DS (Drain-source voltage). To reliably withstand this high electrical stress on a single transistor, complex and expensive transistor configurations may be required, resulting in inefficiency and high cost.

[0028] To address this issue, existing technologies use multiple transistors connected in series, thereby reducing the drain-source voltage of each of the transistors. However, this type of switching device can only reduce electrical stress when the voltage is static (e.g., when the voltages of the global word line and local word line do not change or have reached a stable phase). If the voltage applied to the switching device changes, existing technologies cannot reduce or completely eliminate electrical stress. For example, during a global word line ramp-up, the drain-source voltage of the first transistor connected to the global word line may exceed the maximum permissible voltage. Therefore, under dynamic conditions, the switching device may still experience high electrical stress.

[0029] The circuit techniques described in this disclosure can reduce or eliminate high electrical stress under both static and dynamic conditions. In one example, a capacitor bridge is connected in parallel with a primary transistor, thereby providing a gradient voltage level between the two conductors, limiting the drain-source voltage of the primary transistors in the switching device to a maximum permissible value. The internal nodes of the primary transistors in the switching device can be rapidly charged through the capacitor bridge, thus eliminating high electrical stress under dynamic conditions. Similarly, one or more branches of a secondary transistor can be connected in parallel with the primary transistor to reduce or eliminate high electrical stress under dynamic conditions. The secondary transistor receives a gradient control voltage. In some instances, one or more branches of the primary transistor directly receive the gradient control voltage without requiring a secondary transistor or other circuit elements. All embodiments disclosed herein can be used to reduce or eliminate high electrical stress under both dynamic and static conditions, thereby making the device more reliable.

[0030] Figure 1 This is a simplified block diagram of a memory device 130 communicating with a system controller 115 of the memory system. The memory system may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system may be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital Storage (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-line Memory Module (DIMM), a Small Form Factor DIMM (SO-DIMM), or a Non-Volatile DIMM (NVDIMM), and other devices. The memory system may communicate with a host system, which may include a host system controller. The host system may use one or more processors and a memory system to write data to the memory system, read data from the memory system, erase data, or refresh data.

[0031] A memory system may include one or more memory devices, such as device 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), NOR (e.g., NOR flash) memory, etc. In some cases, memory device 130 is a NAND memory device 130, which may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively or concurrently, NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may be referred to as a multi-level cell (MLC) when configured to store two bits of information, a three-level cell (TLC) when configured to store three bits of information, a four-level cell (QLC) when configured to store four bits of information, or more generally, a multi-level memory cell. Multilevel memory cells can provide greater storage density compared to SLC memory cells, but in some cases may involve narrower read or write margins or greater complexity to support the circuitry.

[0032] like Figure 1 As shown in the diagram and described in more detail below, memory device 130 includes a memory cell array 104 logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access line (e.g., a word line), while memory cells in logical columns are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with memory cells in more than one logical row, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in memory cell array 104 ( Figure 1 (Not shown in the text) It can be programmed to one of at least two target data states to store any number of information bits.

[0033] Continue to refer to Figure 1 Row decoding circuitry 108 and column decoding circuitry 111 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 130 also includes input / output (I / O) control circuitry 112 for managing commands, addresses, and data input to and from memory device 130 and data and status information output from memory device 130. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 111 to latch address signals before decoding. Row decoding circuitry 108 and column decoding circuitry 111 may be simply referred to as row decoder 108 and column decoder 111, respectively. Command register 124 communicates with I / O control circuitry 112 and local controller 135 to latch incoming commands.

[0034] A memory controller (e.g., a local controller 135 within memory device 130) controls access to memory cell array 104 in response to commands and generates status information for external system controller 115. For example, local controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on memory cell array 104. Local controller 135 communicates with row decoding circuitry 108 and column decoding circuitry 111 to control row decoding circuitry 108 and column decoding circuitry 111 based on addresses.

[0035] In some embodiments, the local controller 135 communicates with an external system controller 115, which may be a host controller located in a host system (e.g., a UFS or eMMC controller or a CPU communicating with the local controller 135) or a memory system controller located in a memory system. In some embodiments, the local controller 135 is disposed on the same semiconductor die as the memory array (e.g., array 104), and the separate system controller 115 is disposed on a different die. In other instances, some portions of the memory device 130 may be disposed on a first die, and other portions of the memory device 130 may be disposed on a second die different from the first die. For example, the first die may include the memory cell array 104 and its associated circuitry, such as column decoder 111 and row decoder 108. The second die may include logic circuitry, power circuitry, or other circuitry of the device 130. Thus, the second die may include system controller 115, I / O control 112, etc. In this example, the first die does not have a local controller, and the second die includes system controller 115. The first and second dies can be coupled together, for example, using through-vias (TSVs), to electrically connect them. The first and second dies can also be wafer-bonded using flip-chip bonding techniques, etc. In this disclosure, system controller 115 and local controller 135 may both be simply referred to as memory controllers or first memory controller and second memory controller. It should be understood that although they may be different controllers, unless otherwise specified, certain operations disclosed herein can be caused or performed by either or both memory controllers.

[0036] The local controller 135 also communicates with cache register 118 and data register 121. In some embodiments, one or more cache registers 118 may collectively form at least a portion of a cache buffer. When the memory cell array 104 is busy writing or reading other data, the cache register 118 latches or buffers incoming or outgoing data to temporarily store the data, as directed by the local controller 135. During programming operations (e.g., write operations), data may be transferred from cache register 118 to data register 121 to the memory cell array 104; subsequently, new data may be latched into cache register 118 from I / O control circuitry 112. During read operations, data may be transferred from cache register 118 to I / O control circuitry 112 to output to system controller 115; subsequently, new data may be transferred from data register 121 to cache register 118. In some embodiments, cache register 118 and / or data register 121 may form at least a portion of page buffer 152 of memory device 130. Page buffer 152 may further include sensing means, such as a sensing amplifier, for sensing the data state of the memory cells, for example, by sensing the state of the data lines connected to the memory cells in memory cell array 104. Status register 122 may communicate with I / O control circuitry system 112 and local media controller 135 to latch status information for output to system controller 115.

[0037] like Figure 1 As shown, memory device 130 receives various control signals from system controller 115 via control link 132 and local controller 135. For example, control signals may include chip enable signal CE#, command latch enable signal CLE, address latch enable signal ALE, write enable signal WE#, read enable signal RE#, and write protect signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may be received via control link 132. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from system controller 115 via multiplexed input / output (I / O) bus 134 and outputs data to system controller 115 via I / O bus 134.

[0038] For example, commands can be received at I / O control circuitry 112 via I / O bus 134 input / output (I / O) pins [7:0] and then written to command register 124. Addresses can be received at I / O control circuitry 112 via I / O bus 134 input / output (I / O) pins [7:0] and then written to address register 114. Data can be received at I / O control circuitry 112 via 8-bit device input / output (I / O) pins [7:0] or 16-bit device input / output (I / O) pins [15:0] and then written to cache register 118. Data can then be written to data register 121 for programming memory cell array 104.

[0039] In this embodiment, cache register 118 may be omitted, and data may be written directly to data register 121. Data may also be output via input / output (I / O) pins [7:0] of an 8-bit device or input / output (I / O) pins [15:0] of a 16-bit device. Although references may be made to I / O pins, they may include any conductive nodes, such as common conductive pads or conductive bumps, that provide electrical connections to memory device 130 via external devices, such as system controller 115. While the above description uses a 16-bit I / O bus 134 as an example, it should be understood that bus 134 may be configured to any number of bits (e.g., 64 bits).

[0040] Those skilled in the art should understand that additional circuitry and signals can be provided, and Figure 1 The memory device 130 has been simplified. It should be understood that the reference... Figure 1 The functionality of the various block components described is not necessarily separated into different components or component parts of an integrated circuit device. For example, a single component or component part of an integrated circuit device can be adapted to perform... Figure 1 The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1 The functionality of a single block component. Additionally, while specific I / O pins are described according to general conventions for receiving and outputting various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0041] Figures 2A to 2B This is an example schematic diagram of a portion of a memory cell array 200A, such as a NAND memory array. The memory cell array 200A may be a reference according to an embodiment. Figure 1 An example of a memory array 104 of the described memory device 130. The memory array 200A includes access lines (e.g., word lines 2020 to 202). N) and data lines (e.g., bit lines 2040 to 204) M Word line 202 can be connected to global access lines (e.g., global word lines) in a many-to-one relationship. Figure 2C (as shown in the diagram). In some embodiments, the memory array 200A may be formed over a semiconductor, which may be doped to have a conductivity type, for example, p-type conductivity for forming a p-well or n-type conductivity for forming an n-well.

[0042] The memory array 200A can be arranged in rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can contain a string of memory cells (e.g., non-volatile memory cells) connected in series, such as NAND strings 2060 to 206. M One of them. Each NAND string 206 can be connected (e.g., selectively connected) to the common source (SRC) 216 and can contain memory cells 2080 to 208. N Memory cell 208 may represent a non-volatile memory cell used for data storage. The memory cell 208 of each NAND string 206 may be connected in series with a select transistor 210 (e.g., a field-effect transistor) (e.g., select gates 2100 to 210). M One of them (e.g., it may be a source-select transistor, commonly referred to as a select-gate-source transistor) and select transistor 212 (e.g., a field-effect transistor) (e.g., select transistors 2120 to 212) M Between one of them (for example, it could be a drain-select transistor, often referred to as a select gate-drain). Select gates 2100 to 210 M They can be connected together to select line 214 (e.g., source select line (SGS)), and select gates 2120 to 212. M They can be connected together to select line 215 (e.g., drain select line (SGD)). Although depicted as conventional field-effect transistors, select transistors 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select transistors 210 and 212 can represent several select gates connected in series, wherein each select transistor connected in series is configured to receive the same or independent control signal.

[0043] The source of each select transistor 210 can be connected to the common source 216. The drain of each select transistor 210 can be connected to the memory cell 2080 of the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to the memory cell 2080 of the corresponding NAND string 2060. Therefore, each select transistor 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select transistor 210 can be connected to select line 214.

[0044] The drain of each select transistor 212 can be connected to bit line 204 of the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to bit line 2040 of the corresponding NAND string 2060. The source of each select transistor 212 can be connected to memory cell 208 of the corresponding NAND string 206. N For example, the source of select gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select transistor 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding bit line 204. The control gate of each select transistor 212 can be connected to the select line 215.

[0045] Figure 2A The memory array 200A can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, NAND string 206, and bit line 204 extend in a substantially parallel plane. Alternatively, Figure 2A The memory array 200A in the memory array can be a three-dimensional memory array, for example, in which the NAND string 206 can extend substantially perpendicular to the plane containing the common source 216 and substantially parallel to the plane containing the bit line 204.

[0046] A typical configuration of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trap, or the like) that determines the data state of the memory cell (e.g., through changes in a threshold voltage) and a control gate 236, such as... Figure 2A The data storage structure 234 may include both conductive and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 may further have a source / drain defining a source / drain (e.g., a source) 230 and a source / drain defining a drain (e.g., a drain) 232. The memory cell 208 connects its control gate 236 to (and in some cases forms) a word line 202.

[0047] A row of memory cells 208 may be one or more NAND strings 206 selectively connected to a given word line 204. A row of memory cells 208 may be memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 may (but not necessarily) contain all memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 may typically be divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 typically contains every other memory cell 208 commonly connected to a given word line 202. For example, commonly connected to word line 202... NFurthermore, memory cells 208 selectively connected to even-numbered bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be a physical page of memory cell 208 (e.g., an even-numbered memory cell), while those commonly connected to word line 202... N Furthermore, the memory cell 208 selectively connected to the odd bit line 204 (e.g., bit line 2041, 2043, 2045, etc.) can be another physical page of the memory cell 208 (e.g., the odd memory cell).

[0048] Despite Figure 2A Although bit lines 2043 to 2045 are not explicitly depicted in the figure, it is evident from the diagram that bit lines 204 of the memory cell array 200A can be consecutively numbered from bit line 2040 to bit line 204. M Other groups of memory cells 208 commonly connected to a given word line 202 may also define physical pages of memory cells 208. For a particular memory device, all memory cells commonly connected to a given word line can be considered physical pages of the memory cells. A portion (in some embodiments, this may still be an entire line) of a physical page of a memory cell read during a single read operation or programmed during a single programmable operation (e.g., the previous or next page of the memory cell) can be considered a logical page of the memory cell. A block of memory cells may contain those memory cells configured to be erased together, such as those connected to word lines 2020 to 202. N All memory cells (e.g., all NAND strings 206 sharing a common word line 202). Unless explicitly distinguished, the reference to a memory cell page herein refers to the memory cell of the logical page of the memory cell. A logical page may or may not be the same as a physical page. Although Figure 2A Examples are discussed in conjunction with NAND flash memory, but the embodiments and concepts described herein are not limited to a specific array architecture or structure, but may include other structures (such as SONOS, phase-change, ferroelectric, etc.) and other architectures (such as AND arrays, NOR arrays, etc.).

[0049] Figure 2B This is another schematic diagram that can be used as part of a memory cell array 200B in memory device 130 (e.g., as part of memory cell array 104). Figure 2B The similar numbered elements in the middle correspond to about Figure 2A The description provided. Figure 2BAdditional details are provided for an example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B may be incorporated into a vertical structure that may contain semiconductor pillars, a portion of which may serve as channel regions for the memory cells of NAND strings 206. Each of the NAND strings 206 may be selectively connected to bit lines 2040 to 204 via a select transistor 212 (e.g., which may be a drain select transistor, commonly referred to as a select gate drain) M Furthermore, a select transistor 210 (e.g., a source select transistor, often referred to as a select gate source) is connected to the common source 216. Multiple NAND strings 206 can be selectively connected to the same bit line 204. A subset of the NAND strings 206 can be connected by applying a bias voltage to select lines 2150 to 215. K Each select transistor 212 is connected to its corresponding bit line 204 to selectively activate a specific select transistor 212 located between the NAND string 206 and the bit line 204. Select transistor 210 can be activated by applying a bias voltage to select line 214. In some embodiments, each sub-block or string of memory cells has a select line 214 separate from other sub-blocks or strings. In some embodiments, a pair of sub-blocks share a select line 214. Each word line 202 can be connected to multiple rows of memory cells in the memory array 200B. Rows of memory cells interconnected by specific word lines 202 are collectively referred to as a hierarchy.

[0050] A three-dimensional NAND memory array 200B may comprise multiple stacked layers of memory cell hierarchies connected using vertical channels (e.g., semiconductor pillars). For example, the number of layers in the three-dimensional NAND memory array 200B may be 32, 48, 64, 96, 112, or any number of layers. In some instances, groups of layers may be collectively referred to as layers. Layers in a three-dimensional NAND memory array may be processed together (e.g., etched together to form part of a semiconductor pillar). Memory devices with three-dimensional NAND memory arrays can provide more memory cells on a single chip than memory devices formed by two-dimensional NAND arrays, thus providing higher storage capacity. Furthermore, in memory devices with three-dimensional NAND memory arrays, transistors in the memory cells are spaced apart, thus reducing interference and electron leakage.

[0051] In some instances, memory cells can be grouped into memory blocks. Figure 2C The NAND string is divided into 206 segments to form memory cell blocks 250, for example, memory cell blocks 2500 to 250. LMemory cell block 250 may be a grouping of memory cells 208 that can be erased together in a single erase operation. A group of memory cells that can be erased together is also called an erase block. Each memory cell block 250 may represent those NAND strings 206 that are typically associated with a single select line 215 (e.g., select line 2150). The common source 216 of memory cell block 250 may be associated with memory cell block 250. L The source 216 is the same as the source. For example, each memory cell block 2500 to 250 L They can be selectively connected to source 216. Access lines 202 and select lines 214 and 215 of a memory cell block 250 may not be directly connected to memory cell blocks 2500 to 2500 respectively. L Access lines 202 and select lines 214 and 215 for any other memory cell blocks.

[0052] In some instances, memory blocks are 2500 to 250. L Can be accessed via switch 2720 to 272 L Fully connect to the global word line. For example... Figure 2C As shown, each block can have its own switching device 272. Each switching device 272 is individually controlled by a block selection signal. In some operations of the memory device, a specific block (e.g., block 2500) is selected, while other blocks (e.g., blocks 2501 to 2500) are selected. L The memory block was not selected. Therefore, the controller can turn on the switching device (e.g., 2720) to select the memory block, while turning off other switching devices (e.g., 2721 to 272). L Switching device 272 is also called a series driver.

[0053] Still referencing Figure 2C Bit line 2040 to 204 M It can be connected (e.g., selectively connected) to buffer portion 240, which may be part of page buffer 152 of memory device 130. Buffer portion 240 may correspond to memory planes (e.g., memory cell blocks 2500 to 250). L (Group of). Buffer section 240 may include sensing circuitry (which may include a sensing amplifier) ​​for sensing the data value indicated on the corresponding bit line 204.

[0054] In some cases, concurrent operations can be performed on different memory planes. For example, concurrent operations can be performed on memory cells within different blocks 250, as long as the different blocks 250 are in different planes. In some cases, individual memory blocks 250 may be referred to as physical blocks, and virtual blocks may refer to a group of blocks 250 within which concurrent operations can occur. For example, concurrent operations can be performed on four physical blocks 2500 located in four different planes, and the four blocks 2500 may be collectively referred to as virtual blocks. In some cases, virtual blocks may contain blocks from different memory devices. In some cases, physical blocks within a virtual block may have the same block address in their respective planes. In some cases, performing concurrent operations in different planes may be subject to one or more restrictions, such as performing concurrent operations on memory cells within different pages that have the same page address in their respective planes (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes).

[0055] In some cases, block 250 may contain memory cells organized into rows (pages) and columns (e.g., strings, not shown). For example, memory cells in the same page may share a common word line (e.g., coupled to a common word line), and memory cells in the same string may share a common digital line (which may alternatively be called a bit line) (e.g., coupled to a common digital line).

[0056] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page level or a portion thereof) but erased at a second granularity level (e.g., at the block level). That is, a page can be the smallest unit of memory (e.g., a group of memory cells) that can be independently programmed or read (e.g., partially concurrently programmed or read as a single programming or reading operation), and memory block 250 can be the smallest unit of memory (e.g., a group of memory cells) that can be independently erased (e.g., partially concurrently erased as a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some cases, an old page cannot be updated until the entire block containing the page is erased.

[0057] Continue to refer to Figure 1 and 2A In 2C, during a true erase operation (during which the memory cell is actually erased), the local controller 135 (e.g., using erase operation manager 137) can cause the common-source voltage line (e.g., SRC 216) to... Figure 2A Select door 2100 to 210 MWhen the (SGS transistor) is turned on, it ramps to the erase voltage (VERA or Vera) via an erase pulse. The ramp to this high-bias erase voltage and subsequent ramp-back from this voltage requires a significant amount of time. Concurrently, the erase operation manager 137 can cause select gates 2120 to 212 to be activated. m ( Figure 2A Turn off to allow selection gates 2120 to 212 m The drain can float, which causes the bit line to go from 2040 to 204. M It also floats. Furthermore, the erase operation manager 137 can erase word lines 202 ( Figure 2A This is coupled to ground (e.g., 0 volts) or keeps word line 202 at a low voltage. This set of voltage levels at memory array 200A can generate an erase potential, which causes memory cells 2080 to 208... N Erased, for example, by forcing electrons through the body of each memory cell from floating bit line 2040 to 204. M Exit. In other embodiments, the selection gates 2100 to 210 can be reversed. M The shutdown causes SRC line 216 to float, while selecting gates 2120 to 212... M When switched on, the voltage of the bit line is ramped up to Vera. As previously mentioned, in 3D NAND, one of the channel regions, pillars, or bit lines can also ramp up the voltage to cause the attached memory cell to be erased. Therefore, for simplicity, the reference to "memory line" herein should be understood to refer to any of the SRC lines or bit lines in 2D NAND or any of the channels, pillars, or bit lines in 3D NAND. In some embodiments, one or more sub-blocks of memory cells (containing physical blocks) are erased during the same true erase operation. A block of memory cells can generally be understood to contain four or more sub-blocks, each containing a separate string of memory cells. In some embodiments, during the erase operation, the pillars in the unselected block are ramped up to a high voltage (e.g., about Vera) as the pillars in the selected block. The difference between the unselected block and the selected block during the erase operation is that the word lines in the unselected block are floating (while the word lines in the selected block are not) and then ramp up to about Vera because they are coupled to the pillars.

[0058] Figures 3A and 3B are circuit diagrams of prior art switching devices comprising a single transistor and multiple transistors connected in series. In Figure 3A, switching device 310 is implemented using a single transistor (e.g., an NMOS transistor). Switching device 310 is connected between a global word line and a local word line. When a memory block is not selected, switching device 310 may experience high electrical stress. For example, as shown in Figure 3A, the global word line may have a voltage of 25V, while the local word line may have a voltage of 0V. Therefore, the single-transistor switching device 310 may experience high voltage at the semiconductor junction (e.g., a pn junction between the channel (or body) of the transistor and the doped drain or source region). DS (Drain-source voltage). To reliably withstand this high electrical stress on a single transistor, complex and expensive transistor configurations may be required, resulting in inefficiency and high cost.

[0059] To address this issue, existing technologies use multiple transistors connected in series, thereby reducing the drain-source voltage of each of the transistors. An example is shown in Figure 3B. Switching device 320 comprises five transistors 322A to 322E connected in series. That is, the drain of transistor 322A is connected to the global word line; the source of transistor 322A is connected to the drain of transistor 322B. The source of transistor 322B is then connected to the drain of the next transistor 322C, and so on. Finally, the source of transistor 322E is connected to the local word line. Switching device 320 reduces the electrical stress imposed on each transistor. For example, as shown in Figure 3B, ideally, the drain-source voltage of each transistor 322 is approximately 5V, which is significantly lower than the 25V in single-transistor switching device 310. Internal nodes N4, N3, N2, and N1 between two corresponding adjacent transistors 322 have voltages of 20V, 15V, 10V, and 5V, respectively. Therefore, compared to the junction of device 310 in Figure 3A, the semiconductor junction in each transistor has significantly reduced electrical stress. In Figure 3B, the control terminals of each transistor 322 are connected together and receive a block select signal. If the switching device 320 is turned off, the block select signal can be at 0V.

[0060] Similar to Figure 3B, Figure 3C is a circuit diagram of a prior art switching device 320 having multiple transistors connected in series. Figure 3C illustrates that the number of transistors in the switching device 320 can be determined by the maximum permissible voltage (e.g., Vmax) across the drain and source of each transistor in the switching device 320 and the maximum voltage difference (e.g., 25V) between the global word line and the local word line. Therefore, if a particular transistor used in the switching device 320 can withstand approximately 5V of Vmax and the maximum voltage difference between the global word line and the local word line is approximately 25V, then the number of transistors required for the switching device 320 can be calculated to be 5.

[0061] When the voltage applied to the switching device 320 is static (e.g., when the voltages of the global word line and the local word line do not change or reach a static state), the switching device 320 can reduce the electrical stress on the transistors. However, if the voltage applied to the switching device 320 changes, the switching device 320 may not be able to reduce or completely eliminate the electrical stress. Figure 3D is a voltage curve of the internal node of the prior art switching device 320 during the voltage ramp-up of the global word line. For example, during the voltage ramp-up of the global word line, the drain-source voltage of the first transistor connected to the global word line (i.e., the voltage between the global word line and the internal node N4) may exceed the maximum allowable voltage. In Figure 3D, for example, during the voltage ramp-up of the global word line (e.g., from 0V to 25V), the dynamic drain-source voltage V... DC-AC Comparable static drain-source voltage V DC-DC (For example, 5V) or much larger than the maximum permissible drain-source voltage of transistors used in switching devices. In some cases, the dynamic drain-source voltage V DC-AC It can be approximately or more than half the voltage difference between the global word line and the local word line (e.g., it can be greater than 12V). Therefore, under dynamic conditions (e.g., during voltage ramp-up or ramp-down), the switching device 320 may still experience high electrical stress.

[0062] The high electrical stress under dynamic conditions is caused by the slow charging of the internal nodes of the transistors in the switching device 320. Specifically, as shown in Figure 3C, the switching device 320 is turned off and therefore the associated memory block is not selected. In this case, a voltage of 0V (or any other voltage used to turn off the device 320) is applied to the control terminals of the switching device 320. As the global word line ramps up from 0V to 25V, the internal nodes of the switching device 320 (e.g., N4, N3, N2, and N1) are also charged, causing their voltages to ramp up as well. However, because the transistors are turned off, the internal nodes can only be charged through the drain-source leakage current of the transistors. Typically, the leakage current is very small (e.g., in the picoamp range), and therefore, the charging time is much longer than the ramp-up time of the global word line. In other words, at certain points during the ramp-up of the global word line voltage, the internal nodes of the switching device 320 may still be at a very low voltage, thereby resulting in a large voltage difference between the drain and source of the transistors in the switching device 320.

[0063] In order to reduce or eliminate the high electrical stress imposed on the switching device, several circuits are described in this disclosure. Figure 4This is a block diagram of an example switching device 400 with reduced electrical stress at internal nodes, based on the examples disclosed herein. The switching device 400 may include one or more branches of a primary transistor 410, one or more branches of a circuit 430, and / or a gradient voltage driver circuit 440. In some examples, the switching device 400 may include only one or more branches of the primary transistor 410 and the gradient voltage driver circuit 440, only one or more branches of the primary transistor 410 and one or more branches of the circuit 430, or all circuits 410, 430, and 440. In a preferred embodiment, the switching device 400 may not include the gradient voltage driver circuit 440, which may be a separate circuit or part of another circuit system (e.g., part of the regulator of the switching device). For example, the gradient voltage driver circuit need not be included in every switching device. Instead, it may be shared by some or all blocks in the memory plane or common to all planes in the die.

[0064] like Figure 4 As shown, the switching device 400 may have three terminals. A first terminal 418 may be connected to a first conductive line, and a second terminal 408 may be connected to a second conductive line. For example, the first and second conductive lines may be global word lines or local word lines of the memory device, respectively. However, they may also be other conductive lines, including, for example, bit lines or access lines. In other words, the switching device 400 is not limited to a string driver used together with a global word line to select a memory block, but can also be used in any other circuitry where a switching device is required.

[0065] Continue to refer to Figure 4 The switching device 400 also has a control terminal 420 connected to a control signal (e.g., a block select signal). The control terminal 420 receives a control signal for turning the switching device 400 on or off. If the control signal is high, the switching device 400 is on. A first conductive line (e.g., connected to a first terminal 418) and a second conductive line (e.g., connected to a second terminal 408) are electrically connected together, such that an electrical signal (e.g., a voltage or current signal) is transmitted between the first and second conductive lines (e.g., between a global word line and a local word line). If the control signal is low, the switching device 400 is off. Therefore, there is no electrical connection between the first and second conductive lines (except for possible unintended leakage current, which is typically negligible). Several exemplary embodiments of the switching device 400 will now be described in more detail.

[0066] Figure 5A This is a circuit diagram of an example switching device 500 with a capacitor bridge, based on the examples disclosed herein. The switching device 500 can be used to implement... Figure 4 Switching device 400 and Figure 2CThe switching device 272 is included. In some instances, the switching device 500 includes a primary transistor branch 510 and a circuit branch 530. For example... Figure 5A As shown, primary transistor branch 510 includes multiple primary transistors 510A to 510E connected in series. Specifically, the drain terminal of primary transistor 510A is connected to the source terminal of the next primary transistor 510B, the drain terminal of primary transistor 510B is connected to the source terminal of the next primary transistor 510C, and so on. The source terminal of end transistor 510A is connected to the second conductive line 508, and the drain terminal of the other end transistor 510E is connected to the first conductive line 518. The control terminals of the multiple primary transistors 510A to 510E in branch 510 are connected together and receive a primary control signal V. gmain Therefore, in Figure 5A In this circuit, the control terminals of primary transistors 510A to 510E are connected together to form the control terminal 520 of the switching device 500, which receives the primary control signal V. gmain .

[0067] Figure 5A The circuit branch 530 is also shown for reducing or eliminating electrical stress on primary transistors 510A to 510E. Specifically, circuit branch 530 includes multiple circuit elements, such as capacitors 530A to 530E (also denoted as C1 to C5). Each of capacitors 530A to 530E is connected in parallel to the corresponding primary transistor 510A to 510E. For example, the two terminals of capacitor 530A are connected to the drain and source terminals of primary transistor 510A, respectively; the two terminals of capacitor 530B are connected to the drain and source terminals of primary transistor 510B, respectively, and so on. Capacitors 530A to 530E are connected in series and form a capacitor bridge. One terminal of one end capacitor 530E (e.g., C5) is connected to the first conductive line 518; one terminal of the other end capacitor 530A is connected to the second conductive line 508. Thus, the capacitor bridge formed by capacitors 530A to 530E is coupled between the first conductive line 518 and the second conductive line 508.

[0068] A capacitor bridge formed by multiple capacitors 530A to 530E is configured to provide a gradient voltage level between the first conductive line 518 and the second conductive line 508, such that the drain-source voltage of the multiple primary transistors 510A to 510E is limited to a maximum allowable value. Specifically, if the first conductive line 518 (e.g., a global word line) has a voltage of 25V and the second conductive line 508 (e.g., a local word line) has a voltage of 0V, then when the switching device 500 is turned off (e.g., the primary control signal V applied to the primary control terminal 520), the voltage will be limited. gmainWhen the voltage is 0V, the voltage difference between the primary transistor branches 510 is therefore 25V. Through the capacitor bridge 530, capacitors 530A to 530E can be rapidly charged using this voltage difference. Correspondingly, the internal nodes (e.g., nodes N1 to N4) between the primary transistors 510A to 510E can be rapidly charged by capacitors 530A to 530E. The charging of the internal nodes therefore no longer depends on the leakage current flowing through the primary transistors 510A to 510E (because the transistors are turned off). Therefore, during the voltage ramp-up, the voltage of the internal nodes N1 to N4 can follow the voltage change of the first conductive line 518. This is in Figure 5B The Chinese version explains this more clearly.

[0069] Figure 5B It is based on the examples disclosed in this article. Figure 5A The example switch device 500 shown in the image has internal nodes N1 to N4 voltage curves during the ramp-up of the first conductive line (e.g., a global word line). Figure 5B As shown, due to the capacitor bridge 530, during a ramp-up (e.g., from 0V to 25V), the voltages of internal nodes N1 to N4 can quickly follow the voltage of the first conductor 518. As described above, this is achieved only through the primary transistor and without other circuitry (such as...). Figure 5A The capacitor bridge shown in the diagram allows the charging of internal nodes N1 to N4 to rely solely on the leakage current flowing through the primary transistor. This leakage current is very small (in the picoamp range), and therefore internal nodes N1 to N4 cannot quickly follow changes in the first or second conductors 518 and 508. By using... Figure 5A The capacitor bridge 530 shown in the figure can quickly follow the voltage of the first and / or second conductive lines during ramp-up or ramp-down, thereby eliminating the high electrical stress imposed on the drain-source terminals of the primary transistors 510A to 510E. Figure 5C This is a graph showing the drain-source voltage of the primary transistors 510A to 510E in the switching device 500 according to the examples disclosed herein under dynamic conditions. (See also...) Figure 5C The diagram shows the drain-source voltages (by V) of all primary transistors 510A to 510E under dynamic conditions. DS-AC (This indicates that) the voltage can be limited to below the maximum permissible drain-source voltage (V). DS_max (It can be a value such as 6V).

[0070] In some instances, the capacitance of each of the multiple capacitors 530A to 530E is sized such that the drain-source voltage of the primary transistors 510A to 510E is limited to a maximum permissible value (e.g., 6V) during the voltage ramp-up or ramp-down of the first conductor 518. For example, the capacitance of each of the capacitors 530A to 530E is configured to be greater than the capacitance of the internal nodes N1 to N4, but less than the capacitance of the second conductor 508 (e.g., a local word line). This configuration of the capacitors allows for rapid charging of the internal nodes N1 to N4 to follow the ramp-up or ramp-down of the first conductor 518 (e.g., in real-time or with minimal delay, which does not result in high electrical stress exceeding permissible values). Simultaneously, the capacitance of the capacitors 530A to 530E does not significantly increase the parasitic capacitance of the local word line to avoid increasing (or significantly increasing) the total ramp-up or ramp-down time of the second conductor 508 when the switching device 500 is turned on. In one instance, the selection of capacitor values ​​may follow these rules: 1) Any of capacitors C1 through C5 needs to be significantly smaller than the local word line capacitance (e.g., more than 10 times smaller). Otherwise, additional capacitance could cause a significant delay in voltage ramping on the local word lines of the selected block. 2) Any of capacitors C1 through C5 needs to be significantly larger than the parasitic capacitance at the corresponding internal nodes N1 through N4 and the surrounding bias network (e.g., 10 times larger). The bias network includes any electrical nodes connected to the voltage source. Electrical nodes may be coupled to nodes N1 through N4 of the capacitor ladder, including capacitors C1 through C5, thereby increasing the stray capacitance that can affect the voltage bias of nodes N1 through N4. For example, the upper and lower levels (e.g., upper and lower rows of memory cells) of a selected level in the selected block may have different voltage biases than the selected level (e.g., selected rows of memory cells). In some instances, each of the internal nodes N1 through N4 in the selected level may be coupled to its corresponding node in the lower and / or upper levels of the selected block. Coupling capacitance is a function of the geometry used (e.g., the physical size of the node) and the material.

[0071] If the capacitance values ​​of capacitors C1 to C5 do not meet the above rules, then the capacitor ladder (e.g., formed by C1 to C5) may not function properly and may distribute high voltage on the global word lines. When the capacitance values ​​of each of capacitors C1 to C5 are selected accordingly to have the above range, the smaller the capacitance value, the better, because the area of ​​the capacitor and its value affect the load on the global word lines (and in turn, power and performance) (especially because of all unselected blocks). Selected blocks have little effect on the load because the terminals of capacitors C1 to C5 are shorted by a switching device that is turned on when the block is selected. It should be understood that in Figure 5AIn this diagram, although primary transistor branch 510 is shown to have five primary transistors, any number of primary transistors can be used (e.g., two, three, four, five, six, etc.). The number of primary transistors depends on the maximum possible voltage difference exposed to the switching device and the characteristics of the transistors (e.g., width, length, material, etc.). Similarly, any number of capacitors (not limited to five) can be used to form circuit branch 530. Furthermore, although one primary transistor branch 510 is shown, more branches can be used (as described below). Similarly, circuit branch 530 can use multiple capacitor branches.

[0072] Figures 6A to 6C These are circuit diagrams of other examples of switching devices 600A to 600C disclosed herein, which have one or more secondary transistor branches used as circuitry for reducing or eliminating the high electrical stress imposed on the primary transistor. (Refer to...) Figure 6A In this embodiment, there are multiple primary transistor branches 610, 612, 614 and 616. Figure 6A Each of the primary transistor branches 610, 612, 614 and 616 shown has a plurality of primary transistors connected in series, which may be substantially the same as or similar to the primary transistors in the primary transistor branch 510 described above. Figure 6A Each of the primary transistor branches 610, 612, 614, and 616 shown is coupled in parallel between the first conductive line 618 and the second conductive line 608. Furthermore, corresponding primary transistors spanning multiple primary transistor branches 610, 612, 614, and 616 are connected in parallel to form multiple groups of corresponding primary transistors. For example... Figure 6A As shown, for example, primary transistors spanning all branches 610, 612, 614, and 616 directly connected to the first conductive line 618 form group 622A. Within group 622A, the primary transistors are connected in parallel. Similarly, the primary transistors in the next group 622B are connected in parallel. And primary transistors in other groups can similarly be formed across primary transistor branches 610, 612, 614, and 616.

[0073] Figure 6AThe switching device 600A also includes a circuit branch 630. As shown, the circuit branch 630 includes a branch of secondary transistors 630A to 630E connected in series. The secondary transistors 630A to 630E are coupled between a first conductive line 618 and a second conductive line 608. Each secondary transistor in the secondary transistor branch 630 is connected in parallel to a corresponding primary transistor 622 in a corresponding group. For example, secondary transistor 630A is connected in parallel to a group of primary transistors 622A. Therefore, the drain of secondary transistor 630A is connected to all the drains of the primary transistors in group 622A; and the source of secondary transistor 630A is connected to all the sources of the primary transistors in group 622A. The control terminal of secondary transistor 630A is connected to a gradient control signal V. g4 Instead of the primary control signal V gmain Similarly, secondary transistor 630B is connected in parallel to primary transistor group 622B, and the control terminal of secondary transistor 630B is connected to another gradient control signal V. g3 ; and so on. Therefore, such as Figure 6A As shown, the control terminals of secondary transistors 630A to 630E are each connected to different gradient control signals (V, V ... g4 To V g0 On the other hand, the control terminals of multiple primary transistor branches 610, 612, 614, and 616 are all connected together to form the control terminal 620 of the switching device 600A. The control terminal 620 receives the primary control signal V. gmain Therefore, the multiple primary transistor branches 610, 612, 614, and 616 can depend on the primary control signal V. gmain And to connect or disconnect.

[0074] Next, refer to Figure 6A and Figure 6D Both are used to describe the operation of the 600A switching device. Figure 6D It is based on the examples disclosed in this article. Figure 6A The example switching device 600A (and devices 600B and 600C, as described below) is shown in the diagram, illustrating voltage curves for internal nodes N1 to N4 during the ramp-up of the first conductive line 618 (e.g., a global word line). For illustrative purposes and simplicity, the global word line and the first conductive line are used interchangeably herein; and the local word line and the second conductive line are used interchangeably. However, it should be understood that the first and second conductive lines may, but are not necessarily, be the global word line and the local word line, respectively. Figure 6D In the diagram, the horizontal axis represents time t and the vertical axis represents the voltage value V. For example... Figure 6A and 6D As shown in the diagram, the control terminal 620 of the switching device 600A receives the primary control signal V. gmainIf the switching device 600A will turn off (or remain off), then the primary control signal V... gmain It can be at 0V. Therefore, the primary transistors in branches 610, 612, 614, and 616 are all turned off to decouple the first conductive line 618 (e.g., the global word line) from the second conductive line 618 (e.g., the local word line). This is for the case where the primary transistor is an NMOS transistor. If it is a PMOS transistor, then the primary control signal V... gmain A sufficiently high voltage should be available to turn off the PMOS transistor.

[0075] Turn Figure 6A The operation of secondary transistors 630A to 630E shown in the figure is such that each of these secondary transistors 630A to 630E receives a gradient control signal V at its control terminal (e.g., the gate terminal of the transistor). g4 To V g0 .like Figure 6A and 6D As shown in the diagram, the first gradient control signal V g0 The control terminal of the secondary transistor 630E is applied; the second gradient control signal V g1 The control terminal of the secondary transistor 630D is applied; and so on. In this way, the gradient control signal V... g0 To V g4 Apply to the corresponding secondary transistors 630E to 630A. For example... Figure 6D As shown in the figure, the gradient control signal V g0 To V g4 It can be configured to have gradually increasing voltage values. As an example, assume there is... Figure 6A The diagram shows five secondary transistors 630A to 630E, and the voltage difference between the first conductive line 618 and the second conductive line 608 is 25V. Therefore, the first gradient control signal V... g0 The voltage value is set to approximately equal to the primary control signal V. gmain The voltage value (e.g., V) g0 and V gmain Both are at approximately 0V). Gradient control signal V g1 V g2 V g3 and V g4 The voltage values ​​can be set to approximately 5V, 10V, 15V, and 25V, respectively. This is because the gradient control signal V applied to the control terminal (e.g., the gate) of the secondary transistor 630E... g0 The voltage is at 0V, so the secondary transistor 630E is turned off. Therefore, the entire secondary transistor branch 630 is also turned off, thus isolating the first conductive line 618 from the second conductive line 608 (therefore, when the primary control signal V...). gmainWhen the value is low, the switching device 600A remains off. On the other hand, other gradient control signals V g1 To V g4 These secondary transistors are set to different values, which are approximately threshold voltages higher than the voltage of the corresponding internal nodes. Therefore, these secondary transistors can be configured to operate at the on / off boundary region (e.g., almost not on or almost not off). Thus, these secondary transistors can generate cascaded voltage limits for each of the internal nodes N1 to N4 and therefore limit the drain-source voltage of the corresponding primary transistors in the respective groups (e.g., 622A, 622B, etc.). Simultaneously, because these secondary transistors 630A to 630D are at the on / off boundary region, they can conduct current much faster than leakage current alone. Therefore, internal nodes N1 to N4 can be charged rapidly. Thus, secondary transistors 630A to 630E reduce or eliminate high electrical stress even under dynamic conditions (e.g., ramping up the first conductive line 618) while keeping the switching device 600A off (when the primary control signal V...). gmain and V g0 Both are low (when the switching device 600A is turned off or kept off).

[0076] Figure 6E Based on the internal nodes N1 to N4 of the example disclosed herein, the primary control signal V is used to control the primary transistor. gmain and for control Figure 6A The gradient control signal V of the secondary transistor in the example switching device 600A shown in the figure. g0 To V g4 Voltage curves during programming, programming verification, and read operations. Figure 6E The left side shows the voltage curve when the memory block is not selected, causing the 600A switching device to be turned off. Figure 6E The right side shows the voltage curve when the memory block is selected, causing the 600A switching device to turn on. Figure 6E In the diagram, the horizontal axis represents time t and the vertical axis represents the voltage value V. Figure 6E In this document, for illustrative purposes and for simplicity, a global word line is used as an example of the first conductive line 618 of the switching device 600A; a local word line is used as an example of the second conductive line 608; and the switching device 600A is used to select and deselect memory blocks. The switching device 600A operates during the programming, programming verification, and reading operations of the memory blocks.

[0077] refer to Figure 6A and 6E Both, during programming, programming verification, or read operations, for unselected memory blocks (i.e., when the switching device 600A is turned off or held off), the global word line slopes from, for example, 0V to 25V; and the gradient control signal V g0 To V g4The first gradient control signal V is applied to secondary transistors 630E to 630A respectively. g0 Set to 0V, and the primary control signal V gmain The same applies. Therefore, the primary transistors in branches 610, 612, 614, and 616 are turned off, and the secondary transistor 630E (receiving V at its control terminal) is also turned off. g0 The global word line is also turned off. Therefore, the global word line is not electrically connected to the local word line (except through a negligible leakage current path), thereby isolating the global word line from the local word line. Therefore, programming / verification / read operations are not performed on unselected memory blocks.

[0078] As mentioned above Figure 6A As described in the text, other gradient control signals V g1 To V g4 The gradient control signal V is applied to the other secondary transistors 630D to 630A respectively. g1 To V g4 Approximately set to a threshold voltage V higher than the voltage of internal nodes N1 to N4. th Therefore, these secondary transistors 630D to 630A can be configured to operate at the on or off boundary (e.g., almost not on or almost not off). Thus, these secondary transistors can generate cascaded voltage limits for each of the internal nodes N1 to N4 and therefore limit the drain-source voltage of the corresponding primary transistors in the respective groups (e.g., 622A, 622B, etc.). Simultaneously, because they operate at the on or off boundary region, they can conduct current much faster than when only leakage current is present. Therefore, they can charge the internal nodes N1 to N4 much faster. Therefore, during programming / verification / read operations, secondary transistors 630A to 630E reduce or eliminate high electrical stress even under dynamic conditions (e.g., when the global word line ramps up), while keeping the switching device 600A off (when the primary control signal V...). gmain (When the device is low or kept low to shut off device 600A). Figure 6E In this context, when the global word line voltage slopes down from, for example, 25V to 0V, the voltages of internal nodes N1 to N4 also slope down to 0V. Consequently, the drain-source voltages of all transistors (primary or secondary) are at 0V or have no difference or minimal difference.

[0079] Turn Figure 6E On the right side, during programming / verification / read operations, if a memory block is selected to perform such operations, then the primary control signal V... gmain It can ramp up from, for example, 0V to a specific voltage value greater than 25V. The global word line can also ramp up from, for example, 0V to 25V. Gradient control signal V g0 To V g4The gradient control signal remains the same as when the memory block is not selected. In other words, the gradient control signal V... g0 To V g4 No changes are needed, regardless of whether the memory block is selected. This is because the primary control signal V... gmain The voltage ramps up to a high value, so all the primary transistors in branches 610, 612, 614, and 616 of the switching device 600A are turned on. Therefore, the switching device 600A is turned on to select the memory block and electrically connect the global word line to the local word line. In other words, the voltage of the local word line ramps up from, for example, 0V to approximately 25V (or approximately equal to the global word line minus any drain-source voltage drop caused by the primary transistors of the switching device 600A). Internal nodes N1 to N4 are also pulled up to a high voltage level (e.g., approximately 25V minus any drain-source voltage drop caused by the primary transistors of the switching device 600A). Thus, when the memory block is selected and the switching device 600A is turned on during programming, program verification, or read operations, all the primary transistors in the switching device 600A have no drain-source voltage difference or a very small drain-source voltage difference, even under dynamic conditions (e.g., when the global word line ramps up). Similarly, the secondary transistor 630 has no voltage difference or a very small voltage difference. Therefore, no or minimal electrical stress is applied to the switching device 600A.

[0080] Figure 6F Based on the internal nodes N1 to N4 of the example disclosed herein, the primary control signal V is used to control the primary transistor. gmain and used for Figure 6A The gradient control signal V of the secondary transistor in the example switching device 600A shown in the figure. g0 To V g4 Voltage curve during the erase operation. Figure 6F The left side shows the voltage curve when the memory block is not selected, causing the 600A switching device to be turned off. Figure 6F The right side shows the curve when the memory block is selected, causing the switching device 600A to be turned on. Figure 6F The left and right sides of the image show the voltage curves of various signals and internal nodes during an erase operation. Therefore, some signals may have voltage values ​​opposite to those during programming, program verification, or read operations. For example, during an erase operation, if the memory block is not selected, the global word line voltage remains at 0V, while the local word line rises to a sufficiently high value (e.g., 25V). These values ​​are opposite to the voltage values ​​of the global and local word lines during programming, program verification, or read operations.

[0081] exist Figure 6F In the diagram, the horizontal axis represents time t and the vertical axis represents the voltage value V. Figure 6FIn this illustration, for the sake of simplicity, a global word line is used as an example of the first conductive line 618 of the switching device 600A; a local word line is used as an example of the second conductive line 608; and the switching device 600A is used to select and deselect memory blocks. The switching device 600A operates during the erase operation of the memory block.

[0082] refer to Figure 6A and 6F During the erase operation, for unselected memory blocks (i.e., when switching device 600A is off), the local word line transitions from, for example, 0V to 25V. Gradient control signal V g0 To V g4 Applications were made to secondary transistors 630E through 630A, respectively. However, with Figure 6E In contrast, the gradient control signal V used in the erasure operation g0 To V g4 The voltage value has changed (e.g., compared to) Figure 6E The voltage values ​​shown in the image are the opposite of those used for programming / verification / reading operations. Specifically, during the erase operation, the gradient control signal V... g4 Set to 0V, and the primary control signal V gmain The same. Therefore, because the primary control signal V gmain With the voltage set to 0V, the primary transistors in branches 610, 612, 614, and 616 of the switching device 600A are turned off, and the secondary transistor 630A is also turned off. Therefore, the local word lines are not electrically connected to the global word lines (except through some negligible leakage current paths), thereby isolating the local word lines from the global word lines. Consequently, the erase operation is not performed on unselected memory blocks.

[0083] As mentioned above Figure 6A As described in the text, other gradient control signals V g0 To V g3 This is applied to the other secondary transistors 630E to 630B, respectively. For example... Figure 6E As shown in the figure, the gradient control signal V g0 To V g3 Approximately set to a threshold voltage V higher than the voltage of internal nodes N1 to N4. thTherefore, these secondary transistors 630E to 630B can be configured to operate at the on or off boundary regions (e.g., almost not on or almost not off). Thus, these secondary transistors 630E to 630B can generate cascaded voltage limits for each of the internal nodes N1 to N4 and thus limit the drain-source voltage of the corresponding primary transistors in the respective groups (e.g., 622B and other corresponding groups). Simultaneously, because the secondary transistors 630E to 630B are configured to operate at the on or off boundary regions, they can conduct current much faster than using only leakage current. Therefore, internal nodes N1 to N4 can be rapidly charged under dynamic conditions (e.g., when local word lines ramp up). Therefore, during erase operations, the secondary transistors 630A to 630E reduce or eliminate high electrical stress even under dynamic conditions, while keeping the switching device 600A off (when the primary control signal V...). gmain (For low-voltage shutdown device 600A). Figure 6F In this context, when the local word line voltage slopes down from, for example, 25V to 0V, the voltages of internal nodes N1 to N4 also slope down to approximately 0V. Therefore, after the local word line voltage slopes down, the drain-source voltages of all transistors (primary or secondary) are at approximately 0V or are indistinguishable.

[0084] Turn Figure 6E On the right side, during the erase operation, if a memory block is selected to perform the erase operation, then the primary control signal V... gmain The voltage can be gradually increased from, for example, 0V to a specific voltage value high enough to turn on the primary transistor. Gradient control signal V g0 To V g4 The gradient control signal is held to be the same as when the memory block is not selected. In other words, the gradient control signal V... g0 To V g4 No changes are needed, regardless of whether the memory block is selected. This is because the primary control signal V... gmain The gradient is raised to a sufficiently high value for the erase operation, so the primary transistors in branches 610, 612, 614, and 616 of the switching device 600A are all turned on. Gradient control signal V g4 The switch also ramps up to turn on secondary transistor 630A. Therefore, switching device 600A is turned on to select the memory block and electrically connects the global word line to the local word line. Thus, during the erase operation, the voltages of both the local and global word lines are at 0V. Internal nodes N1 to N4 are also pulled down to 0V. Therefore, when the memory block is selected and switching device 600A is turned on during the erase operation, all primary transistors in switching device 600A have no drain-source voltage difference or a very small drain-source voltage difference. Similarly, secondary transistor 630 has no voltage difference or a very small voltage difference. Therefore, no or minimal electrical stress is imposed on the primary or secondary transistors in switching device 600A.

[0085] Return to reference Figure 6B This illustrates another example, switching device 600B. Device 600B is essentially the same as... Figure 6A The device shown is the same as the 600A, except that the secondary transistor branch 630 is physically placed among multiple primary transistor branches 610, 612, 614, and 616. Specifically, in... Figure 6A In the switching device 600A, the secondary transistor branch 630 is physically placed on one side (e.g., the right side) of the primary transistor branches 610, 612, 614, and 616. The physical locations of the primary and secondary transistors refer to their positions in the physical layout on a photomask or semiconductor chip. Figure 6B In this configuration, the secondary transistor branch 630 is physically positioned in the middle of the overall physical layout of the switching device 600B (e.g., branch 630 is positioned in the middle, with two primary transistor branches on either side). This physical placement of the secondary transistor branch 630 further reduces the resistance of the conductive lines or connections between the transistors and thus improves the current distribution within the switching device 600B. The primary control signal V of the switching device 600B during programming / verification / reading / erasing operations... gmain Gradient control signal V g0 To V g4 The voltage curve is essentially the same as described above regarding device 600A (e.g., in conjunction with...). Figures 6D to 6F These descriptions are the same and therefore will not be repeated.

[0086] Figure 6C Another example of a switching device, 600C, is described. Compared to devices 600A or 600B, device 600C includes multiple secondary transistor branches (e.g., three such branches 630, 631, and 632 are described). Similar to devices 600A and 600B, in device 600C, each of the multiple secondary transistor branches includes multiple secondary transistors connected in series. Corresponding secondary transistors across the multiple secondary transistor branches are connected in parallel to form multiple groups of corresponding secondary transistors. Each group of the multiple groups of secondary transistors is connected in parallel to a primary transistor of the corresponding group. For example, as... Figure 6C As shown, secondary transistors 630A, 631A, and 632A in branches 630, 631, and 632 respectively form a first group of secondary transistors. The first group of secondary transistors is connected in parallel with the primary transistor group 622A. Other secondary transistors can form similar groups and be connected to the primary transistors of corresponding groups, such as... Figure 6C It is displayed in the middle.

[0087] In some instances, multiple groups of secondary transistors are configured to receive gradient control signals V with different voltage levels for each of the multiple groups of secondary transistors. g0 To Vg4 For example, the secondary transistors of the first group, including transistors 630A, 631A, and 632A, receive a gradient control signal V at the control terminal. g4 The secondary transistors 630B, 631B, and 632B in the next group receive the gradient control signal V at the control terminal. g3 And so on. The physical layout of the switching device 600C can be configured such that multiple secondary transistor branches (630, 631, and 632) are physically interleaved with multiple primary transistor branches (610 to 617). For example... Figure 6C As shown, secondary transistor branch 630 is physically placed on the far left, with primary transistor branches 610, 612, 614, and 616 placed to the right of secondary transistor branch 630; secondary transistor branch 631 is placed to the right of primary transistor branches 610, 612, 614, and 616; and so on. This physical interleaving of secondary and primary transistor branches reduces the resistance of the conductive lines or connections between transistors and thus improves the current distribution within the switching device 600C. It also enhances the reliability of the switching device 600C by using more branches. The primary control signal V during programming / verification / reading / erasing operations of the switching device 600C... gmain Gradient control signal V g0 To V g4 The voltage curve is essentially the same as described above regarding device 600A (e.g., in conjunction with...). Figures 6D to 6F These descriptions are the same and therefore will not be repeated. For example, in device 600C, the primary control signal V gmain Connected to all primary transistors; and gradient control signal V g0 To V g4 Connected to the corresponding secondary transistors in branches 630, 631, and 632, such as Figure 6C It is displayed in the middle.

[0088] Figure 7A This is a circuit diagram of an example switching device 700 that receives gradient control signal 723 according to the examples disclosed herein. Switching device 700 may be configured to include multiple primary transistor branches 710, 712, 714, and 716, which are substantially the same as the primary transistor branches 610, 612, 614, and 616 of switching device 600A described above. The differences between switching device 700 and switching device 600A are: (1) switching device 700 does not include any secondary transistors or capacitor bridges; and (2) switching device 700 does not receive primary control signals from all primary transistors, but instead receives gradient control signal 723 (e.g., Vg0 to Vg4).

[0089] Specifically, Figure 7AThe switching device 700 shown is configured to controllably connect a first conductive line 718 (e.g., a global word line of a memory block) to a second conductive line (e.g., a local word line of a memory block) or decouple the first conductive line 718 from the second conductive line. The switching device 700 includes a plurality of primary transistor branches 710, 712, 714, and 716. Similar to the switching device 600A, each of the plurality of primary transistor branches 710, 712, 714, and 716 includes a plurality of primary transistors connected in series. Taking branch 710 as an example, it includes five primary transistors 710A to 710E connected in series (e.g., the drain terminal of one transistor can be connected to the source terminal of the next transistor in the branch, the source terminal of the first primary transistor 710A is connected to the second conductive line 708, and the drain terminal of the last primary transistor 710E is connected to the first conductive line 718).

[0090] Still referencing Figure 7A The corresponding primary transistors across multiple primary transistor branches 710, 712, 714, and 716 are connected in parallel to form multiple groups 722A, 722B, ..., 722E of the corresponding primary transistors. This is essentially the same as... Figure 6A The switching device 700 is the same as the switching device 600A shown in the figure. However, unlike the switching device 600A, the control terminals of the multiple groups of primary transistors 710A to 710E in the switching device 700 are configured to receive gradient control signals 720A to 720E (e.g., V). g0 To V g4 (instead of the primary control signal V) gmain .like Figure 7A As shown in the diagram, the control terminal of the primary transistor in group 722A receives the gradient control signal V. g0 The control terminal of the primary transistor in group 722B receives the gradient control signal V. g1 And so on.

[0091] The operation and voltage profiles associated with the various terminals / nodes of the switching device 700 are then used. Figure 7A and 7B To describe. Figure 7B It is based on the examples disclosed in this article. Figure 7A The example switching device 700 is shown in the diagram, illustrating the voltage curves of internal nodes N1 to N4 during the global word line ramp-up. For illustrative purposes and simplicity, the global word line and the first conductive line are used interchangeably herein; and the local word line and the second conductive line are used interchangeably here. However, it should be understood that the first and second conductive lines may, but are not necessarily, global and local word lines, respectively. Reference Figure 7B The horizontal axis represents time t and the vertical axis represents voltage value V. For example... Figure 7A and 7BAs shown in the diagram, unlike switch 600A, switch 700's control terminals 720A to 720E receive gradient control signals 723 (e.g., V). g0 To V g4 In other words, different groups of primary transistors (e.g., 722A and 722B) receive different gradient control signals 723.

[0092] Each of the primary transistors in these groups (e.g., 722A to 722E) receives a different gradient control signal 723 (e.g., V) at its respective control terminal 720 (e.g., the gate terminal of the transistor). g0 To V g4 ).like Figure 7A and 7B As shown in the diagram, the first gradient control signal V g0 The control terminal 720A of the primary transistor group 722A is applied; the second gradient control signal V g1 The control terminal 720B of the primary transistor group 722B is applied; and so on. In this way, the gradient control signal V... g0 To V g4 The primary transistors 722 of the corresponding group are applied in the device 700. Gradient control signal V g0 To V g4 They have gradually increasing voltage values. As an example, assume there exists... Figure 7A The diagram shows five primary transistors, and the voltage difference between the first conductive line 718 and the second conductive line 708 is 25V. Therefore, the first gradient control signal V... g0 The voltage value is set to approximately 0V. Gradient control signal V g1 V g2 V g3 and V g4 The voltage value can be set to approximately 5V, 10V, 15V, and 25V. This is because the gradient control signal V applied to the control terminal 720A (e.g., the gate) of the primary transistor 722A in the first group... g0 At 0V, the primary transistor 722A of the first group is turned off. Therefore, each of the primary transistor branches 710, 712, 714 and 716 is also turned off, thereby isolating the first conductive line 718 from the second conductive line 708 (thus the switching device 700 is turned off).

[0093] On the other hand, reference Figure 7B Other gradient control signals V g1 To V g4 Set to different values, which are approximately the threshold voltages (V) higher than the voltages of the corresponding internal nodes N1 to N4. th Therefore, the gradient control signal V is received. g1 To V g4The primary transistors 722B to 722E of these groups can be configured to operate at the boundary between on and off (e.g., almost not on or almost not off). Therefore, the primary transistors of these groups (e.g. Figure 7A Groups 722B to 722E can generate cascaded voltage limits for each of the internal nodes N1 to N4, and thus limit the drain-source voltage of the corresponding primary transistors in the respective groups (e.g., 722A, 722B, etc.). Simultaneously, because the primary transistors 722B to 722E of these groups operate at the on- or off boundary, they can conduct current much faster than when only leakage current is present. Therefore, internal nodes N1 to N4 can charge rapidly under dynamic conditions (e.g., when the global word line ramps up). Thus, primary transistor branches 710, 712, 714, and 716 reduce or eliminate high electrical stress under the control of gradient control signals, while keeping switching device 700 off (when the first gradient control signal V...). g0 (For low-frequency shutdown device 700).

[0094] Figure 7C It is based on the examples disclosed in this article. Figure 7A The example switching device 700 shown in the image has internal nodes N1 to N4 of the primary transistor group and gradient control signal V. g0 To V g4 Voltage curves during programming, programming verification, and read operations. Figure 7C The left side shows the voltage curve when the memory block is not selected, causing the switching device 700 to be turned off. Figure 7C The right side shows the curve when the memory block is selected, causing the switch 700 to be turned on. Figure 7C In the diagram, the horizontal axis represents time t and the vertical axis represents the voltage value V. Figure 7C In this document, for illustrative purposes and for simplicity, a global word line is used as an example of the first conductive line 718 of the switching device 700; a local word line is used as an example of the second conductive line 708; and the switching device 700 is used to select and deselect memory blocks. The switching device 700 operates during the programming, programming verification, and reading operations of the memory blocks.

[0095] refer to Figure 7A and 7C Both, during programming, programming verification, or read operations, for unselected memory blocks (e.g., when switching device 700 is off), the global word line ramps from, for example, 0V to 25V, and the gradient control signal V... g0 To V g4 The primary transistors 722A to 722E of the corresponding groups are respectively applied. The first gradient control signal V... g0The voltage is set to 0V. Therefore, the primary transistor group 722A in branches 710, 712, 714, and 716 is turned off. Consequently, the global word line is not electrically connected to the local word line (except through some negligible leakage current paths), thereby isolating the global word line from the local word line. Therefore, programming / verification / read operations are not performed at unselected memory blocks.

[0096] As mentioned above Figure 7A As described in the text, other gradient control signals V g1 To V g4 The gradient control signal V is applied to the primary transistors 722B to 722E in other groups, respectively. g1 To V g4 Approximately set to a threshold voltage V higher than the corresponding voltages of internal nodes N1 to N4. th Therefore, the primary transistors 722B to 722E of these groups can be configured to operate at the on or off boundary (e.g., almost not on or almost not off). Thus, these secondary transistors can generate cascaded voltage limits for each of the internal nodes N1 to N4 and therefore limit the drain-source voltage of the corresponding primary transistor in the respective group (e.g., 722A, 722B, etc.). Simultaneously, the primary transistor groups 722B to 722E operate at the on or off boundary region, thus conducting current much faster than when only leakage current is present. Therefore, they can quickly charge the internal nodes N1 to N4. Therefore, during programming / verification / reading operations, the primary transistor groups 722A to 722E reduce or eliminate high electrical stress while keeping the switching device 700 off (when the first gradient control signal V...). g0 (For low-frequency shutdown device 700). Figure 7C In this scenario, when the global word line voltage slopes down from, for example, 25V to 0V, the voltages at internal nodes N1 to N4 also slope down to 0V. Consequently, the drain-source voltages of the primary transistors in all groups are at 0V or have no difference. As a result, no electrical stress is applied to these primary transistors.

[0097] Turn Figure 7C On the right side, during programming / verification / read operations, if a memory block is selected to perform such operations, the global word line can ramp up from, for example, 0V to 25V. Gradient control signal V g0 To V g4 It can also be ramped up to a sufficiently high voltage (e.g., >25V). Local word lines can also be ramped up to, for example, 25V or essentially the same as the global word line. Gradient control signal V g0 To V g4 It can be set to be higher than the local word line voltage by a threshold voltage (e.g., V). thThe voltage of the primary transistors in branches 710, 712, 714, and 716 of the switching device 700 is turned on. Therefore, the switching device 700 is turned on to select the memory block and electrically connect the global word line to the local word line. In other words, the voltage of the local word line is ramped up from, for example, 0V to approximately 25V (or approximately equal to the global word line minus any drain-source voltage drop caused by the primary transistors of the switching device 700). Internal nodes N1 to N4 are also pulled up to a high voltage level (e.g., approximately 25V minus any drain-source voltage drop caused by the primary transistors of the switching device 700). Therefore, when the memory block is selected and the switching device 700 is turned on during programming, program verification, or read operations, all primary transistors in the switching device 700 have no drain-source voltage difference or a very small drain-source voltage difference. Therefore, no or minimal electrical stress is imposed on the primary or secondary transistors in the switching device 700. Therefore, the gradient control signal V... g0 To V g4 Applying electrical stress directly to the primary transistor can also reduce or eliminate electrical stress without the need for secondary transistors or other circuit elements such as capacitors.

[0098] Figure 7D It is based on the examples disclosed in this article. Figure 7A The example switching device 700 shown in the image has internal nodes N1 to N4 of the primary transistor and a gradient control signal V. g0 To V g4 Voltage curve during the erase operation. Figure 7D The left side shows the voltage curve when the memory block is not selected and the switching device 700 is turned off. Figure 7D The right side shows the voltage curve when the memory block is selected and the switching device 700 is turned on. Figure 7D The left and right sides of the image show the voltage curves of various signals and internal nodes during an erase operation. Therefore, some signals may have voltage values ​​that are opposite to those during programming, program verification, or read operations. For example, during an erase operation, if the memory block is not selected, the global word line voltage remains at 0V, while the local word line voltage ramps up to a sufficiently high value (e.g., equal to or greater than 25V). These values ​​are opposite to the voltage values ​​of the global and local word lines during programming, program verification, or read operations.

[0099] exist Figure 7D In the diagram, the horizontal axis represents time t and the vertical axis represents the voltage value V. Figure 7D In this document, for illustrative purposes and for simplicity, a global word line is used as an example of the first conductive line 718 of the switching device 700; a local word line is used as an example of the second conductive line 708; and the switching device 700 is used to select and deselect memory blocks. The switching device 700 operates during the erase operation of the memory block.

[0100] refer to Figure 7A and 7D During the erase operation, for unselected memory blocks (i.e., when switching device 700 is off), the local word line transitions from, for example, 0V to 25V. Gradient control signal V g0 To V g4 Control terminals 720A to 720E are respectively applied to primary transistor groups 722A to 722E. However, with Figure 7C In contrast, the gradient control signal V used in the erasure operation g0 To V g4 The voltage value has changed (e.g., compared to) Figure 7C The voltage values ​​shown in the image are the opposite of those used for programming / verification / reading operations. Specifically, during the erase operation, the gradient control signal V... g4 Set to 0V. Therefore, because of the gradient control signal V g4 With the voltage set to 0V, the primary transistor group 722E in branches 710, 712, 714, and 716 of the switching device 700 is turned off. Therefore, the global word line is not electrically connected to the local word line (except through some negligible leakage paths), thereby isolating the local word line from the global word line. Consequently, the erase operation is not performed on unselected memory blocks.

[0101] As mentioned above Figure 7A As described in the text, other gradient control signals V g0 To V g3 The gradient control signal V is applied to the primary transistors 722A to 722D in other groups, respectively. g0 To V g3 Approximately set to a threshold voltage V higher than the corresponding voltages of internal nodes N1 to N4. th Therefore, the primary transistors 722A to 722D of these groups can be configured to operate at the on- or off boundary regions (e.g., almost not on or almost not off). Thus, the primary transistors 722A to 722D of these groups can generate cascaded voltage limits for each of the internal nodes N1 to N4, and thus limit the drain-source voltage of the primary transistors in the corresponding groups (e.g., 722A, 722B, etc.). Simultaneously, the primary transistor groups 722A to 722D operate at the on- or off boundary regions, and therefore can conduct current much faster than when only leakage current is present. Therefore, the internal nodes N1 to N4 can charge rapidly under dynamic conditions (e.g., when local word lines ramp up). Therefore, during erase operations, the primary transistor groups 722A to 722E use a predetermined gradient control signal V. g0 To V g4 To reduce or eliminate high electrical stress while keeping the switching device 700 off (when the gradient control signal V) g4 (For low-frequency shutdown device 700). Figure 7D In this scenario, when the local word line voltage slopes down from, for example, 25V to 0V, the voltages at internal nodes N1 to N4 also slope down to 0V. Therefore, after this local word line voltage slope, the drain-source voltages of all primary transistors are at 0V or show no difference. Consequently, after this local word line slope, there is no electrical stress or minimal electrical stress.

[0102] Turn Figure 7D On the right side, during the erase operation, if a memory block is selected to perform the erase operation, then the gradient control signal V... g0 To V g4 Full ramp up to a sufficiently high value (e.g., greater than or higher than the source voltage V of the primary transistors 722A to 722E in the corresponding group). th The primary transistors 722A to 722E in the corresponding groups of branches 710, 712, 714, and 716 of the switching device 700 are turned on. Therefore, the switching device 700 is turned on to select a memory block and electrically connect the global word line to the local word line. During the erase operation, the voltage of the global word line is set to 0V, thereby causing the local word line to also be at approximately 0V. Internal nodes N1 to N4 are also pulled down to 0V. Therefore, when the memory block is selected and the switching device 700 is turned on during the erase operation, all primary transistors in the switching device 700 have no drain-source voltage difference or a very small drain-source voltage difference. Figure 7D This means that during the erase operation, the drain-source voltage of the multiple primary transistors in each of branches 710, 712, 714, and 716 is limited to the maximum allowable value, regardless of whether the memory block is selected.

[0103] The above examples use gradient control signals to control the voltage applied to the control terminals of the primary or secondary transistors of the switching device. Figure 8 This is a block diagram illustrating an example gradient control signal generation circuit 800 according to the examples disclosed herein. The gradient control generation circuit 800 can be used to generate a gradient control signal V. g0 To V g4 To control the primary transistor (e.g.) Figures 7A to 7D The primary transistor in the switching device 700 shown above is an example. In some instances, the gradient control signal generation circuit 800 includes multiple multiplexers 820A to 820E (also referred to as MUX 820A to 820E). Each of the multiplexers 820A to 820E has two inputs and one output. For example, the MUX 820A has two inputs V. C0 and V SEL and an output V g0 The MUX 820B has two input V. C1 and V SEL and an output V g1And so on. Each MUX 820 also has a mux control signal (e.g., BlockSel) configured to control which input should be passed to the output. For example, if the gradient control signal V... g0 To V g4 If transistors 810A to 810E are supplied to the switching device, then the control signal BlockSel can be set to a first value (e.g., high), causing signal V... c0 To V c4 The signal is transmitted to the outputs of MUX 820A through 820E respectively. c0 To V c4 Then they are converted into gradient control signals V. g0 To V g4 (See Figure 6D , 6E (6F, 7C, and 7D). Transistors 810A to 810E can receive gradient control signals V. g0 To V g4 Any of the aforementioned primary or secondary transistors. If the mux control signal BlockSel is set to a second value (e.g., low), then the other input signal V of the MUX 820A to 820E... SEL It can be transmitted to the output. Input signal V SEL It can be set to any desired value. For example, it can be set to a sufficiently high value (e.g., greater than the voltage of the global word line) during programming / verification / read / erase operations to turn on all transistors (primary or secondary) of the selected memory block (see...). Figure 7C and 7D ).

[0104] The above description relating to the gradient control generation circuit 800 can be used to generate the gradient control signal V. g0 To V g4 To control the primary transistor (e.g.) Figures 7A to 7D The primary transistor in the switching device 700 shown in the image). Similar circuits can be configured to control secondary transistors (e.g., Figures 6A to 6F The secondary transistors in the switching devices 600A to 600C shown above are examples of this. For instance, for the switching devices 600A to 600C, the gradient control signal V is used to control the secondary transistors. gx (e.g. V) g0 To V g4 The signal can be similarly generated using a planar logic 830 (e.g., equal to V). Cx (output), while V gmainThe signal can be provided by a single multiplexer (not shown) driven by the “BlockSel” signal. The single multiplexer has two inputs, containing the VSEL value on the selected block and voltage ground (GND) or, in any case, a lower voltage available on the unselected block.

[0105] It should be understood that Figure 8 The circuit system represented in the block selector can be used to drive Figure 7A The diagram illustrates a conceptual circuit for the gate of the switching transistor in the arrangement shown. Other arrangements shown in other figures can be driven by similar circuit systems. For example, it might only require a unique gate control signal for each of the switching transistors, ranging from a voltage greater than the global word line voltage when the block is selected to 0V when the block is not selected. Figure 8 The planar logic 830 shown is used to switch between erase bias and all other conditions. Figure 6A The example multiplexer circuit illustrates the gate voltage of the secondary transistor in the arrangement shown. Therefore, when the block is under an erase operation, the multiplexer of the planar logic 830 can be configured to receive... Figure 6A The diagram shows the gate voltage of each of the secondary transistors 630A to 630E; and the multiplexer of the planar logic 830 can be configured to receive [data / data] when the block is in another operation (e.g., programming / reading / verification, etc.). Figure 6A The image shows the different gate voltages of each of the secondary transistors 630A to 630E.

[0106] It should be noted that the described techniques include possible implementations, and the operations and blocks can be rearranged, reordered, or otherwise modified, and other implementations are possible. Furthermore, portions from two or more of the methods can be combined.

[0107] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols referred to throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal can represent a signal bus, where the bus can have various bit widths.

[0108] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to a relationship between components that supports the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connection, or coupling) if any conductive path exists between them that can support the flow of signals between them at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connection, or coupling) may be open or closed based on the operation of the device containing the connected component. The conductive path between connected components may be a direct conductive path between the components, or it may be an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some instances, the flow of signals between connected components may be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0109] The term "coupling" (e.g., "electrical coupling") can refer to a condition that changes from an open-circuit relationship between components (where signals cannot currently be transmitted between components via conductive paths) to a closed-circuit relationship between components (where signals can be transmitted between components via conductive paths). If, for example, a component of a controller couples other components together, then the component triggers a change that allows signals to flow between other components via conductive paths that were previously not permitted to allow signals.

[0110] The term "isolation" refers to a relationship between components in which signals cannot currently flow between them. If there is an open circuit between components, then the components are isolated from each other. For example, if a switch positioned between two components is turned on, then the components separated by the switch are isolated from each other. If a controller isolates two components, then the controller causes a change that prevents signals from flowing between the components using previously permitted conductive paths.

[0111] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe the connection between conditional actions, conditional procedures, or parts of a procedure.

[0112] The term "in response to" can refer to a condition or action that occurs at least partially (if not entirely) as a result of a preceding condition or action. For example, a first condition or action may be performed and a second condition or action may occur at least partially as a result of the preceding condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions that occur after the first condition or action).

[0113] The devices discussed herein (including memory arrays) can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species, including (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0114] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "off" or "deactivated." In the above description, the primary and / or secondary transistors may be complementary metal-oxide-semiconductor (CMOS) transistors. In other embodiments, the primary and / or secondary transistors may be thin-film transistors (TFTs). Compared to planar CMOS transistors, a single TFT transistor may be more difficult to withstand high voltages and therefore requires the use of the techniques described above (e.g., using multiple TFTs with gradient control, capacitor ladders, etc.). Furthermore, for TFT transistors, a series of transistors does not require the same area as planar CMOS transistors. For example, a series of TFT transistors may be fabricated in the vertical direction (z-direction) or a dedicated layer may be built on a CMOS silicon wafer.

[0115] The descriptions presented herein, taken in conjunction with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" rather than "preferred" or "superior to other instances." "Detailed Description" contains specific details used to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concept of the described instances.

[0116] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by adding a hyphen after the reference numeral and a second numeral to differentiate similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0117] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor (e.g., processor 310 of FIG. 3), the functions can be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the described functions can be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions can also be physically located at various locations, including distribution such that portions of the functions are implemented at different physical locations.

[0118] As used herein (included in the claims), the word "or" in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0119] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure are possible, and that the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A switching device for controllably coupling a first conductive line to a second conductive line or decoupling the first conductive line from the second conductive line, the switching device comprising: One or more branches of the primary transistor, wherein: At least one of the one or more branches of the primary transistors comprises a plurality of primary transistors connected in series. The control terminals of the plurality of primary transistors are connected together and receive primary control signals, and The plurality of primary transistors are controllably switched based on the primary control signal to couple the first conductive line to the second conductive line or to decouple the first conductive line from the second conductive line; and One or more branches of the circuit, wherein: At least one of the one or more branches of the circuit includes a plurality of circuit elements connected in series, and Each of the plurality of circuit elements is connected in parallel to a corresponding primary transistor, and The plurality of circuit elements are configured to provide a gradient voltage level between the first conductive line and the second conductive line, such that the drain-source voltage of the plurality of primary transistors is limited to a maximum permissible value.

2. The switching device according to claim 1, wherein: The first conductive line is the global word line of the memory device; The second conductive line is a local word line of a memory block in the memory device; and The one or more branches of the primary transistor are coupled between the global word line and the local word line.

3. The switching device according to any one of claims 1 to 2, wherein: The series-connected circuit elements form a capacitor bridge comprising a series-connected capacitor bridge, and the capacitor bridge is coupled between the first conductive line and the second conductive line.

4. The switching device according to claim 3, wherein: Each of the plurality of capacitors is coupled in parallel to the corresponding primary transistor in the plurality of primary transistors.

5. The switching device of claim 4, wherein the capacitance of each of the plurality of capacitors is sized such that during a ramp-up or ramp-down of the voltage applied to the first conductive line, the drain-source voltage of the plurality of primary transistors is limited to the maximum permissible value.

6. The switching device according to claim 4, wherein the capacitance of each of the plurality of capacitors is: The capacitance is greater than the capacitance of the corresponding internal node between two adjacent primary transistors in the plurality of primary transistors; and It is less than the capacitance associated with the second conductive line.

7. The switching device according to any one of claims 1 to 2, wherein: The one or more branches of the primary transistor include multiple branches of the primary transistor; The corresponding primary transistors across the multiple branches of the primary transistor are connected in parallel to form multiple groups of corresponding primary transistors; The one or more branches of the circuit include one or more branches of secondary transistors; and The secondary transistors in each of the one or more branches of the secondary transistor are connected in series.

8. The switching device according to claim 7, wherein: The one or more branches of the secondary transistor include the first branch of the secondary transistor; Each secondary transistor of the first branch of the secondary transistor is connected in parallel to the corresponding primary transistor of the corresponding group; and The control terminal of the first branch of the secondary transistor is configured to receive multiple gradient control signals with different voltage levels for each stage of the first branch of the secondary transistor.

9. The switching device of claim 8, wherein the first branch of the secondary transistor is physically placed between the plurality of branches of the primary transistor.

10. The switching device according to claim 7, wherein: The one or more branches of the secondary transistor include the multiple branches of the secondary transistor. Each of the plurality of branches of the secondary transistor includes a plurality of secondary transistors connected in series. The corresponding secondary transistors of the multiple branches of the secondary transistor are connected in parallel to form multiple groups of corresponding secondary transistors. Each of the plurality of groups of secondary transistors is connected in parallel to the primary transistor of the corresponding group; and The secondary transistors of the plurality of groups are configured to receive gradient control signals with different voltage levels for each of the plurality of groups of secondary transistors.

11. The switching device of claim 10, wherein the plurality of branches of the secondary transistor are physically interleaved with the plurality of branches of the primary transistor.

12. The switching device according to claim 7, wherein the primary transistor or the secondary transistor is a thin-film transistor (TFT).

13. A switching device for controllably connecting a first conductive line to a second conductive line or decoupling the first conductive line from the second conductive line, the switching device comprising a plurality of branches of a primary transistor, wherein: Each of the plurality of branches of the primary transistors includes a plurality of primary transistors connected in series; The corresponding primary transistors across the multiple branches of the primary transistor are connected in parallel to form multiple groups of corresponding primary transistors; and The control terminals of the primary transistors in the plurality of groups are configured to receive gradient control signals such that the drain-source voltage of the plurality of primary transistors in each branch is limited to a maximum permissible value.

14. The switching device according to claim 13, wherein: The first conductive line is the global word line of the memory device; The second conductive line is a local word line of a memory block in the memory device; and The plurality of primary transistors in each of one or more branches of the primary transistors are coupled between the global word line and the local word line.

15. The switching device according to any one of claims 13 to 14, wherein the plurality of groups of primary transistors includes a first group, and the control terminals of the first group of primary transistors are configured to: Receive the first control signal from the gradient control signals, and The first conductive line is coupled to the second conductive line or decoupled from the second conductive line based on the first control signal and other control signals besides the gradient control signal.

16. The switching device of claim 15, wherein the control terminals of other groups of the plurality of groups of primary transistors are configured to: Receive the other control signals in the gradient control signals, wherein the other control signals have a voltage level that is approximately a threshold voltage higher than the voltage level of the corresponding internal node of the primary transistor.

17. The switching device according to any one of claims 13 to 14, wherein the primary transistor is a thin-film transistor (TFT).

18. A memory device comprising: Memory cell array, which is arranged into multiple memory blocks ； The switching device according to any one of claims 1 to 17, wherein the switching device is configured to select a memory block and deselect one or more other memory blocks.

19. The memory device of claim 18, further comprising a gradient voltage driver circuit system configured to generate a gradient control signal and provide the gradient control signal to the switching device.

20. A memory system comprising: processor; and A memory device coupled to the processor, the memory device being any of the memory devices according to claims 18 to 19.

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