Refreshing method and device of memory, electronic equipment, chip and storage medium
By dynamically selecting the DRAM refresh mode and choosing between single-bank or full-bank refresh mode based on service density, the problem that the fixed refresh mode in the existing technology cannot meet the needs of different service densities is solved, achieving a balance between performance and power consumption and improving the overall efficiency of the memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING X RING TECHNOLOGY CO LTD
- Filing Date
- 2025-12-12
- Publication Date
- 2026-04-17
AI Technical Summary
In existing technologies, the refresh mode of DRAM is fixed, which cannot meet the performance and power consumption requirements under different service densities.
The refresh mode is dynamically selected based on the service scenario of the memory. By determining whether the target scenario is low service density or high service density, the corresponding single memory cell or full memory cell refresh mode is adopted.
It achieves a balance between performance and power consumption under different service densities, improves the overall efficiency of memory, reduces the instruction scheduling overhead and timing coordination complexity of the controller, and reduces dynamic power consumption and resource overhead.
Smart Images
Figure CN121884897A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of computer technology, and more particularly to a method, apparatus, electronic device, vehicle, chip, and storage medium for refreshing a memory. Background Technology
[0002] Dynamic Random Access Memory (DRAM) relies on the charge of its gate capacitors to represent data bits. However, this charge decays continuously due to physical mechanisms such as dielectric leakage, PN junction reverse bias current, and subthreshold conduction, causing the storage voltage to degrade to an unrecognizable level within milliseconds. To prevent data loss, the memory must be refreshed periodically. Current technologies refresh DRAM using a fixed refresh pattern, which fails to meet operational requirements. Summary of the Invention
[0003] This disclosure provides a method, apparatus, electronic device, chip, and storage medium for refreshing memory, in order to solve the problem that DRAM refreshes according to a fixed refresh mode in related technologies, which cannot meet business requirements.
[0004] The technical solution disclosed herein is as follows: According to a first aspect of the present disclosure, a memory refresh method is provided, comprising: Determine that the memory service scenario is in a target scenario, wherein the target scenario is one of at least two service scenarios with different service densities; Based on the target scenario, determine the target refresh mode of the memory; The memory is refreshed based on the target refresh mode.
[0005] According to a second aspect of the present disclosure, a memory refresh apparatus is provided, comprising: The scenario determination module is configured to determine whether the memory service scenario is a target scenario, wherein the target scenario is one of at least two service scenarios with different service densities; The mode determination module is configured to determine the target refresh mode of the memory based on the target scenario. The refresh module is configured to refresh the memory based on the target refresh mode. (Memory refresh.)
[0006] According to a third aspect of the present disclosure, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the steps of the memory refresh method described in the first aspect of the present disclosure.
[0007] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided that stores computer program instructions thereon, which, when executed by a processor, implement the steps of the memory refresh method described in the first aspect of the present disclosure.
[0008] According to a fifth aspect of the present disclosure, a chip is provided, the chip including an interface circuit and a processing circuit coupled to each other, the interface circuit being used to input or output signals, and the processing circuit being configured to implement the steps of the memory refresh method described in the first aspect of the present disclosure.
[0009] According to a sixth aspect of the present disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the memory refresh method described in the first aspect of the present disclosure.
[0010] The technical solutions provided by the embodiments of this disclosure have at least the following beneficial effects: In this embodiment, the memory service scenario is determined to be a target scenario, which is one of at least two service scenarios with different service densities. Based on the target scenario, a target refresh mode for the memory is determined, and the memory is refreshed based on the target refresh mode. In this application, the refresh mode can be dynamically selected based on the current target scenario of the memory, instead of using a fixed refresh mode to refresh the memory. This allows for a balance between performance and power consumption under service scenarios with different service densities, improving the overall efficiency of the memory.
[0011] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0012] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.
[0013] Figure 1 This is a flowchart illustrating a memory refresh method according to an exemplary embodiment.
[0014] Figure 2 This is a flowchart illustrating a memory refresh method according to another exemplary embodiment.
[0015] Figure 3 This is a flowchart illustrating a memory refresh method according to another exemplary embodiment.
[0016] Figure 4 This is a schematic diagram illustrating a memory refresh method according to another exemplary embodiment.
[0017] Figure 5 This is a schematic diagram of the structure of a memory refresh device according to another exemplary embodiment.
[0018] Figure 6 This is a schematic diagram of the structure of an electronic device according to an exemplary embodiment.
[0019] Figure 7 This is a schematic diagram of the structure of a vehicle according to another exemplary embodiment.
[0020] Figure 8 This is a schematic diagram of the structure of a chip according to an exemplary embodiment. Detailed Implementation
[0021] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings.
[0022] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.
[0023] The following description, with reference to the accompanying drawings, describes a memory refresh method, apparatus, electronic device, chip, and storage medium according to embodiments of the present disclosure.
[0024] Figure 1 This is a flowchart illustrating a memory refresh method according to an exemplary embodiment.
[0025] It should be noted that the memory refresh method of this application embodiment can be applied to a memory refresh device. In some possible embodiments, the memory refresh device can be configured in an electronic device or chip so that the electronic device or chip can perform the memory refresh function. Additionally, in some possible embodiments, the memory refresh device can also be software in the electronic device.
[0026] In any embodiment of this application, the chip can be integrated into an electronic device. The chip includes a Central Processing Unit (CPU), an Image Signal Processing (ISP), an Application-Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a Field-Programmable Gate Array (FPGA), a System-on-Chip (SOC), a Reduced Instruction Set Computer (RISC), etc., which will not be listed here.
[0027] The electronic devices mentioned include, but are not limited to, terminals, personal computers (PCs), etc. A terminal is a user-side entity used to receive or transmit signals, such as a mobile phone. A terminal can also be called a terminal device (terminal), user equipment (UE), mobile station (MS), mobile terminal device (MT), etc. Terminals can be communication-enabled vehicles, smart cars, mobile phones, wearable devices, tablets, computers with wireless transceiver capabilities, virtual reality (VR) terminals, augmented reality (AR) terminals, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, etc. The embodiments of this application do not limit the specific technology or device form used in the terminal.
[0028] For ease of explanation, the following description will use an electronic device as the subject executing the memory refresh method.
[0029] like Figure 1As shown, the memory refresh method of this disclosure includes the following steps.
[0030] S101, determine that the memory service scenario is in the target scenario, and the target scenario is one of at least two service scenarios with different service densities.
[0031] In some embodiments, the service scenarios of the memory can be distinguished according to the service density, with different service densities corresponding to different service scenarios.
[0032] In some embodiments, the service scenario of the memory can be identified based on the current service load of the memory, and the current target scenario can be determined.
[0033] In some embodiments, different load conditions can be pre-configured for business scenarios with different service densities. The current monitored service load can be compared with the load conditions of each business scenario to determine the current service scenario of the storage.
[0034] In some embodiments, business scenarios may include, but are not limited to: low business density business scenarios and high-low business density business scenarios.
[0035] In some embodiments, business scenarios may include, but are not limited to: low business density business scenarios, medium business density business scenarios, and high and low business density business scenarios.
[0036] In some embodiments, the business scenarios may include, but are not limited to, business scenarios with a first business density to business scenarios with an Nth business density, each with a different business density. It should be noted that this is merely an example and should not be taken as a limitation of this application.
[0037] For example, memory utilization can be used as a measure of workload to differentiate between business scenarios. For instance, utilization less than 30% indicates a low-density business scenario, 30%–70% indicates a medium-density business scenario, and 70%–100% indicates a high-density business scenario. If the current monitored utilization is 25%, the target scenario is determined to be a low-density business scenario; if the current monitored utilization is 65%, the target scenario is determined to be a medium-density business scenario; and if the current monitored utilization is 85%, the target scenario is determined to be a high-density business scenario.
[0038] It is understandable that business load can also be characterized by monitoring parameters such as power consumption and business processing latency. This is only an example and should not be used as a condition to limit this application.
[0039] In some embodiments, a scenario classification model can be pre-trained, and the monitored business load can be input into the scenario classification model. The scenario classification model can then make predictions based on the business load and output the classification label of the business scenario, thereby determining that the memory business scenario is in the target scenario.
[0040] For example, the scenario classification model can be a multi-classification model, capable of distinguishing between low-density, medium-density, and high-low-density business scenarios. For instance, a classification label value of "0" corresponds to a low-density business scenario; a classification label value of "1" corresponds to a medium-density business scenario; and a classification label value of "2" corresponds to a high-density business scenario. If the currently monitored business load is input into the scenario classification model, and the output classification label value is "2," then it can be determined that the storage business scenario falls within the target scenario of a high-density business scenario.
[0041] S102, determine the target refresh mode of the memory based on the target scenario.
[0042] In some embodiments, different refresh modes can be used for service scenarios with different service densities to match the service scenarios, thereby enabling reasonable refresh of the memory.
[0043] In some embodiments, after determining the target scene, the target refresh mode matching the target scene can be determined from the pre-configured correspondence between scene identifiers and refresh mode identifiers based on the target scene identifier of the target scene.
[0044] In some embodiments, the refresh mode of the memory may include, but is not limited to, a per-bank refresh mode and an all-bank refresh mode.
[0045] S103 refreshes the memory based on the target refresh mode.
[0046] In some embodiments, after determining the target refresh mode of the memory, the memory can be refreshed based on the target refresh mode. If the target refresh mode is a single memory refresh mode, the memory can be refreshed based on the refresh mechanism corresponding to the single memory refresh mode. If the target refresh mode is a full memory refresh mode, the memory can be refreshed based on the refresh mechanism corresponding to the full memory refresh mode.
[0047] In this embodiment, the refresh mode can be dynamically selected based on the current target scenario of the memory, instead of using a fixed refresh mode to refresh the memory. This allows for a balance between performance and power consumption in business scenarios with different service densities, thereby improving the overall efficiency of the memory.
[0048] Figure 2 This is a flowchart illustrating a memory refresh method according to another exemplary embodiment.
[0049] like Figure 2 As shown, the memory refresh method of this disclosure includes the following steps.
[0050] S201, determine the service load of the memory.
[0051] In some embodiments, the access frequency of the memory within a set time period is monitored, and the service load of the memory is determined based on the access frequency within the set time period.
[0052] In some embodiments, a counter can be pre-deployed by the memory controller or the on-chip integrated performance monitoring unit, and the counter can be configured to count the rows of operations used to access the memory within a set time period. Further, after the timeout period ends, the memory access frequency within the set time period can be determined based on the count value and the set time period. Optionally, read and write operations of the memory can be counted to obtain the memory access frequency within the set time period.
[0053] S202, determine the state information of the memory bank.
[0054] In some embodiments, the state of the memory bank can be monitored by the memory controller in the memory or the performance monitoring unit integrated on the chip to obtain the state information of the memory bank.
[0055] In some embodiments, the state information of the storage unit may include, but is not limited to, active state, idle state, and closed state.
[0056] S203, determine the target scenario based on the business load and storage status information.
[0057] Understandably, with high traffic volume, more memory modules need to be activated; conversely, with low traffic volume, fewer memory modules need to be activated. In other words, the volume of traffic is positively correlated with the number of activated memory modules, and the number of activated memory modules reflects the current traffic status of the memory. In some embodiments, the number of activated memory modules is determined based on their status information. Further, a target scenario is determined from at least two traffic scenarios with different traffic densities, based on the traffic load and the number of memory modules.
[0058] In some embodiments, a target scenario can be determined from a first business scenario and a second business scenario based on the business load and the number of storage units. Optionally, the business density of the first business scenario is lower than that of the second business scenario.
[0059] In some embodiments, in response to the business load being less than a set load threshold and the number of storage units being less than a set quantity threshold, the target scenario is determined as the first business scenario.
[0060] In some embodiments, the target scenario is determined to be a second business scenario in response to the business load not being less than a set load threshold and / or the number of active storage units not being less than a set quantity threshold. Optionally, the target scenario is determined to be a second business scenario in response to the business load not being less than a set load threshold and the number of active storage units not being less than a set quantity threshold; alternatively, the target scenario is determined to be a second business scenario in response to the business load not being less than a set load threshold and the number of storage units being less than a set quantity threshold; or the target scenario is determined to be a second business scenario in response to the business load being less than a set load threshold and the number of storage units not being less than a set quantity threshold.
[0061] In some embodiments, a load threshold and / or a quantity threshold may be determined based on the service type and performance parameters of the memory.
[0062] In some embodiments, the service type may include audio and video data processing, autonomous driving sensor fusion, user interface rendering, big data batch processing, web page loading, etc.
[0063] In some embodiments, the performance parameters of the memory can be determined, which may include, but are not limited to, computing resources and computing frequency.
[0064] In some embodiments, different load thresholds and / or quantity thresholds can be pre-set for different combinations of service types and performance parameters, and a mapping relationship between combinations and thresholds can be established. Further, based on the current service type and performance parameters of the memory, the pre-built mapping relationship between combinations and thresholds can be queried to obtain a set load threshold and / or set quantity threshold adapted to the memory.
[0065] In some embodiments, model estimation or prediction can be performed based on the current service type and performance parameters of the memory to obtain a set load threshold and / or a set quantity threshold adapted to the memory.
[0066] In this embodiment, the memory service scenarios are identified by comprehensively considering the memory load and the number of activated memory blocks, making the memory service scenario identification more accurate. This allows for the determination of a more suitable refresh mode and better memory refresh.
[0067] S204, determine the target refresh mode of the memory based on the target scenario.
[0068] In some embodiments, in response to the target scenario being a first business scenario, the target refresh mode of the memory can be determined to be a single-bank refresh mode. That is, in a business scenario with low business density, a single-bank refresh mode can be selected for the memory.
[0069] In some embodiments, in response to the target scenario being the second business scenario, the target refresh mode of the memory can be determined to be the full memory refresh mode. That is, in a business scenario with high business density, the full memory refresh mode can be selected for the memory.
[0070] S205 refreshes the memory based on the target refresh mode.
[0071] In some embodiments, after determining the target refresh mode of the memory, the memory can be refreshed based on the target refresh mode. If the target refresh mode is a single memory refresh mode, the memory can be refreshed based on the refresh mechanism corresponding to the single memory refresh mode. If the target refresh mode is a full memory refresh mode, the memory can be refreshed based on the refresh mechanism corresponding to the full memory refresh mode.
[0072] In some embodiments, under the first business scenario, a centralized refresh of the memory banks can be performed based on a full memory bank refresh mode. Optionally, all memory banks in the memory can be turned off, or further, all memory banks in the memory can be collectively refreshed.
[0073] In this embodiment, under low-service-density scenarios, a full-storage-bank refresh mode can be adopted. This mode triggers a synchronous refresh of all storage banks, allowing all storage banks to complete charge regeneration operations in parallel within a unified refresh window. This eliminates the need for the memory controller to perform polling scheduling and state differentiation management for individual storage banks, significantly reducing the controller's instruction scheduling overhead and timing coordination complexity. It also reduces dynamic power consumption and resource overhead caused by frequent single-storage-bank refresh commands. Furthermore, it ensures high synchronization of the row refresh cycle time (tRFC) for all storage banks, and because memory access requests are sparse in low-service-density scenarios, it reduces conflicts between refresh operations and memory access requests.
[0074] In some embodiments, under the second business scenario, the memory banks in the memory can be refreshed based on a single memory bank refresh mode. Optionally, the memory banks in the memory that are in an idle state are identified, and the memory banks in the idle state are refreshed first, while the memory banks in the active state are deactivated and refreshed.
[0075] In this embodiment, under high-density business scenarios, a single-storage-bank refresh mode can be adopted, reducing the load from full refresh to single refresh. This allows the memory controller to continuously schedule and execute memory access requests for other storage banks within the same rank while performing a refresh operation on a single storage bank, thereby reducing the impact on business responsiveness. Furthermore, the tRFC of the single-storage-bank refresh mode is much shorter than the refresh cycle of the full-storage-bank refresh mode, which can significantly reduce the time occupied by a single refresh operation, reduce the waiting latency of read and write requests caused by refresh under high-density business scenarios, and improve the throughput and response timeliness of memory access in high-density business scenarios.
[0076] In some embodiments, after obtaining the service load and storage status information, refresh commands for the storage can be monitored. In response to the detected refresh command, the target refresh mode of the storage is determined based on the service load and storage status information; that is, the target scenario is determined based on the service load and storage status information. Further, the target refresh mode of the storage is determined based on the target scenario. Optionally, the storage can receive refresh commands input by the user or refresh according to a set refresh cycle. When the set refresh cycle is reached, a refresh command can be triggered.
[0077] In response to the absence of a refresh command, the system continues to monitor the service load and storage status information of the memory until a refresh command is detected. Based on the service load and storage status information, the memory is then refreshed.
[0078] In this embodiment, the refresh mode can be dynamically selected based on the current target scenario of the memory, instead of using a fixed refresh mode to refresh the memory. This allows for a balance between performance and power consumption in business scenarios with different service densities, thereby improving the overall efficiency of the memory.
[0079] Figure 3 This is a flowchart illustrating a memory refresh method according to another exemplary embodiment.
[0080] like Figure 3 As shown, the memory refresh method of this disclosure includes the following steps.
[0081] S301 determines the service load of the memory and the status information of the memory blocks.
[0082] S302. Determine mode indication information according to the service load and the status information of the memory banks.
[0083] In some embodiments, according to the status information of the memory banks, the memory banks in the active state in the memory can be determined. Further, the number of memory banks in the active state can be determined. Optionally, the number of memory banks can be marked as "ActiveBankCount".
[0084] In some embodiments, the current access frequency of the memory can be determined and marked as "CurrentBandwidth".
[0085] Further, the following formula can be used to determine the mode indication information S: S = (ActiveBankCount < reg_act_bank_threshold) & (CurrentBandwidth < reg_bw_threshold) where reg_act_bank_threshold is the set quantity threshold; reg_bw_threshold is the set load threshold.
[0086] If (ActiveBankCount < reg_act_bank_threshold) & (CurrentBandwidth < reg_bw_threshold), determine that the value of S is 1, that is, the first service scenario of low service density; If (ActiveBankCount < reg_act_bank_threshold) or (CurrentBandwidth < reg_bw_threshold), determine that the value of S is 0, that is, the second service scenario of high service density.
[0087] S303. Monitor the refresh commands of the memory.
[0088] In some embodiments, in response to detecting a refresh command, execute steps S304 - S305, or execute steps S306 - 307. In response to not detecting a refresh command, execute step S301.
[0089] S304. In response to the value 0 of the mode indication information, determine that the target refresh mode is the all - memory - bank refresh mode.
[0090] S305. Turn off all the memory banks in the memory and perform a collective refresh on all the memory banks in the memory.
[0091] S306, in response to the mode indication information being 1, determine that the target refresh mode is single-cell refresh mode.
[0092] S307: Determine which memory banks are in an idle state, refresh the idle memory banks first, and then deactivate and refresh the active memory banks.
[0093] In this embodiment, the refresh mode can be dynamically selected based on the current target scenario of the memory, instead of using a fixed refresh mode to refresh the memory. This allows for a balance between performance and power consumption in business scenarios with different service densities, thereby improving the overall efficiency of the memory.
[0094] Furthermore, in high-density business scenarios, a single-bank refresh mode can be adopted, reducing the load from full refresh to single-bank refresh. This allows the memory controller to continuously schedule and execute memory access requests for other banks within the same rank while performing a refresh operation on one bank, thereby reducing the impact on business responsiveness. Moreover, the tRFC of the single-bank refresh mode is much shorter than that of the full-bank refresh mode, significantly reducing the time occupied by a single refresh operation. This lowers the latency caused by refresh for read / write requests under high-density business scenarios, improving the throughput and response time of memory access in such scenarios.
[0095] In low-density business scenarios, a full-storage-bank refresh mode can be adopted. This mode triggers a synchronous refresh of all storage banks, allowing them to perform charge regeneration operations in parallel within a unified refresh window. This eliminates the need for the memory controller to perform polling scheduling and state differentiation management for individual storage banks, significantly reducing the controller's instruction scheduling overhead and timing coordination complexity. It also reduces dynamic power consumption and resource overhead caused by frequent single-storage-bank refresh commands. Furthermore, it ensures high synchronization of the row refresh cycle time (tRFC) across all storage banks, and because memory access requests are sparse in low-density business scenarios, it reduces conflicts between refresh operations and memory access requests.
[0096] Figure 4 This is a schematic diagram illustrating a storage system according to another exemplary embodiment. For example... Figure 4 As shown, the memory 400 includes a memory controller 410, which may include multiple functional modules, namely a memory status monitoring module 411, a service load monitoring module 412, a refresh mode decision module 413, a refresh control module 414, a read / write control module 415, and a command scheduling module 416.
[0097] The storage status monitoring module 411 is used to monitor the working status of the storage, such as whether it is in an active, refreshed, or idle state.
[0098] The business load monitoring module 412 is used to perceive the business density of the system in real time. For example, it can monitor the frequency of access to the memory within a set time to determine whether the current business scenario is a high-density business scenario or a low-density business scenario.
[0099] The refresh mode decision module 413 is used to determine the target refresh mode that the memory should adopt based on the information monitored by the memory status monitoring module 411 and the service load monitoring module 412. That is, it decides whether to adopt the All Bank Refresh mode or the Per Bank Refresh mode.
[0100] The refresh control module 414 is used to execute specific refresh commands and perform refresh operations on the memory bank in the memory based on the target refresh mode determined by the refresh mode decision module 413.
[0101] In some embodiments, the memory 400 further includes physical storage units 420, including RANK0 and RANK1, which can be controlled by the memory controller via chip select signals (CS0, CS1). Address lines (ADDR) are used to specify the storage unit to be accessed, data lines (DATA) are used to transmit data, and clock signals (CLK) are used for synchronization.
[0102] In some embodiments, the memory controller 410 interacts with a central processing unit (CPU), graphics processing unit (GPU), neural processing unit (NPU), direct memory access (DMA), and slave devices via a bus (BUS). These devices are the primary accessors to memory and represent different types of computing and data processing units in the system.
[0103] The read / write control module 415 is used to handle read / write requests to memory from devices such as CPU, GPU, NPU, DMA, and SLAVE DEVICE.
[0104] The command scheduling module 416 is used to coordinate the execution order of refresh commands and read / write commands to avoid conflicts and optimize performance.
[0105] In this embodiment, the memory controller can intelligently manage memory refresh and read / write operations. By dynamically selecting the refresh mode (All Bank or Per Bank), it can balance performance and power consumption under different business density scenarios, thereby improving the overall efficiency of the memory system.
[0106] Furthermore, in high-density business scenarios, a single-bank refresh mode can be adopted, reducing the load from full refresh to single-bank refresh. This allows the memory controller to continuously schedule and execute memory access requests for other banks within the same rank while performing a refresh operation on one bank, thereby reducing the impact on business responsiveness. Moreover, the tRFC of the single-bank refresh mode is much shorter than that of the full-bank refresh mode, significantly reducing the time occupied by a single refresh operation. This lowers the latency caused by refresh for read / write requests under high-density business scenarios, improving the throughput and response time of memory access in such scenarios.
[0107] In low-density business scenarios, a full-storage-bank refresh mode can be adopted. This mode triggers a synchronous refresh of all storage banks, allowing them to perform charge regeneration operations in parallel within a unified refresh window. This eliminates the need for the memory controller to perform polling scheduling and state differentiation management for individual storage banks, significantly reducing the controller's instruction scheduling overhead and timing coordination complexity. It also reduces dynamic power consumption and resource overhead caused by frequent single-storage-bank refresh commands. Furthermore, it ensures high synchronization of the row refresh cycle time (tRFC) across all storage banks, and because memory access requests are sparse in low-density business scenarios, it reduces conflicts between refresh operations and memory access requests.
[0108] In this embodiment, the refresh mode can be dynamically switched, meaning the refresh strategy is adjusted according to real-time business load to reduce performance loss under high load (e.g., reducing bank closing time) and power consumption under low load (e.g., reducing the number of refresh command transmissions). Furthermore, it supports All Bank / Per Bank refresh commands under the JEDEC standard without requiring hardware architecture modifications, ensuring compatibility. Moreover, in high-load scenarios, Per Bank Refresh can reduce the number of bank closings, lower read / write latency, and maximize performance.
[0109] In a scenario with 32Gb fifth-generation low-power double-data-rate synchronous dynamic random access memory (LPDDR5 DRAM) at a frequency of 6400Mbps, considering extreme cases where all banks are accessed, only per-bank precharge is supported, and the refresh cycle is 3.906us.
[0110] Using the All Bank Refresh mode requires 16 * Precharge + All Bank Refresh + 16 * Active; The total blocking time is: 30*tCK+tRPpb+tRFCab+15*tRRD+tRCD=528.5ns; Using the Per Bank Refresh mode requires 8*(2*Precharge+Per Bank Refresh+2*Active); The total blocking time is: 8*(2*tCK+tRPpb+tRFCpb+tRRD+tRCD)=1868ns; Precharge is a command sent by the memory controller to the bank to close the bank. All Bank Refresh refers to all Bank refresh commands sent by the memory controller; Activation is the command sent by the memory controller to reactivate the bank; tCK is the clock cycle, which is the basic time unit for DRAM operation; tRPpb is the Row Precharge Time, the shortest time required to execute a precharge command; tRFCab is the refresh cycle time for all banks in the entire memory. It is the time required for all banks in the entire memory to be refreshed after the All Bank Refresh command is executed. tRFCpb is the refresh cycle time per bank, which is the time required to refresh a single bank after executing a Per Bank Refresh command. tRFCab is much shorter than tRFCab.
[0111] tRRD stands for Row Active to Row Active Delay, which is the minimum interval required to send two activation commands consecutively to different banks within the same Bank Group.
[0112] tRCD stands for Row to Column Delay, which is the shortest time required from sending an activation command to being able to send a read / write command.
[0113] As shown above, under low-load scenarios, All Bank Refresh reduces the number of command transmissions, thereby reducing DRAM power consumption by up to 25%~50% (DRAM power consumption can be reduced by more than 50% under PD, and by about 25% under IDLE no PD). Taking 32Gb LPDDR5 at a frequency of 6400Mbps as an example, the average power consumption per bank refresh of DRAM is 31.31mW, with a single refresh time of 190ns; the average power consumption of all bank refresh is 30.12mW, with a single refresh time of 380ns. The average power consumption in idle power-down mode is 4.526mW, and the average power consumption in no power-down mode is 13.766mW, with a refresh cycle of 3.906us. Therefore, in all bank refresh mode, if in idle power-down, the average power consumption of DRAM including refresh is 7.02mW, and if in no power-down, the average power consumption of DRAM including refresh is 15.36mW. In per bank refresh mode, if in idle power-down, the average power consumption of DRAM including refresh is 14.4mW, and if in no power-down, the average power consumption of DRAM including refresh is 20.23mW.
[0114] Figure 5 This is a schematic diagram illustrating the structure of a memory refresh device according to an exemplary embodiment. (Refer to...) Figure 5 The memory refresh device 500 of this embodiment includes: a scene determination module 501, a mode determination module 502 and a refresh module 503.
[0115] The scenario determination module 501 is configured to determine whether the memory service scenario is in a target scenario, wherein the target scenario is one of at least two service scenarios with different service densities. The mode determination module 502 is configured to determine the target refresh mode of the memory based on the target scenario. The refresh module 503 is configured to refresh the memory based on the target refresh mode. (Memory refresh.)
[0116] In some embodiments, the scenario determination module 501 is further configured to determine the service load of the memory, determine the state information of the storage in the memory, and determine the target scenario based on the service load and the state information of the storage.
[0117] In some embodiments, the scenario determination module 501 is further configured to perform the following actions: determine the number of active storage units in the memory based on the state information of the storage units; and determine the target scenario from a first business scenario and a second business scenario based on the service load and the number of storage units, wherein the service density of the first business scenario is lower than the service density of the second business scenario.
[0118] In some embodiments, the scenario determination module 501 is further configured to determine the target scenario as a first business scenario in response to the business load being less than a set load threshold and the number of storage units being less than a set number threshold.
[0119] In some embodiments, the mode determination module 502 is further configured to determine the target refresh mode as a full storage refresh mode based on the first business scenario.
[0120] In some embodiments, the refresh module 503 is further configured to shut down all memory banks in the memory; Perform a collective refresh on all memory banks in the memory.
[0121] In some embodiments, the scenario determination module 501 is further configured to determine the target scenario as a second business scenario in response to the business load not being less than a set load threshold and / or the number of storage units in the active state not being less than a set number threshold.
[0122] In some embodiments, the mode determination module 502 is further configured to determine the target refresh mode as a single storage bank refresh mode based on the second business scenario.
[0123] In some embodiments, the refresh module 503 is further configured to determine the memory banks in the memory that are in an idle state, refresh the memory banks in the idle state first, and then deactivate and refresh the memory banks in the active state.
[0124] In some embodiments, the scenario determination module 501 is further configured to determine the service type and performance parameters of the memory, and determine the set load threshold and / or set quantity threshold based on the service type and the performance parameters.
[0125] In some embodiments, the scenario determination module 501 is further configured to monitor the access frequency of the memory within a set time period and determine the service load of the memory based on the access frequency within the set time period.
[0126] In some embodiments, the mode determination module 502 is further configured to monitor refresh commands for the memory, and in response to detecting the refresh command, determine the target refresh mode for the memory based on the service load and the state information of the memory.
[0127] In this embodiment, the refresh mode can be dynamically selected based on the current target scenario of the memory, instead of using a fixed refresh mode to refresh the memory. This allows for a balance between performance and power consumption in business scenarios with different service densities, thereby improving the overall efficiency of the memory.
[0128] Furthermore, in high-density business scenarios, a single-bank refresh mode can be adopted, reducing the load from full refresh to single-bank refresh. This allows the memory controller to continuously schedule and execute memory access requests for other banks within the same rank while performing a refresh operation on one bank, thereby reducing the impact on business responsiveness. Moreover, the tRFC of the single-bank refresh mode is much shorter than that of the full-bank refresh mode, significantly reducing the time occupied by a single refresh operation. This lowers the latency caused by refresh for read / write requests under high-density business scenarios, improving the throughput and response time of memory access in such scenarios.
[0129] In low-density business scenarios, a full-storage-bank refresh mode can be adopted. This mode triggers a synchronous refresh of all storage banks, allowing them to perform charge regeneration operations in parallel within a unified refresh window. This eliminates the need for the memory controller to perform polling scheduling and state differentiation management for individual storage banks, significantly reducing the controller's instruction scheduling overhead and timing coordination complexity. It also reduces dynamic power consumption and resource overhead caused by frequent single-storage-bank refresh commands. Furthermore, it ensures high synchronization of the row refresh cycle time (tRFC) across all storage banks, and because memory access requests are sparse in low-density business scenarios, it reduces conflicts between refresh operations and memory access requests.
[0130] To implement the above embodiments, this disclosure also proposes an electronic device, such as... Figure 6As shown, the electronic device 600 includes a memory 601, a processor 602, and a computer program stored in the memory 601 and executable on the processor 602. When the processor 602 executes the program, it implements the steps of the memory refresh method provided in this disclosure.
[0131] Figure 7 This is a schematic diagram illustrating the structure of a vehicle according to an exemplary embodiment. For example, vehicle 700 can be a hybrid vehicle, a non-hybrid vehicle, an electric vehicle, a fuel cell vehicle, or other types of vehicles. Vehicle 700 can be an autonomous vehicle, a semi-autonomous vehicle, or a non-autonomous vehicle.
[0132] Reference Figure 7 The vehicle 700 may include various subsystems, such as an infotainment system 710, a perception system 720, a decision control system 730, a drive system 740, and a computing platform 750. The vehicle 700 may also include more or fewer subsystems, and each subsystem may include multiple components. Furthermore, each subsystem and each component of the vehicle 700 can be interconnected via wired or wireless means.
[0133] In some embodiments, the infotainment system 710 may include a communication system, an entertainment system, and a navigation system, etc.
[0134] The perception system 720 may include several sensors for sensing information about the environment surrounding the vehicle 700. For example, the perception system 720 may include a global positioning system (which may be GPS, BeiDou, or other positioning systems), an inertial measurement unit (IMU), lidar, millimeter-wave radar, ultrasonic radar, and a camera device.
[0135] The decision control system 730 may include a computing system, a vehicle controller, a steering system, a throttle, and a braking system.
[0136] The drive system 740 may include components that provide powered motion to the vehicle 700. In one embodiment, the drive system 740 may include an engine, an energy source, a transmission system, and wheels. The engine may be one or a combination of internal combustion engines, electric motors, and compressed air engines. The engine is capable of converting energy provided by the energy source into mechanical energy.
[0137] Some or all of the functions of vehicle 700 are controlled by computing platform 750. Computing platform 750 may include at least one processor 751 and memory 752, and processor 751 may execute instructions 753 stored in memory 752.
[0138] Processor 751 can be any conventional processor, such as a commercially available CPU. Processors may also include graphics processing units (GPUs), field-programmable gate arrays (FPGAs), systems-on-chips (SoCs), application-specific integrated circuits (ASICs), or combinations thereof.
[0139] The memory 752 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.
[0140] In addition to instruction 753, memory 752 can also store data, such as road maps, route information, vehicle position, direction, speed, and other data. The data stored in memory 752 can be used by computing platform 750.
[0141] In this embodiment of the disclosure, processor 751 may execute instruction 753 to implement all or part of the steps of the memory refresh method provided in this disclosure.
[0142] To implement the above embodiments, this disclosure also proposes a computer-readable storage medium storing computer program instructions thereon, which, when executed by a processor, implement the steps of the memory refresh method provided in this disclosure.
[0143] Alternatively, the computer-readable storage medium may be ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.
[0144] To implement the above embodiments, this disclosure also proposes a chip including an interface circuit and a processing circuit coupled to each other, the interface circuit being used to input or output signals, and the processing circuit being configured to implement the steps of the memory refresh method provided in this disclosure.
[0145] Figure 8 This is a schematic diagram illustrating the structure of a chip according to an exemplary embodiment. See also... Figure 8 The diagram shown is a schematic representation of the structure of chip 800, but is not limited to this.
[0146] Chip 800 includes processing circuitry 801, which is configured to perform any of the above memory refresh methods.
[0147] In some embodiments, the chip 800 further includes one or more interface circuits 802. Optionally, the interface circuit 802 is connected to the memory 803, and the interface circuit 802 can be used to receive signals from the memory 803 or other devices, and the interface circuit 802 can be used to send signals to the memory 803 or other devices. For example, the interface circuit 802 can read instructions stored in the memory 803 and send the instructions to the processing circuit 801.
[0148] In some embodiments, the interface circuit 802 performs at least one of the communication steps such as sending and / or receiving in the above method, and the processing circuit 801 performs other steps.
[0149] In some embodiments, the terms interface circuit, interface, transceiver pin, transceiver, etc., can be used interchangeably.
[0150] In some embodiments, chip 800 further includes one or more memories 803 for storing instructions. Optionally, all or part of the memories 803 may be located outside of chip 800.
[0151] To implement the above embodiments, this disclosure also proposes a computer program product, including a computer program that, when executed by a processor, implements the steps of the memory refresh method provided in this disclosure.
[0152] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.
[0153] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.
Claims
1. A method for refreshing a memory, characterized in that, The method includes: Determine that the memory service scenario is in a target scenario, wherein the target scenario is one of at least two service scenarios with different service densities; Based on the target scenario, determine the target refresh mode of the memory; The memory is refreshed based on the target refresh mode.
2. The method according to claim 1, characterized in that, The determination that the memory service scenario is in the target scenario includes: Determine the service load of the memory; Determine the state information of the memory blocks within the memory; The target scenario is determined based on the business load and the status information of the storage.
3. The method according to claim 2, characterized in that, Determining the target scenario based on the business load and the state information of the storage unit includes: Based on the state information of the storage bank, determine the number of storage banks in the memory that are in an active state; Based on the business load and the number of storage units, the target scenario is determined from the first business scenario and the second business scenario, wherein the business density of the first business scenario is lower than that of the second business scenario.
4. The method according to claim 3, characterized in that, Determining the target scenario based on the business load and the number of active storage units includes: In response to the fact that the service load is less than a set load threshold and the number of storage units is less than a set quantity threshold, the target scenario is determined to be the first service scenario.
5. The method according to claim 4, characterized in that, Determining the target refresh mode of the memory based on the target scenario includes: Based on the first business scenario, the target refresh mode is determined to be a full storage refresh mode.
6. The method according to claim 5, characterized in that, In response to a full memory refresh mode, refreshing the memory based on the target refresh mode includes: Shut down all memory banks in the memory; Perform a collective refresh on all memory banks in the memory.
7. The method according to claim 3, characterized in that, Determining the target scenario based on the business load and the number of storage units includes: In response to the fact that the service load is not less than a set load threshold, and / or the number of active storage units is not less than a set quantity threshold, the target scenario is determined to be the second service scenario.
8. The method according to claim 7, characterized in that, Determining the target refresh mode of the memory based on the target scenario includes: Based on the second business scenario, the target refresh mode is determined to be a single storage bank refresh mode.
9. The method according to claim 8, characterized in that, In response to a single-bank refresh mode, refreshing the memory based on the target refresh mode includes: Identify the memory blocks in the memory that are in an idle state; The storage devices that are in an idle state are refreshed first, and then the storage devices that are in an active state are deactivated and refreshed.
10. The method according to claim 4 or 7, characterized in that, The method further includes: Determine the service type and performance parameters of the memory; Based on the service type and the performance parameters, determine the set load threshold and / or set quantity threshold.
11. The method according to any one of claims 1-9, characterized in that, The determination of the memory's service load includes: The access frequency of the memory within a set time period is monitored; The service load of the memory is determined based on the access frequency within the set time period.
12. The method according to any one of claims 1-9, characterized in that, Determining the target refresh mode of the memory based on the service load and the state information of the storage unit includes: Monitor the refresh commands of the memory; In response to the detected refresh command, the target refresh mode of the memory is determined based on the service load and the status information of the storage.
13. A memory refresh device, characterized in that, The method includes: The scenario determination module is configured to determine whether the memory service scenario is a target scenario, wherein the target scenario is one of at least two service scenarios with different service densities; The mode determination module is configured to determine the target refresh mode of the memory based on the target scenario. A refresh module is configured to refresh the memory based on the target refresh mode. (Memory refresh.) 14. The apparatus according to claim 13, characterized in that, The scenario determination module is also configured to determine the service load of the memory, determine the state information of the storage units in the memory, and determine the target scenario based on the service load and the state information of the storage units.
15. The apparatus according to claim 14, characterized in that, The scenario determination module is further configured to determine the number of active storage units in the memory based on the status information of the storage units; and to determine the target scenario from the first business scenario and the second business scenario based on the service load and the number of storage units, wherein the service density of the first business scenario is lower than the service density of the second business scenario.
16. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the steps of the method according to any one of claims 1-12.
17. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, When executed by a processor, the program instructions implement the steps of the method described in any one of claims 1-12.
18. A chip, characterized in that, The chip includes an interface circuit and a processing circuit coupled to each other. The interface circuit is used to input or output signals, and the processing circuit is configured to implement the steps of the method according to any one of claims 1-12.
19. A computer program product, characterized in that, Includes a computer program, which, when executed by a processor, implements the steps of the method according to any one of claims 1-12.