Signal sampling circuit and method and electronic equipment

Abstract

The invention provides a signal sampling circuit, a signal sampling method and electronic equipment. The sampling power consumption can be reduced. The circuit comprises a controller used for determining m to-be-tested devices and performing at least one round of data sampling on the m to-be-tested devices according to a first sampling frequency, and in each round of data sampling, the controller is used for performing signal sampling on the m to-be-tested devices by using a signal sampling module in m first sampling periods of a first time period, in each first sampling period, the signal sampling module performs signal sampling on the corresponding to-be-tested device at a second sampling frequency to obtain a first sampling signal of the to-be-tested device corresponding to each first sampling period; in the second time period, the signal sampling module is controlled to be in a dormant state; wherein the second sampling frequency is a first multiple of the first sampling frequency, and the first multiple is equal to the ratio of the total duration of the first time period and the second time period to the duration of the first time period.

Description

Technical Field

[0001] This application relates to the field of electronic equipment technology, and in particular to a signal sampling circuit, method and electronic equipment. Background Technology

[0002] With the development of electronic equipment technology, data sampling of electrical components is often required for power consumption testing and other purposes.

[0003] However, the power consumption of data sampling in existing technologies is relatively high. Therefore, how to reduce the power consumption of data sampling in electrical devices has become an urgent technical problem to be solved. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a signal sampling circuit, method, and electronic device that can perform high-power detection on the sampled signal in a first time period and enter sleep mode in a second time period, thereby reducing signal sampling power consumption while ensuring that the overall data sampling efficiency remains unchanged.

[0005] In a first aspect, this application provides a signal sampling circuit included in an electronic device, comprising: a signal sampling module including n input terminals and an output terminal, each input terminal corresponding to a power device of the electronic device, each input terminal being used to acquire the sampling signal of the corresponding power device, wherein n is a positive integer greater than or equal to 2; and a controller being used to determine m devices under test from the n power devices, and to perform at least one round of data sampling on the m devices under test according to a first sampling frequency, wherein m is a positive integer less than or equal to n, wherein, in each round of data sampling, the controller is used to: utilize m first sampling periods in a first time period to... The signal sampling module samples signals from m devices under test (DUTs). Each first sampling period corresponds to one DUT. In each first sampling period, the signal sampling module samples the corresponding DUT signal at a second sampling frequency to obtain the first sampled signal of the DUT corresponding to each first sampling period. During the second time period, the control signal sampling module is in a sleep state. The second sampling frequency is a first multiple of the first sampling frequency, and the first multiple is equal to the ratio of the first duration to the second duration. The first duration is the sum of the duration of the first time period and the duration of the second time period, and the second duration is the duration of the first time period.

[0006] Through the embodiments of this application, high-power detection of the sampled signal at a second sampling rate can be performed in the first time period, and sleep mode can be entered in the second time period, thereby reducing the power consumption of signal sampling while ensuring that the overall data sampling efficiency remains unchanged.

[0007] For example, the first time period can be the first half of the first period T, the first quarter of the first period, etc.

[0008] For example, the first sampling period can be the sampling period in the embodiments of this application. The first sampling period and the second sampling frequency are reciprocals of each other.

[0009] For example, the controller can stop the voltage multiplexer or current multiplexer in the signal sampling module from working. Alternatively, the controller can put itself into sleep mode / sleep state.

[0010] For example, the sampling signal may include a voltage sampling signal and / or a current sampling signal.

[0011] For example, the signal sampling module may include a power consumption test circuit 150.

[0012] For example, the controller may include a power consumption test controller 170.

[0013] For example, the device under test (DUT) can be a device among electrical components that requires signal sampling or power consumption testing. The DUT corresponding to any two sampling periods in the m first sampling periods can be different. For example, the 8 first sampling periods can be used to test the 1st through 8th electrical components respectively. Alternatively, the DUT corresponding to any two sampling periods in the m first sampling periods can be the same. For example, the 1st and 3rd first sampling periods can both be used to test the 1st electrical component.

[0014] According to the first aspect, the sampling signal includes a current sampling signal, and the signal sampling module includes: a first multiplexing module, a preset amplifier, and a first analog-to-digital converter. The controller is further configured to: control the first multiplexing module to output the current sampling signal of the i-th device under test during the i-th first sampling period; the preset amplifier is configured to perform differential operation on the current sampling signal to obtain the differential voltage of the i-th device under test; and control the first analog-to-digital converter to calculate the differential voltage of the i-th device under test to obtain the current sampling signal in digital signal form of the i-th device under test; wherein i is an integer greater than or equal to 1 and less than or equal to m; the controller is further configured to turn off the first analog-to-digital converter during the second time period.

[0015] In this way, the power consumption of current sampling can be reduced by using a sleep mode during the current sampling process.

[0016] For example, the first analog-to-digital converter may be a current analog-to-digital converter ADC1.

[0017] For example, the preset amplifier can be a preset amplifier PGA1.

[0018] For example, the first multiplexing module may include a current multiplexer MUX01.

[0019] According to the first aspect, or any implementation of the first aspect above, the sampling signal includes a voltage sampling signal, and the signal sampling module includes: a second multiplexing module and a second analog-to-digital converter. The controller is further configured to: control the second multiplexing module to output the voltage sampling signal of the i-th device under test during the i-th first sampling period, and control the second analog-to-digital converter to calculate the voltage sampling signal of the i-th device under test to obtain the voltage sampling signal in digital signal form of the i-th device under test; the controller is further configured to turn off the second analog-to-digital converter during the second time period.

[0020] In this way, the power consumption of voltage sampling can be reduced by using a sleep mode during voltage sampling.

[0021] For example, the second analog-to-digital converter can be a voltage analog-to-digital converter ADC2.

[0022] For example, the second multiplexing module may include Figure 6 The voltage multiplexer MUX02 in the middle.

[0023] According to the first aspect, or any implementation of the first aspect above, the sampling signal includes a voltage sampling signal, and the signal sampling module includes: a third multiplexing module, the third multiplexing module including a first input terminal connected to the positive terminal of the battery of the electronic device; and a second analog-to-digital converter. The controller is further configured to: control the third multiplexing module to output the voltage sampling signal of the battery during the first sampling period, control the second analog-to-digital converter to calculate the sampling signal of the battery to obtain the voltage sampling signal in the form of a digital signal of the battery, and determine the voltage sampling signal in the form of a digital signal of the battery as the voltage sampling signals of m devices under test; the controller is further configured to turn off the second analog-to-digital converter after the first sampling period ends.

[0024] In this way, after acquiring the voltage sampling signals of m devices under test in the first sampling period, the second analog-to-digital converter can be controlled to enter sleep mode, further reducing sampling power consumption.

[0025] For example, the third multiplexing module may include Figure 13 The voltage multiplexer MUX02 in the middle.

[0026] For example, the first input terminal may include a common input pin V_BUS_IN.

[0027] According to the first aspect, or any implementation of the first aspect above, the signal sampling circuit further includes: a reference voltage source for generating a reference voltage; a driving module for driving the reference voltage to obtain a reference voltage, and outputting the reference voltage to the signal sampling module; the controller is further configured to: turn off the driving module after the first time period ends; and, further configured to turn on the driving module at a first moment, wherein the first moment is earlier than the end moment of the second time period, and the difference between the first moment and the end moment is equal to a preset duration.

[0028] For example, the preset duration can be a first preset duration, which can be determined by simulation results of the stabilization process of the reference voltage during the driver turn-on process, for example, it can be equal to 356us.

[0029] For example, the drive module can be a current driver DR1 or a voltage driver DR2.

[0030] According to the first aspect, or any implementation of the first aspect above, a reference voltage source is used to generate a reference voltage; a first driving module is used to drive the reference voltage to obtain a reference voltage, and to output the reference voltage to a third analog-to-digital converter; the controller is further used to: shut down the first driving module after the first sampling period ends; and is further used to turn on the first driving module at a first moment, wherein the first moment is earlier than the end moment of the second time period, and the difference between the first moment and the end moment is equal to a preset duration.

[0031] For example, the first driving module may be a voltage driver DR2.

[0032] According to the first aspect, or any implementation of the first aspect above, the controller includes one or more of a first register, a second register, and a third register; wherein, the first register is used to set the test order of m devices under test; and the second register is used to set the number of devices under test.

[0033] The third register is used to set the duration of the second time period.

[0034] In this way, the sampling frequency, sleep duration, number of devices under test, and test sequence can be accurately set through the register, reducing sampling power consumption.

[0035] For example, the first register can be first registers SN0 through SN8. The second register can be the second register SLEN. The third register can be the third register BYNS.

[0036] According to the first aspect, or any implementation of the first aspect above, the controller is further configured to acquire the operating mode of the electronic device; when the electronic device is in the first mode, to perform at least one round of data sampling on the m devices under test at a first sampling frequency; and when the electronic device is in the second mode, to determine k devices under test from among the n electrical devices, and to perform at least one round of data sampling on the k devices under test at a third sampling frequency.

[0037] According to the first aspect, or any implementation of the first aspect above, in each round of data sampling for the k devices under test, the controller is used to:

[0038] In the k second sampling periods of the third time period, the signal sampling module is used to sample the signals of the k devices under test. Each second sampling period corresponds to one device under test. In each second sampling period, the signal sampling module samples the signal of the corresponding device under test at the fourth sampling frequency to obtain the second sampling signal of the device under test corresponding to each second sampling period.

[0039] For example, the fourth sampling frequency is the reciprocal of the second sampling period.

[0040] According to the first aspect, or any implementation of the first aspect above, in each round of data sampling for the k devices under test, the controller is further configured to:

[0041] During the fourth time period, the control signal sampling module is in a sleep state.

[0042] According to the first aspect, or any implementation of the first aspect above, the first mode is one of a first power consumption mode and a second power consumption mode, the second mode is the other of the first power consumption mode and the second power consumption mode, and the operating power consumption of the first electronic device in the first power consumption mode is lower than the operating power consumption in the second power consumption mode.

[0043] Secondly, embodiments of this application provide a signal sampling method. A controller determines m devices under test (DUTs) from n electrical devices and performs at least one round of data sampling on the m DUTs according to a first sampling frequency, where m is a positive integer less than or equal to n. In each round of data sampling, the following steps are executed: During m first sampling cycles in a first time period, the signal sampling module samples the signals of the m DUTs using the signal sampling module. Each first sampling cycle corresponds to one DUT. In each first sampling cycle, the signal sampling module samples the signal of the corresponding DUT at a second sampling frequency to obtain a first sampling signal of the DUT corresponding to each first sampling cycle. During a second time period, the signal sampling module is controlled to be in a sleep state. The second sampling frequency is a first multiple of the first sampling frequency, and the first multiple is equal to the ratio of a first duration to a second duration. The first duration is the sum of the duration of the first time period and the duration of the second time period, and the second duration is the duration of the first time period.

[0044] The second aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects corresponding to the second aspect and any implementation thereof are similar to those corresponding to the first aspect and any implementation thereof, and will not be repeated here.

[0045] Thirdly, embodiments of this application provide an electronic device, including: n electrical devices; a signal sampling module, including n input terminals and an output terminal, each input terminal corresponding to one electrical device of the electronic device, each input terminal being used to acquire the sampling signal of the corresponding electrical device, wherein n is a positive integer greater than or equal to 2; a controller, used to determine m devices under test among the n electrical devices, and to perform at least one round of data sampling on the m devices under test according to a first sampling frequency, wherein m is a positive integer less than or equal to n, wherein in each round of data sampling, the controller is used to: utilize the signal sampling module in m first sampling periods of a first time period. Signal sampling is performed on the m devices under test (DUTs), wherein each first sampling period corresponds to one DUT. In each first sampling period, the signal sampling module samples the corresponding DUT signal at a second sampling frequency to obtain a first sampled signal of the DUT corresponding to each first sampling period. During a second time period, the signal sampling module is controlled to be in a sleep state. The second sampling frequency is a first multiple of the first sampling frequency, and the first multiple is equal to the ratio of the first duration to the second duration. The first duration is the sum of the duration of the first time period and the duration of the second time period, and the second duration is the duration of the first time period.

[0046] The third aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects corresponding to the third aspect and any implementation thereof are similar to those corresponding to the first aspect and any implementation thereof, and will not be repeated here. Attached Figure Description

[0047] Figure 1 A schematic diagram of the circuit structure of an electronic device provided in an embodiment of this application is shown;

[0048] Figure 2 A schematic diagram of the circuit structure of an exemplary electronic device provided in an embodiment of this application is shown;

[0049] Figure 3 A schematic diagram of another exemplary power supply circuit provided in an embodiment of this application is shown;

[0050] Figure 4 A schematic diagram of an exemplary voltage conversion circuit provided in an embodiment of this application is illustrated.

[0051] Figure 5 A schematic diagram of a power consumption test circuit provided in an embodiment of this application is shown;

[0052] Figure 6 A schematic diagram of an exemplary power consumption test circuit is shown.

[0053] Figure 7 This paper shows a schematic diagram of a reference voltage generation circuit provided in an embodiment of this application.

[0054] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0055] Figures 9A-9B A schematic diagram of a signal sampling method provided in an embodiment of this application is shown;

[0056] Figure 10 A schematic diagram of another signal sampling method provided in an embodiment of this application is shown;

[0057] Figure 11 A schematic diagram of another signal sampling method provided in an embodiment of this application is shown;

[0058] Figure 12 A schematic diagram of another power consumption test circuit provided in an embodiment of this application is shown;

[0059] Figure 13 This paper shows a schematic diagram of the structure of a voltage multiplexer provided in an embodiment of this application;

[0060] Figure 14 A schematic diagram of another signal sampling method provided in an embodiment of this application is shown;

[0061] Figure 15 A schematic diagram of another signal sampling method provided in an embodiment of this application is shown;

[0062] Figure 16 This diagram illustrates a variation of a reference voltage according to an embodiment of this application.

[0063] Figure 17 A schematic diagram of another signal sampling method provided in an embodiment of this application is shown;

[0064] Figure 18 A schematic diagram of another signal sampling method provided in an embodiment of this application is shown;

[0065] Figure 19 A schematic diagram of another signal sampling method provided in an embodiment of this application is shown;

[0066] Figure 20 A schematic diagram of another signal sampling method provided in an embodiment of this application is shown.

[0067] Figure 21 A schematic diagram of the structure of a power consumption test controller provided in an embodiment of this application is shown;

[0068] Figure 22 A schematic diagram of an exemplary battery structure provided in an embodiment of this application is shown;

[0069] Figure 23 A schematic diagram of an exemplary battery structure provided in an embodiment of this application is shown;

[0070] Figure 24 A schematic flowchart of a signal sampling method provided in an embodiment of this application is shown;

[0071] Figure 25 A flowchart illustrating another signal sampling method provided in an embodiment of this application is shown;

[0072] Figure 26 A schematic flowchart of another signal sampling method provided in an embodiment of this application is shown;

[0073] Figure 27 A schematic flowchart of another signal sampling method provided in an embodiment of this application is shown;

[0074] Figure 28 A schematic flowchart of another signal sampling method provided in an embodiment of this application is shown. Detailed Implementation

[0075] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0076] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0077] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0078] In the embodiments of this application, directional terms such as "up," "down," "left," and "right" may include, but are not limited to, the orientation relative to the schematic placement of the components in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly based on the orientation of the components in the accompanying drawings.

[0079] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or a connection through an intermediate medium. Furthermore, the term "coupled" can refer to an electrical connection method for achieving signal transmission.

[0080] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0081] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0082] Furthermore, in the embodiments of this application, the control terminal of each transistor is the gate of the transistor, the first connection terminal is one of the source and drain of the transistor, and the second connection terminal is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, their source and drain can be structurally indistinguishable.

[0083] To facilitate understanding, the technical terms involved in the embodiments of this application will be explained before introducing the technical solutions of the embodiments of this application.

[0084] (1) A multiplexer (MUX) may include multiple input pins and one output pin. A multiplexer can receive multiple input signals through multiple input pins and select one signal from the received input signals for output.

[0085] (2) Programmable Gain Amplifier (PGA) is a flexible, programmable electronic operational amplifier whose gain can be programmed to meet different application requirements. By adjusting the configuration of internal resistors or electronic switches, the PGA can switch between different gain settings to meet different signal processing needs. It is commonly used in applications such as data acquisition and automatic control systems. In addition, because the gain of the PGA is digitally controlled, the amplification factor can be precisely controlled, avoiding the errors and drift problems that may occur in analog operational amplifiers.

[0086] (3) Low-pass filter (LPF): It allows low-frequency signals to pass through while allowing high-frequency signals to pass through, and can filter high-frequency noise signals in the circuit. For example, an LPF can be implemented as a passive low-frequency filter such as an RC filter or an active low-frequency filter, etc., without specific limitations.

[0087] (4) Analog-to-Digital Converter (ADC), also known as analog-to-digital converter, etc. ADC can convert analog signals into digital signals. It can include successive approximation ADC, Sigma-Delta (Σ-Δ) ADC, indirect ADC, parallel comparator ADC, etc., without specific limitations.

[0088] (5) Buffer, which can increase the driving capability of the signal.

[0089] (6) A bandgap voltage reference circuit, which is a circuit used to generate a stable reference voltage, can output a highly stable, low-noise voltage that is unaffected by temperature changes, greatly improving the reliability and stability of the circuit. In the embodiments of this application, the voltage output by the bandgap reference circuit can be called the bandgap reference voltage or the reference voltage.

[0090] The principle of a bandgap reference is to add a voltage with a positive temperature coefficient and a voltage with a negative temperature coefficient in a certain ratio to obtain a bandgap reference voltage that hardly changes with temperature.

[0091] After introducing the above technical terms, the technical solutions of the embodiments of this application will be described next.

[0092] To ensure the normal operation of various components in electronic devices, batteries are often used to power these components.

[0093] Since the power consumption of each component affects the safety, battery life, and heat dissipation of electronic devices, it is often necessary to detect the power consumption of each component during the use of electronic devices.

[0094] For example, by detecting the power consumption of each device, it can be determined whether the power consumption of each device meets the requirements. For instance, when the power consumption of a device is too high, the device may have problems such as low efficiency or failure, and the device can be repaired or improved. As another example, device power consumption detection can support the thermal design of electronic devices. For instance, when a device's power consumption is detected to be too high, thermal design can be implemented for that device or the load on that device can be reduced.

[0095] To facilitate understanding of power consumption detection, the circuit structure of the electronic device in this application embodiment will be described below.

[0096] Figure 1This illustration shows a circuit structure diagram of an electronic device according to an embodiment of this application. The electronic device provided in this embodiment may include, but is not limited to, mobile phones, tablets, laptops, Ultra-Mobile Personal Computers (UMPCs), Personal Digital Assistants (PDAs), Point-of-Sale (POS) machines, walkie-talkies, in-vehicle computers, televisions, smart wearable devices (such as smartwatches or smart bracelets), smart home devices (such as Bluetooth speakers), dashcams, security equipment, and other electronic devices capable of power consumption testing. This embodiment does not specifically limit the type of the aforementioned electronic device. For ease of explanation, a mobile phone is used as an example for the following description.

[0097] like Figure 1 As shown, the electronic device may include a battery 110, n test resistors 121 to 12n, n voltage conversion circuits 131 to 13n, n power-consuming devices 141 to 14n, a power consumption test circuit 150, a reference voltage generation circuit 160, a power consumption test controller 170, and a microcontroller (MCU) 180, where n is an integer greater than or equal to 2. Each component will be described in detail below.

[0098] A battery 110 is used to power various components of an electronic device. In some embodiments, the battery 110 may include a single battery cell. In other embodiments, the battery may include at least one parallel branch, with two or more single battery cells connected in series in each branch. Exemplarily, Figure 2 A schematic diagram of the circuit structure of an exemplary electronic device provided in an embodiment of this application is shown. Figure 2 As shown, battery 110 can be represented as power supply VIN0.

[0099] Among them, battery 110, the i-th voltage conversion circuit 13i and the i-th power-consuming device 14i constitute the power supply circuit of the i-th power-consuming device 14i, where i is any integer greater than or equal to 1 and less than or equal to n.

[0100] For example, the power supply circuit of the first electrical device 141 will be used as an example for explanation. Figure 2 A schematic diagram of an exemplary power supply circuit provided in an embodiment of this application is shown. For example... Figure 2 As shown, the power supply circuit for the first electrical device may include a power supply VIN0, a voltage conversion circuit 131, and the electrical device 141.

[0101] The power supply VIN0 can be connected to the electrical device 141 via the voltage conversion circuit 131. For example, ... Figure 2 As shown, the positive terminal of the power supply VIN0 can be connected to the first input terminal IN01 of the voltage conversion circuit 131, and the negative terminal of the power supply VIN0 can be connected to the second input terminal IN02 of the voltage conversion circuit 131. The first output terminal OUT1 of the voltage conversion circuit 131 can be connected to the first terminal of the device 141, and the second output terminal OUT2 of the voltage conversion circuit 131 can be connected to the other terminal of the device 141. The power supply voltage provided by the power supply voltage VIN0 can be converted by the voltage conversion circuit 131, and the converted voltage can be used to power the device 141.

[0102] It should be noted that the power supply circuits for the second electrical device 142 to the nth electrical device 14n can be referred to the above-mentioned combination. Figure 2 The power supply circuit shown will not be described in detail.

[0103] Each of the n test resistors 121 to 12n is used for power consumption testing. For example, the i-th test resistor 12i can be placed in the power supply circuit of the i-th electrical device 14i. For example, taking i=1 as an example, see further... Figure 2 The first test resistor 121 can be implemented as Figure 2 The resistor R0 is used in this circuit. Resistor R0 can be placed between the power supply VIN0 and the voltage conversion circuit 131, for example, on the line between the power supply VIN0 and the voltage conversion circuit 131. That is, the positive terminal of the power supply VIN0 can be connected to the voltage conversion circuit 131 through resistor R0. For example, the resistance value of resistor R0 can be very small, such as 5mΩ, so that its impact on the supply voltage and current provided by the power supply VIN0 is negligible, ensuring the accuracy of power sampling. It should be noted that the second test resistor 122 to 12n can refer to the above-mentioned combination... Figure 2 The relevant description of resistor R0 will not be elaborated upon here. Alternatively, Figure 3 A schematic diagram of another exemplary power supply circuit provided in an embodiment of this application is shown. Figure 3 and Figure 2 The difference is that resistor R0 can also be placed between voltage conversion circuit 131 and power device 141.

[0104] Each of the n voltage conversion circuits 131 to 13n can be a circuit that converts the supply voltage of the power supply VIN0 into the operating voltage of the device. For example, each voltage conversion circuit can be a buck converter, a boost converter, or a buck-boost converter, etc., using an inductor as the energy storage element. Alternatively, the voltage conversion circuit can also be a switch capacitor converter (SC) circuit, etc., using a capacitor as the energy storage element. This application embodiment does not impose specific limitations on this. It should be noted that the specific selection of the voltage conversion circuit can be based on the power requirements of the device under test, and there are no specific limitations on this.

[0105] For example, taking voltage conversion circuit 131 as an example, if the voltage consumed by electrical device 141 is lower than the supply voltage of power supply VIN0, voltage conversion circuit 131 can be implemented as a BUCK circuit. For example, Figure 4 A schematic diagram of an exemplary voltage conversion circuit provided in an embodiment of this application is illustrated. For example... Figure 4 As shown, the voltage conversion circuit 131 may include a switch Sa, a freewheeling diode Xa, an energy storage inductor La, and a filter capacitor Ca. The first terminal of the switch Sa serves as the first input terminal IN01 of the voltage conversion circuit 131. The second terminal of the switch Sa is connected to one end of the energy storage inductor La and one end of the freewheeling diode Xa. The other end of the freewheeling diode Xa serves as the second input terminal IN02 of the voltage conversion circuit 131, and is also connected to the other end of the filter capacitor Ca. The other end of the energy storage inductor La serves as the first output terminal OUT1 of the voltage conversion circuit 131, and is also connected to one end of the filter capacitor Ca. The other end of the filter capacitor Ca serves as the second output terminal OUT2 of the voltage conversion circuit 131.

[0106] Additionally, it should be noted that since different components in electronic devices may have different operating voltages, the output voltage of the voltage conversion circuit of different devices under test may also be different, and no specific restrictions are imposed on this.

[0107] Each of the n electrical components 141 to 14n can be an electrical component or structure within an electronic device. For example, an electrical component can be a cooling fan, CPU core, screen, speaker, camera module, etc., in a mobile phone, without specific limitations. It should be noted that the n electrical components 141 to 14n in this embodiment refer to electrical components connected to a power consumption test circuit 150. The electronic device may also include other electrical components, such as those connected to other power consumption test circuits, or those that do not require power consumption testing, without specific limitations.

[0108] The power consumption test circuit 150 can acquire analog voltage signals corresponding to the supply voltage U1 and supply current I1 of the power supply VIN0 from both ends of the test resistor, and perform analog-to-digital conversion on the acquired analog voltage signals to obtain digital signals. For example, taking the power consumption detection of the first electrical device 141 as an example, signal acquisition can be performed from both ends of resistor R0 (i.e., the first test resistor 121). See also... Figure 2 In this embodiment of the application, the voltage sampling data may be the voltage at one end of resistor R0. Furthermore, since the supply current I1 can be calculated based on the voltage difference across resistor R0 (i.e., the ratio of the voltage difference to the resistance), the current sampling data may include the voltage sampled from one end of resistor R0 (hereinafter referred to as the first voltage signal) and the voltage sampled from the other end of resistor R0 (hereinafter referred to as the second voltage signal).

[0109] In one embodiment, Figure 5 A schematic diagram of a power consumption test circuit provided in an embodiment of this application is shown. Figure 5 As shown, the power consumption test circuit 150 may include a current signal acquisition circuit 151 and a voltage signal acquisition circuit 152. The power consumption test circuit 150 can sample the power of n electrical devices using n test resistors, where n is an integer greater than or equal to 2, such as 4, 8, or 16, etc., without specific limitations. Specifically, the first test resistor 121 (i.e., resistor R0) is located in the power supply circuit of the first electrical device 141, the second test resistor 122 is located in the power supply circuit of the second electrical device 142, ..., the nth test resistor 12n is located in the power supply circuit of the nth electrical device 14n. It should be noted that the specific arrangement of the n test resistors 121 to 12n can be found in the embodiments of this application. Figure 2 and Figure 3 The description of the power supply circuit for the first electrical device 141 is not specifically limited.

[0110] Specifically, the current signal acquisition circuit 151 is used to acquire current sampling data (such as the first voltage signal and the second voltage signal of the test resistor). Specifically, the current signal acquisition circuit 151 includes a current multiplexer MUX01 (i.e., a multiplexer for current sampling data), a preset operational amplifier PGA1, a preset low-pass filter LPF1, and a current analog-to-digital converter ADC1 (i.e., an analog-to-digital converter for current sampling data).

[0111] The current multiplexer MUX01 includes n pairs of input pins. The first pair of input pins includes input pins AIN0 and AIN1, the second pair includes input pins AIN2 and AIN3, ..., and the nth pair includes input pins AIN2n-2 and AIN2n-1. Input pin AIN0 in the first pair is connected to the first test resistor 121 (i.e., ...). Figure 5 One end of the resistor R0 is connected to acquire the first voltage signal of the resistor R0 (or the first voltage signal of the first electrical device 141). Input pin AIN1 of the first pair of input pins is connected to the other end of the resistor R0 to acquire the second voltage signal of the resistor R0 (or the second voltage signal of the first electrical device 141). Input pin AIN2 of the second pair of input pins is connected to one end of the second test resistor 122 to acquire the first voltage signal of the second test resistor 122 (or the first voltage signal of the second electrical device 142). Input pin AIN3 of the second pair of input pins is connected to the second test... The other end of resistor 122 is used to acquire the second voltage signal of the second test resistor 122 (or the second voltage signal of the second electrical device 142); ...; input pin AIN2n-2 of the nth pair of input pins is connected to one end of the nth test resistor 122 to acquire the first voltage signal of the nth test resistor 122 (or the first voltage signal of the nth electrical device 14n), and input pin AIN2n-1 of the nth pair of input pins is connected to the other end of the nth test resistor 122 to acquire the second voltage signal of the nth test resistor 122 (or the second voltage signal of the nth electrical device 14n).

[0112] In addition, the current multiplexer MUX01 includes two output pins, namely the first output pin B1 and the second output pin B2.

[0113] During the current sampling process of the i-th electrical device (i can be any positive integer greater than or equal to 1 and less than or equal to n), the current multiplexer MUX01 selects the i-th pair of input pins to be turned on from the n pairs of input pins. At this time, the first output pin B1 outputs the first voltage signal of the i-th test resistor 12i to the non-inverting input terminal of the preset operational amplifier PGA1. Figure 5 The port marked with "+" in the middle), the second output pin B2 outputs the second voltage signal of the i-th test resistor 12i to the negative input terminal of the preset operational amplifier PGA1 (the port marked with "+" in the middle). Figure 5(Ports marked with "-"). The preset operational amplifier PGA1 generates a differential voltage for the i-th test resistor 12i based on the first and second voltage signals. This differential voltage is then filtered at high frequency by LPF1 and output to the current analog-to-digital converter ADC1. ADC1 samples the differential voltage in analog signal format and performs analog-to-digital conversion to obtain a digital signal format differential voltage, thus acquiring the current sampling data in digital signal format.

[0114] In one example Figure 6 A schematic diagram of an exemplary power consumption test circuit is shown. If the current multiplexer MUX01 includes 16 input pins, then the current multiplexer MUX01 can connect to 8 test resistors. For example... Figure 6 As shown, the current multiplexer MUX01 may include 16 first control switches. Specifically, the first input pin AIN0 is connected to the first output pin B1 via the first first control switch K0; the third input pin AIN2 is connected to the first output pin B1 via the third first control switch K2, ..., the 15th input pin AIN14 is connected to the first output pin B1 via the 15th first control switch K14. The second input pin AIN1 is connected to the second output pin B2 via the second first control switch K1; the fourth input pin AIN3 is connected to the second output pin B2 via the fourth first control switch K3, ..., the 16th input pin AIN15 is connected to the second output pin B2 via the 16th first control switch K15.

[0115] In addition, the voltage signal sampling circuit 152 is used to acquire voltage sampling data. Specifically, the voltage signal acquisition circuit 152 includes a voltage multiplexer MUX02 (i.e., a multiplexer for voltage sampling data) and a voltage analog-to-digital converter ADC2 (i.e., an analog-to-digital converter for voltage).

[0116] The voltage multiplexer MUX02 includes n input pins. The first input pin is connected to input pin AIN0 to acquire the voltage at one end of the first test resistor R0 (i.e., the first voltage signal of the test resistor). The second input pin is connected to input pin AIN2 to acquire the first voltage signal of the second test resistor; ...; the nth input pin is connected to input pin AIN2n-2 to acquire the first voltage signal of the nth test resistor. For example, the voltage multiplexer MUX02 may include n second control switches. The j-th input pin is connected to the output pin B3 of the voltage multiplexer MUX02 through the j-th second control switch. Here, j is any positive integer greater than or equal to 1 and less than or equal to n.

[0117] During the voltage sampling process of the i-th device under test, the voltage multiplexer MUX02 selects the i-th input pin from the n input pins to conduct, so as to output the first voltage signal of the i-th test resistor to the voltage analog-to-digital converter ADC2. The voltage analog-to-digital converter ADC2 samples the first voltage signal in analog signal format and performs analog-to-digital conversion to obtain the first voltage signal in digital signal format, that is, to acquire the voltage sampling data in digital signal format.

[0118] In one example, see [link to example]. Figure 6 The voltage multiplexer MUX02 may include eight second control switches S0 to S7. The first input pin of the voltage multiplexer MUX02 is connected to the output pin B3 of the voltage multiplexer MUX02 through the first second control switch K0; the second input pin of the voltage multiplexer MUX02 is connected to the output pin B3 of the voltage multiplexer MUX02 through the second second control switch K1; ...; the eighth input pin of the voltage multiplexer MUX02 is connected to the output pin B3 of the voltage multiplexer MUX02 through the eighth second control switch K7.

[0119] At this point, the voltage across one end N01 of resistor R0 is the voltage consumed by device 141. The ratio between the voltage difference across the power consumption detection resistor R0 and the resistance of R0 is the current consumed by device M0 under test. Then, the power consumption of device M0 can be obtained by multiplying the voltage consumed by device M0 under test by the current consumed by device M0 under test.

[0120] Through the aforementioned power consumption test circuit 150, when the power consumption test of the i-th electrical device is required, the i-th second control switch in the voltage multiplexer MUX02 is turned on. The voltage signal sampling circuit 152 can acquire the voltage at one end N01 of the test resistor 12i, and the voltage in digital signal form (referred to as the first digital voltage) obtained through the voltage analog-to-digital converter ADC2, and use the first digital voltage as the power supply voltage U1 of the power supply VIN0. Additionally, the 2i-1 first control switches and the 2i-th first control switch in the current multiplexer MUX01 are turned on. The current multiplexer MUX01 can acquire the first voltage signal and the second voltage signal of the test resistor 12i. Furthermore, the first differential voltage can be obtained through the preset operational amplifier PGA1. The first differential voltage can represent the voltage difference across the test resistor. For example, taking resistor R0 as an example, the voltage difference between one end N01 of resistor R0 and the other end N02 of resistor R0 can be obtained. Furthermore, the current analog-to-digital converter ADC1 can process the first differential voltage to obtain a differential voltage in digital signal form (referred to as the second digital voltage). Then, the electronic device can calculate the ratio between the second digital voltage and the resistance value of resistor R0 to obtain the supply current I1 of the power supply VIN0. Additionally, the electronic device can calculate the product of the supply voltage U1 and the supply current I1 of the power supply VIN0 to obtain the power consumption of the i-th electrical device.

[0121] In other embodiments, for Figure 3 The power supply circuit shown differs from the calculation method described above in that the current signal acquisition circuit 151 can acquire the voltage difference (in digital signal form) across resistor R0. The electronic device can then calculate the ratio between the voltage difference across resistor R0 and the resistance value of R0 to obtain the current consumed by the device 141. Furthermore, the voltage signal acquisition circuit 152 can acquire the voltage (in digital signal form) across one end of resistor R0, i.e., the voltage consumed. The electronic device then calculates the product of the voltage consumed by device 141 and the current consumed by device 141 to obtain the power consumption of device 141.

[0122] The reference voltage generation circuit 160 is used to provide a reference voltage (also known as a reference voltage) for the power consumption test 150. Figure 7 A schematic diagram of a reference voltage generation circuit provided in an embodiment of this application is shown. Figure 7 As shown, the reference voltage generation circuit 160 may include a reference voltage source 161, a current driver DR1, a voltage driver DR2, a third control switch Sc1, and a fourth control switch Sc2.

[0123] Reference voltage source 161 is used to generate a reference voltage (or bandgap reference voltage). Exemplarily, the reference voltage source can be implemented as a bandgap reference circuit, or it can be implemented as other voltage sources capable of generating a reference voltage, without particular limitation.

[0124] The third control switch Sc1 has its first connection terminal connected to the reference voltage source 161, its second connection terminal connected to the negative phase input terminal of the current driver DR1, and its control terminal connected to the power consumption test controller 170. It is used to turn on (the first connection terminal and the second connection terminal are connected) or turn off (the first connection terminal and the second connection terminal are disconnected) according to the control signal of the power consumption test controller 170.

[0125] The fourth control switch Sc2 has its first connection terminal connected to the reference voltage source 161, its second connection terminal connected to the negative phase input terminal of the voltage driver DR2, and its control terminal connected to the power consumption test controller 170, which is used to turn the switch on or off according to the control signal of the power consumption test controller 170.

[0126] The current driver DR1 has its non-inverting input connected to its output, and its output also connected to the current analog-to-digital converter ADC1. The current driver DR1 is used to increase the driving capability of the reference voltage output from the reference voltage source 161, thus obtaining the reference voltage Vr1 (Reference0) for the current analog-to-digital converter ADC1. Exemplarily, the current driver DR1 can be implemented as a buffer, such as a current buffer.

[0127] Voltage driver DR2 has its non-inverting input connected to its output, and its output is also connected to voltage analog-to-digital converter ADC2. Voltage driver DR2 is used to increase the driving capability of the reference voltage output from reference voltage source 161, thus obtaining the reference voltage Vr2 of voltage analog-to-digital converter ADC2. Exemplarily, current driver DR1 can be implemented as a buffer, such as a voltage buffer.

[0128] Furthermore, it should be noted that, in order to reduce noise, the reference voltage generation circuit 160 may also include a noise reduction capacitor Cc and a noise reduction resistor Rc. One end of the noise reduction capacitor Cc is connected to the reference voltage source 161 through the noise reduction resistor Rc, and the other end of the noise reduction capacitor Cc is grounded to GND.

[0129] The power consumption test controller 170 is used to control the power consumption test process. In this embodiment, the power consumption test controller 170 can control the on / off state of the first control switch in the voltage multiplexer MUX02 and the second control switch in the voltage analog-to-digital converter ADC2. The power consumption test controller 170 can also control the current analog-to-digital converter ADC1 and the voltage analog-to-digital converter ADC2. Furthermore, the power consumption test controller 170 can also control the on / off state of the third control switch Sc1 and the fourth control switch Sc2, and can also control the current driver DR1 and the voltage driver DR2 to be in operating mode or sleep mode. Exemplarily, the power consumption test controller 170 can be implemented as a control chip, control circuit, control structure, or control module, etc., without specific limitations.

[0130] A microcontroller unit (MCU) 180 can be connected to a power consumption test controller 170, for example, via a Serial Peripheral Interface (SPI) bus, or via other wired or wireless methods; no specific limitation is made. In this embodiment, the MCU 180 can control the power consumption test controller 170. Alternatively, the power consumption test controller can be controlled by other structures with control functions; no specific limitation is made. Alternatively, the MCU 180 may also include the power consumption test controller 170; no specific limitation is made in this regard.

[0131] After the above Figures 1 to 7 After introducing the circuit structure of the electronic device according to the embodiments of this application, the hardware structure of the electronic device will be described next.

[0132] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 8As shown in the illustration, this application provides an electronic device. This electronic device may include, but is not limited to, mobile phones, tablets, laptops, Ultra-Mobile Personal Computers (UMPCs), Personal Digital Assistants (PDAs), Point-of-Sale (POS) machines, walkie-talkies, in-vehicle computers, televisions, smart wearable devices (such as smartwatches or smart bracelets), smart home devices (such as Bluetooth speakers), dashcams, security equipment, and other electronic devices with power consumption testing functions. This application does not specifically limit the specific type of the aforementioned electronic device. For ease of explanation, a mobile phone is used as an example for the following description.

[0133] in, Figure 8 (1) is a schematic diagram of the front structure of the electronic device. Figure 8 (2) A schematic diagram of the rear structure of the electronic device. For example... Figure 8 As shown, the electronic device 100 includes a display module 10, a back cover (also known as a battery cover) 20, and a mid-frame 30.

[0134] The display module 10 includes a cover plate and a display screen stacked together. The cover plate, for example, protects the display screen. The display screen includes, for example, a liquid crystal display (LCD), an organic light-emitting diode (OLED) display screen, and an LED display screen, wherein the LED display screen includes, for example, a micro-LED display screen and a mini-LED display screen. This application embodiment does not limit the type of display screen.

[0135] The material of the back cover 20 may include, for example, opaque materials such as plastic, vegan leather, and fiberglass; or light-transmitting materials such as glass. This application does not limit the material of the back cover 20.

[0136] The middle frame 30 includes an annular outer part 31 and a support (not shown) located within the annular outer part 31 and between the display module 10 and the back cover 20.

[0137] The display module 10, the back cover (also known as the battery cover) 20, and the annular outer part 31 surround a housing cavity, within which are housed a battery, a printed circuit board (PCB) 40, and functional components 50, among other structures. Figure 8(Not shown in the image), the functional device 50 includes a first functional component and a second functional component. The first functional component can be disposed on PCB 40 and electrically connected to PCB 40; the second functional component is not disposed on PCB 40, but is electrically connected to PCB 40. The first functional component may include devices such as a processor, a power supply module (such as a power management chip and / or a charging management module), a display driving circuit, and a measurement circuit, etc., and the second functional component may include devices such as a flash, a camera 55, and a cooling fan. Each device is electrically connected through PCB 40, thereby realizing signal transmission and interaction. The support member can support part of the structure inside the cavity. In the embodiments of this application, the battery 110, n test resistors 121 to 12n, n voltage conversion circuits 131 to 13n, power consumption test circuit 150, reference voltage generation circuit 160, power consumption test controller 170, and microcontroller (MicroController Unit, MCU) 180, etc., can be disposed on PCB 40. The device under test may be disposed on PCB 40 or not, and its position is not specifically limited.

[0138] The processor may include one or more processing units, such as a baseband processor, application processor (AP), modem processor, graphics processing unit (GPU), image signal processor (ISP), controller, memory, video codec, digital signal processor (DSP), and / or neural network processing unit (NPU). Different processing units may be independent devices or integrated into one or more processors.

[0139] The processor may include a memory for storing instructions and data. In some embodiments, the memory in the processor is a cache memory. This memory can store instructions or data that the processor has just used or that are used repeatedly. If the processor needs to use the instruction or data again, it can directly retrieve it from the memory. This avoids repeated accesses, reduces processor waiting time, and thus improves system efficiency. In this embodiment, the memory may store compressed data that needs to be stored and sent by the measurement circuit.

[0140] In some embodiments, the processor may include one or more interfaces. Interfaces may include inter-integrated circuit (I2C) interfaces, serial peripheral interfaces (SPI), inter-integrated circuit sound (I2S) interfaces, pulse code modulation (PCM) interfaces, universal asynchronous receiver / transmitter (UART) interfaces, mobile industry processor interfaces (MIPI), general-purpose input / output (GPIO) interfaces, subscriber identity module (SIM) interfaces, and / or universal serial bus (USB) interfaces, etc.

[0141] The I2C interface is a bidirectional synchronous serial bus, including a serial data line (SDA) and a serial clock line (SCL). In some embodiments, the processor may include multiple I2C buses. The processor can couple to a flash, camera 55, etc., through different I2C bus interfaces. In this embodiment, the processor can couple to a measurement circuit through the I2C interface, enabling the processor and the measurement circuit to communicate through the I2C bus interface, thereby realizing the detection function of the electronic device 100.

[0142] The charging management module receives charging input from the charger, which can be either a wireless or wired charger. While charging the battery, the charging management module can also supply power to the electronic device via the power management module.

[0143] The power management module connects the battery, the charging management module, and the processor. It receives input from the battery and / or the charging management module to power the processor, display screen, camera 55, etc. In some other embodiments, the power management module may be located within the processor. In still other embodiments, the power management module and the charging management module may be located in the same device. The display driver circuit drives the display screen to display images or videos, etc.

[0144] Camera 55 is used to capture still images or videos. An object is projected onto a photosensitive element by an optical image generated through a lens. The photosensitive element can be a charge-coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the light signal into an electrical signal, which is then passed to an ISP for conversion into a digital image signal. The ISP outputs the digital image signal to a DSP for processing. The DSP converts the digital image signal into image signals in standard RGB, YUV, or other formats. In some embodiments, the electronic device may include one or more cameras. A flash is used to provide supplemental lighting for camera 55.

[0145] It is understood that the above description only schematically illustrates some of the components included in the mobile phone 100. The actual mobile phone 100 may have more or fewer components than described above, or combine some components, or separate some components, or have different component arrangements. The illustrated components can be implemented in hardware, software, or a combination of both.

[0146] It should be noted that, Figure 8 In this embodiment, the mobile phone 100 is shaped like a rectangular tablet. In other alternative embodiments, the electronic device can also be shaped like a square tablet, a circular tablet, an elliptical tablet, etc. Of course, the electronic device can also be a foldable electronic device, etc.

[0147] After gaining an overall understanding of the electronic device through the above content, the power consumption test scheme of the embodiments of this application will be described next.

[0148] In existing power consumption testing technologies, the power consumption itself is often relatively high. Therefore, how to reduce the power consumption of power consumption testing has become an urgent technical problem to be solved.

[0149] The inventors discovered through research that power consumption testing often requires signal sampling of electrical devices. However, existing signal sampling methods often consume relatively high power. Therefore, reducing the power consumption of signal sampling has become one of the problems in reducing power consumption during power consumption testing.

[0150] Based on this, embodiments of this application provide a signal sampling circuit, method, and electronic device, which can reduce the power consumption of power consumption testing by reducing the power consumption of signal sampling. It should be noted that when the sampled signal of the electrical device can also be used for other purposes or functions, the power consumption of those other purposes or functions can also be reduced; no specific limitations are imposed in this regard.

[0151] Figure 9A A schematic diagram of a signal sampling method provided in an embodiment of this application is shown. Figure 9A As shown, taking an example with 8 electrical devices, in the first sampling method (i.e., sampling method one), the power consumption test circuit 150 can complete one round of signal sampling for the 8 devices (i.e., n=8 above) within the first period T. Specifically, during each round of signal sampling, the power consumption test circuit 150 can acquire the sampling signal of the first electrical device 141 through the first channel CH0; and the power consumption test circuit 150 can acquire the sampling signal of the second electrical device 142 through the second channel CH1; ...; using the power consumption test circuit 150, the sampling signal of the eighth electrical device 148 can be acquired through the eighth channel CH7.

[0152] It should be noted that, in this embodiment, when power consumption detection is performed on the first electrical device, the first first control switch K0, the second first control switch K1, and the first second control switch S0 are turned on. At this time, the first channel CH0 is turned on, and the current analog-to-digital converter ADC1 can obtain the first current sampling data through the first channel CH0, and the voltage analog-to-digital converter ADC2 can obtain the first voltage sampling data through the first channel CH0. When power consumption detection is performed on the second electrical device, the third first control switch K2, the fourth first control switch K3, and the second second control switch S1 are turned on. At this time, the second channel... When CH1 is turned on, the current analog-to-digital converter ADC1 can obtain the second current sampling data through the second channel CH1, and the voltage analog-to-digital converter ADC2 can obtain the second voltage sampling data through the second channel CH1; ...; when power consumption detection is performed on the 8th electrical device, the 15th first control switch K14, the 16th first control switch K15, and the 8th second control switch S7 are turned on. At this time, the eighth channel CH7 is turned on, and the current analog-to-digital converter ADC1 can obtain the eighth current sampling data through the eighth channel CH7, and the voltage analog-to-digital converter ADC2 can obtain the eighth voltage sampling data through the eighth channel CH7.

[0153] Continue with Figure 9A For example, in the second sampling method (i.e., sampling method two), the power consumption test circuit 150 can complete one round of signal sampling for eight devices in the first half of the first cycle T (within the time interval 0 to T / 2), and then enter sleep mode in the second half of the first cycle T (within the time interval T / 2 to T). Alternatively, it can enter sleep mode in the first half of the cycle and perform one round of signal acquisition in the second half of the cycle, or it can enter sleep mode in the middle half of the cycle (within the time interval 1 / 4T to 3 / 4T). It should be noted that the specific sleep time within the first cycle T is not limited in this embodiment of the application, and it can be set according to the actual situation and specific scenario. In this embodiment of the application, the first cycle T is the cycle or time required for the eight power-consuming devices to complete one round of testing.

[0154] During the sleep state, the power consumption test controller 170 can control the ADC of the power consumption test circuit 150 to turn off, or it can control the ADC to operate in a low-power state according to the actual situation and specific settings; no specific limitation is made in this regard. Optionally, to reduce power consumption, the power consumption test controller 170 can also control the switches in the multiplexer of the power consumption test circuit 150 to turn off. Alternatively, to reduce power consumption, the power consumption test controller 170 can also be in a sleep state, such as a low-power operating state. This embodiment of the application does not impose specific limitations on the sleep state.

[0155] In sampling mode one, the ADC operates at the first sampling frequency f1. In sampling mode two, the sampling frequency of the ADC is increased by 2 times (i.e., 2*f1).

[0156] The inventors discovered through research that the signal sampling frequency (or data output frequency) is the same in both sampling method one and sampling method two, that is, both complete the sampling or output of 8 sampling signals within the first period T. However, the power consumption of sampling method two is lower than that of sampling method one. Therefore, by using the above-mentioned sampling method two, the power consumption of signal sampling can be reduced.

[0157] Furthermore, the applicant should clarify that in the eight samplings of a single round of signal sampling in this application embodiment, the same electrical device can be sampled once (i.e., Figure 9A (As shown in sampling method two in the text), or, the same electrical device can be sampled multiple times.

[0158] For example, such as Figure 9B As shown in sampling mode 2', the first electrical device (via the first channel CH0) can be sampled twice consecutively (or four times consecutively, etc., with no specific limit on the number of consecutive samples). Furthermore, the remaining six signal samples can be taken consecutively from different electrical devices, or samples can be taken from different electrical devices, etc., without restriction.

[0159] For example, such as Figure 9B As shown in sampling mode 2, the first to the fourth electrical device can be sampled twice (the number of samplings is not specifically limited). The two samplings can be discontinuous. That is, the signals of the first to the fourth electrical device can be sampled separately during the first to the fourth signal sampling, and then the signals of the first to the fourth electrical device can be sampled again during the fifth to the eighth signal sampling.

[0160] Optionally, in this embodiment, the power consumption test can be completed in the first 1 / 4 of the first cycle T, and the system can sleep in the last 3 / 4 of the cycle. In this method, the ADC sampling frequency is increased by four times. This implementation method can further reduce the power consumption of signal sampling and improve signal sampling efficiency. It should be noted that in this embodiment, other sampling rates can also be used for ADC sampling, such as 8x speed for the first 1 / 8 of the cycle, or 3 / 2x speed for the first 2 / 3 of the cycle. These can be set according to actual conditions and specific test requirements, and the specific frequency is not limited.

[0161] In other embodiments, Figure 10 A schematic diagram of another signal sampling method provided in an embodiment of this application is shown. Figure 9A and Figure 10 The difference lies in the fact that the power consumption test circuit can perform power consumption testing only on a portion of the connected electrical components. For example, such as Figure 10 As shown, the power consumption test circuit can perform power consumption tests on four electrical components through the first channel CH0 to the fourth channel CH3.

[0162] like Figure 10 As shown, in the third sampling mode (i.e., sampling mode three), the power consumption test circuit 150 can complete one round of signal sampling for four devices (i.e., n=8 above) within the first period T. And, in the fourth sampling mode (i.e., sampling mode four), the power consumption test circuit 150 can complete one round of signal sampling for four devices within the first 1 / 4 period of the first period T (the time from 0 to T / 4), and then sleep during the remaining 3 / 4 period.

[0163] In sampling mode three, the ADC operates at half the speed of the first sampling frequency f1, i.e., 1 / 2f1. In sampling mode four, the sampling frequency of the ADC is increased by 2 times compared to the first sampling frequency (i.e., 2*f1).

[0164] In sampling modes three and four, the signal sampling frequency (or data output frequency) is the same, meaning that four signals are sampled or output within the first period T. However, sampling mode four consumes less power than sampling mode three, thus reducing the power consumption of signal sampling.

[0165] It should be noted that, in the embodiments of this application, the power consumption test circuit can also perform power consumption tests on other numbers of electrical devices. The specific number can be set according to the actual test situation and specific test requirements, and there is no specific limitation on this.

[0166] In some embodiments, Figure 11 This illustration shows another signal sampling method provided in an embodiment of this application. Figure 11Taking the second sampling method described above as an example, the operation of the current analog-to-digital converter ADC1 and the voltage analog-to-digital converter ADC2 will be explained. Figure 11 As shown, the current analog-to-digital converter ADC1 and the voltage analog-to-digital converter ADC2 can sample data at the same frequency (in this embodiment, the data sampling process of the ADC may include data acquisition and analog-to-digital conversion). During this detection process, current sampling data and voltage sampling data can be acquired synchronously.

[0167] For example, the first half of the first period T can include 8 sampling periods. Specifically, in the first sampling period, the current sampling data of the first electrical device (hereinafter referred to as the first current sampling data) is acquired through the current analog-to-digital converter ADC1, and the voltage sampling data of the first electrical device (hereinafter referred to as the first voltage sampling data) is acquired through the voltage analog-to-digital converter ADC2; in the second sampling period, the current sampling data of the second electrical device (hereinafter referred to as the second current sampling data) is acquired through the current analog-to-digital converter ADC1, and the voltage sampling data of the second electrical device (hereinafter referred to as the second voltage sampling data) is acquired through the voltage analog-to-digital converter ADC2; ...; in the eighth sampling period, the current sampling data of the eighth electrical device (hereinafter referred to as the eighth current sampling data) is acquired through the current analog-to-digital converter ADC1, and the voltage sampling data of the eighth electrical device (hereinafter referred to as the eighth voltage sampling data) is acquired through the voltage analog-to-digital converter ADC2.

[0168] It should be noted that the sampling method provided in the embodiments of this application can be applied to Figure 2 and Figure 3 The circuit structure shown demonstrates that, through the embodiments of this application, voltage sampling data and current sampling data can be accurately acquired.

[0169] Furthermore, in this embodiment, the current analog-to-digital converter ADC1 enters a sleep state, which can also be referred to as the current signal sampling circuit 151 entering a sleep state. Similarly, the voltage analog-to-digital converter ADC2 enters a sleep state, which can also be referred to as the voltage signal sampling circuit 152 entering a sleep state.

[0170] In other embodiments, this application also provides another power consumption test circuit. Figure 12 A schematic diagram of another power consumption test circuit provided in an embodiment of this application is shown. Figure 12 and Figure 5 The difference in the power consumption test circuit shown is that the voltage multiplexer MUX02 also includes a common input pin V_BUS_IN (if n is 8, then the common input pin is the 9th input pin of the voltage multiplexer MUX02).

[0171] The common input pin V_BUS_IN can be connected to the common terminal of the eight power supply circuits. For example, V_BUS_IN can be connected to the positive terminal of battery 110, and correspondingly, V_BUS_IN can sample the voltage of battery 110. See also: [example example follows] Figure 2 The common input pin V_BUS_IN can be connected to the positive terminal A0 of the power supply VIN0.

[0172] Accordingly, Figure 13 A schematic diagram of a voltage multiplexer provided in an embodiment of this application is shown. (Comparison) Figure 13 and Figure 6 It can be seen that, Figure 12 The voltage multiplexer MUX02 may also include a ninth second control switch S8. The common input pin V_BUS_IN (the ninth input pin of the voltage multiplexer MUX02) is connected to the output pin B3 of the voltage multiplexer MUX02 via the ninth second control switch K8. Accordingly, when the ninth second control switch K8 is closed, the power consumption test circuit 150 can obtain the power supply voltage of the battery 110 through the common input pin V_BUS_IN.

[0173] It should be noted that since all electrical components are powered by battery 110, the first voltage signal of each component can theoretically be obtained from the positive terminal voltage of battery 110. For example, the power consumption of each component can be calculated directly using the product of the battery voltage and the current in each power supply circuit. Therefore, the battery voltage acquired by the common input pin V_BUS_IN can be used as the voltage sampling data for the eight electrical components. In one example, for Figure 2 The circuit structure shown allows the battery voltage acquired from the common input pin V_BUS_IN to be directly used as voltage sampling data for the eight electrical components. In another example, for Figure 3 The circuit structure shown can acquire the battery voltage through the common input pin V_BUS_IN, calculate the voltage of each electrical component based on the voltage conversion ratio of the voltage conversion circuit, and then calculate the power consumption based on the calculated voltage of each electrical component.

[0174] Based on the above Figure 12 The circuit structure shown in one embodiment also provides another signal sampling method. Figure 14 This illustration shows another signal sampling method provided in an embodiment of this application.

[0175] Figure 14 and Figure 11The difference is that the voltage analog-to-digital converter ADC2 can obtain the battery voltage through the common input pin V_BUS_IN in the first sampling cycle, and use the battery voltage as voltage sampling data for 8 electrical devices.

[0176] Accordingly, after the current analog-to-digital converter ADC1 acquires the current sampling data of each of the eight electrical devices through eight sampling cycles, it can calculate the power consumption of each electrical device based on the current sampling data and the voltage sampling data of each electrical device.

[0177] In this embodiment, the voltage analog-to-digital converter ADC2 can sample voltage in one sampling cycle and sleep during the remaining time, thereby further reducing signal sampling power consumption.

[0178] Based on the above Figure 12 The circuit structure shown is provided in another embodiment, and in yet another embodiment, this application also provides a different signal sampling method. Figure 15 A schematic diagram of another signal sampling method provided in an embodiment of this application is shown.

[0179] Figure 15 and Figure 14 The difference lies in the fact that the voltage analog-to-digital converter ADC2 can also collect voltage sampling data again through the common input pin V_BUS_IN during sleep time, for example, as Figure 15 As shown, during the fifth sampling cycle, when the current analog-to-digital converter ADC1 acquires the voltage sampling data of the fifth electrical device through the fifth channel CH4, the voltage analog-to-digital converter ADC2 can again acquire the voltage sampling data through the common input pin V_BUS_IN.

[0180] This embodiment avoids the problem of inaccurate sampling data caused by long voltage sampling data acquisition time intervals, thereby reducing sampling power consumption and further improving data sampling accuracy.

[0181] In some embodiments, to further reduce sampling power consumption, during the sleep mode of the above sampling method, the power consumption test controller 170 can also control the driver in the reference voltage generation circuit 160 to disconnect. For example, when the current analog-to-digital converter ADC1 is in sleep mode, the current driver DR1 can be controlled to turn off. And when the current analog-to-digital converter ADC1 exits sleep mode and resumes operation, the current driver DR1 can be controlled to start. As another example, when the voltage analog-to-digital converter ADC2 is in sleep mode, the voltage driver DR2 can be controlled to turn off. And when the voltage analog-to-digital converter ADC2 exits sleep mode and resumes operation, the voltage driver DR2 can be controlled to start.

[0182] However, the applicant discovered through research that after the hibernation period, during the turn-on process of the current driver DR1 and the voltage driver DR2, the change in charge of the noise reduction capacitor Cc will cause the reference voltage to oscillate.

[0183] For example, Figure 16 This diagram illustrates a variation of a reference voltage according to an embodiment of this application. Figure 16 As shown, the change in the reference voltage is illustrated by curve L1.

[0184] Because current driver DR1 and voltage driver DR2 are turned off during sleep mode to save power, and when current signal sampling is required, current driver DR1 will turn on from the off state. At this time, such as... Figure 16 As shown, due to the noise reduction capacitor Cc at the op-amp input of current driver DR1, the reference voltage will rise momentarily when current driver DR1 is turned on. Also, when voltage signal sampling is required, voltage driver DR2 will change from the off state to the on state. At this time, continue to refer to... Figure 16 Because of the noise reduction capacitor Cc at the op-amp input of voltage driver DR2, the moment DR2 turns on, it charges Cc, causing a sudden drop in the reference voltage input. Furthermore, since the noise reduction capacitor Cc is variable, it decreases after charging to a certain level. According to Q=CV, as the capacitance decreases, the reference voltage input increases again, eventually reaching a stable value after a period of time. For example, simulations of the reference voltage during the turn-on process of current driver DR1 and voltage driver DR2 show that the time delay required to stabilize the reference voltage to one-thousandth of an error is 356µs. This delay significantly affects the measurement accuracy of the sampled signal.

[0185] Based on this, in some embodiments, this application provides another sampling scheme. In this sampling scheme, the voltage driver or current driver can be turned on in advance before the sleep state ends, so as to improve the measurement accuracy of the sampling signal.

[0186] Figure 17 A schematic diagram of another signal sampling method provided in an embodiment of this application is shown. For example... Figure 17As shown, the first quarter of the first period T can include four sampling periods. Specifically, in the first sampling period, the current sampling data of the first electrical device (hereinafter referred to as the first current sampling data) is acquired through the current analog-to-digital converter ADC1, and the voltage sampling data of the first electrical device (hereinafter referred to as the first voltage sampling data) is acquired through the voltage analog-to-digital converter ADC2; in the second sampling period, the current sampling data of the second electrical device (hereinafter referred to as the second current sampling data) is acquired through the current analog-to-digital converter ADC1, and the voltage sampling data of the second electrical device (hereinafter referred to as the second voltage sampling data) is acquired through the voltage analog-to-digital converter ADC2; ...; in the fourth sampling period, the current sampling data of the fourth electrical device (hereinafter referred to as the fourth current sampling data) is acquired through the current analog-to-digital converter ADC1, and the voltage sampling data of the fourth electrical device (hereinafter referred to as the fourth voltage sampling data) is acquired through the voltage analog-to-digital converter ADC2.

[0187] Furthermore, after the fourth sampling cycle, the power consumption test control circuit 160 can simultaneously turn off the current driver DR1 and the voltage driver DR2. The power consumption test control circuit 160 can also simultaneously turn off the current analog-to-digital converter ADC1 and the voltage analog-to-digital converter ADC2. For example, if the current analog-to-digital converter ADC1 and the voltage analog-to-digital converter ADC2 are located on the detection chip, the detection chip can be controlled to enter a sleep mode. For instance, the power consumption test circuit 150 containing the current analog-to-digital converter ADC1 and the voltage analog-to-digital converter ADC2 can be implemented as a power consumption test chip, which can be controlled to enter a sleep mode after the fourth sampling cycle. It should be noted that the power consumption test controller can be located on or outside the power consumption test chip, and it can choose to enter a sleep mode or not; there are no specific limitations on this.

[0188] Furthermore, before the start of the second first cycle, the current driver DR1 and voltage driver DR2 can be turned on in advance by a first preset time to allow for the stabilization time of the reference voltage. This ensures that a stable reference voltage can be obtained when the current-to-digital converter ADC1 and voltage-to-digital converter ADC2 start working, improving test accuracy. The first preset time can be longer than the time required for the reference voltage to stabilize after the current driver DR1 and voltage driver DR2 are turned on (hereinafter referred to as the stabilization time). For example, in this embodiment, the first preset time can be set by simulating the stabilization time. For instance, if the simulation determines the stabilization time to be 356µs, the first preset time can be set to a value greater than 356µs.

[0189] In one embodiment, the current analog-to-digital converter ADC1 and the voltage analog-to-digital converter ADC2 can be turned on at the start of a new first cycle. Alternatively, the current analog-to-digital converter ADC1 and the voltage analog-to-digital converter ADC2 can be turned on in advance before the start of a new first cycle, without any specific limitation.

[0190] In another embodiment, to avoid the influence of the settling time of the preset operational amplifier PGA1 on the differential voltage, the first control switch that needs to be turned on in the current multiplexer MUX01 can be turned on in advance for a second preset duration before the first cycle. The first preset duration can be longer than or equal to the settling time of the preset operational amplifier PGA1.

[0191] In some other embodiments, Figure 18 A schematic diagram of another signal sampling method provided in an embodiment of this application is shown. Figure 18 and Figure 14 The difference lies in that, after the first sampling period ends (i.e., after the battery sampling voltage is sampled), the power consumption test controller 170 turns off the voltage driver DR2. And, after the eighth sampling period ends (i.e., after the current sampling signal is sampled), the power consumption test controller 170 turns off the current driver DR1.

[0192] Furthermore, before the start of a new first cycle, the current driver DR1 and voltage driver DR2 can be turned on in advance for a preset time to allow time for the reference voltage to stabilize. This ensures that a stable reference voltage can be obtained when the current analog-to-digital converter ADC1 and the voltage analog-to-digital converter ADC2 start working, thus improving the test accuracy.

[0193] It should be noted that the first preset duration and other details can be found in the relevant descriptions of the above embodiments, and will not be repeated here.

[0194] In yet another embodiment, Figure 19 A schematic diagram of another signal sampling method provided in an embodiment of this application is shown. For example... Figure 19 As shown, the power consumption test circuit can acquire the power consumption mode of the electronic device. When the electronic device is in normal power consumption mode, signal sampling of eight electrical components can be completed within the first half of the first cycle T. It then enters sleep mode during the second half of the first cycle T. Similarly, when the electronic device is in high power consumption mode, signal sampling of the eight electrical components can be completed within the first half of the first cycle T. Finally, signal sampling of the eight electrical components is performed again during the second half of the first cycle T.

[0195] High-power mode can be a mode that requires the electronic device to run at full speed, such as running games, running multiple tasks, or a lab mode. Normal power mode can be the mode in which the phone runs normally.

[0196] It should be noted that the data transmission rates differ between high-power mode and low-power mode, and one or more of the sleep mode's operation and duration may also differ. Optionally, the power devices used for signal sampling can differ between high-power mode and normal power mode. For example, in normal mode, signals may be sampled from eight power devices, while in high-power mode, signals may be sampled from four power devices related to the CPU.

[0197] It should be noted that the embodiments of this application can also be applied to standby mode, for example... Figure 20 A schematic diagram of another signal sampling method provided in an embodiment of this application is shown. Figure 20 and Figure 19 The difference lies in that, in low-power mode, signal sampling of the four necessary power-consuming devices is completed within the first quarter of the first cycle T. Furthermore, the device enters a sleep state during the remaining three-quarters of the first cycle T. In other words, the power-consuming devices used for signal sampling can differ between low-power mode and other power modes (normal or high power), and the data transmission frequency can also differ.

[0198] Alternatively, standby mode can collect data in one round, while sleep mode can collect data in 15 rounds, without any specific limitation. In other words, the duration of collecting data in a single round can differ between low-power mode and other power consumption modes (normal power consumption or high power consumption).

[0199] This embodiment allows for the use of different signal sampling schemes in different modes, balancing signal sampling requirements with power consumption, thus achieving power optimization.

[0200] In yet another embodiment, Figure 21 A schematic diagram of the structure of a power consumption test controller provided in an embodiment of this application is shown. Figure 21 As shown, the power consumption test controller 180 may include eight first registers SN0 to SN8. For example, the data written to the first register can be 3 bits. It should be noted that when a power consumption test circuit can connect to more electrical devices, such as 16, the data written to the first register can be 4 bits. The length of the written data can be determined according to the number of electrical devices connected to the power consumption test circuit, and there is no specific limitation on this.

[0201] The first register SN0 is used to set the first electrical device to be tested in each round of testing, the second register SN1 is used to set the second electrical device to be tested in each round of testing, and so on, with the eighth register SN7 used to set the eighth electrical device to be tested in each round of testing. For example, each of the first registers can be set by writing the serial number of the electrical device.

[0202] For example, such as Figure 21 As shown, in each round of sampling, the first electrical device needs to be tested sequentially through the first channel CH0, the eighth electrical device through the eighth channel CH7, the sixth electrical device through the sixth channel CH5, and the fourth electrical device through the fourth channel CH3. Therefore, the MCU180 can write the serial number 0 of the first electrical device to the first register SN0, the serial number 7 of the eighth electrical device to the second register SN1, the serial number 5 of the sixth electrical device to the third register SN2, and the serial number 3 of the fourth electrical device to the fourth register SN3.

[0203] In some embodiments, the power consumption test controller 180 may further include a second register SLEN. Exemplarily, the data written to the second register SLEN may be 3 bits. The length of the data written to the second register SLEN can be found in the relevant description of the first register, and will not be repeated here.

[0204] The second register, SLEN, can be set to the number of electrical devices sampled in each round of signal sampling. For example, see [link to previous section]. Figure 21 If four electrical devices need to be tested in each round of sampling, then the quantity 4 can be written into the second register SLEN.

[0205] In some embodiments, the power consumption test controller 180 may further include a third register BYNS for setting the sleep duration. Exemplarily, the data written to the third register BYNS may be 3 bits (or more). The length of the data written to the third register BYNS can be found in the description of the first register, and will not be repeated here.

[0206] The third register BYNS can be set to the sleep duration. For example, the third register BYNS can be set to a first quantity. Then the duration of each round of signal detection is equal to the product of the duration of each round of signal detection and the first quantity. For instance, if the third register BYNS is set to 0, no sleep occurs. For example, when sampling signals according to the above sampling method one, the third register BYNS can be set to 0. Or, for example, if the third register BYNS is set to 1, the sleep duration is the same as the sampling duration, for example, according to... Figure 9A When sampling the signal using sampling mode two, the third register BYNS can be set to 1. For example, if the third register BYNS is set to 3, the sleep duration is three times the sampling duration, for example, according to... Figure 10 When sampling the signal using sampling mode three, the third register BYNS can be set to 3.

[0207] It should be noted that the power consumption test controller 180 can also be configured with other registers to control the signal sampling process, and the MCU180 can write data to each register.

[0208] In some other embodiments, Figure 22 A schematic diagram of an exemplary battery structure provided in an embodiment of this application is shown. For example... Figure 22 As shown, the battery 110 may include four cells P1 to P4, and each electrical component is connected to the positive terminal of cell P4. Figure 13 The common input pin V_BUS_IN is connected to the positive terminal A0 of cell P4.

[0209] In some other embodiments, Figure 23 A schematic diagram of an exemplary battery structure provided in an embodiment of this application is shown. For example... Figure 23 As shown, each electrical component is connected to the positive terminal of a different battery cell, so it can be arranged according to... Figure 17 Sampling is performed using the sampling method shown. Alternatively, a common input pin V_BUS_IN can be set at the positive terminal of each cell; there are no specific restrictions on this.

[0210] After introducing the above sampling methods, the signal sampling methods involved in the embodiments of this application will be described next.

[0211] Figure 24 This illustration shows a flowchart of a signal sampling method provided in an embodiment of this application; as shown Figure 24 As shown, the signal sampling method includes the following steps:

[0212] S2401, in the i-th sampling period, the power consumption test controller 170 controls the first control switches K2i-2 and K2i-1 of the current multiplexer MUX01 to turn on. Also, the power consumption test controller controls the second control switch S8 of the voltage multiplexer MUX02 to turn on. Where i = 1, 2, ..., 8.

[0213] S2402, the preset operational amplifier PGA1 acquires the current sampling signal sent by the current multiplexer MUX01, generates the i-th differential voltage, and the preset operational amplifier PGA1 outputs the i-th differential voltage to the current analog-to-digital converter ADC1.

[0214] S2403, the power consumption test controller 170 controls the current analog-to-digital converter ADC1 to perform analog-to-digital conversion on the i-th differential voltage to obtain the i-th digital current signal.

[0215] S2404, the voltage multiplexer MUX02 outputs the battery voltage to the voltage analog-to-digital converter ADC2, and the power consumption test controller 170 controls the voltage analog-to-digital converter ADC2 to perform analog-to-digital conversion on the first voltage sampling signal to obtain the i-th digital voltage signal.

[0216] S2405, after the eighth sampling cycle, the power consumption test controller 170 controls the current multiplexer MUX01 and the current analog-to-digital converter ADC1 to enter sleep mode.

[0217] S2406, after the first cycle T ends, proceed to the next first cycle and return to step S2401.

[0218] Figure 25 This paper illustrates a flowchart of another signal sampling method provided in an embodiment of this application; as shown. Figure 25 As shown, the signal sampling method includes the following steps:

[0219] S2501, in the first sampling period, the power consumption test controller 170 controls the first control switches K0 and K1 of the current multiplexer MUX01 to turn on. Also, the power consumption test controller controls the second control switch S0 of the voltage multiplexer MUX02 to turn on.

[0220] S2502, the preset operational amplifier PGA1 acquires the current sampling signal sent by the current multiplexer MUX01, generates the first differential voltage, and the preset operational amplifier PGA1 outputs the first differential voltage to the current analog-to-digital converter ADC1.

[0221] S2503, the power consumption test controller 170 controls the current analog-to-digital converter ADC1 to perform analog-to-digital conversion on the first differential voltage to obtain the first digital current signal.

[0222] The S2504 voltage multiplexer MUX02 obtains the battery sampling voltage through the common input pin V_BUS_IN and outputs the battery sampling voltage to the voltage analog-to-digital converter ADC2.

[0223] S2505, the power consumption test controller 170 controls the voltage analog-to-digital converter ADC2 to perform analog-to-digital conversion on the battery sample voltage to obtain the target digital voltage signal.

[0224] S2506, after the first sampling period ends, the power consumption test controller 170 controls the voltage analog-to-digital converter ADC2 to enter sleep mode.

[0225] S2507, in the j-th sampling period, the power consumption test controller 170 controls the first control switches K0 and K1 of the current multiplexer MUX01 to turn on. Also, the power consumption test controller controls the second control switch S0 of the voltage multiplexer MUX02 to turn on. Where j = 2, ..., 8.

[0226] S2508, the preset operational amplifier PGA1 acquires the current sampling signal sent by the current multiplexer MUX01, generates the j-th differential voltage, and the preset operational amplifier PGA1 outputs the j-th differential voltage to the current analog-to-digital converter ADC1.

[0227] S2509, the power consumption test controller 170 controls the current analog-to-digital converter ADC1 to perform analog-to-digital conversion on the j-th differential voltage to obtain the j-th digital current signal.

[0228] After the eighth sampling cycle, the power consumption test controller 170 controls the current multiplexer MUX01 to enter sleep mode.

[0229] S2511, after the first cycle T ends, proceed to the next first cycle and return to step S2501.

[0230] Figure 26 This illustration shows a flowchart of yet another signal sampling method provided in an embodiment of this application; as shown Figure 26 As shown, the signal sampling method includes the following steps:

[0231] S2601, before the start of the first sampling cycle, turns on the current driver DR1 and the voltage driver DR2 for a first preset time.

[0232] S2602, in the i-th sampling period, the power consumption test controller 170 controls the first control switches K2i-2 and K2i-1 of the current multiplexer MUX01 to turn on. Also, the power consumption test controller controls the second control switch S8 of the voltage multiplexer MUX02 to turn on. Where i = 1, 2, ..., 8.

[0233] S2603, the preset operational amplifier PGA1 acquires the current sampling signal sent by the current multiplexer MUX01, generates the i-th differential voltage, and the preset operational amplifier PGA1 outputs the i-th differential voltage to the current analog-to-digital converter ADC1.

[0234] S2604, the power consumption test controller 170 controls the current analog-to-digital converter ADC1 to perform analog-to-digital conversion on the i-th differential voltage to obtain the i-th digital current signal.

[0235] S2605, the voltage multiplexer MUX02 outputs the battery voltage to the voltage analog-to-digital converter ADC2, and the power consumption test controller 170 controls the voltage analog-to-digital converter ADC2 to perform analog-to-digital conversion on the first voltage sampling signal to obtain the i-th digital voltage signal.

[0236] S2606, after the eighth sampling cycle, the power consumption test controller 170 controls the current multiplexer MUX01 and the current analog-to-digital converter ADC1 to enter sleep mode.

[0237] S2607, after the eighth sampling cycle, turns off current driver DR1 and voltage driver DR2.

[0238] S2608, before the next first cycle, turn on the current driver DR1 and voltage driver DR2 for a first preset time, and return to step S2601 in the next first cycle.

[0239] Figure 27 This illustration shows a flowchart of another signal sampling method provided in an embodiment of this application; as shown Figure 27 As shown, the signal sampling method includes the following steps:

[0240] S2701, before the start of the first sampling cycle, turns on the current driver DR1 and the voltage driver DR2 for a first preset time.

[0241] S2702, in the first sampling period, the power consumption test controller 170 controls the first control switches K0 and K1 of the current multiplexer MUX01 to turn on. Also, the power consumption test controller controls the second control switch S0 of the voltage multiplexer MUX02 to turn on.

[0242] S2703, the preset operational amplifier PGA1 acquires the current sampling signal sent by the current multiplexer MUX01, generates the first differential voltage, and the preset operational amplifier PGA1 outputs the first differential voltage to the current analog-to-digital converter ADC1.

[0243] S2704, the power consumption test controller 170 controls the current analog-to-digital converter ADC1 to perform analog-to-digital conversion on the first differential voltage to obtain the first digital current signal.

[0244] The S2705 voltage multiplexer MUX02 obtains the battery sampling voltage through the common input pin V_BUS_IN and outputs the battery sampling voltage to the voltage analog-to-digital converter ADC2.

[0245] S2706, the power consumption test controller 170 controls the voltage analog-to-digital converter ADC2 to perform analog-to-digital conversion on the battery sample voltage to obtain the target digital voltage signal.

[0246] S2707, after the first sampling period ends, the power consumption test controller 170 controls the voltage analog-to-digital converter ADC2 to enter sleep mode.

[0247] S2708, after the first sampling period ends, turns off the voltage driver DR2.

[0248] S2709, in the j-th sampling period, the power consumption test controller 170 controls the first control switches K0 and K1 of the current multiplexer MUX01 to turn on. Also, the power consumption test controller controls the second control switch S0 of the voltage multiplexer MUX02 to turn on. Where j = 2, ..., 8.

[0249] S2710, the preset operational amplifier PGA1 acquires the current sampling signal sent by the current multiplexer MUX01, generates the j-th differential voltage, and the preset operational amplifier PGA1 outputs the j-th differential voltage to the current analog-to-digital converter ADC1.

[0250] S2711, the power consumption test controller 170 controls the current analog-to-digital converter ADC1 to perform analog-to-digital conversion on the j-th differential voltage to obtain the j-th digital current signal.

[0251] S2712, after the eighth sampling cycle, the power consumption test controller 170 controls the current multiplexer MUX01 to enter sleep mode.

[0252] S2713, before the next first cycle, the power consumption test controller 170 turns on the current driver DR1 and the voltage driver DR2 for a first preset time in advance, and returns to step S2701 in the next first cycle.

[0253] Figure 28 A schematic flowchart of another signal sampling method provided in an embodiment of this application is shown. Figure 28 As shown, the signal sampling method includes the following steps:

[0254] S2801, obtain the power consumption mode of the electronic device.

[0255] S2802, when the electronic device is in a high-power mode, sampling is performed according to the first sampling scheme corresponding to the high-power mode.

[0256] S2803, when the electronic device is in normal power consumption mode, samples according to the second sampling scheme of normal power consumption mode.

[0257] S2804, when the electronic device is in low power mode, samples according to the third sampling scheme of low power mode.

[0258] It is understood that, in order to achieve the above-mentioned functions, electronic devices include hardware and / or software modules that perform the respective functions. Based on the algorithmic steps of the examples described in the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed by hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in conjunction with the embodiments, but such implementation should not be considered beyond the scope of this application.

[0259] The steps performed by the electronic device 100 in the signal sampling method provided in the above-described embodiments of this application can also be performed by a chip system included in the electronic device 100. This chip system may include a processor and a Bluetooth chip. The chip system may be coupled to a memory, enabling it to call a computer program stored in the memory during runtime to implement the steps performed by the electronic device 100. The processor in the chip system may be an application processor or a non-application processor.

[0260] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A signal sampling circuit, characterized by comprising: Included in electronic devices, including: The signal sampling module includes n input terminals and an output terminal. Each input terminal corresponds to a power-consuming device of the electronic device. Each input terminal is used to acquire the sampling signal of the corresponding power-consuming device, where n is a positive integer greater than or equal to 2. The controller is configured to identify m devices under test from n electrical devices, and to perform at least one round of data sampling on the m devices under test at a first sampling frequency, wherein m is a positive integer less than or equal to n. In each round of data sampling, the controller is used to: In the first time period of m first sampling cycles, the signal sampling module is used to sample the signals of the m devices under test. Each first sampling cycle corresponds to one device under test. In each first sampling cycle, the signal sampling module samples the signal of the corresponding device under test at a second sampling frequency to obtain the first sampling signal of the device under test corresponding to each first sampling cycle. During the second time period, the signal sampling module is kept in a sleep state. Wherein, the second sampling frequency is a first multiple of the first sampling frequency, the first multiple being equal to the ratio of the first duration to the second duration, wherein the first duration is the sum of the duration of the first time period and the duration of the second time period, and the second duration is the duration of the first time period.

2. The signal sampling circuit of claim 1, wherein, The sampling signal includes a current sampling signal, and the signal sampling module includes: First reuse module, Preset amplifier, The first analog-to-digital converter, The controller is further configured to: in the i-th first sampling period, control the first multiplexing module to output the current sampling signal of the i-th device under test; the preset amplifier is configured to perform differential operation on the current sampling signal to obtain the differential voltage of the i-th device under test; and control the first analog-to-digital converter to calculate the differential voltage of the i-th device under test to obtain the current sampling signal in digital signal form of the i-th device under test; wherein, i is an integer greater than or equal to 1 and less than or equal to m; The controller is also configured to shut down the first analog-to-digital converter during the second time period.

3. The signal sampling circuit of claim 1 or 2, wherein The first sampling signal includes a voltage sampling signal, and the signal sampling module includes: Second reuse module, Second analog-to-digital converter, The controller is also configured to: in the i-th first sampling period, control the second multiplexing module to output the voltage sampling signal of the i-th device under test, and control the second analog-to-digital converter to calculate the voltage sampling signal of the i-th device under test to obtain the voltage sampling signal of the i-th device under test in digital signal form; The controller is also configured to shut down the second analog-to-digital converter during the second time period.

4. The signal sampling circuit according to claim 1 or 2, characterized in that, The sampling signal includes a voltage sampling signal, and the signal sampling module includes: The third multiplexing module includes a first input terminal, which is connected to the positive terminal of the battery of the electronic device; Second analog-to-digital converter, The controller is also configured to: in the first sampling period, control the third multiplexing module to output the voltage sampling signal of the battery, control the second analog-to-digital converter to calculate the sampling signal of the battery to obtain the voltage sampling signal in digital form of the battery, and determine the voltage sampling signal in digital form of the battery as the voltage sampling signal of the m devices under test; The controller is also configured to turn off the second analog-to-digital converter after the first sampling period ends.

5. The signal sampling circuit of any one of claims 1-4, wherein, The signal sampling circuit further includes: A reference voltage source is used to generate a reference voltage. A driving module is used to drive a reference voltage to obtain a reference voltage, and to output the reference voltage to the signal sampling module; The controller is also used for: After the first time period ends, the driver module is turned off; and it is also used to turn the driver module on at the first moment. Wherein, the first moment is earlier than the end moment of the second time period, and the difference between the first moment and the end moment is equal to a preset duration.

6. The signal sampling circuit according to claim 4, characterized in that, A reference voltage source is used to generate a reference voltage. The first driving module is used to drive the reference voltage to obtain the reference voltage, and to output the reference voltage to the third analog-to-digital converter; The controller is also used for: After the first sampling period ends, the first driving module is turned off; and it is also used to turn on the first driving module at a first moment. Wherein, the first moment is earlier than the end moment of the second time period, and the difference between the first moment and the end moment is equal to a preset duration.

7. The signal sampling circuit of claim 1, wherein, The controller includes one or more of a first register, a second register, and a third register; The first register is used to set the test order of the m devices under test; The second register is used to set the number of devices under test; The third register is used to set the duration of the second time period.

8. The signal sampling circuit according to claim 1, characterized in that, The controller is also configured to acquire the operating mode of the electronic device; when the electronic device is in the first mode, to perform at least one round of data sampling on the m devices under test according to the first sampling frequency. Furthermore, when the electronic device is in the second mode, k devices under test are determined from the n electrical devices, and the k devices under test are sampled for at least one round of data sampling at a third sampling frequency.

9. The signal sampling circuit according to claim 8, characterized in that, In each round of data sampling for the k devices under test, the controller is used to: In the k second sampling periods of the third time period, the signal sampling module is used to sample the signals of the k devices under test. Each second sampling period corresponds to one device under test. In each second sampling period, the signal sampling module samples the signal of the corresponding device under test at a fourth sampling frequency to obtain the second sampling signal of the device under test corresponding to each second sampling period.

10. The signal sampling circuit of claim 9, wherein, In each round of data sampling for the k devices under test, the controller is further configured to: During the fourth time period, the signal sampling module is kept in a sleep state.

11. The signal sampling circuit according to any one of claims 8-10, characterized in that, The first mode is one of a first power consumption mode and a second power consumption mode, and the second mode is the other of the first power consumption mode and the second power consumption mode. The power consumption of the first electronic device in the first power consumption mode is lower than that in the second power consumption mode.

12. A signal sampling circuit, comprising: The method, applied to the signal sampling circuit as described in any one of claims 1-11, comprises: The controller identifies m devices under test from n electrical devices and performs at least one round of data sampling on the m devices under test according to a first sampling frequency, where m is a positive integer less than or equal to n. In each round of data sampling, the following steps are performed: In the first time period of m first sampling cycles, the signal sampling module is used to sample the signals of the m devices under test. Each first sampling cycle corresponds to one device under test. In each first sampling cycle, the signal sampling module samples the signal of the corresponding device under test at a second sampling frequency to obtain the first sampling signal of the device under test corresponding to each first sampling cycle. During the second time period, the signal sampling module is kept in a sleep state. Wherein, the second sampling frequency is a first multiple of the first sampling frequency, the first multiple being equal to the ratio of the first duration to the second duration, wherein the first duration is the sum of the duration of the first time period and the duration of the second time period, and the second duration is the duration of the first time period.

13. An electronic device, comprising: include: n electrical components; The signal sampling module includes n input terminals and an output terminal. Each input terminal corresponds to a power-consuming device of the electronic device. Each input terminal is used to acquire the sampling signal of the corresponding power-consuming device, where n is a positive integer greater than or equal to 2. The controller is configured to determine m devices under test from the n electrical devices, and to perform at least one round of data sampling on the m devices under test according to a first sampling frequency, wherein m is a positive integer less than or equal to n. In each round of data sampling, the controller is used to: In the first time period of m first sampling cycles, the signal sampling module is used to sample the signals of the m devices under test. Each first sampling cycle corresponds to one device under test. In each first sampling cycle, the signal sampling module samples the signal of the corresponding device under test at a second sampling frequency to obtain the first sampling signal of the device under test corresponding to each first sampling cycle. During the second time period, the signal sampling module is kept in a sleep state. Wherein, the second sampling frequency is a first multiple of the first sampling frequency, the first multiple being equal to the ratio of the first duration to the second duration, wherein the first duration is the sum of the duration of the first time period and the duration of the second time period, and the second duration is the duration of the first time period.

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