Signal processing apparatus, signal processing method thereof, control apparatus, and storage medium

Abstract

The invention discloses a signal processing device, a signal processing method thereof, a control device and a storage medium. The device comprises a DA converter; the CPU is provided with an ADC module and an IO interface, and the ADC module is connected with the output end of the DA converter; comprising a plurality of signal receiving ports, and an output end of the modulation circuit is connected with an input end of the DA converter; the modulation circuit modulates all the received external signals into first PWM waves and sends the first PWM waves to an ADC module of the CPU through a DA converter; and the CPU generates a second PWM wave from the signal output by the ADC module based on a target demand, converts the second PWM wave into a plurality of digital signals and outputs the digital signals from the IO interface. According to the invention, the modulation circuit and the CPU are combined, a plurality of digital signals are converted into a single PWM signal and a single PWM signal is converted into a plurality of digital signals, and a single CPU can complete the input and output of the plurality of digital signals, thereby reducing the power consumption during the realization of the IO demand of the terminal equipment.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of signal processing technology, and in particular to a signal processing apparatus, signal processing method, control device, and storage medium thereof. Background Technology

[0002] In the field of distribution network automation, terminal equipment (including DTU and FTU equipment) requires a large number of remote signaling signals to achieve information interaction with other equipment in the distribution network system, and also requires a large number of IO outputs to control multiple LEDs to indicate the current status.

[0003] In existing technologies, the I / O requirements of terminal devices are met in two ways: The first is to use a CPU in conjunction with an external expansion chip (including an FPGA chip or a CPLD chip). The CPU receives and processes remote signaling signals, while the external expansion chip generates and sends output signals to control LEDs. The second is to use multiple CPUs. For example, assuming two CPUs, one receives and processes remote signaling signals, while the other generates and sends output signals to control LEDs. The first approach requires more I / O interfaces for communication between the CPU and the external expansion chip, while the second approach requires a larger minimum CPU system. Both approaches significantly increase the hardware cost of the product, and the power consumption of multiple chips operating simultaneously is also high. Summary of the Invention

[0004] This application provides a signal processing device, signal processing method, control device, and storage medium, which can effectively reduce power consumption when fulfilling the I / O requirements of terminal devices.

[0005] In a first aspect, embodiments of this application provide a signal processing apparatus, comprising: DA converter; The CPU is equipped with an ADC module and an I / O interface, and the ADC module is connected to the output of the DA converter. A modulation circuit, comprising multiple signal receiving ports, wherein the output of the modulation circuit is connected to the input of the DA converter; The modulation circuit can receive external signals from the signal receiving port, modulate all the received external signals into a first PWM wave, and convert the first PWM wave into an analog signal through the DA converter and send it to the ADC module of the CPU. The CPU can convert the analog signal into a second PWM wave through the ADC module based on the target requirements, convert the second PWM wave into multiple digital signals, and output the digital signals from the IO interface to the target device corresponding to the target requirements.

[0006] In some embodiments, the output of the modulation circuit is connected to the I / O interface.

[0007] In some embodiments, the modulation circuit includes: The modulation circuit modulates the external signals received from all of the signal receiving ports into the first PWM wave and sends the first PWM wave to the DA converter. The DA converter converts the first PWM wave into an analog signal and sends the analog signal to the CPU; The CPU determines the signal state of each of the external signals based on the first mapping table and the analog quantity, wherein the first mapping table is used to indicate the mapping relationship between the analog quantity and the signal state of the external signal; In response to the target requirement, the CPU converts the analog signal into a second PWM wave through the ADC module, converts the second PWM wave into multiple digital signals, and outputs the digital signals from the IO interface to the target device corresponding to the target requirement.

[0008] In some embodiments, the output terminal of the modulation circuit is connected to an I / O interface, and after the modulation circuit modulates the external signals received from all the signal receiving ports into the first PWM wave, the method further includes: The modulation circuit sends the first PWM wave to the IO interface, wherein the first PWM wave corresponds to a reference duty cycle; The CPU determines the signal state of each of the external signals based on the second mapping table and the reference duty cycle, wherein the second mapping table is used to indicate the mapping relationship between the duty cycle of the PWM wave and the signal state of the external signal.

[0009] In some embodiments, the CPU determines the signal state of each of the external signals based on a first mapping table and the analog quantity, including: Determine the state of the first target signal corresponding to the analog quantity from the first mapping table; The first target signal state is determined as the signal state of each of the external signals.

[0010] In some embodiments, the CPU determines the signal state of each of the external signals based on the second mapping table and the reference duty cycle, including: Determine the second target signal state corresponding to the reference duty cycle from the second mapping table; The second target signal state is determined as the signal state of each of the external signals.

[0011] In some embodiments, the modulation circuit includes: a counter connected to a reset module and each of the signal receiving ports; a MOSFET, the gate of which is connected to the output of the counter, the drain of which is connected to a power supply voltage, and the source of which is grounded through a resistor, the source of which is connected to the input of the DA converter and the I / O interface respectively. The modulation circuit modulates the external signals received from all the signal receiving ports into the first PWM wave, including: Each of the signal receiving ports of the counter receives each of the external signals in real time, and obtains the encoded value based on the combination of the signal states of each of the external signals; The count value of the counter is determined in real time; When the count value is greater than or equal to the encoded value, the MOS transistor is turned on, and the source of the MOS transistor outputs a high level. When the count value reaches a preset threshold, the reset module clears the counter to zero, turns off the MOS transistor again, and outputs a low level at the source of the MOS transistor to control the counter to receive new external signals again. The periodic high and low level sequence output from the source of the MOS transistor is determined as the first PWM wave.

[0012] Thirdly, embodiments of this application provide a control device, including at least one control processor and a memory for communicatively connecting to the at least one control processor; the memory stores instructions executable by the at least one control processor, which, when executed by the at least one control processor, enable the at least one control processor to perform the signal processing method as described in the second aspect.

[0013] Thirdly, embodiments of this application also provide a signal processing apparatus, including the control device of the second aspect.

[0014] Fourthly, embodiments of this application also provide a computer-readable storage medium storing computer-executable instructions for performing the signal processing method as described in the second aspect.

[0015] This application provides a signal processing apparatus, signal processing method, control device, and storage medium. The apparatus includes: a DA converter; a CPU, the CPU having an ADC module and an I / O interface, the ADC module being connected to the output of the DA converter; and a modulation circuit, the modulation circuit including multiple signal receiving ports, the output of the modulation circuit being connected to the input of the DA converter. The modulation circuit can receive external signals from the signal receiving ports, modulate all received external signals into a first PWM wave, and send the first PWM wave to the ADC module of the CPU via the DA converter. The CPU can generate a second PWM wave based on the signal output by the ADC module according to target requirements, convert the second PWM wave into multiple digital signals, and output the digital signals from the I / O interface to the target device corresponding to the target requirements. According to the solution provided by this application, by combining the modulation circuit and the CPU, multiple digital signals can be converted into a single PWM signal, and a single PWM signal can be converted into multiple digital signals. This means that a single CPU can complete the input and output of multiple digital signals, thereby effectively reducing power consumption when fulfilling the I / O requirements of terminal devices. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a signal processing device provided in one embodiment of this application; Figure 2 This is a circuit structure diagram of a modulation circuit provided in another embodiment of this application; Figure 3 This is a flowchart of the signal processing method provided in another embodiment of this application; Figure 4 This is a structural diagram of a control device provided in another embodiment of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0018] It is understandable that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, or the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0019] In the field of distribution network automation, terminal equipment (including DTU and FTU equipment) requires a large number of remote signaling signals to achieve information interaction with other equipment in the distribution network system, and also requires a large number of IO outputs to control multiple LEDs to indicate the current status.

[0020] In existing technologies, the I / O requirements of terminal devices are met in two ways: The first is to use a CPU in conjunction with an external expansion chip (including an FPGA chip or a CPLD chip). The CPU receives and processes remote signaling signals, while the external expansion chip generates and sends output signals to control LEDs. The second is to use multiple CPUs. For example, assuming two CPUs, one receives and processes remote signaling signals, while the other generates and sends output signals to control LEDs. The first approach requires more I / O interfaces for communication between the CPU and the external expansion chip, while the second approach requires a larger minimum CPU system. Both approaches significantly increase the hardware cost of the product, and the power consumption of multiple chips operating simultaneously is also high.

[0021] To address the aforementioned problems, this application provides a signal processing apparatus, method, control device, and storage medium. The apparatus includes: a DA converter; a CPU, which has an ADC module and an I / O interface, the ADC module being connected to the output of the DA converter; and a modulation circuit, which includes multiple signal receiving ports, the output of which is connected to the input of the DA converter. The modulation circuit receives external signals from the signal receiving ports, modulates all received external signals into a first PWM wave, and sends the first PWM wave to the ADC module of the CPU via the DA converter. The CPU generates a second PWM wave based on the signal output from the ADC module according to target requirements, converts the second PWM wave into multiple digital signals, and outputs the digital signals from the I / O interface to the target device corresponding to the target requirements. According to the solution provided in this application, by combining the modulation circuit and the CPU, multiple digital signals can be converted into a single PWM signal, and a single PWM signal can be converted into multiple digital signals. This allows a single CPU to handle the input and output of multiple digital signals, effectively reducing power consumption when fulfilling the I / O requirements of terminal devices.

[0022] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0023] refer to Figure 1 , Figure 1 This is a schematic diagram of a signal processing apparatus according to an embodiment of this application. The signal processing apparatus includes: DA converter 130; CPU110 is equipped with ADC module 112 and IO interface 111. ADC module 112 is connected to the output of DA converter 130. The modulation circuit 120 includes multiple signal receiving ports 121, and the output of the modulation circuit 120 is connected to the input of the DA converter 130. The modulation circuit 120 can receive external signals from the signal receiving port 121, modulate all received external signals into a first PWM wave, and convert the first PWM wave into an analog signal through the DA converter 130 and send it to the ADC module 112 of the CPU 110. The CPU 110 can convert the analog signal into a second PWM wave through the ADC module 112 based on the target requirements, convert the second PWM wave into multiple digital signals, and output the digital signals from the IO interface 111 to the target device corresponding to the target requirements.

[0024] Specifically, in this embodiment, the IO interface 111 is a GPIO interface 111. The specific number of IO interfaces 111 in this embodiment can be determined by those skilled in the art based on actual needs.

[0025] It is understood that the signal processing device in this application embodiment includes: a DA converter 130; a CPU 110, the CPU 110 being provided with an ADC module 112 and an IO interface 111, the ADC module 112 being connected to the output terminal of the DA converter 130; a modulation circuit 120, the modulation circuit 120 including multiple signal receiving ports 121, the output terminal of the modulation circuit 120 being connected to the input terminal of the DA converter 130; wherein, the modulation circuit 120 is capable of receiving external signals from the signal receiving ports 121, modulating all received external signals into a first PWM wave, and converting the first PWM wave into an analog quantity through the DA converter 130 and sending it to the ADC module 112 of the CPU 110; the CPU 110 is capable of converting the analog quantity into a second PWM wave through the ADC module 112 based on the target requirement, and converting the second PWM wave into a digital signal based on the modulation function module inside the CPU 110, and outputting the digital signal from the IO interface 111 to the target device corresponding to the target requirement. Based on this structural foundation, in the case of multiple I / O requirements, this embodiment uses modulation circuit 120 to convert multiple digital signals (e.g., remote signaling signals, which are not limited here) involved in the I / O requirements into a single PWM signal (i.e., the first PWM wave). Then, modulation circuit 120 converts the first PWM wave into an analog signal through DA converter 130 and sends it to CPU 110. When CPU 110 responds to the target requirement (e.g., it needs I / O output to control multiple LEDs to indicate the current status), CPU 110 converts the analog signal into a second PWM wave through internal ADC module 112 and internal modulation function module. Then, the second PWM wave is converted into multiple digital signals and output from I / O interface 111. That is, multiple digital signal inputs and outputs can be completed using a single CPU 110. Compared with the prior art, where input and output operations are controlled by different chips, this can effectively reduce the power consumption when fulfilling the I / O requirements of terminal devices.

[0026] In some embodiments, the output of the modulation circuit 120 is connected to the I / O interface 111.

[0027] Understandably, reference Figure 1 In this embodiment, the output terminal of the modulation circuit 120 is connected to the IO interface 111. At this time, the CPU 110 can use the second mapping table, which indicates the mapping relationship between the duty cycle of the PWM wave and the signal state of the external signal, to determine the signal state of the external signal, providing effective support for the subsequent operation of the CPU 110 to generate feedback signals in response to the target requirements.

[0028] In some embodiments, reference Figure 2 , Figure 2This is a circuit diagram of a modulation circuit 120 provided in another embodiment of this application. The modulation circuit 120 includes: Counter 122 is connected to reset module 123 and various signal receiving ports 121; MOSFET 124 has its gate connected to the output of counter 122, its drain connected to power supply VCC, and its source grounded through resistor R1. The source of MOSFET 124 is connected to the input and second interface of DA converter 130.

[0029] It is understood that the embodiments of this application do not limit the specific number of signal receiving ports 121 in the modulation circuit 120. Those skilled in the art can determine, based on actual I / O requirements, that one signal receiving port 121 receives one external signal. For example, as Figure 2 As shown, in this embodiment, the counter 122 receives three external signals. At this time, the counter 122 can output a high level after different times based on the state of the three external signals. The high level acts on the gate of the MOS transistor 124, causing the MOS transistor 124 to conduct. After the MOS transistor conducts for a period of time, the counter 122 is reset, and the MOS transistor 124 is turned off again. After this cycle, the periodic high and low level sequence output from the source of the MOS transistor 124 is determined as the first PWM wave output by the modulation circuit 120. That is to say, the modulation circuit 120 of this embodiment provides effective support for the signal processing device to realize the function of a single CPU 110 to realize multiple signal inputs.

[0030] Additionally, refer to Figure 3 , Figure 3 This is a flowchart illustrating the steps of a signal processing method provided in another embodiment of this application. This application provides a signal processing method applied to the signal processing apparatus provided in the above embodiments. The method includes, but is not limited to, the following steps: Step S10: The modulation circuit modulates the external signals received from all signal receiving ports into a first PWM wave and sends the first PWM wave to the DA converter. In step S20, the DA converter converts the first PWM wave into an analog signal and sends the analog signal to the CPU; Step S30: The CPU determines the signal state of each external signal based on the first mapping table and the analog quantity, wherein the first mapping table is used to indicate the mapping relationship between the analog quantity and the signal state of the external signal; In step S40, in response to the target requirement, the CPU converts the analog signal into a second PWM wave through the ADC module, converts the second PWM wave into multiple digital signals, and outputs the digital signals from the IO interface to the target device corresponding to the target requirement.

[0031] It is understood that, referring to the description of the above embodiments, applications such as Figure 1 The signal processing method of the signal processing device shown includes: modulation circuit 120 modulates all external signals received from signal receiving port 121 into a first PWM wave, and sends the first PWM wave to DA converter 130. DA converter 130 converts the first PWM wave into an analog signal and sends the analog signal to CPU 110. CPU 110 determines the signal state of each external signal based on a first mapping table and the analog signal, wherein the first mapping table is used to indicate the mapping relationship between the analog signal and the signal state of the external signal. In response to the target demand, CPU 110 generates a second PWM wave according to the signal output by ADC module 112, and outputs the second PWM wave from IO interface 111 to the target device corresponding to the target demand. That is, in this embodiment, the output of PWM wave by modulation circuit 120 is controlled by adjusting the high-level duration (i.e., pulse width) of the signal; when the IO demand is a signal input, the first PWM wave is generated by modulation circuit 120; when the IO demand is a signal output, the second PWM wave is generated by CPU 110, and a corresponding digital signal is generated and output to the corresponding target device through IO interface 111. In this way, multiple digital signal inputs and outputs can be completed using a single CPU110. Compared with the existing technology, which uses different chips to control input and output operations, this can effectively reduce power consumption and hardware costs when fulfilling the I / O requirements of terminal devices.

[0032] Additionally, in some embodiments, when the output of the modulation circuit is connected to the I / O interface, during execution... Figure 1 After the modulation circuit in step S10 modulates all the external signals received from the signal receiving ports into a first PWM wave, the signal processing method of this application embodiment also includes, but is not limited to, the following steps: Step S16: The modulation circuit sends the first PWM wave to the IO interface, wherein the first PWM wave corresponds to a reference duty cycle; In step S17, the CPU determines the signal state of each external signal based on the second mapping table and the reference duty cycle, wherein the second mapping table is used to indicate the mapping relationship between the duty cycle of the PWM wave and the signal state of the external signal.

[0033] Specifically, step S12 includes, but is not limited to, the following steps: Step S171: Determine the state of the second target signal corresponding to the reference duty cycle from the second mapping table; Step S172: Determine the second target signal state as the signal state of each external signal. It is understandable that, when three external signals are received, the second mapping table of the mapping relationship between the duty cycle of the indicator PWM wave and the signal state of the external signals in this embodiment is as follows: Second mapping table

[0034] It is understood that in this embodiment, the signal state of the received external signal can be determined based on the second mapping table mentioned above. Suppose that at a certain moment, the CPU detects that the duty cycle of the first PWM wave is 30%, and determines the corresponding state of the first PWM wave as "0,1,1" through the second mapping table. Then, it can be determined that the corresponding digital signal 1 is low level, and digital signals 2 and 3 are high level.

[0035] Specifically, in some embodiments, Figure 1 Step S30 includes, but is not limited to, the following steps: Step S31: Determine the state of the first target signal corresponding to the analog quantity from the first mapping table; Step S32: Determine the first target signal state as the signal state of each external signal.

[0036] It is understandable that, when three external signals are received, and the analog quantity is a voltage value, the first mapping table used in this embodiment to indicate the mapping relationship between the analog quantity and the signal state of the external signals is as follows: First mapping table

[0037] It is understood that in this embodiment, the signal state of the received external signal can be determined based on the second mapping table mentioned above. Suppose that at a certain moment, the CPU detects that the analog quantity is 1.2V, then the corresponding state is "0,1,1". At this time, the corresponding digital signal 1 is low level, and digital signals 2 and 3 are high level, which can provide effective data support for the subsequent generation of new instruction operations.

[0038] Specifically, in some embodiments, the modulation circuit 120 includes: a counter 122 connected to a reset module 123 and various signal receiving ports 121; a MOSFET 124, the gate of which is connected to the output of the counter 122, the drain of which is connected to the power supply VCC, and the source of which is grounded through a resistor R1. The source of which is connected to the input of the DA converter 130 and the IO interface 111, respectively. The modulation circuit in step S10 modulates the external signals received from all the signal receiving ports into a first PWM wave, including but not limited to the following steps: Step S11: Each signal receiving port of the counter receives each external signal in real time, and obtains the encoded value based on the combination of the signal states of each external signal. Step S12: Determine the counter value in real time; Step S13: When the count value is greater than or equal to the encoded value, the MOS transistor is turned on, and the source of the MOS transistor outputs a high level. Step S14: When the count value reaches the preset threshold, the reset module clears the counter to zero, turns off the MOS transistor again, and outputs a low level at the source of the MOS transistor to control the counter to receive new external signals again. Step S15: The periodic high and low level sequence output from the source of the MOSFET is determined as the first PWM wave.

[0039] It is understood that this embodiment is based on, as follows Figure 2 The modulation circuit 120 shown is based on the following structure: it receives various external signals in real time through the signal receiving ports 121 of the counter 122, and obtains the encoded value based on the signal state combination of each external signal; it determines the count value of the counter 122 in real time; when the count value is greater than or equal to the encoded value, the MOSFET 124 is turned on, and the source of the MOSFET 124 outputs a high level; when the count value reaches a preset threshold, the reset module 123 clears the counter 122 to zero, turns off the MOSFET 124 again, and the source of the MOSFET 124 outputs a low level, controlling the counter 122 to receive new external signals again; finally, the periodic high and low level sequence output by the source of the MOSFET 124 is determined as the first PWM wave. That is to say, this embodiment controls the output of the first PWM wave by adjusting the high level duration (i.e., pulse width) of the signal. Figure 1 By inputting the first PWM wave, representing multiple digital signals, to the IO interface 111 of the CPU 110, the resources of the IO interface 111 of the CPU 110 can be greatly saved.

[0040] like Figure 4 As shown, Figure 4 This is a structural diagram of a control device provided in one embodiment of this application. The present invention also provides a control device 400, comprising: The processor 410 can be implemented using a general-purpose central processing unit (CPU), microprocessor, application specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application. The memory 420 can be implemented as a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 420 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 420 and is called and executed by the processor 410 using the signal processing method of the embodiments of this application. Input / output interface 430 is used to realize information input and output; The communication interface 440 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 450 transmits information between various components of the device (e.g., processor 410, memory 420, input / output interface 430, and communication interface 440); The processor 410, memory 420, input / output interface 430 and communication interface 440 are connected to each other within the device via bus 450.

[0041] In addition, this application also provides a signal processing device, including the control device 400 of the above embodiments.

[0042] In addition, this application embodiment also provides a storage medium, which is a computer-readable storage medium, storing a computer program that, when executed by a processor, implements the above-described signal processing method.

[0043] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof. The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate, and may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0044] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically include computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0045] The above provides a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of the present invention.

Claims

1. A signal processing device, characterized in that, include: DA converter; The CPU is equipped with an ADC module and an I / O interface, and the ADC module is connected to the output of the DA converter. A modulation circuit, comprising multiple signal receiving ports, wherein the output of the modulation circuit is connected to the input of the DA converter; The modulation circuit can receive external signals from the signal receiving port, modulate all the received external signals into a first PWM wave, and convert the first PWM wave into an analog signal through the DA converter and send it to the ADC module of the CPU. The CPU can convert the analog signal into a second PWM wave through the ADC module based on the target requirements, convert the second PWM wave into multiple digital signals, and output the digital signals from the IO interface to the target device corresponding to the target requirements.

2. The signal processing apparatus according to claim 1, characterized in that, The output of the modulation circuit is connected to the IO interface.

3. The signal processing apparatus according to claim 2, characterized in that, The modulation circuit includes: A counter, which is connected to a reset module and each of the signal receiving ports; The MOS transistor has its gate connected to the output terminal of the counter, its drain connected to the power supply voltage, and its source grounded through a resistor. The source of the MOS transistor is connected to the input terminal of the DA converter and the IO interface, respectively.

4. A signal processing method, characterized in that, The method, applied to the signal processing apparatus according to any one of claims 1 to 3, comprises: The modulation circuit modulates the external signals received from all of the signal receiving ports into the first PWM wave and sends the first PWM wave to the DA converter. The DA converter converts the first PWM wave into an analog signal and sends the analog signal to the CPU; The CPU determines the signal state of each of the external signals based on the first mapping table and the analog quantity, wherein the first mapping table is used to indicate the mapping relationship between the analog quantity and the signal state of the external signal; In response to the target requirement, the CPU converts the analog signal into a second PWM wave through the ADC module, converts the second PWM wave into multiple digital signals, and outputs the digital signals from the IO interface to the target device corresponding to the target requirement.

5. The signal processing method according to claim 1, characterized in that, The output terminal of the modulation circuit is connected to the IO interface. After the modulation circuit modulates the external signals received from all the signal receiving ports into the first PWM wave, the method further includes: The modulation circuit sends the first PWM wave to the IO interface, wherein the first PWM wave corresponds to a reference duty cycle; The CPU determines the signal state of each of the external signals based on the second mapping table and the reference duty cycle, wherein the second mapping table is used to indicate the mapping relationship between the duty cycle of the PWM wave and the signal state of the external signal.

6. The signal processing method according to claim 4, characterized in that, The CPU determines the signal state of each of the external signals based on the first mapping table and the analog quantity, including: Determine the state of the first target signal corresponding to the analog quantity from the first mapping table; The first target signal state is determined as the signal state of each of the external signals.

7. The signal processing method according to claim 5, characterized in that, The CPU determines the signal state of each of the external signals based on the second mapping table and the reference duty cycle, including: Determine the second target signal state corresponding to the reference duty cycle from the second mapping table; The second target signal state is determined as the signal state of each of the external signals.

8. The signal processing method according to claim 4, characterized in that, The modulation circuit includes: a counter connected to a reset module and each of the signal receiving ports; a MOSFET, the gate of which is connected to the output of the counter, the drain of which is connected to a power supply voltage, and the source of which is grounded through a resistor. The source of the MOSFET is connected to the input of the DA converter and the I / O interface, respectively. The modulation circuit modulates the external signals received from all the signal receiving ports into the first PWM wave, including: Each of the signal receiving ports of the counter receives each of the external signals in real time, and obtains the encoded value based on the combination of the signal states of each of the external signals; The count value of the counter is determined in real time; When the count value is greater than or equal to the encoded value, the MOS transistor is turned on, and the source of the MOS transistor outputs a high level. When the count value reaches a preset threshold, the reset module clears the counter to zero, turns off the MOS transistor again, and outputs a low level at the source of the MOS transistor to control the counter to receive new external signals again. The periodic high and low level sequence output from the source of the MOS transistor is determined as the first PWM wave.

9. A control device, characterized in that, It includes at least one control processor and a memory for communicatively connecting to the at least one control processor; the memory stores instructions executable by the at least one control processor to enable the at least one control processor to perform the signal processing method as described in any one of claims 4 to 8.

10. A signal processing apparatus, characterized in that, Includes the control device as described in claim 8.

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