Fan-out wafer level packaging unit

Abstract

The invention discloses a fan-out type wafer level packaging unit, which comprises a carrier plate, at least one chip, a dielectric layer, at least one conducting circuit and an outer protective layer, wherein each chip is provided with a bare chip, a plurality of chip conducting lines, a chip dielectric layer, a plurality of chip welding pads, a chip first surface and a chip second surface, and the bare chips can be electrically connected to the outside through the chip welding pads; wherein each conducting circuit is formed by filling metal paste in at least one groove of the dielectric layer and then grinding the metal paste, and each conducting circuit is formed by forming a welding pad in each opening of the outer protective layer; wherein each chip can be electrically connected with the outside through each welding pad on the periphery of the chip area on the second surface of the chip, so that the problems that the manufacturing cost is high and the environmental protection is not facilitated when each conducting circuit is manufactured by the existing fan-out packaging technology are solved.

Description

Technical Field

[0001] This invention relates to a packaging unit, and more particularly to a fan-out wafer-level packaging unit. Background Technology

[0002] Packaging technologies that are thin, light, compact, efficient, and highly reliable are the development trend of the semiconductor industry. Among them, fan-out wafer level packaging (FOWLP) is an existing packaging technology.

[0003] In advanced FOWLP packaging, the redistribution layer (RDL) is the most critical component. This is because the conductors in the RDL enable multiple pads on the die to achieve XY-planar electrical extension and interconnection, allowing for the formation of more dispersed solder pads around the die. This effectively improves the design space and reliability of each conductor. However, the fabrication of each conductor in the RDL is crucial in ensuring that it maintains or achieves a certain degree of thinness and compactness while achieving XY-planar electrical extension and interconnection.

[0004] However, the existing FOWLP packaging technology uses RDL technology to form the conductors by chemical plating or electroplating. This results in relatively high material and manufacturing costs, and the existing process does not meet or is detrimental to environmental protection requirements.

[0005] In addition, existing fan-out wafer-level packaging technologies are mostly designed for die designs and lack designs for chips (formed by dividing the die on the wafer after completing the RDL). Summary of the Invention

[0006] The main objective of this invention is to provide a fan-out wafer-level packaging unit, comprising a carrier board, at least one chip, a dielectric layer, at least one conductive line, and an outer sheath. Each chip has a bare die, multiple chip conductive lines, a chip dielectric layer, multiple chip pads, a first chip surface, and a second chip surface. Each bare die is electrically connected to the outside via each chip pad. Each conductive line is formed by filling at least one groove in the dielectric layer with metal paste and then grinding the metal paste. Each conductive line is formed as a pad within an opening in the outer sheath. Each chip is electrically connected to the outside via pads surrounding the chip area on the second chip surface. This effectively solves the problem of high manufacturing costs and environmental disadvantages associated with existing fan-out packaging technologies in modular applications when fabricating conductive lines.

[0007] To achieve the above objectives, the present invention provides a fan-out wafer-level packaging unit, which includes a carrier board, at least one chip, a dielectric layer, at least one conductive line, and an outer sheath. The carrier board has a first surface and an opposing second surface. Each chip has a bare die, multiple chip conductive lines, a chip dielectric layer, multiple chip pads, a first chip surface, and a second chip surface. Each chip is disposed on the carrier board via the first chip surface, and each chip pad is disposed on the second chip surface. A vertical chip region on the second chip surface defines a chip region. The bare die has at least one chip pad, and the bare die can be sequentially routed through the at least one chip pad, the multiple chip conductive lines, and the multiple chip pads. Each chip pad is electrically connected to the external surface; wherein the dielectric layer is disposed on the second surface of the substrate and covers each chip, the dielectric layer has at least one groove extending horizontally, each groove allowing the plurality of chip pads to be exposed to the external surface; wherein each conductive line is formed by filling the groove with metal paste, and each conductive line is electrically connected to the plurality of chip pads; wherein an outer sheath is disposed on the dielectric layer and each conductive line, the outer sheath having a plurality of openings, at least one of which is located around the chip region on the second surface of the chip, and each conductive line is exposed to the external surface through each opening, with a pad formed within each opening; wherein each chip can sequentially pass through each A chip pad, each conductive line, and each pad surrounding the chip region on the second surface of the chip are electrically connected to form a fan-out wafer-level package (WLP). The manufacturing method of the fan-out WLP includes the following steps: Step S1: Providing a carrier board having a first surface and an opposing second surface; Step S2: Spacingly disposing of a plurality of chips on the second surface of the carrier board, wherein each chip has a bare die, a chip conductive line, a chip dielectric layer, a plurality of chip pads, a first surface, and a second surface, wherein each chip is disposed on the carrier board via the first surface, and the plurality of chip pads are disposed on the second surface. The vertical chip area on the second side of the substrate is defined as a chip area, wherein the bare die has at least one chip pad, and each bare die can be electrically connected to the outside through each chip pad, the chip conductive lines and the plurality of chip pads in sequence; Step S3: A dielectric layer is formed on the second side of the substrate and the dielectric layer covers each chip, wherein the dielectric layer has at least one groove formed in a horizontal direction, and each groove allows the plurality of chip pads to be exposed to the outside; Step S4: Metal paste is filled into each groove of the dielectric layer, and the thickness of the metal paste is higher than the surface of the dielectric layer; Step S5: The metal paste above the surface of the dielectric layer is ground so that the surface of the metal paste is flush with the surface of the dielectric layer to form a plurality of conductive lines;Step S6: Deposit an outer sheath on the dielectric layer; Step S7: Form a plurality of openings in the outer sheath, with at least one opening formed around the chip region on the second surface of each chip, such that each conductive line can be exposed to the outside through each opening and a pad is formed within each opening; and Step S8: Perform a dicing operation to divide and form a plurality of fan-out wafer-level packaging units.

[0008] In a preferred embodiment of the invention, each of the openings further includes a protrusion, and each of the protrusions is disposed on each of the solder pads.

[0009] In a preferred embodiment of the present invention, each of the bumps is further provided with a solder ball.

[0010] In a preferred embodiment of the present invention, the fan-out wafer-level packaging unit can be electrically connected to a printed circuit board (PCB) using each of the solder balls.

[0011] In a preferred embodiment of the present invention, each chip is further manufactured using a redistribution layer (RDL) packaging technology; wherein each chip's conductive lines are further composed of multiple first conductive lines and multiple second conductive lines; wherein the chip's dielectric layer is further composed of a first dielectric layer and a second dielectric layer; wherein each first conductive line is formed by filling at least one groove in the first dielectric layer with metal paste, and each first conductive line is electrically connected to each of the die pads of the bare die; wherein each second conductive line is formed by filling at least one groove in the second dielectric layer with metal paste. The chip is composed of metal paste, and each of the second conductive lines is electrically connected to each of the first conductive lines; wherein the manufacturing method of each chip further includes the following steps: Step S11: providing a wafer having a plurality of bare dies, wherein each bare die has at least one die pad; Step S12: depositing a first dielectric layer on each bare die and forming at least one groove on the first dielectric layer; Step S13: filling each groove of the first dielectric layer with metal paste, wherein the thickness of the metal paste is higher than the surface of the first dielectric layer; Step S14: Grind the metal paste above the surface of the first dielectric layer so that the surface of the metal paste is flush with the surface of the first dielectric layer to form multiple first conductive lines, wherein each first conductive line is electrically connected to each of the die pads of the bare die; Step S15: Deposit a second dielectric layer on the first dielectric layer and form at least one groove on the second dielectric layer; Step S16: Fill each groove of the second dielectric layer with metal paste, and the thickness of the metal paste is higher than the surface of the second dielectric layer; Step S 17: Polish the metal paste above the surface of the second dielectric layer so that the surface of the metal paste is flush with the surface of the second dielectric layer to form multiple second conductive lines, wherein each of the second conductive lines is electrically connected to each of the first conductive lines; and step S18: Perform a dicing operation to dice multiple chips on the wafer, wherein each of the first conductive lines and each of the second conductive lines further constitutes multiple chip conductive lines, wherein the first dielectric layer and the second dielectric layer further constitute a chip dielectric layer.

[0012] In a preferred embodiment of the present invention, the metal paste constituting each of the first conductive lines includes silver paste, nano silver paste, copper paste or nano copper paste; wherein the metal paste constituting each of the second conductive lines includes silver paste, nano silver paste, copper paste or nano copper paste.

[0013] In a preferred embodiment of the present invention, the carrier plate comprises a silicon (Si) carrier plate, a glass carrier plate, or a ceramic carrier plate.

[0014] In a preferred embodiment of the present invention, the metal paste constituting each conductive line includes silver paste, nano-silver paste, copper paste, or nano-copper paste.

[0015] In a preferred embodiment of the present invention, the first surface of each chip is further disposed on the second surface of the carrier using a die attach film (DAF). Attached Figure Description

[0016] Figure 1 This is a side cross-sectional plan view of an application embodiment of the fan-out wafer-level packaging unit of the present invention.

[0017] Figure 2 This is a side view of the cross-section of the carrier plate of the present invention.

[0018] Figure 3 Is Figure 2 A side view of the cross-section of the chip mounted on the carrier.

[0019] Figure 4 Is Figure 3 A side view of the cross-section of the substrate and the chip in the diagram.

[0020] Figure 5 Is Figure 4 A side view of the cross-section of the groove filled with metal paste.

[0021] Figure 6 It is Figure 5 A side view of the cross-section of the metal paste used to form the conductive lines.

[0022] Figure 7 Is Figure 6 A side view of the conductor line with an outer sheath.

[0023] Figure 8 Is Figure 7 A side view of the cross-section of the solder pads with bumps.

[0024] Figure 9 Is Figure 8 A side view of the cross-section of a protrusion with solder balls.

[0025] Figure 10 This is a planar schematic diagram of an enlarged side cross-section of the chip of the present invention.

[0026] Figure 11 This is a magnified side view of the bare die in the chip of the present invention.

[0027] Figure 12 Is Figure 11 A side view of the cross-section of the bare die with the first dielectric layer disposed thereon.

[0028] Figure 13 Is Figure 12 A side view of the cross-section of the groove in the first dielectric layer of the material filled with metal paste.

[0029] Figure 14 It is Figure 13 A side view of the cross-section of the metal paste used to form the first conductive line.

[0030] Figure 15 Is Figure 14 A side view of the cross-section of a second dielectric layer disposed on the first dielectric layer.

[0031] Figure 16 Is Figure 15 A side view of the cross-section of the second dielectric layer filled with metal paste.

[0032] Explanation of reference numerals in the attached figures: 1-Fan-out wafer-level packaging unit; 1a-Chip area; 10-Carrier board; 11-First side; 12-Second side; 20-Chip; 21-Bare die; 211-Die pad; 22-Chip conductive line; 221-First conductive line; 221a-Metal paste; 222-Second conductive line; 222a-Metal paste; 23-Chip dielectric layer; 231-First dielectric layer; 2311-Groove; 232-Second dielectric layer; 2321-Groove; 24-Chip solder pad; 25-Chip first side; 26-Chip second side; 30-Dielectric layer; 31-Groove; 40-Conductive line; 40a-Metal paste; 41-Solder pad; 50-Outer sheath; 51-Opening; 60-Bump; 70-Solder ball; 80-Chip bonding film; 2-Printed circuit board. Detailed Implementation

[0033] The structure and technical features of the present invention are described in detail below with reference to the illustrations. The illustrations are only used to illustrate the structural relationships and related functions of the present invention. Therefore, the dimensions of the components in the illustrations are not drawn to actual scale and are not intended to limit the present invention.

[0034] refer to Figure 1 The present invention provides a fan-out wafer-level packaging unit 1, which includes a carrier board 10, at least one chip 20, a dielectric layer 30, at least one conductive line 40 and an outer sheath 50.

[0035] The carrier plate 10 has a first surface 11 and an opposite second surface 12, such as Figure 2 As shown.

[0036] Each chip 20 has a bare die 21, multiple chip conductive lines 22, a chip dielectric layer 23, multiple chip pads 24, a first chip surface 25, and a second chip surface 26, as shown below. Figure 3As shown; each chip 20 is mounted on the carrier board 10 via its first surface 25, as... Figure 3 As shown; each chip pad 24 is disposed on the second surface 26 of the chip, and the vertical chip area of ​​the second surface 26 of the chip is defined as a chip area 1a, as shown. Figure 3 As shown; wherein the bare die 21 has at least one die pad 211, and each bare die 21 can be electrically connected to the outside via each die pad 211, each chip conductive line 22 and each chip solder pad 24 in sequence, as shown. Figure 3 As shown.

[0037] The dielectric layer 30 is disposed on the second surface 12 of the carrier 10 and covers each chip 20. The dielectric layer 30 has at least one groove 31 formed in a horizontal direction, and each groove 31 allows the bonding pads 24 of each chip to be exposed to the outside. Figure 4 As shown.

[0038] Each conductive line 40 is composed of metal paste 40a filled in each groove 31, such as... Figure 6 As shown; each conductive line 40 is electrically connected to each chip pad 24, such as... Figure 6 As shown.

[0039] The outer sheath 50 is disposed on the dielectric layer 30 and each conductive line 40. The outer sheath 50 has a plurality of openings 51, and at least one of the openings 51 is located around the chip region 1a on the second surface 26 of the chip 20, such as... Figure 7 As shown; each conductive line 40 is exposed to the outside through each opening 51, and a solder pad 41 is formed within each opening 51, as shown. Figure 7 As shown. In Figure 7 In the embodiment shown, the fan-out wafer-level packaging unit 1 has 5 of the solder pads 41, but this is not intended to limit the invention.

[0040] Each chip 20 can be electrically connected to the external circuitry via each chip pad 24, each conductive line 40, and each pad 41 surrounding the chip region 1a on the second surface 26 of the chip 20, thereby forming the fan-out wafer-level package unit 1, as shown below. Figure 7 As shown.

[0041] The manufacturing method of the fan-out wafer-level packaging unit 1 includes the following steps:

[0042] Step S1: Provide a carrier board 10, such as Figure 2 As shown; wherein the carrier plate 10 has a first surface 11 and an opposite second surface 12, as Figure 2 As shown.

[0043] Step S2: Arrange multiple chips 20 at intervals on the second surface 12 of the carrier board 10, such as... Figure 3 As shown; each chip 20 has a bare die 21, a chip conductive line 22, a chip dielectric layer 23, multiple chip pads 24, a first chip surface 25, and a second chip surface 26, as shown. Figure 3 As shown; each chip 20 is mounted on the carrier board 10 via its first surface 25, as... Figure 3 As shown; each chip pad 24 is disposed on the second surface 26 of the chip, and the vertical chip area of ​​the second surface 26 of the chip is defined as a chip area 1a, as shown. Figure 3 As shown; wherein the bare die 21 has at least one die pad 211, and each bare die 21 can be electrically connected to the external circuitry via each die pad 211, the chip conductive line 22, and each chip solder pad 24 in sequence, as shown. Figure 3 As shown.

[0044] Step S3: A dielectric layer 30 is formed on the second surface 12 of the carrier board 10, and the dielectric layer 30 covers each chip 20, such as... Figure 4 As shown; wherein the dielectric layer 30 has at least one groove 31 formed in a horizontal direction, each groove 31 allowing each chip pad 24 to be exposed to the outside, such as Figure 4 As shown.

[0045] Step S4: Fill each groove 31 of the dielectric layer 30 with metal paste 40a, and the thickness of the metal paste 40a is higher than the surface of the dielectric layer 30, such as... Figure 5 As shown.

[0046] Step S5: Grind the metal paste 40a above the surface of the dielectric layer 30 so that the surface of the metal paste 40a is flush with the surface of the dielectric layer 30 to form multiple conductive lines 40, such as... Figure 6 As shown.

[0047] Step S6: Lay an outer sheath 50 on the dielectric layer 30, such as... Figure 7 As shown.

[0048] Step S7: A plurality of openings 51 are formed in the outer sheath 50, with at least one opening 51 formed around the chip region 1a on the second surface 22 of each chip 20, such that each conductive line 40 can be exposed to the outside through each opening 51, and a solder pad 41 is formed within each opening 51. Figure 7 As shown.

[0049] Step S8: Perform a dicing operation to divide and form multiple fan-out wafer-level packaging units 1, such as... Figure 7 As shown.

[0050] Steps S3 to S5 in the manufacturing method of the fan-out wafer-level packaging unit 1 described above can be regarded as key steps in the fabrication of the redistribution layer (RDL) of the fan-out wafer-level packaging unit 1. Step S3 involves setting a dielectric layer 30 on the second surface 12 of the substrate 10 and forming at least one groove 31 extending horizontally on the dielectric layer 30. Step S4 involves filling each groove 31 of the dielectric layer 30 with metal paste 40a. Step S5 involves making the surface of the metal paste 40a flush with the surface of the dielectric layer 30 to form multiple conductive lines 40. Since steps S3 to S5 are easy to implement with precision, the process is relatively simplified. This allows the conductive lines in the redistribution layer (RDL) to achieve XY plane electrical extension and interconnection while maintaining or achieving a certain degree of thinness and compactness in the finished fan-out wafer-level packaging unit 1.

[0051] refer to Figure 8 Each opening 51 further has a protrusion 60, but this is not limited, and each protrusion 60 is provided on each solder pad 41, which helps to protect the solder pad and increase the product yield.

[0052] refer to Figure 9 Each protrusion 60 is further provided with a solder ball 70, but this is not limited.

[0053] refer to Figure 1 The fan-out wafer-level packaging unit 1 can be electrically connected to each solder ball 70 on a printed circuit board (PCB) 2, but there are no restrictions, which helps to increase the diversity of products.

[0054] refer to Figure 10 Each chip 20 is further manufactured using redistribution layer (RDL) packaging technology, but is not limited to it, and does not employ existing chemical plating or electroplating technologies, thus reducing the cost and pollution generated during the manufacturing process; wherein each chip's conductive line 22 is further composed of multiple first conductive lines 221 and multiple second conductive lines 222, such as Figure 10 As shown; wherein the dielectric layer 23 of the chip is further composed of a first dielectric layer 231 and a second dielectric layer 232, as shown. Figure 10 As shown; each first conductive line 221 is composed of metal paste 221a filling at least one groove 2311 of the first dielectric layer 231, and each first conductive line 221 is electrically connected to each pad 211 of the bare die 21, as shown. Figure 10As shown; each second conductive line 222 is composed of metal paste 222a filling at least one groove 2321 in the second dielectric layer 232, and each second conductive line 222 is electrically connected to each first conductive line 221, as shown. Figure 10 As shown.

[0055] The manufacturing method of each chip 20 further includes the following steps:

[0056] Step S11: Provide a wafer 3 having multiple bare dies 21, such as Figure 11 As shown; each bare crystal 21 has at least one crystal pad 211, such as Figure 11 As shown.

[0057] Step S12: Deposit a first dielectric layer 231 on each bare die 21, and form at least one groove 2311 on the first dielectric layer 231, such as... Figure 12 As shown.

[0058] Step S13: Fill each groove 2311 of the first dielectric layer 231 with metal paste 221a, and the thickness of the metal paste 221a is higher than the surface of the first dielectric layer 231, such as... Figure 13 As shown.

[0059] Step S14: Grind the metal paste 221a above the surface of the first dielectric layer 231 so that the surface of the metal paste 221a is flush with the surface of the first dielectric layer 231 to form multiple first conductive lines 221, such as... Figure 14 As shown; each of the first conductive lines 221 is electrically connected to each of the pads 211 of the bare die 21, as... Figure 14 As shown.

[0060] Step S15: Deposit a second dielectric layer 232 on the first dielectric layer 231, and form at least one groove 2321 on the second dielectric layer 232, such as... Figure 15 As shown.

[0061] Step S16: Fill each groove 2321 of the second dielectric layer 232 with metal paste 222a, and the thickness of the metal paste 222a is higher than the surface of the second dielectric layer 232, such as... Figure 16 As shown.

[0062] Step S17: Grind the metal paste 222a above the surface of the second dielectric layer 232 so that the surface of the metal paste 222a is flush with the surface of the second dielectric layer 231 to form multiple second conductive lines 222, such as... Figure 10 As shown; each of the second conductors 222 is electrically connected to each of the first conductors 221, as follows. Figure 10 As shown.

[0063] Step S18: Perform a dicing operation on the wafer 3 to form multiple chips 20, such as... Figure 10 As shown; each of the first conductive lines 221 and each of the second conductive lines 222 further constitutes multiple chip conductive lines 22, such as... Figure 10 As shown; wherein the first dielectric layer 231 and the second dielectric layer 232 further constitute a chip dielectric layer 23, as... Figure 10 As shown.

[0064] refer to Figure 10 The metal paste 221a constituting each first conductive line 221 may include silver paste, nano-silver paste, copper paste, or nano-copper paste, but is not limited thereto. The nano-silver paste material has the characteristics of low cost, high conductivity, and low-temperature sintering capability, but since nano-silver paste material is a common material, it will not be described in detail here.

[0065] refer to Figure 10 The metal paste 222a constituting each second conductive line 222 may include silver paste, nano silver paste, copper paste or nano copper paste, but is not limited thereto.

[0066] refer to Figure 2 The substrate 10 may include a silicon (Si) substrate, a glass substrate, or a ceramic substrate, but is not limited thereto, in order to increase the diversity of products.

[0067] refer to Figure 6 The metal paste 40a constituting each conductive line 40 may include silver paste, nano silver paste, copper paste or nano copper paste, but is not limited thereto.

[0068] refer to Figure 3 Each chip 20's first chip surface 25 is further disposed on the second surface 12 of the carrier plate 10 using a chip adhesive film (DAF) 80, but this is not a limitation.

[0069] Compared with existing fan-out wafer-level packaging technology, the fan-out wafer-level packaging unit 1 of the present invention has the following advantages:

[0070] (1) The fan-out wafer-level packaging unit 1 manufactured by the process of steps S3 to S5 in the manufacturing method of the fan-out wafer-level packaging unit 1 of the present invention, compared with the existing related manufacturing technology of fan-out wafer-level packaging units, the fan-out wafer-level packaging unit 1 of the present invention can maintain or achieve a certain degree of thinness and small size by making each conductive line in the RDL so that each conductive line in the RDL can generate XY plane electrical extension and interconnection effect. These are all simplified and easy to implement precisely, which is especially beneficial to reduce the thickness of the packaging unit. Therefore, the process of the present invention is not only simpler and saves costs, but also effectively improves the efficiency and reliability of the fan-out wafer-level packaging unit 1.

[0071] (2) In the manufacturing method of the present invention, the process of steps S3 to S5 is to use the technique of filling the groove with metal paste and then grinding to form the conductive lines to form multiple conductive lines on the dielectric layer, instead of using existing chemical plating or electroplating techniques, which reduces the cost and pollution generated by the process. Therefore, the present invention can effectively solve the problem that the existing fan-out packaging technology is prone to high manufacturing costs and is not conducive to environmental protection when making each conductive line.

[0072] (3) Each chip 20 of the present invention can be further made using RDL technology, which effectively solves the problem that the existing fan-out wafer-level packaging unit technology is mostly aimed at die design, but lacks design for chip (formed by dividing the die after completing RDL on the wafer), which is conducive to increasing product diversity.

[0073] The above are merely preferred embodiments of the present invention and are illustrative rather than restrictive. Those skilled in the art will understand that many changes, modifications, and even equivalent alterations can be made within the spirit and scope defined by the claims of the present invention, but all such changes will fall within the protection scope of the present invention.

Claims

1. A fan-out wafer level package unit, characterized by, Include: A carrier plate having a first surface and an opposite second surface; At least one chip, each chip having a bare die, multiple chip conductive lines, a chip dielectric layer, multiple chip pads, a first chip surface, and a second chip surface; wherein each chip is disposed on the carrier board via the first chip surface; wherein each chip pad is disposed on the second chip surface, and the vertical chip area of ​​the second chip surface defines a chip area; wherein the bare die has at least one chip pad, and each bare die is electrically connected to the external environment sequentially via the at least one chip pad, the multiple chip conductive lines, and the multiple chip pads; A dielectric layer is disposed on the second surface of the substrate and covers each chip. The dielectric layer has at least one groove formed in a horizontal direction, and each groove allows the plurality of chip pads to be exposed to the outside. At least one conductive line, each conductive line being formed by filling each of the recesses with metal paste; wherein each conductive line is electrically connected to the plurality of chip pads; and An outer sheath is disposed on the dielectric layer and each of the conductive lines, the outer sheath having a plurality of openings and at least one of the openings being located around the chip region on the second surface of the chip. Each of the conductive lines is exposed to the outside by the plurality of openings, and a solder pad is formed in each of the openings. Each of the chips can be electrically connected to the outside via the plurality of chip pads, the at least one conductive line and the plurality of pads around the chip area on the second surface of the chip, thereby forming the fan-out wafer-level package unit. The manufacturing method of this fan-out wafer-level packaging unit includes the following steps: Step S1: Provide a carrier plate; wherein the carrier plate has a first side and an opposite second side; Step S2: Multiple chips are spaced apart on the second surface of the carrier board; each chip has a bare die, a chip conductive line, a chip dielectric layer, multiple chip pads, a first chip surface and a second chip surface; each chip is disposed on the carrier board through the first chip surface; each chip pad is disposed on the second chip surface, and the vertical chip area of ​​the second chip surface is defined as a chip area; the bare die has at least one chip pad, and each bare die can be electrically connected to the outside via the at least one chip pad, the chip conductive line and the multiple chip pads in sequence; Step S3: A dielectric layer is formed on the second surface of the substrate, and the dielectric layer covers each chip; wherein the dielectric layer has at least one groove formed in a horizontal direction, and each groove is capable of exposing the multiple chip pads to the outside. Step S4: Fill each groove in the dielectric layer with metal paste, and the thickness of the metal paste is higher than the surface of the dielectric layer; Step S5: Grind the metal paste above the surface of the dielectric layer so that the surface of the metal paste is flush with the surface of the dielectric layer to form multiple conductive lines. Step S6: Lay an outer sheath on the dielectric layer; Step S7: Form a plurality of openings in the outer sheath and form at least one of the openings around the chip area on the second surface of each chip, such that each conductive line can be exposed to the outside through the plurality of openings and a solder pad is formed in each opening. and Step S8: Perform a dicing operation to divide the wafer into multiple fan-out wafer-level packaging units.

2. The fan-out wafer level package unit of claim 1, wherein, Each opening also has a bump, and each bump is provided on each solder pad.

3. The fan-out wafer level packaging unit of claim 2, wherein, Each of these protrusions also has a solder ball.

4. The fan-out wafer level packaging unit of claim 3, wherein, The fan-out wafer-level packaging unit can be electrically connected on a printed circuit board using each of the solder balls.

5. The fan-out wafer-level packaging unit as described in claim 1, characterized in that, Each chip is manufactured using redistribution layer packaging technology; wherein each chip's conductive lines consist of multiple first conductive lines and multiple second conductive lines; wherein the chip's dielectric layer consists of a first dielectric layer and a second dielectric layer; wherein each first conductive line is formed by filling at least one groove in the first dielectric layer with metal paste, and each first conductive line is electrically connected to each of the die pads of the bare die; wherein each second conductive line is formed by filling at least one groove in the second dielectric layer with metal paste, and each second conductive line is electrically connected to each first conductive line; The manufacturing method of each of these chips also includes the following steps: Step S11: Provide a wafer having a plurality of bare dies; wherein each of the bare dies has at least one dies pad; Step S12: Deposit a first dielectric layer on each of the bare dies and form at least one groove on the first dielectric layer; Step S13: Fill each of the grooves in the first dielectric layer with metal paste, and the thickness of the metal paste is higher than the surface of the first dielectric layer; Step S14: Grind the metal paste above the surface of the first dielectric layer so that the surface of the metal paste is flush with the surface of the first dielectric layer to form multiple first conductive lines; wherein each of the first conductive lines is electrically connected to each of the die pads of the bare die. Step S15: Deposit a second dielectric layer on the first dielectric layer and form at least one groove on the second dielectric layer; Step S16: Fill each of the grooves in the second dielectric layer with metal paste, and the thickness of the metal paste is higher than the surface of the second dielectric layer; Step S17: Grind the metal paste above the surface of the second dielectric layer so that the surface of the metal paste is flush with the surface of the second dielectric layer to form a plurality of second conductive lines; wherein each of the second conductive lines is electrically connected to each of the first conductive lines. and Step S18: Perform a dicing operation to dice multiple chips onto the wafer; wherein each of the first conductive lines and each of the second conductive lines constitutes multiple chip conductive lines; wherein the first dielectric layer and the second dielectric layer constitute a chip dielectric layer.

6. The fan-out wafer-level packaging unit as described in claim 5, characterized in that, The metal paste constituting each of the first conductive lines includes silver paste, nano silver paste, copper paste, or nano copper paste; wherein the metal paste constituting each of the second conductive lines includes silver paste, nano silver paste, copper paste, or nano copper paste.

7. The fan-out wafer-level packaging unit as described in claim 1, characterized in that, The substrate may be a silicon substrate, a glass substrate, or a ceramic substrate.

8. The fan-out wafer-level packaging unit as described in claim 1, characterized in that, The metal paste constituting each of these conductive lines includes silver paste, nano-silver paste, copper paste, or nano-copper paste.

9. The fan-out wafer-level packaging unit as described in claim 1, characterized in that, Each chip has its first side disposed on the second side of the carrier plate using a chip bonding film.

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