Sensor electronic device

Abstract

An electronic device (100) includes a package structure (108) having opposing first and second sides (101, 102), opposing third and fourth sides (103, 104) spaced apart along a first direction (X), opposing fifth and sixth sides (105, 106) spaced apart along an orthogonal second direction (Y), the first and second sides (101, 102) are spaced apart along a third direction (Z) orthogonal to the first and second directions (X, Y) and extend along the third direction (Z) to an opening (120) in the first side (101); a first semiconductor die (111) having a first side (121) exposed in the opening (120) of the package structure (108) and an opposite second side (122) partially enclosed by the package structure (108); and a second semiconductor die (112) electrically connected to the first semiconductor die (111), the second semiconductor die (112) being enclosed by the package structure (108) and laterally spaced apart from the first semiconductor die (111).

Description

Background Technology

[0001] Integrated circuit pressure sensors can use microelectromechanical systems (MEMS) sensor films to detect pressure, where a glass cap and application-specific integrated circuits (ASICs) are stacked on top of a thin-film MEMS die. However, the resulting device has a high profile that may be undesirable in some applications. Furthermore, the MEMS die must be etched during wafer fabrication to create cavities and a sensing surface film exposed to the atmosphere for pressure sensing, and a reference cavity must be etched into the bottom of the glass cap during wafer processing. Manufacturing this type of pressure sensor is expensive, requiring multiple wafer-level processing operations and masks in a complex and cost-inefficient process flow. Summary of the Invention

[0002] In one aspect, an electronic device includes a package structure and a first semiconductor die and a second semiconductor die. The package structure has opposing first and second sides, opposing third and fourth sides spaced apart along a first direction, opposing fifth and sixth sides spaced apart along an orthogonal second direction, the first and second sides being spaced apart along a third direction orthogonal to the first and second directions, and an opening extending along the third direction into the first side. The first semiconductor die has a first side exposed in the opening of the package structure and opposing second sides partially enclosed by the package structure, and the second semiconductor die is electrically connected to the first semiconductor die, the second semiconductor die being enclosed by the package structure and laterally spaced apart from the first semiconductor die.

[0003] In another aspect, the system includes an electronic device and a circuit board. The electronic device includes a package structure and a first semiconductor die and a second semiconductor die. The package structure has opposing first and second sides, opposing third and fourth sides spaced apart along a first direction, opposing fifth and sixth sides spaced apart along an orthogonal second direction, the first and second sides being spaced apart along a third direction orthogonal to the first and second directions; and an opening extending along the third direction into the first side. The first semiconductor die has a first side exposed in the opening of the package structure and opposing second sides partially enclosed by the package structure, and the second semiconductor die is electrically connected to the first semiconductor die. The second semiconductor die is enclosed by the package structure and laterally spaced from the first semiconductor die.

[0004] In another aspect, a method of manufacturing an electronic device includes: positioning a semiconductor die, wherein a side of the semiconductor die is coplanar with a bottom side of a conductive lead feature of a lead frame; forming a molded package structure that encloses a portion of the conductive lead feature; and etching an exposed side of the semiconductor die to form an opening extending into the bottom side of the molded package structure. Attached Figure Description

[0005] Figure 1 For along Figure 1A The partial cross-sectional side front view taken by line 1-1 shows a sensor system with pressure sensor electronics having a MEMS sensor die and an ASIC die side by side and an opening in a molded package structure that exposes the bottom side of the MEMS sensor die; and a cap die that forms a closed reference pressure cavity on the top side of the MEMS sensor die.

[0006] Figure 1A for Figure 1 A bottom view of an electronic device.

[0007] Figure 1B This is a partial cross-sectional side front view of another pressure sensor electronics device, which has a membrane cap forming a closed reference pressure cavity on the top side of the MEMS sensor die.

[0008] Figure 2 A flowchart of a method for manufacturing an electronic device.

[0009] Figures 3 to 13 for Figure 1 and 1A Pressure sensor electronics have undergone according to Figure 2 The method of manufacturing a partial cross-sectional side front view. Detailed Implementation

[0010] In the drawings, the same element symbols refer to the same element throughout, and various features are not necessarily drawn to scale. Furthermore, the term "couple" includes indirect or direct electrical connections or mechanical connections, or combinations thereof. For example, if a first device is coupled to or with a second device, the connection can be a direct electrical connection or an indirect electrical connection via one or more intervening devices and connections. The following describes one or more operating characteristics of various circuits, systems, and / or components in the context of function, which in some cases stems from the configuration and / or interconnection of various structures when the circuit system is powered and operated. In the following description and claims, the terms "including / includes," "having / has / with," or variations thereof are inclusive in a manner similar to the term "comprising," and are therefore interpreted as meaning "including, but not limited to."

[0011] Unless otherwise stated, "approximately," "roughly," or "substantially" preceding a value means + / - 10% of the stated value. The following describes one or more operating characteristics of various circuits, systems, and / or components in the context of functionality, which in some cases stems from the configuration and / or interconnection of various structures when the circuit system is powered and operated. For ease of description in conjunction with specific figures, one or more structures, features, aspects, components, etc., may be referred to herein as first, second, third, etc., e.g., first terminal and second terminal, first hole, second hole, and third hole, etc., which should not be construed as limiting with respect to the claims. The various structures and methods described in the embodiments can be advantageously applied to electronic devices and systems and / or electronic devices for manufacturing, for example, integrated circuits. While these examples may contemplate providing various improvements, specific results are not required by the embodiments unless expressly stated in the specific claims.

[0012] Figure 1 and 1A An example quad flat no-lead (QFN) packaged electronic device 100 is shown in an instance location in three-dimensional space having a first direction X, perpendicular (or orthogonal) to a second direction Y, and perpendicular (or orthogonal) to a third direction Z corresponding to the first and second directions X and Y, respectively. Structures or features along any two of these directions are orthogonal to each other. The electronic device 100 and its molded package structure 108 each have opposing first sides 101 and second sides 102 (e.g., bottom and top sides). Figure 1 The electronic device 100 and the molded package structure 108 also have opposing third sides 103 and fourth sides 104 spaced apart from each other along a first direction X, and fifth sides 105 and sixth sides 106 spaced apart from each other along a second direction Y in the illustrated position. Figure 1A ).

[0013] Electronic device 100 also has conductive metal leads 107 partially exposed to the exterior of the molded package structure 108 along the bottom or first side 101. In various embodiment examples, electronic device 100 may have one or more individuals of any integer number of leads 107, wherein the respective lateral sides are at least partially exposed to the exterior of the package structure 108 along one or more of the lateral sides 103 to 106. Although the illustrated example has a leadless package shape with substantially flush leads 107 along all four lateral sides 103 to 106, other partially extending leads may be used alone or in combination with one or more flush leads 107 along any one or more of the lateral sides 103 to 106 for other examples (e.g., J-leads, gull-wing leads, short post leads, combinations thereof, etc., not shown). Furthermore, in the illustrated QFN example, the conductive leads 107 have configurations for soldering to conductive pads or Figure 1 The structure of the main printed circuit board 130 of the sensor system shown is on the lower or bottom side.

[0014] The electronic device 100 also includes a die attachment pad 110, for example, a conductive metal such as copper, aluminum, or other suitable metal or alloy thereof. Figure 1 and 1A In one example, the bottom side of the die attachment pad 110 is generally flush with the bottom or first side 101 of the electronic device 100, and the bottom side of the die attachment pad 110 is exposed along the first side 101 to the outside of the molded package structure 108, such as... Figure 1A The best display in China. For example... Figure 1A As seen, for example, when the electronic device 100 is mounted on the circuit board 130 of the host system to facilitate heat removal from the electronic device 100 during power-on operation in the host system, the bottom side of the die attachment pad 110 can function as a heat sink or thermal pad. In another possible implementation, the bottom side of the die attachment pad 110 is enclosed (e.g., covered) by a molded package structure 108.

[0015] Electronic device 100 has a first semiconductor die 111 and a second semiconductor die 112. For example... Figure 1Further illustrating, the electronic device 100 is installed in a system operating as a low-profile compact pressure sensor, the low-profile compact pressure sensor having a first die 111 and a second die 112 (e.g., a MEMS sensor die 111 and an ASIC die 112) side-by-side and an opening 120 in a molded package structure 108, the opening exposing the bottom side or first side 121 of the MEMS sensor first semiconductor die 111, and a cap 114 forming a closed reference pressure cavity 117 on the top side or second side 122 of the MEMS sensor first semiconductor die 111. In one example, the second semiconductor die 112 is attached to the top side of a die attachment pad 110 by a conductive or non-conductive die attachment adhesive 113. In one example, the first semiconductor die 111 is a MEMS die. In this example or another example, the second semiconductor die 112 is an ASIC die and is electrically connected to the first semiconductor die 111. The second semiconductor die 112 is enclosed by the package structure 108 and in Figure 1 The orientation shown is laterally spaced from the first semiconductor die 111 along the first direction.

[0016] Figure 1 and 1A An example electronic device includes a cap 114 having a top or cover 116 formed of a third semiconductor die. The cover 116 is supported by a cured die attachment adhesive structure 115. The die attachment adhesive 115 forms sidewalls of the cap 114, and the cap 114 forms a closed reference pressure cavity 117 over a portion of the first semiconductor die 111. In one example, the reference pressure cavity 117 is sealed during manufacturing. The cap 114 is attached to a second side 122 of the first semiconductor die 111 and defines the closed reference pressure cavity 117 over a portion of the second side 122 of the first semiconductor die 111.

[0017] A first semiconductor die 111 is configured to detect a sensed pressure (e.g., pressure in a reference pressure cavity 117) relative to a first side 121 of the first semiconductor die 111 and a second side 122 of the first semiconductor die 111. The first semiconductor die 111 is configured to provide an electrical signal to a second semiconductor die 112 based on the sensed pressure. In one example, the first semiconductor die 111 includes a sensor assembly that converts the pressure signal into an electrical signal via a small strain gauge embedded in a thin semiconductor region (referred to as a thin film or diaphragm) extending between the reference pressure cavity 117 and a first (e.g., bottom) side 121 of the first semiconductor die 111. In some examples, the sensor assembly may be a silicon piezoresistive pressure sensor, a silicon capacitive pressure sensor, a surface acoustic wave (SAW) pressure sensor, etc. In one or more embodiments, the first semiconductor die 111 and / or the second semiconductor die 112 may include integrated digital and / or analog signal conditioning components and circuitry for drift, sensitivity, and / or linearity compensation.

[0018] In one example, a first semiconductor die 111 provides capacitive MEMS pressure sensing or detection functionality by having one or more conductive layers (not shown) on a bottom first side 121 and / or a top second side (122), said conductive layers forming one or more capacitors with a conductive layer (not shown) on a third semiconductor die 116. In another example, one or more capacitors are formed between a conductive layer on one of sides 121 and 122 of the first semiconductor die 111 and a conductive layer on the bottom side of the third semiconductor die 116. In one example, the capacitor has a nominal capacitance of 1 to 10 pH when the ambient (e.g., sensed) pressure at the first side of the first semiconductor die 111 is approximately the same as the pressure in a closed reference pressure cavity 117 on a portion of the second (top) side 122 of the first semiconductor die 111.

[0019] A portion of the first semiconductor die 111 within the closed reference pressure cavity 117 acts as a diaphragm and moves in response to a pressure difference between the first side 121 and the reference pressure in the closed cavity 117. This diaphragm movement or displacement changes the spacing between the conductors of the sensing capacitor plate, thereby altering the capacitance representing the sensed pressure at the first side 121 relative to the reference pressure in the closed cavity 117. In one example, the first semiconductor die 111 detects the sensed pressure of the first side 121 of the first semiconductor die 111 relative to the pressure of the second side 122 of the first semiconductor die 111 (e.g., the pressure in the reference pressure cavity 117) based on the sensed capacitance. The first semiconductor die 111 provides an electrical signal to the second semiconductor die 112 based on the sensed pressure. In one example, the first semiconductor die 111 and / or the second semiconductor die 112 include a circuit system for detecting a nominal value of capacitance or a change in capacitance. The circuit system includes a tuned oscillator circuit or an RC charging circuit with an operating frequency that varies with pressure. The RC charging circuit includes one or more sensor capacitors that generate an output signal based on the time it takes to charge a capacitor from a current source (not shown).

[0020] In another example, the first semiconductor die 111 may include one or more MEMS piezoresistive strain gauge sensors formed as conductors on a diaphragm and connected in a bridge circuit (not shown). In operation, the differential pressure of the first side 121 relative to a reference pressure in the enclosed cavity 117 changes the resistance of the conductor to detect the pressure difference via a bridge circuit (e.g., a Wheatstone bridge). In these or other examples, the first semiconductor die 111 may implement a MEMS surface acoustic wave (SAW) pressure sensor that generates vibrations via a thin film or diaphragm. The first semiconductor die 111 may include a transducer that receives waves and detects changes in the amplitude or phase of the acoustic signal caused by surface deformation to provide an output signal based on the detected pressure.

[0021] exist Figure 1 In one example, the electronic device 100 includes a bonding wire electrical connection. A first bonding wire 118 is electrically connected between a conductive terminal (e.g., a metal bonding pad) of a first semiconductor die 111 and a conductive terminal of a second semiconductor die 112. Figure 1 The second bonding wire 119 is electrically connected between the second semiconductor die 112 and one of the conductive leads 107. In other instances, other types of electrical connections may be used alone or in combination with one or more bonding wires in the electronic device 100, such as lead frames, substrates, etc. (not shown).

[0022] Electronic device 100 is soldered to by solder 131 Figure 1The conductive pads of circuit board 130 in the system, and in this example, circuit board 130 is spaced apart from the bottom of electronic device 100 along a third direction Z to expose device opening 120 to the ambient pressure of the system, which is measured by electronic device 100. Electronic device 100 is attached to circuit board 130, for example, by soldering with solder paste, the soldering using surface mount technology (SMT) soldering processes to create solder joints 131. Opening 120 of package structure 108 extends along a third direction Z into a first side 101 of electronic device. A first (e.g., bottom) side 121 of a first semiconductor die 111 is exposed in opening 120 of package structure 108, and the opposite (e.g., top) second side 122 of the first semiconductor die 111 is partially enclosed by package structure 108. Opening 120 provides access to the first side 121 of the first semiconductor die 111 to detect ambient pressure of the system.

[0023] The die attachment pad 110 and the second semiconductor die 112 are laterally spaced from the first semiconductor die 111 and the opening 120 in a plane in the first direction X and the second direction Y. In the illustrated example, no part of the second semiconductor die 112 is above the first semiconductor die 111. The side-by-side arrangement of the first semiconductor die 111 and the second semiconductor die 112 provides a low-profile electronic device structure 100 compared to a stacked arrangement of MEMS dies and ASIC dies.

[0024] The thickness of the first semiconductor die 111 can be customized for a given pressure sensing application (e.g., the distance between the first side 121 and the second side 122 along the third direction Z). In the illustrated example, the bottom or first side 121 of the first semiconductor die 111 is etched during manufacturing after die-cutting to set the final thickness of the first semiconductor die 111. The etching creates an opening 120, in which the first side 121 of the first semiconductor die 111 is spaced apart from the first side 101 of the package structure 108 along the third direction Z. The package structure 108 has sidewalls of the opening 120 that extend along the third direction Z from the first side 121 of the first semiconductor die 111 to the first side 101 of the package structure 108, as shown. Figure 1 The best display in China.

[0025] Figure 1BA cross-sectional side view of another example of a pressure sensor electronics device 132, mounted on a circuit board 130 in a pressure sensing system application, is shown. This example includes individuals of the structures, features, and materials 101 to 104, 107, 108, 110 to 113, 117, 120 to 122, 130, and 131 described above. In this example, the electronics device 132 has a membrane cap 134 forming a closed reference pressure cavity 117 on the top or second side 122 of a first semiconductor die 111. The cap 134 includes a sidewall 135 forming the closed reference pressure cavity 117 and a die attachment adhesive material for a cover 136 of the cap, which is spaced apart from the second side 122 of the first semiconductor die 111 along a third direction Z above the closed reference pressure cavity 117.

[0026] Also refer to Figures 2 to 13 , Figure 2 Example method 200 for manufacturing electronic devices is shown, and Figures 3 to 13 exhibit Figure 1 and 1A The pressure sensor electronics 100 is shown in a side view of the fabrication process according to method 200. Method 200 and the electronics 10 and 132 described above offer advantages and cost-effectiveness regarding the fabrication of MEMS-based sensors and other sensor applications for pressure sensing, including reducing wafer-level etching steps and associated masks. Specifically, stacked arrangements of MEMS and ASIC dies typically require bottom cavity etching and associated masks, as well as wafer-level MEMS formation processes. In contrast, method 200 forms the bottom side 121 of the MEMS die after package molding without requiring etch masks for MEMS formation or cavity formation. In the illustrated example, the MEMS thin film formation is set to a thickness between the first side 121 and the second side 122 of the first semiconductor die 111, and the package opening 120 is created by a blanket silicon etching process without an etch mask.

[0027] Method 202 includes wafer processing at 202 to fabricate a first wafer having a MEMS die region. Figure 3 An example is shown in which a wafer-level process 300 is performed to form MEMS sensor elements on and / or within a semiconductor wafer 301, the semiconductor wafer having a starting bottom or first side 121 and a top or second side 122 as described above. In one example, wafer 301 is a silicon wafer, which includes... Figure 3 and 4Multiple die regions, designated 111, individually correspond to the subsequently separated first semiconductor die 111. In other instances, different types of semiconductor wafers may be used. Process 300 forms conductive features, such as traces (not shown), on the second side 122 of the first semiconductor wafer 301 for use in MEMS strain gauges, capacitor plates, resistor structures, surface acoustic wave transducers, etc.

[0028] In one instance, method 200 is... Figure 2 Continue at 204 or 206, where the cap is attached to the second side 122 of the bare die region 111 of the wafer 301. Figure 4 Show an example where in Figure 2 At location 204, a capping attachment process 400 is performed, which attaches individual caps 114 to corresponding portions of the second side 122 of the semiconductor wafer 301 in each die region designated 111. In this example, an individual cap 114 includes another semiconductor die 116 forming a cover that closes a reference pressure cavity 117, the cover being spaced apart from the second side 122 of the semiconductor die 111. In this example, the attachment process 400 includes forming and patterning a die attachment adhesive 115 that forms sidewalls that close the reference pressure cavity 117 in each die region of the wafer 301.

[0029] In one implementation, a separate semiconductor wafer (e.g., referred to as a capping wafer) is processed by selectively etching the space between the intended caps to form cap dies 116. Example attachment process 400 includes forming and patterning die attachment adhesive material to create a sidewall structure 115, and die bonding the two wafers with capping individuals soldered to corresponding portions of a second side 122 of wafer 301. In this example, process 400 also includes back-side grinding to remove material from the capping wafers between the respective caps 116 to produce… Figure 4 The structure shown in the figure has a finished cap and a bare sheet attachment adhesive 115 forming the sidewall of a closed reference pressure cavity 117.

[0030] In another implementation, the reference cavity 117 is sealed by forming a film cap 134 on individual die regions of the first wafer 301. Figure 2 This occurs at position 206. In this example, the cap 134 includes a die attachment adhesive forming: a cap 136 that closes the reference pressure cavity 117, the cap being spaced apart from the second side 122 of the semiconductor die 111; and a sidewall 135 that closes the reference pressure cavity 117, as described above. Figure 1BAs illustrated and described herein. In one embodiment, the process at 206 includes attaching a laminated structure having a film material 135 attached to a second side 122 of a first wafer 301 and patterning the material 135 to form sidewalls of a desired capping structure in each cell region of the wafer 304. In this example, a second laminated structure is attached to the top of the sidewall feature 135, and the second laminated structure is patterned to form a cap portion 136 of a capping structure 134.

[0031] Method 200 in Figure 2 The 208 locations within the wafer were further processed into individual wafers. Figure 5 An example is shown where a die-monopolization process 500 is performed to perform individual individualization or otherwise separate the first semiconductor die 111 from the starting wafer. Any suitable wafer dicing process may be used at 208.

[0032] exist Figure 2 At position 210, method 200 in one instance includes attaching a lead frame panel array to a carrier strip or other suitable carrier structure. Figure 6 An example is shown in which a leadframe panel array 601 is attached to the upper adhesive side of a carrier tape 602 by an attachment process 600. In one implementation, the leadframe panel array 601 includes a plurality of rows and columns individually corresponding to intended cell regions 604 of a manufactured intended electronic device, one of which is shown in Figure 6 In this example, the illustrated cell region 604 includes portions of the intended conductive lead 107 initially connected to corresponding leads of adjacent cell regions 604, and an example die attachment pad structure 110, wherein the lead frame features in this example include semi-etched features to facilitate die adhesion and reduce delamination in the finished electronic device, but not all possible requirements. In one example, process 600 positions and attaches a lead frame 601 to a carrier 602, wherein the bottom side of the conductive lead feature 107 engages a first portion of the adhesive top side of the carrier 602.

[0033] Method 200 continues Figure 2 The die attachment process is performed at locations 212 and 213. At location 212, the first semiconductor die 111 is attached to the second portion of the adhesive top side of the carrier tape 602 in each cell region of the panel array. Figure 7An example of attachment process 700 is shown, wherein an individual first semiconductor die 111 and a previously attached cap 114 are disposed on a carrier strip 602 in the illustrated cell region 604, wherein the bottom or first side 121 of the semiconductor die 111 is bonded to the adhesive top side of the carrier strip 602 and is coplanar with the bottom side of the conductive lead feature 107 and the bottom side of the die attachment pad 110 of the lead frame 601. In one example, attachment process 700 uses an automated pick-and-place device (not shown).

[0034] exist Figure 2 At position 213, method 200 includes attaching an individual of the second semiconductor die 112 to each cell region of the panel array. Figure 8 One example is shown where a first die attachment process or a second die attachment process 800 is performed, wherein the attachment process attaches a second semiconductor die 112 to the top side of a die attachment pad 110 in each cell region 604 of the panel array. In one example, process 800 includes dispensing die attachment adhesive material 113 on selected portions of the top side of the die attachment pad 110 in each cell region 604, and using an automated pick-and-place device to attach individual second semiconductor dies 112 to the die attachment adhesive material 113 over the top side of the die attachment pad 110 in each cell region 604. In one example, die attachment process 800 may include subsequent adhesive curing steps (e.g., thermal, UV, etc.), but not all possible implementations are required.

[0035] Method 200 in Figure 2 Electrical connection processing continues at point 214 to form one or more electrical interconnects between any two or more of the conductive lead 107, the first semiconductor die 111, the second semiconductor die 112, or a combination thereof. Figure 9 As an example, a wire bonding electrical connection process 900 forms a bonding line 118 electrically connecting a terminal of a first semiconductor die 111 to a first terminal of a second semiconductor die 112. In this example, the wire bonding process 900 also forms a second bonding line 119 in the illustrated cell region 604, which electrically connects a second terminal of the second semiconductor die 112 to a conductive lead feature 107 of the lead frame 601. Any suitable number of bonding lines or other electrical interconnect structures (e.g., conductive metal clips, routeable lead frames, or other single or multi-level package substrates, etc.) can be formed or attached for any desired electrical interconnection in any individual cell region 604 of the lead frame panel array.

[0036] Method 200 in Figure 2 The 216 points in the middle are further molded to form the molded encapsulated structure 108. Figure 10An example is shown in which a molding process 1000 is performed to form a molded package structure 108, which encloses a portion of a conductive lead feature 107, a portion of a die attachment pad 110, bonding lines 118 and 119, a first semiconductor die 111 and its cap 114, and a second semiconductor die 112. In the illustrated example, the molding process 1000 is performed at 216, wherein a carrier 602 is bonded to the bottom side of the conductive lead feature 107 and the bottom or first side 121 of the first semiconductor die 111.

[0037] Method 200 in Figure 2 Continue removing the carrier band at position 218. Figure 11 An example is shown where a strip removal process 1100 is performed, which removes carrier strips from the bottom or first side 101 of the molded package structure 108 and from the bottom or first side 121 of the first semiconductor die 111 (e.g., as described above). Figures 6 to 10 (Carrier 602 in the example). In this example, after performing molding process 1000 and before etching the exposed side 121 of the semiconductor die 111 in 222, carrier 602 is removed from lead frame 601 and semiconductor die 111 to expose the first side 121 of the first semiconductor die 111 and the bottom side 101 of the molded package structure 108.

[0038] In one instance, method 200 further includes Figure 2 The package is separated at position 220. Figure 12 An example is shown in which the processed array structure is mounted together with the top or second side 102 of the bonding second carrier structure 1202 of the molded package structure 108, and a package separation process 1200 (e.g., saw cutting, laser cutting, chemical etching, or a combination thereof) is performed from the bottom side of the illustrated structure, the package separation process separating the individual packaged electronic devices from each other and from the starting array structure along line 1204.

[0039] Method 200 includes Figure 2 Etching is performed at position 222. In one embodiment, this etching at 222 can be performed after package separation at 220, or in another embodiment, before package separation. Furthermore, the etching at 222 does not require masking and is performed during packaging to form the opening 120 of the finished electronic devices 100, 132. Moreover, molding etching after 222 eliminates the need for etching the MEMS sensor cavity during wafer processing of the first semiconductor die 111, thereby reducing the manufacturing cost and complexity of producing the finished electronic devices 100, 132. Figure 13An example is shown in which an etching process 1300 is performed while the separated electronics remain attached to the second carrier 1202. The etching process at 222 performed after package separation at 220 advantageously mitigates contamination of the finished bottom side 121 of the first semiconductor die 111 by residual material associated with the package separation process at 220.

[0040] Etching process 1300 forms an opening 120 extending into the bottom side 101 of the molded package structure 108. Any suitable etching process 1300 selective for silicon or other semiconductor materials of the first semiconductor die 111 can be used to remove material from the first side 121 of the first semiconductor die 111 while leaving the remaining portion of the molded package structure 108 and the conductive metal structures 107 and 110 largely unaffected. Etching process 1300 sets the final thickness between the first side 121 and the second side 122 of the first semiconductor die 111 and leaves the sidewalls of the opening 120 formed by the molded package structure 108 to provide a cavity exposing the first side or bottom side 121 of the first semiconductor die 111, thereby allowing the relative pressure between the sensing reference pressure cavity 117 and the bottom side 121 of the first semiconductor die 111.

[0041] The described electronic devices 100 and 132 and method 200 advantageously reduce or minimize wafer-level processing steps and costs in manufacturing electronic devices such as pressure sensors, including reducing the number of masking and etching processes during wafer processing. Furthermore, some implementations can reduce the number of wafer bonding steps used to build pressure sensors and other MEMS-based electronic devices. Additionally, the illustrated examples provide a lower profile sensor electronics device compared to a stacked arrangement of multiple dies. The above-described devices are illustrated in a context where a quad flat no-lead (QFN) package type facilitates direct exposure of the sensing surface of the first semiconductor die 111 to the environment, but other implementations may provide MEMS-based pressure sensors and other electronic devices with different package forms and types.

[0042] Modifications are possible in the described examples, and other implementations are possible within the scope of the claims.

Claims

1. An electronic device comprising: An encapsulation structure having opposing first and second sides, opposing third and fourth sides spaced apart from each other along a first direction, opposing fifth and sixth sides spaced apart from each other along a second direction orthogonal to the first direction, the first and second sides being spaced apart from each other along a third direction orthogonal to the first and second directions, and the encapsulation structure having an opening extending into the first side along the third direction. A first semiconductor die has a first side exposed in the opening of the package structure and an opposing second side partially enclosed by the package structure; and A second semiconductor die is electrically connected to the first semiconductor die, the second semiconductor die being enclosed by the packaging structure and laterally spaced from the first semiconductor die.

2. The electronic device of claim 1, comprising a die attachment pad that is laterally spaced from at least a portion of the opening of the package structure in a plane of the first and second directions and partially enclosed by the package structure, wherein the second semiconductor die is attached to the die attachment pad.

3. The electronic device of claim 2, wherein the die attachment pad has a side that is partially exposed outside the package structure along the first side.

4. The electronic device of claim 1, wherein the first semiconductor die is configured to detect a sensed pressure of a first side of the first semiconductor die relative to a second side of the first semiconductor die, and to provide an electrical signal to the second semiconductor die based on the sensed pressure.

5. The electronic device according to claim 1, comprising: A conductive lead, which is partially enclosed by the encapsulation structure and has a side that is partially exposed outside the encapsulation structure along the first side; A first bonding line (118) is electrically connected between the first semiconductor die and the second semiconductor die; and The second bonding wire (119) is electrically connected between the second semiconductor die and the conductive lead.

6. The electronic device according to claim 1, wherein: The first side of the first semiconductor die is spaced apart from the first side of the package structure along the third direction; and The packaging structure has a sidewall extending along the third direction from the first side of the first semiconductor die to the first side of the packaging structure.

7. The electronic device of claim 1, comprising a cap attached to the second side of the first semiconductor die and forming a closed reference pressure cavity over a portion of the second side of the first semiconductor die.

8. The electronic device of claim 7, wherein the cover comprises a third semiconductor die forming the cover of the closed reference pressure cavity and a die attachment adhesive forming the sidewall of the closed reference pressure cavity, the cover being spaced apart from the second side of the first semiconductor die along the third direction.

9. The electronic device of claim 7, wherein the cover comprises a die attachment adhesive forming the following: a cover for enclosing a reference pressure cavity, the cover being spaced apart from the second side of the first semiconductor die along the third direction; and a sidewall for enclosing the reference pressure cavity.

10. The electronic device of claim 7, wherein the first semiconductor die is configured to detect a sensed pressure of the first side relative to the pressure of the reference pressure cavity, and to provide an electrical signal to the second semiconductor die based on the sensed pressure.

11. A system comprising: Circuit boards; and An electronic device attached to the circuit board and comprising a package structure and a first semiconductor die and a second semiconductor die; The encapsulation structure has opposing first and second sides, opposing third and fourth sides spaced apart from each other along a first direction, opposing fifth and sixth sides spaced apart from each other along a second direction orthogonal to the first direction, the first and second sides being spaced apart from each other along a third direction orthogonal to the first and second directions, and the encapsulation structure having an opening extending into the first side along the third direction. The first semiconductor die has a first side exposed in the opening of the package structure, and an opposing second side partially enclosed by the package structure; and The second semiconductor die is electrically connected to the first semiconductor die, and the second semiconductor die is enclosed by the packaging structure and laterally spaced from the first semiconductor die.

12. The system of claim 11, comprising a die attachment pad that is laterally spaced from at least a portion of the opening of the package structure in a plane of the first and second directions and partially enclosed by the package structure, wherein the second semiconductor die is attached to the die attachment pad.

13. The system according to claim 11, wherein: The first side of the first semiconductor die is spaced apart from the first side of the package structure along the third direction; and The packaging structure has a sidewall extending along the third direction from the first side of the first semiconductor die to the first side of the packaging structure.

14. The system of claim 11, comprising a cap attached to the second side of the first semiconductor die and forming a closed reference pressure cavity over a portion of the second side of the first semiconductor die.

15. The system of claim 14, wherein the first semiconductor die is configured to detect a sensed pressure of the first side relative to the pressure of the reference pressure cavity, and to provide an electrical signal to the second semiconductor die based on the sensed pressure.

16. A method of manufacturing an electronic device, the method comprising: Positioning a semiconductor die, wherein one side of the semiconductor die is coplanar with the bottom side of the conductive lead feature of the lead frame; A molded encapsulation structure forming a portion of the conductive lead features; and The exposed side of the semiconductor die is etched to form an opening extending into the bottom side of the molded package structure.

17. The method of claim 16, further comprising attaching a cap to a second side of the semiconductor die to form a closed reference pressure cavity over a portion of the second side of the semiconductor die, the cap including another semiconductor die forming the cap of the closed reference pressure cavity and a die attachment adhesive forming the sidewall of the closed reference pressure cavity, the cap being spaced apart from the second side of the semiconductor die.

18. The method of claim 16, further comprising attaching a cap to a second side of the semiconductor die to form a closed reference pressure cavity over a portion of the second side of the semiconductor die, the cap comprising a die attachment adhesive forming: a cap of the closed reference pressure cavity, the cap being spaced apart from the second side of the semiconductor die; and a sidewall of the closed reference pressure cavity.

19. The method of claim 16, wherein: Positioning the semiconductor die includes: attaching the lead frame to a carrier, wherein the bottom side of the conductive lead features engages a first portion of one side of the carrier; and attaching the semiconductor die to the carrier, wherein the side of the semiconductor die engages a second portion of the side of the carrier. Forming the molded package structure includes performing a molding process, wherein the carrier is bonded to the bottom side of the conductive lead feature and the side of the semiconductor die; and The method further includes removing the carrier from the lead frame and the semiconductor die after performing the molding process and before etching the exposed side of the semiconductor die to expose the side of the semiconductor die and the bottom side of the molded package structure.

20. The method of claim 16, wherein the semiconductor die is a first semiconductor die, the method further comprising, prior to forming the molded package structure: The second semiconductor die is attached to the die attachment pad of the lead frame; Electrically connect the terminals of the first semiconductor die to the first terminal of the second semiconductor die; and The second terminal of the second semiconductor die is electrically connected to the conductive lead feature of the lead frame.

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