Calculation device and data moving method

Abstract

A computing device (10) sets an arrangement of virtual PEs (12B) such that at least one of rows and columns is inverted with respect to an arrangement of real PEs (12A), and continuously arranges data in the real PEs (12A) and the virtual PEs (12B). Then, the arithmetic device (10) moves the data in the order of arrangement of the data by performing data movement between the virtual PEs (12B) in a direction different from the data movement between the real PEs (12A).

Description

Cross-reference of related applications

[0001] This application is based on Japanese Application No. 2023-154064, filed on September 21, 2023, the contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to computing devices and data movement methods. Background Technology

[0003] A computing device consisting of multiple processors arranged in an array (two-dimensional) has been developed.

[0004] In such computing devices, there is a need to increase the data processing speed. For example, Patent Document 1 describes a computing device that includes a first plurality of processing cores arranged in an array and a second plurality of processing cores arranged in an array. A subset of the first plurality of processing cores of the computing device is configured between a data processor and the second plurality of processing cores.

[0005] Existing technical documents Patent documents Patent Document 1: US Patent No. 11086574 Summary of the Invention

[0006] Figure 20 This is a schematic diagram of a conventional computing device 100, in which processors (Processing Elements, hereinafter referred to as "PEs") 102 are arranged in an array. Furthermore, the coordinates of each PE 102 are represented by (0,0), x=0 indicates the first column (hereinafter referred to as column 0), and y=0 indicates the first row (hereinafter referred to as row 0). Additionally, symbol 104 indicates wiring for inputting and outputting data between PEs 102 or between PEs 102 and external memory 106. In the conventional computing device 100, data is configured to be input to each PE 102, for example, starting from the upper left PE 102 with coordinates (0,0) and sequentially input from external memory 106.

[0007] Here, when the amount of data to be processed exceeds the number of PE102s, it is impossible to configure all the data on PE102s. For example, if data held in a PE102 with a width of 4 and located at the right end (column 3), and processing is performed using data adjacent to the right side (hereinafter referred to as "end-adjacent data") by the PE102 at column 3, the end-adjacent data needs to be transferred from the external memory 106 on the opposite end (column 0) of the PE102. In this data transfer, the distance the end-adjacent data moves becomes longer, thus processing takes time.

[0008] Furthermore, when data is not configured on PE102 itself, but rather the required data is pre-configured on PE102, typically the data adjacent to the right side of the right-hand PE102 is configured on the left-hand PE102 (x=0), and the data adjacent to its right side is configured on the right-hand adjacent PE102 (x=1). That is, if we use two-dimensional coordinates (X, Y) to represent the arrangement of data before it is configured on PE102, then in the case of 4 rows and 4 columns, the data configured on PE102 is located at the position (x, y) = (the remainder of X divided by 4, the remainder of Y divided by 4). In this case, adjacent data at one end needs to be transferred from the opposite end of PE102, increasing the distance traveled and thus requiring processing time.

[0009] The purpose of this disclosure is to provide a computing device and a data movement method that can efficiently process more data than the number of processors arranged in a row.

[0010] One aspect of the computing device disclosed herein is a computing device having multiple processors, wherein a virtual processor is arranged based on the actual arrangement of the processors, with at least one of the rows and columns being in reverse order, data is continuously configured in the actual processors and the virtual processors, and data movement between the virtual processors is performed in a direction different from data movement between the actual processors, thereby moving the data according to the configuration order of the data.

[0011] The computing device of this structure uses the arrangement of real processors as a reference, and arranges virtual processors in a manner where at least one of the rows and columns is reversed. Furthermore, data is continuously configured for both the real and virtual processors. The virtual processors are physically positioned at the same location as the real processors corresponding to the configured arrangement, and data is maintained and moved. Data assigned to virtual processors is stored in registers of the processors at the corresponding coordinates. That is, the remaining data in a sequence of consecutive data that is configured after the real processors is returned and configured in the virtual processors. Moreover, by moving together in the same direction between the real and virtual processors, data can be moved according to the data configuration order. At this time, the direction of movement of the virtual processors is physically different from that of the real processors.

[0012] In this architecture, the data held in the processor's registers is maintained in either forward or reverse order when input from an external source. For example, if the arrangement of data before the processor is represented by two-dimensional coordinates (X, Y), the (x, y) of the data arranged in the processor when there are four rows and four columns is as follows: If the quotient of X divided by 4 is even, x = "the remainder of X divided by 4"; if the quotient of X divided by 4 is odd, x = "3 - (the remainder of X divided by 4)". Similarly, if the quotient of Y divided by 4 is even, y = "the remainder of Y divided by 4"; if the quotient of Y divided by 4 is odd, y = "3 - (the remainder of Y divided by 4)". Furthermore, the data represented by (X, Y) is allocated to a processor located at the calculated (x, y) coordinate.

[0013] Therefore, data that could not previously be stored on the real processor is now stored on a virtual processor and moved from the virtual processor to the real processor, allowing the real processor to input data with a shorter travel distance. Furthermore, because data moves from the virtual processor to the real processor, there is no need for data input / output between external memory and the processor, enabling continuous data processing. Therefore, according to this structure, it is possible to efficiently process more data than the number of processors arranged in a single array.

[0014] In the computing device, data that moves from the registers of the actual processor and the corresponding virtual processor can also be set for the actual processor and the corresponding virtual processor.

[0015] In the aforementioned computing device, the computing device may also include: a first wiring for moving data between the actual processors; and a second wiring for moving data between the virtual processors, wherein the first wiring and the second wiring move the data in different directions, respectively. Thus, data movement between actual processors and between virtual processors can be performed in a single process. Alternatively, the second wiring may be omitted, and in data movement between virtual processors, only the actual processors and the first wiring are used to move the data in their respective directions multiple times.

[0016] In the aforementioned computing device, in order to perform convolution operations using a processor group consisting of multiple processors arranged in a two-dimensional configuration, virtual processors are configured around the real processors. Data of interest is defined for the real processors, and data surrounding the data of interest is defined for the virtual processors. The data of interest is the data located at the center of the convolution operation, and from the perspective of other processors, it is also the data surrounding the data of interest.

[0017] In the computing device, the actual processor located at the corner of the processor group may have at least three movement circuits for moving data between the actual processor and the three virtual processors in the tilt direction, and the actual processor located on the side of the processor group other than the corner may have at least one movement circuit for moving data between the actual processor and one of the virtual processors.

[0018] In the aforementioned computing device, the actual processor may also have eight moving circuits, which move data between the eight moving circuits and eight virtual processors, including those in the up, down, left, and right tilting directions.

[0019] In the aforementioned computing device, if data is input from external memory (16) to the actual processor, the actual processor moves the data to the virtual processor and reverses the order, storing the data in a register provided by the processor.

[0020] In the aforementioned computing device, data may be input from external memory to the processors located at the ends and the processors located inside the two-dimensionally arranged real processors, and the real processors may cause the arrangement of the data input from the ends and the inside to be reversed by moving the arrangement of the data input from the virtual processors.

[0021] In the computing device, the real processor and the virtual processor may be configured as a continuous one-dimensional arrangement, with one-dimensional data continuously configured in the real processor and the virtual processor.

[0022] In the aforementioned computing device, the processor may also arrange the one-dimensional data in ascending or descending order in each row or column of the processor according to a two-dimensional configuration.

[0023] In the aforementioned computing device, the real processor and the virtual processor may be configured to divide the input data into multiple data segments according to a predetermined number of bits, and move each data segment obtained by dividing it into the predetermined number of bits.

[0024] In the aforementioned computing device, the data obtained by the segmentation can also be obtained by the processor being configured in a two-dimensional configuration such that the bit positions are alternately arranged in ascending or descending order.

[0025] One aspect of the data movement method disclosed herein can also be a data movement method for a computing device having multiple processors. Based on the actual arrangement of the processors, a virtual processor arrangement is set in a manner where at least one of the rows and columns is reversed. Data is continuously configured between the actual processors and the virtual processors, and data movement between the virtual processors is performed in a direction different from the data movement between the actual processors, thereby moving the data according to the configuration order of the data.

[0026] Invention Effects According to this disclosure, it is possible to efficiently process more data than the number of processors arranged in a row. Attached Figure Description

[0027] The foregoing and other objects, features, and advantages of this disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. These drawings are: Figure 1 This is a schematic structural diagram of the computing device in the implementation method. Figure 2 This is a schematic diagram illustrating the real PE and virtual PE of the implementation method. Figure 3 This is a schematic diagram showing the arrangement order of the data input to the PE in the implementation method. Figure 4 This is a schematic diagram illustrating data movement within the computing device of an embodiment. Figure 5 This is a schematic diagram illustrating data movement within the computing device of an embodiment. Figure 6 This is a schematic diagram illustrating data movement within the computing device of an embodiment. Figure 7 This is a schematic diagram illustrating the relationship between the data set of interest and the necessary data set when performing convolution operations in an implementation method. Figure 8 This is a schematic diagram illustrating the setup of the real PE group and the virtual PE group when performing convolution operations in an implementation method. Figure 9 This is a schematic diagram illustrating the case where the data set of interest is shifted to the right during the convolution operation in the implementation method. Figure 10 This is a schematic diagram illustrating the case where the data set of interest is shifted to the right and down in the convolution operation of the implementation method. Figure 11 This is a schematic diagram illustrating data input from the external memory of the embodiment to the computing device. Figure 12 This is a schematic diagram illustrating data output from the computing device of the embodiment to the external memory. Figure 13 This is a schematic diagram illustrating how data is input from the end and interior of the actual PE assembly in the implementation embodiment. Figure 14 This is a schematic diagram showing a one-dimensional arrangement of the real PE and virtual PE in the implementation method. Figure 15 This is a schematic diagram of one-dimensional data input to the computing device in the implementation method. Figure 16 This is a schematic diagram illustrating the data movement of one-dimensional data in a computing device according to an embodiment. Figure 17 This is a schematic diagram illustrating the data movement of one-dimensional data in a computing device according to an embodiment. Figure 18 This is a schematic diagram illustrating the data movement of one-dimensional data in a computing device according to an embodiment. Figure 19 This is a schematic diagram illustrating data movement accompanying SIMD processing in an embodiment. Figure 20 This is a schematic diagram of an existing computing device. Detailed Implementation

[0028] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. Furthermore, the embodiments described below represent one example of implementing the present disclosure and are not intended to limit the present disclosure to the specific configurations described below. When implementing the present disclosure, specific configurations may be appropriately adopted according to the embodiments.

[0029] Figure 1 This is a schematic diagram of the computing device 10 in this embodiment.

[0030] The computing device 10 includes multiple processing elements (PEs) 12. Furthermore, in... Figure 1 In the example, 16 PE12s in 4 rows and 4 columns are arranged in two dimensions, but the computing device 10 can have as many PE12s as possible. In addition, multiple PE12s can not only be arranged in two dimensions (array), but also in three dimensions or more, as described later.

[0031] The PE12 in this embodiment has an arithmetic circuit and a register.

[0032] The arithmetic circuit performs various operations such as ==, !=, >, >=, <, <=, >>, <<, or, and, min, max, clip, add, sub, mul, div, mod, and macc. The arithmetic circuit performing these operations can be appropriately selected by the arithmetic device 10. In the arithmetic device 10 of this embodiment, one PE12 can have multiple arithmetic circuits, allowing one PE12 to select multiple arithmetic operations from different operations or multiple prepared identical operations and perform them simultaneously. Alternatively, each PE12 can perform its own different arithmetic operations, thereby enabling the arithmetic device 10 to perform multiple different operations simultaneously.

[0033] A register is a storage unit that holds (stores) data. For example, an arithmetic circuit performs operations on the data held in a register, and the register holds the result of the operation. In addition, the PE12 can also have multiple registers.

[0034] In addition, the arithmetic unit 10 is capable of performing various processes, such as data movement or calculation according to each PE12. However, if each PE12 is configured by a program, the program size will increase.

[0035] Therefore, the actions of the computing device 10 to perform the required functions can be preset for each PE12 or set by data, and different actions can be performed for each PE12 according to the requirements of the functions. In addition, the data is the setting data input to the PE12, which is different from the data for moving between PE12. As a result, it is not necessary to set the actions of each PE12 by program, reducing the amount of program required to enable the computing device 10 to function.

[0036] In addition, each PE12 has a moving circuit for moving data to other adjacent PE12s. The direction and timing of the data movement by the moving circuit are preset or set by data.

[0037] PE12 retrieves data from external memory 16 via wiring 14 and stores it in a register. Furthermore, PE12 is electrically connected via wirings 14A and 14B for data movement between adjacent PE12. Even if the wirings 14 between PE12 are omitted in other figures, PE12 is connected to external memory 16 and adjacent PE12 via wirings 14, etc. In this embodiment, data movement also includes the concept of data copying. Wirings 14A and 14B will be described in detail later.

[0038] Here, refer to Figure 2 The computing device 10 of this embodiment will be described in detail. Figure 2In this embodiment, x represents the column coordinate (column number), and y represents the row coordinate (row number). The computing device 10 in this embodiment is as follows: Figure 2 As shown, the arrangement of virtual PE12 is based on the actual arrangement of PE12, and the columns are arranged in reverse order. In the following explanation, the actual PE12 is also referred to as actual PE12A, and the group of actual PE12A is referred to as actual PE group 20A. Furthermore, the virtual PE12 is also referred to as virtual PE12B, and the group of virtual PE12B is referred to as virtual PE group 20B. That is, in Figure 2 In the example, a virtual PE group 20B is set up that is adjacent to the real PE group 20A and has its columns reversed.

[0039] Real PE12A and Figure 1 The PE12 shown is identical to the one used in the circuit, which performs various operations on the input data. On the other hand, the virtual PE12B is a non-existent PE12 and therefore does not perform any operations. Furthermore, the real PE12A at the same coordinates (row and column numbers) corresponds to the virtual PE12B. That is, the virtual PE12B is physically positioned at the same location as the real PE12A corresponding to the set arrangement, and performs data retention and data movement. The data set in the virtual PE12B is stored in the register of the corresponding PE12 at the same coordinates.

[0040] Together with the real PE12A, the data moved from the registers of the PE12 is set in the corresponding virtual PE12B. Alternatively, the circuit can be configured to set the data for the corresponding virtual PE12B simultaneously with the real PE12A.

[0041] Specifically, multiple data sets are held in the register of PE12. When processing a data set of interest, the data set of interest is set in the moving circuit of the actual PE12A. Moreover, by setting (copying) the surrounding data from the register in the moving circuit of the virtual PE12B, the data set can be moved at once. Thus, even if the data set of interest becomes a data set one to the right of it, the same processing can be performed even for different data sets by setting (copying) the data from the register. That is, the data is not initially placed in the virtual PE12B.

[0042] Furthermore, the data stored in the registers of the PE12 in this embodiment is maintained in either forward or reverse order when input from an external source. For example, if the arrangement of data before the PE12 is represented by two-dimensional coordinates (X, Y), the (x, y) of the data arranged in the PE12 when there are 4 in each direction is as follows: When the quotient of X divided by 4 is even, x = "the remainder of X divided by 4"; when the quotient of X divided by 4 is odd, x = "3 - (the remainder of X divided by 4)". Similarly, when the quotient of Y divided by 4 is even, y = "the remainder of Y divided by 4"; when the quotient of Y divided by 4 is odd, y = "3 - (the remainder of Y divided by 4)". Moreover, the data represented by (X, Y) is arranged in one PE12 located at the calculated (x, y).

[0043] Figure 3 It is the order in which the data input from external memory 16 to each PE12 is arranged. Figure 3 The x and y coordinates correspond to the column and row of PE12. For example... Figure 3 As shown, the x and y coordinates alternate in ascending and descending order, such as “0”~“3”, “3”~“0”, and “0”~“3”. Correspondingly, the data is input into PE12 in rows (two-dimensional).

[0044] Will Figure 3 The data configuration shown is the state of the real PE12A and the virtual PE12B. Figure 2 The values ​​within the actual PE12A and the virtual PE12B. For example... Figure 2 As shown, in the computing device 10 of this embodiment, data is configured continuously in rows in the real PE12A and the virtual PE12B.

[0045] In addition, Figure 2 , Figure 3 In the example, the real PE12A for (0,0) to (3,0) is set to data "00" to "03", and the virtual PE12B for (3,0) to (0,0) in reverse order is set to data "04" to "07". That is, PE12 wraps the continuous data at the end of the column, sets the data before wrapping to the data of the real PE12A, and sets the data after wrapping to the data of the virtual PE12B.

[0046] In this way, the computing device 10 of this embodiment continuously configures data in the real PE12A and the virtual PE12B. Then, the computing device 10 moves the data between the virtual PE12Bs in a direction different from the data movement between the real PE12A, so that the data moves according to the data configuration order. Furthermore, by moving the real PE12A and the virtual PE12B together in the same direction, the data can be moved according to the data configuration order. At this time, the movement direction of the virtual PE12B is physically different from that of the real PE12A.

[0047] Figures 4-6 This is a schematic diagram illustrating data movement within the computing device 10 of this embodiment. Figure 4 From Figure 2 The diagram illustrates the state after the data configuration is moved one time to the left and the state after moving the data twice. The data movement occurs simultaneously in all PE12s in one direction, following the data configuration order. Furthermore, in the real PE12A, data moves simultaneously from (3,0) to (0,0), while in the virtual PE12B, data moves simultaneously from (0,0) to (3,0). That is, the data in the virtual PE12B moves in the opposite direction to the arrangement order in the real PE12A.

[0048] Therefore, the computing device 10 of this embodiment includes wiring 14A and 14B between PEs 12. Wiring 14A is used to move data between real PEs 12A. Wiring 14B is used to move data between virtual PEs 12B. Wiring 14A and wiring 14B move data in different directions (opposite directions). By using wiring 14A and 14B to move data, data movement between real PEs 12A and between virtual PEs 12B can be performed simultaneously. Alternatively, the computing device 10 of this embodiment may not include wiring 14B, and in the data movement between virtual PEs 12B, only wiring 14A is used to move data in different directions multiple times.

[0049] To enable data to move in different directions between real PE12A and virtual PE12B, PE12 is equipped with a moving circuit for data movement between real PE12A and a moving circuit for data movement between virtual PE12B. These moving circuits can move data not only between real PE12A or virtual PE12B adjacent vertically, horizontally, and vertically, but also between real PE12A or virtual PE12B adjacent diagonally.

[0050] Furthermore, the data set in the virtual PE12B (numbered in column 3) is actually stored in the register of the PE12 (numbered in column 3). Therefore, data movement from the virtual PE12B (numbered in column 3) to the actual PE12A (numbered in column 3) occurs within the actual PE12A. Thus, the PE12 located at the end of the column has a movement circuit for performing data movement within itself.

[0051] Here, for example, when a 3-column numbered PE12A performs calculations based on adjacent data such as "04", "14", "24", and "34" held by itself, conventionally, the 3-column numbered PE12A retrieves this data from external memory 16 each time. In such a case, the 3-column numbered PE12A needs to retrieve data from external memory 16 via the 0-2 column numbered PE12A, and data retrieval takes time. Furthermore, referring to... Figure 20 When PE102 is pre-configured with necessary data instead of being configured with a single data entry, typically, the right neighbor of the rightmost PE102 is configured in the leftmost PE102 (x=0), and its right neighbor is configured in the leftmost PE102 (x=1). That is, if we use two-dimensional coordinates (X, Y) to represent the arrangement of data before it is configured in PE102, then when PE102 is arranged with four entries in both directions, the data configured in PE102 is configured in the PE102 with (x, y) = (the remainder of X divided by 4, the remainder of Y divided by 4). In this case, adjacent data at the ends need to be transferred from the opposite end PE102, increasing the travel distance and thus requiring processing time.

[0052] In contrast, in this embodiment, such as Figure 4 As shown, the real PE12A with 3 columns of numbers obtains data from the virtual PE12B with 3 adjacent columns of numbers, so the data retrieval time is shorter than before.

[0053] Additionally, after each data movement, the data moves to the left, and according to... Figure 3 The data configuration order shown is as follows: the virtual PE12B, numbered in column 0, is newly configured with data "08", "18", "28", and "38". Furthermore, after the data is moved twice, the virtual PE12B in column 0 becomes empty instead of retaining the data.

[0054] exist Figure 5 After the three moves shown, the data moves to the left, and according to... Figure 3The data configuration order shown is as follows: the virtual PE12B in column 1 is newly configured with data "09", "19", "29", and "39". On the other hand, the virtual PE12B in column 0 is empty and does not retain any data. Furthermore, after four shifts, as the data shifts to the left, the virtual PE12Bs in columns 0 and 1 are also empty and do not retain any data.

[0055] Although the illustration is omitted, after five shifts, the data moves to the left, and new data "0a", "1a", "2a", and "3a" are configured in the virtual PE12B with column 2 numbers. On the other hand, the virtual PE12Bs with column 0 and column 1 numbers become empty without retaining any data. Furthermore, after six shifts, as the data moves to the left, the virtual PE12Bs with column 0 to column 2 numbers become empty without retaining any data.

[0056] Then, in Figure 6 After seven moves, the data moves to the left and new data “0b”, “1b”, “2b”, and “3b” are configured in the virtual PE12B with the 3 columns numbered.

[0057] Furthermore, after eight moves, the data shifts to the left, and according to... Figure 3 The data configuration order shown is the virtual PE12B configuration data numbered in columns 3 to 0: “0f”~“0c”, “1f”~“1c”, “2f”~“2c”, and “3f”~“3c”. Furthermore, the data is then moved to the left in the same manner as above, but no new data is configured.

[0058] In this embodiment, the arithmetic unit 10 arranges the virtual PE12B in a manner where at least one of the rows and columns is reversed, based on the arrangement of the actual PE12A. Furthermore, the arithmetic unit 10 continuously configures data in the actual PE12A and the virtual PE12B. Data set as virtual PE12B is stored in a register of the PE12 corresponding to the virtual PE12B. That is, the remaining data in a series of consecutive data that is configured after the actual PE12A is returned and configured in the virtual PE12B. Moreover, by moving data between virtual PE12B in a direction different from the data movement between actual PE12A, data movement can be performed according to the data configuration order.

[0059] Therefore, data that could not previously be stored in the real PE12A is set in the virtual PE12B and moves from the virtual PE12B to the real PE12A, thus inputting data to the real PE12A with a shorter travel distance. Furthermore, since the data moves from the virtual PE12B to the real PE12A, no data input / output occurs between the external memory 16 and the PE12, enabling continuous data processing. Therefore, the computing device 10 of this embodiment can efficiently process more data than the number of arranged PE12s.

[0060] Furthermore, in this embodiment, the hypothetical PE group 20B with reversed columns is defined, but it is not limited to this. As mentioned above, the hypothetical PE group 20B only needs to have at least one of its rows and columns reversed. That is, the hypothetical PE group 20B can be reversed in rows, or it can be reversed in both rows and columns.

[0061] (Applications of convolution operation) Reference Figures 7-10 The following describes the application of the above implementation method to convolution operations.

[0062] Figure 7 This is a schematic diagram illustrating the relationship between the data used in the convolution operation of this embodiment and PE12. Figure 7 In this example, the computing device 10 has 16 (4 rows and 4 columns) PE12. The data groups “44” to “47”, “54” to “57”, “64” to “67”, and “74” to “77”, which form the central data group, are the data of interest for the convolution operation. The data of interest is the data located at the center of the convolution operation, and is also the data surrounding the data of interest from the perspective of the other PE12. In the data groups surrounding the central data group, the data within the inner dashed line is the necessary data for the 3×3 convolution operation, and the data within the outer dashed line is the necessary data for the 5×5 convolution operation.

[0063] In this embodiment, the computing device 10 is configured to arrange virtual PE12B around the real PE12A in order to perform convolution operations using a PE group (real PE group 20A) in which PE12 are arranged in a two-dimensional shape. Then, data of interest are set in the real PE12A, and data surrounding the data of interest, i.e., necessary data, are set in the virtual PE12B.

[0064] Figure 8 The settings for the real PE group 20A and the virtual PE group 20B in this embodiment are shown. Figure 8In the example, the area enclosed by the dashed lines (0,0)~(0,3) and (0,0)~(3,0) is the real PE group 20A. Furthermore, the area surrounding the real PE group 20A is the virtual PE group 20B. Additionally, the virtual PE12B group (6 virtual PE12B on one side) within the dashed lines adjacent to the real PE group 20A in one row and one column is set up with the necessary data for a 3×3 convolution operation. The virtual PE12B group (8 virtual PE12B on one side) within the dashed lines adjacent to the real PE group 20A in two rows and two columns is set up with the necessary data for a 5×5 convolution operation. Then, PE12 is folded back as described above, and the data of the real PE12A and virtual PE12B are configured with the same coordinates.

[0065] Figure 9 This is a schematic diagram illustrating the case where the data group of interest is shifted to the right during the convolution operation in this embodiment. Figure 9 In the diagram, virtual PE12B is represented by a dashed line. Virtual PE12B is illustrated as a portion overlapping the corresponding real PE12A. PE12 holds the data of real PE12A and virtual PE12B at the same coordinates. For example, PE12 at (0,0) holds the data "44" of real PE12A and the data "43" of virtual PE12B.

[0066] In the first move used to shift the data group of interest to the right, the data held by the actual PE12A in each row moves to the actual PE12A in the column to its right. Meanwhile, the data held by the virtual PE12B in each row moves to the actual PE12A in the column to its left. Thus, the data movement between actual PE12A and between virtual PE12B occurs in opposite directions. Furthermore, the data movement from the virtual PE12B (column 0) to the actual PE12A (column 0) is actually a data movement within PE12 (column 0).

[0067] Reference Figure 8 ,exist Figure 9 The data movement described herein is entirely from left to right. Additionally, the second movement, used to move the data group of interest to the right, is the same as the first: the data held by the actual PE12A in each row moves to the actual PE12A in the adjacent column to the right, and the data moves from the virtual PE12B numbered in column 0 to the actual PE12A numbered in column 0.

[0068] Figure 10 This is a schematic diagram illustrating the case where the data group of interest is moved to the right and down (diagonally down-right) during the convolution operation in this embodiment. Figure 10In this context, PE12 retains the data of the real PE12A and the virtual PE12B, which share the same coordinates. That is, PE12 retains the data of the real PE12A and the data of the virtual PE12B, which overlaps with the left, top, and upper left sides of the real PE12A. For example, PE12 at (0,0) retains the data "44" of the real PE12A and the data "33", "34", and "43" of the virtual PE12B.

[0069] In the first move used to move the data group of interest to the right and down (diagonally down-right), the data held by real PE12A is moved to real PE12A diagonally down-right. Additionally, the data held by the left-neighboring virtual PE12B is moved to real PE12A at (1,0), (2,0), and (3,0). The data held by the upper-neighboring virtual PE12B is moved to real PE12A at (0,1), (0,2), and (0,3).

[0070] Additionally, the data “33” of the virtual PE12B at (0,0) moves to the real PE12A at (0,0).

[0071] The data “32” of the virtual PE12B at (1,0) moves to the left neighboring virtual PE12B at (0,0), and the data “42” of the virtual PE12B at (1,0) moves to the left diagonally below the virtual PE12B at (0,1).

[0072] The data “24” of the virtual PE12B at (0,1) is moved to the virtual PE12B at (1,0) in the upper right, and the data “23” of the virtual PE12B at (0,1) is moved to the virtual PE12B at (0,0) above.

[0073] The data “22” of the virtual PE12B at (1,1) is moved to the virtual PE12B at (0,0) in the upper left, the data “25” of the virtual PE12B at (1,1) is moved to the virtual PE12B at (2,0) in the upper right, and the data “52” of the virtual PE12B at (1,1) is moved to the virtual PE12B at (0,2) in the lower left.

[0074] Thus, the data between real PE12A moves diagonally downwards to the right, while the data between virtual PE12B moves in a different direction than the data between real PE12A. Additionally, refer to... Figure 8 ,exist Figure 10 The data movement described herein is all in the direction of right-downward movement.

[0075] The second move is the same as the first: the data held by real PE12A moves diagonally to the lower right of real PE12A. Then, the data held by the left neighboring virtual PE12B is moved to real PE12A at (1,0), (2,0), and (3,0). Additionally, the data held by the upper neighboring virtual PE12B is moved to real PE12A at (0,1), (0,2), and (0,3). Data moves from virtual PE12B at (0,0) to real PE12A at (0,0).

[0076] As described above, in order to perform convolution operations using the real PE group 20A, the computing device 10 of this embodiment is configured to arrange virtual PE 12B around the real PE 12A. Then, data of interest is set in the real PE 12A, and data surrounding the data of interest, i.e., necessary data, is set in the virtual PE 12B. As a result, it is not necessary to prepare PE 12 for holding necessary data in order to perform convolution operations, and the data movement path is also shortened.

[0077] Furthermore, if the data movement direction between real PE12A is determined, the data movement direction between virtual PE12B is also determined. Therefore, the data movement setting between virtual PE12B can also be determined in conjunction with the data movement setting between real PE12A.

[0078] Here, in the PE12 of this embodiment, the real PE12A located at the corner of the real PE group 20A has at least three movement circuits for data movement between it and three virtual PE12Bs including the tilt direction. In addition, the real PE12A located on the side of the real PE group 20A other than the corner has at least one movement circuit for data movement between it and one virtual PE12B.

[0079] For example, refer to Figure 8 In the case of a 3×3 convolution operation, the real PE12A located at (0,0) in the upper left corner of the real PE group 20A moves data between itself and three virtual PE12Bs located at (0,0). Therefore, the real PE12A at (0,0) has at least three movement circuits to move data between itself and the three virtual PE12Bs located at (0,0). The same applies to the real PE12A located at (0,3) in the lower left, (3,0) in the upper right, and (3,3) in the lower right.

[0080] Furthermore, the real PE12A located on the left side (0,1) of the real PE group 20A (excluding the corner) performs data movement between itself and a virtual PE12B located on its left (0,1). Therefore, the real PE12A at (0,1) has at least one movement circuit for performing data movement with a virtual PE12B at (0,1). The same applies to the real PE12A on the left (0,2), above (1,0), (2,0), right (3,1), (3,2), and below (1,3), (2,3).

[0081] Similarly, refer to the above. Figure 8 In the case of a 5×5 convolution operation, the real PE12A located in the upper left corner of the real PE group 20A is not only (0,0), but also (1,0), (0,1), and (1,1) with a width of 2 for PE12. Therefore, these real PE12A have at least three movement circuits for data movement between them and the three virtual PE12B respectively. The same applies to the real PE12A at the lower left (0,2), (1,2), (0,3), (1,3), upper right (2,0), (3,0), (2,1), (3,1), and lower right (2,2), (3,2), (2,3), (3,3).

[0082] Furthermore, in the actual PE group 20A, the side portions, excluding the corner portions, are also PE12 with a width of 2, just like the corner portions. However, in the case of PE12 with a width of 4, all PE12 are equivalent to corner portions, so there are no PE12 as side portions.

[0083] Additionally, in cases requiring a large amount of peripheral data, such as 7×7 or 9×9 convolution operations, more virtual PE12Bs and moving circuits can be added. In this case, the width of PE12 is made greater than 4.

[0084] On the other hand, in order to enable data movement between more virtual PE12Bs, the real PE12A can also have eight moving circuits for data movement between eight virtual PE12Bs, including those in the up, down, left, and right tilt directions.

[0085] Furthermore, the movement circuit for data movement between real PE12A and virtual PE12B may not be provided in all real PE12A. Alternatively, the aforementioned movement circuit may only be provided in real PE12A that has virtual PE12B with the same coordinates. That is, real PE12A that does not have virtual PE12B with the same coordinates does not have a movement circuit for data movement between it and virtual PE12B. For example, in cases where only... Figure 8In the case of a 3×3 convolution operation, the central (1,1), (2,1), (1,2), (2,2) are equivalent to the real PE12A without the virtual PE12B.

[0086] (Data input / output between external memory and PE) The following describes the data input / output between external memory 16 and PE12.

[0087] In this embodiment, when the arithmetic device 10 inputs data from the external memory 16 to the real PE12A (PE12), it moves the data of the real PE12A to the virtual PE12B so that the arrangement is reversed, and keeps the data in the register provided by PE12.

[0088] Figure 11 This is a schematic diagram illustrating data input from the external memory 16 to the arithmetic device 10 in this embodiment. Figure 11 In the diagram, PE12 within the dashed line is the actual PE12A, and PE12 within the single-dotted line is the virtual PE12B. Virtual PE group 20B1 enables row (…) by moving data from the actual PE12A. Figure 11 (In the opposite direction) to the up-down direction, the data is held in the registers possessed by PE12. Then, the virtual PE group 20B2 moves the column ( Figure 11 The left and right directions are reversed, and the data is stored in the registers of PE12. That is, virtual PE12B performs the process of reversing the data input from external memory 16, storing the data that has not been reversed in the registers of PE12, and storing the reversed data in the registers of PE12. In addition, when the data is reversed in both rows and columns, the data is first moved to virtual PE group 20B1, then moved to the real PE12A at the same coordinates, and then moved to virtual PE group 20B2.

[0089] exist Figure 11 In this example, data (data sets) is input from external memory 16 to three row-numbered physical PE12A (PE12), with each physical PE12A holding the data in forward order. Then, the physical PE12A holds the data in reverse row order in its registers by moving data from the input data that reverses the row order to virtual PE group 20B1. Furthermore, the physical PE12A holds the data in reverse column order in its registers by moving data from the input data that reverses the column order to virtual PE group 20B2.

[0090] Furthermore, as an example, after the first data set is input from external memory 16 to the physical PE12A, when the second data set is input, the physical PE12A can also move the first input data set to the virtual PE12B. In this way, the physical PE12A can simultaneously input data sets and reverse the order of the data sets.

[0091] In addition, Figure 11 In the example, the registers of PE12 hold data in reverse row or reverse column order, but the virtual PE12B holds data in reverse row and reverse column order in the same way. Additionally, external memory 16 is configured below, but it can also be above, left, or right; furthermore, it can simultaneously input other data from all directions.

[0092] Figure 12 This is a schematic diagram showing the data output from the computing device 10 of this embodiment to the external memory 16.

[0093] The data output process from the arithmetic unit 10 to the external memory 16 is the reverse of the data input process described above. Specifically, data is set from the registers of PE12 to the virtual PE12B. The data is then moved from the virtual PE12B to the real PE12A, reversing the data order and returning it to the correct order. The real PE12A then outputs the data back to the correct order to the external memory 16. Alternatively, the real PE12A can simultaneously output data to the external memory 16 while performing the process of moving data from the virtual PE12B to return it to the correct order. The external memory 16 can be positioned at the top, but it can also be positioned at the bottom, left, or right. Furthermore, it can simultaneously output other data in all directions.

[0094] Figure 13 This is a schematic diagram illustrating how data is input from the end and interior of the actual PE group 20A. (See diagram for example.) Figure 13 As shown, data can also be input from the intermediate external memory 18 to the real PE12A located at the ends and the real PE12A located inside the real PE12A arranged in a two-dimensional shape. The real PE12A moves the data input from the ends and inside to the virtual PE12B, thereby reversing the order of the data.

[0095] exist Figure 13 In the example, the real PE12A is virtually divided into four real PE groups 20A1 to 20A4. Furthermore, it is assumed that each of the virtually divided real PE groups 20A1 to 20A4 contains the same number of real PE12As.

[0096] exist Figure 13In the example, data corresponding to real PE group 20A1 is input from intermediate external memory 18A to real PE12A at (0,1) and (1,1). Additionally, data corresponding to real PE group 20A2 is input from intermediate external memory 18B to real PE12A at (2,1) and (3,1). Data corresponding to real PE group 20A3 is input from intermediate external memory 18C to real PE12A at (0,3) and (1,3). Data corresponding to real PE group 20A4 is input from intermediate external memory 18D to real PE12A at (2,3) and (3,3). Then, in real PE groups 20A1~22A4, the input data groups are moved to the corresponding virtual PE groups 20B1 and 20B2, reversing the data order.

[0097] Here, when the data rows are reversed, the data moved to the virtual PE12B in row 0 is the data input to the real PE12A in row 3 before being reversed, and the data moved to the virtual PE12B in row 1 is the data input to the real PE12A in row 2 before being reversed. Therefore, the intermediate external memories 18A and 18B, when the rows are in ascending order, input the data in rows 0 and 1 that maintain the real PE12A; when the rows are in reverse order, they input the data in rows 2 and 3 into the real PE12A. Then, the real PE12A reverses the rows by moving the data in rows 2 and 3 to the virtual PE12B.

[0098] Additionally, intermediate external memories 18C and 18D input data containing row numbers 2 and 3, which are maintained in the real PE12A, when the rows are set to ascending order. When the rows are set to descending order, data containing row numbers 0 and 1 are input into the real PE12A. Then, the real PE12A reverses the rows by moving the data containing row numbers 0 and 1 to the virtual PE12B.

[0099] Similarly, in the column case, intermediate external memories 18A and 18C input data containing column numbers 0 and 1, which are maintained in the real PE12A, when the columns are set to ascending order. When the columns are set to descending order, data containing column numbers 2 and 3 are input into the real PE12A. Then, the real PE12A reverses the column order by moving the data containing column numbers 2 and 3 to the virtual PE12B. Additionally, intermediate external memories 18B and 18D input data containing column numbers 2 and 3, which are maintained in the real PE12A. When the columns are set to descending order, data containing column numbers 0 and 1 are input into the real PE12A. Then, the real PE12A reverses the column order by moving the data containing column numbers 0 and 1 to the virtual PE12B.

[0100] Alternatively, instead of inputting the data corresponding to the configuration of the virtual PE12B from the intermediate external memory 18A~18D to the real PE12A as described above, it can be done as follows: Figure 11 After data is input from intermediate external memories 18A-18D to the physical PE12A, the physical PE12A moves to the virtual PE12B, thus reversing the data order. To achieve this, when reversing rows, row numbers 0 and 1 of the physical PE12A need to be changed to row numbers 2 and 3, and row numbers 2 and 3 to row numbers 0 and 1. Therefore, a moving circuit is added to enable simultaneous reversal with the input. The same applies when reversing columns.

[0101] In addition, when outputting data from the actual PE12A to the intermediate external memory 18A~18D, the reverse processing of the data input is performed to restore the reversed data to the forward order and output it.

[0102] In addition, Figure 13 In the example, there are four intermediate external memories 18, but for example, the arithmetic unit 10 can input data to the actual PE12A from two or more intermediate external memories 18, or it can simultaneously input and output more data for each group of more and finer PE12s. In addition, the external memory 16 is configured at the top and bottom, but it can also be configured at the top, bottom, left and right. Furthermore, it can simultaneously input and output other data in all directions.

[0103] (Processing one-dimensional data) The data input to the computing device 10 of this embodiment can also be one-dimensional continuous data (hereinafter referred to as "one-dimensional data"). Therefore, the computing device 10 of this embodiment sets the real PE12A and the virtual PE12B as a continuous one-dimensional arrangement, and continuously arranges one-dimensional data in the real PE12A and the virtual PE12B.

[0104] like Figure 14As shown, the computing device 10 of this embodiment starts with the real PE12A at (0,0) in the real PE group 20A. Furthermore, the real PE12A at (3,0) and the real PE12A at (3,1) at the end of the column undergo row data movement, as do the real PE12A at (0,1) and (0,2) on the opposite side, and so on, with the real PE12A at (3,2) and (3,3) on the opposite side. The other real PE12A undergo only column data movement. The virtual PE group 20B also undergoes the same data movement, allowing data movement between the real PE12A at (0,3) and the virtual PE12B. With this configuration, the computing device 10 of this embodiment becomes a continuous one-dimensional arrangement of real PE12A and virtual PE12B.

[0105] Figure 15 It is the order in which the data input from external memory 16 to each PE12 is arranged. Figure 3 In this context, 'x' represents the column number and 'y' represents the row number. Additionally, 'data' is an example of values ​​input into PE12, where multiple data points are consecutive one-dimensional data. Furthermore, Figure 14 still Figure 15 The data shown is configured for the real PE12A and virtual PE12B states.

[0106] Figures 16-18 This is a schematic diagram illustrating data movement within the computing device 10 of the embodiment. Figure 16 From Figure 14 The data configuration states are the state after one data movement and the state after two data movements. Data movement is performed in the order of consecutive data configuration. Furthermore, in the arrangement order of PE12, for example, in the real PE12A, data moves from (0,3) to (0,0), while in the virtual PE12B, data moves from (0,0) to (0,3). That is, the data in the virtual PE12B moves in the opposite direction to the arrangement order of the real PE12A.

[0107] Additionally, after one data move, along with the data move, a new data "20" is configured in the virtual PE12B at (0,0). Then, after two data moves, the virtual PE12B at (0,0) becomes empty instead of retaining the data.

[0108] exist Figure 17After the data is moved three times, the data "21" is newly configured in the virtual PE12B at (1,0) along with the data movement, while the virtual PE12B at (0,0) remains empty. This data movement is repeated, and after seven data movements, the data "23" is newly appended to the virtual PE12B at (3,0) along with the data movement, while the virtual PE12Bs at (0,1) to (0,2) remain empty.

[0109] Furthermore, in Figure 18 After the data is moved 31 times, along with the data movement, the data "2f" is added to the virtual PE12B at (0,3), while the virtual PE12Bs outside (0,3) are empty. Furthermore, after the data is moved 32 times, along with the data movement, the data "30" to "3f" are added to the virtual PE12B.

[0110] in addition, Figure 14 The one-dimensional arrangement of the real PE12A and virtual PE12B shown is one example, and is not limited to this. Figure 14 In this arrangement, if the horizontal axis is filled, the vertical axis is changed to arrange the real PE12A and virtual PE12B in a one-dimensional manner. Alternatively, if the vertical axis is filled, the horizontal axis is changed to arrange them in a one-dimensional manner. Furthermore, the arrangement can be done by setting the real PE12A at (3,0) as the first, or by setting the real PE12A other than the real PE12A at (0,0) as the first.

[0111] Thus, in this embodiment, the one-dimensional data held by PE12 is arranged alternately in ascending or descending order according to each row of the two-dimensional PE12. Therefore, the computing device 10 of this embodiment can move the data arranged in the plurality of PE12 as one-dimensional data between PE12. Furthermore, in Figure 14 In the example, the data is moved by columns, but when the data is moved by rows, the data held by PE12 is arranged alternately in ascending or descending order for each column of the two-dimensional PE12.

[0112] Furthermore, in this embodiment where PE12 is arranged in a one-dimensional manner, similar to the "data input / output between external memory and PE" in the embodiment where PE12 is arranged in a two-dimensional manner, when inputting data, data is input from external memory 16 or intermediate external memory 18 and moved to virtual PE12B, thereby reversing the order. When outputting data, the reverse processing is performed, restoring the reversed data to the forward order and outputting the data to external memory 16 or intermediate external memory 18.

[0113] (Applications of SIMD processing) In this embodiment, the real PE12A and the virtual PE12B divide the input data into multiple data segments according to a specified number of bits and then move each data segment according to the specified number of bits.

[0114] Furthermore, in this embodiment, PE12 performs parallel processing based on SIMD (Single Instruction Multiple Data) to simultaneously operate and move multiple data segments divided by a specified number of bits within a single PE12. Additionally, the data segmented by a specified number of bits will be referred to as segmented data below.

[0115] In this embodiment, as an example, 128 bits of data are input to PE12, which divides the data into 32-bit segments and stores them in a register. That is, PE12 stores four 32-bit segments of data in the register. Figure 19 In the example, PE12 is set as a continuous one-dimensional arrangement, where one PE12 holds the four segmented data from the upper 32 bits to the lower 32 bits in sequence. Moreover, the lower 32 bits of the segmented data of each PE12 are configured to be continuous with the upper 32 bits of the segmented data of the other PE12 on the right (the PE12 with the larger column number).

[0116] Reference Figure 19 The segmented data held by PE12 in row 0 moves to the left towards PE12 at (0,0). Therefore, the upper 32 bits of the segmented data of the right-adjacent PE12 move to the position of the lower 32 bits of the segmented data held by PE12 in row 0. On the other hand, the segmented data held by PE12 in row 1 moves to the right. Therefore, the lower 32 bits of the segmented data of the left-adjacent PE12 move to the position of the upper 32 bits of the segmented data held by PE12 in row 1. Furthermore, a moving circuit is provided in PE12 for moving the segmented data within PE12.

[0117] To achieve the aforementioned one-dimensional data movement, in Figure 19 In the example, the data in odd-numbered rows is arranged in reverse order relative to the even-numbered rows. That is, the data is split in reverse order within each PE12 of the odd-numbered rows. Figure 19 For example, in PE12, which is a 1-row, 2-column number (2,1), the lower 32 bits configure the preceding data "14", and the upper 32 bits configure the following data "17".

[0118] In addition, the PE12 at the end of each row, except for PE12 at (0,0), can move data with the PE12 above or below the row. Therefore, the lower 32 bits of the segmented data of PE12 at (3,1) are moved to the position of the lower 32 bits of the segmented data of PE12 at (3,0).

[0119] Thus, in this embodiment, the multiple segmented data held by PE12 are arranged alternately in ascending or descending order according to each row of the two-dimensional PE12. Therefore, the computing device 10 of this embodiment can move the segmented data arranged in the multiple PE12 as one-dimensional data between PE12. Furthermore, in Figure 19 In the example, the split data is moved by columns, but when moving by rows, the multiple split data held by PE12 are configured in a two-dimensional manner, with each column of PE12 alternately arranged in ascending or descending order.

[0120] Additionally, the bit positions of multiple segmented data held by PE12 can be alternately configured in ascending or descending order for each PE12, so that movement between different PE12 results in the same bit movement. In this case, when data is input from the outside, it is held in ascending or descending order, and when data is output to the outside, it is returned and output in ascending order. However, it can also be reversed in one go by having a switching circuit within PE12 to reverse the bit positions.

[0121] In addition, Figure 19 In the example, the configuration of multiple segmented data in the real PE12A is shown, but the configuration of the segmented data in the virtual PE12B is the same, with the data configured sequentially in both the real PE12A and the virtual PE12B. Then, the data movement described above is performed on the multiple segmented data configured in both the real PE12A and the virtual PE12B.

[0122] Alternatively, it can be different. Figure 19 Instead of holding the segmented data in a 1x4 grid, each PE12 holds the segmented data in a two-dimensional grid, for example, 2x2. In this case, the segmented data held in two dimensions within the PE12 is arranged alternately in ascending or descending order by row or column. Thus, the computing device 10 of this embodiment can move the segmented data arranged in the plurality of PE12 as one-dimensional data between the PE12.

[0123] Alternatively, the number of rows and columns of the segmented data within a PE12 can be arbitrarily determined based on the number of bits and the number of segments in the input data to the PE12. Furthermore, the above describes one-dimensional data movement of the segmented data; however, to enable two-dimensional data movement of the segmented data, the processing of the segmented data and the processing of two-dimensional data movement can be combined.

[0124] The present disclosure has been described above using the aforementioned embodiments, but the technical scope of the present disclosure is not limited to the scope described in the above embodiments. Various changes or modifications can be made to the above embodiments without departing from the spirit of the disclosure, and the manner in which such changes or modifications are made is also included in the technical scope of the present disclosure.

[0125] In the above embodiments, the data is arranged from left to right from PE12 at (0,0) toward PE12 at (3,0), but this disclosure is not limited thereto. For example, the data may also be arranged from top to bottom, or from right to left and from bottom to top.

[0126] In addition, to enable faster data movement, data movement using both the real PE12A and the virtual PE12B can be reused.

[0127] Alternatively, instead of arranging the PE12s in a two-dimensional configuration and limiting data movement to only vertical, horizontal, and vertical directions, the data can be tilted or moved in three or four dimensions. Multidimensional arrangement of PE12s refers to representing PE12s using a multidimensional coordinate system that includes other directions (ZW, etc.) in addition to the two dimensions representing the vertical and horizontal directions (XY). In this multidimensional arrangement, PE12s can input and output data with adjacent PE12s in the XY direction, and also with adjacent PE12s in other dimensions such as the ZW direction. When PE12s are arranged in three or more dimensions, each PE12 is connected to PE12s in the XY and ZW directions via wiring 14A and 14B.

[0128] Next, the features of the present invention are as follows.

[0129] (Method 1) A computing device (10) includes multiple processors (12), wherein, Based on the arrangement of the actual processors (12A), the arrangement of the virtual processors (12B) is set in such a way that at least one of the rows and columns is reversed, and data is continuously configured in the actual processors and the virtual processors. The virtual processors move data in a direction different from the real processors, thereby moving the data according to the configured order of the data.

[0130] (Method 2) According to the computing device of method 1, wherein... The data to be moved from the registers of the actual processor and the corresponding virtual processor are set.

[0131] (Method 3) The computing device according to method 1 or method 2, wherein, The computing device includes: a first wiring (14A) for moving data between the actual processors; and a second wiring (14B) for moving data between the virtual processors. The first wiring and the second wiring respectively cause the data to move in different directions.

[0132] (Method 4) The arithmetic device according to any one of methods 1 to 3, wherein, In order to perform convolution operations using a processor group consisting of multiple processors arranged in a two-dimensional configuration, the virtual processors are configured to be positioned around the real processors. Set focus data for the real processor, and set surrounding data for the virtual processor.

[0133] (Method 5) According to the computing device described in method 4, wherein... The real processor located at the corner of the processor group has at least three movement circuits for data movement between itself and the three virtual processors, which are positioned in a tilt direction. The real processor located on the side of the processor group, excluding the corners, has at least one moving circuit for moving data between itself and one of the virtual processors.

[0134] (Method 6) According to the computing device described in method 4, wherein... The real processor has eight moving circuits that move data between itself and eight virtual processors, which are tilted in the up, down, left, and right directions.

[0135] (Method 7) According to any one of the computing devices from Method 1 to Method 6, wherein, If data is input from external memory (16) to the actual processor, the actual processor moves the data to the virtual processor and reverses the order, while the registers of the processor hold the data.

[0136] (Method 8) According to the computing device described in method 7, wherein... Data is input from external memory to the processors located at the ends and the processors located inside the two-dimensional array of processors. The real processor causes the data input from the terminal and the internal system to be moved in reverse order to the virtual processor.

[0137] (Method 9) The computing device according to any one of methods 1 to 8, wherein, The real processor and the virtual processor are configured as a continuous one-dimensional arrangement, with one-dimensional data continuously configured in both the real processor and the virtual processor.

[0138] (Method 10) According to the computing device described in method 9, wherein... The processor, in a two-dimensional configuration, alternately arranges the one-dimensional data in ascending or descending order for each row or column.

[0139] (Method 11) According to any one of the computing devices described in methods 1 to 10, wherein, The real processor and the virtual processor are configured to divide the input data into multiple data segments according to a predetermined number of bits, and to move each data segment obtained according to the predetermined number of bits.

[0140] (Method 12) According to the computing device of method 11, wherein, The processors are configured in a two-dimensional configuration, each processor, to perform the segmentation of the data in such a way that the bit positions are alternately arranged in ascending or descending order.

[0141] (Method 13) A data movement method is a data movement method for a computing device equipped with multiple processors, wherein, Based on the actual processor arrangement, the virtual processors are arranged in reverse order, with at least one of the rows and columns reversed. Data is then configured consecutively between the actual processors and the virtual processors. The virtual processors move data in a direction different from the real processors, thereby moving the data according to the configured order of the data.

Claims

1. A computing device (10) comprising a plurality of processors (12), characterized in that, Based on the arrangement of the actual processors (12A), the arrangement of the virtual processors (12B) is set in such a way that at least one of the rows and columns is reversed, and data is continuously configured in the actual processors and the virtual processors. The virtual processors move data in a direction different from the real processors, thereby moving the data according to the configured order of the data.

2. The computing device according to claim 1, characterized in that, The data to be moved from the registers of the actual processor and the corresponding virtual processor are set.

3. The computing device according to claim 1 or 2, characterized in that, The computing device includes: a first wiring (14A) for moving data between the actual processors; and a second wiring (14B) for moving data between the virtual processors. The first wiring and the second wiring respectively cause the data to move in different directions.

4. The computing device according to claim 1 or 2, characterized in that, In order to perform convolution operations using a processor group consisting of multiple processors arranged in a two-dimensional configuration, the virtual processors are configured to be positioned around the real processors. Set focus data for the real processor, and set surrounding data for the virtual processor.

5. The computing device according to claim 4, characterized in that, The real processor located at the corner of the processor group has at least three movement circuits for data movement between itself and the three virtual processors, which are positioned in a tilt direction. The real processor located on the side of the processor group, excluding the corners, has at least one moving circuit for moving data between itself and one of the virtual processors.

6. The computing device according to claim 4, characterized in that, The real processor has eight moving circuits that move data between itself and eight virtual processors, which are tilted in the up, down, left, and right directions.

7. The computing device according to claim 1 or 2, characterized in that, If data is input from external memory (16) to the actual processor, the actual processor moves the data to the virtual processor and reverses the order, while the registers of the processor hold the data.

8. The computing device according to claim 7, characterized in that, Data is input from external memory to the processors located at the ends and the processors located inside the two-dimensional array of processors. The real processor causes the data input from the terminal and the internal system to be moved in reverse order to the virtual processor.

9. The computing device according to claim 1 or 2, characterized in that, The real processor and the virtual processor are configured as a continuous one-dimensional arrangement, with one-dimensional data continuously configured in both the real processor and the virtual processor.

10. The computing device according to claim 9, characterized in that, The processor, in a two-dimensional configuration, alternately arranges the one-dimensional data in ascending or descending order for each row or column.

11. The computing device according to claim 1 or 2, characterized in that, The real processor and the virtual processor are configured to divide the input data into multiple data segments according to a predetermined number of bits, and to move each data segment obtained according to the predetermined number of bits.

12. The computing device according to claim 11, characterized in that, The processors are configured in a two-dimensional configuration, each processor, to perform the segmentation of the data in such a way that the bit positions are alternately arranged in ascending or descending order.

13. A data movement method, which is a data movement method of a computing device equipped with multiple processors, characterized in that, Based on the actual processor arrangement, the virtual processor arrangement is set in a manner where at least one of the rows and columns is in reverse order. Data is then continuously configured in both the actual and virtual processors. The virtual processors move data in a direction different from the real processors, thereby moving the data according to the configured order of the data.

Images