High-density interconnected chip detection mechanism and preparation method

Abstract

The invention discloses a high-density interconnected chip detection mechanism and a preparation method, and belongs to the technical field of semiconductor testing. The mechanism mainly comprises a ceramic probe assembly and a PCB which are integrally formed, the ceramic probe assembly is composed of a detection contact part in the center and an extension part on the periphery, and an electric connection path is formed in the ceramic probe assembly through a first wire set, a second wire set and a third wire set which are integrated; the PCB is provided with a wire arrangement groove which is used for accommodating and fixing the leading-out end of the third wire group. Through the unique structural design, complex horizontal wiring is transferred from the ceramic main body to the extension part, the technical problems of difficult wiring and high cost in the ceramic are effectively solved, and the wiring efficiency is improved by combining with the process of filling an insulating heat-conducting material in the wiring groove or performing plastic package. The stability and reliability of signal transmission and the heat dissipation capability of the system are remarkably improved, and the system is particularly suitable for high-performance testing of chips manufactured in an advanced mode.

Description

Technical Field

[0001] This invention relates to the field of semiconductor testing technology, and more specifically to a high-density, high-stability chip testing mechanism and its preparation method for performing electrical performance testing on chips. Background Technology

[0002] In semiconductor manufacturing, chips undergo electrical performance testing of their internal circuitry using probe stations and other testing equipment before and after packaging to ensure that their functionality and performance meet design requirements. This process requires probes to make precise contact with micron-sized pads or bumps on the chip and transmit electrical signals to external testing instruments.

[0003] Currently, the mainstream solutions for achieving electrical connections between probes and back-end printed circuit boards (PCBs) face the following technical challenges: Difficulty in internal ceramic wiring: To ensure contact accuracy, high-temperature resistance, and insulation performance, probes are often made of ceramic materials. However, ceramics are hard and brittle, making it extremely difficult to directly manufacture complex, high-density metal wiring within them. Typically, high-temperature co-fired ceramic (HTCC) or low-temperature co-fired ceramic (LTCC) processes are required, resulting in high costs and long manufacturing cycles.

[0004] Limitations of signal extraction: Because it is difficult to perfectly match the spacing between traces on the PCB board and the contact spacing of probes, signals are usually extracted using "flying wires". Traditional flying wire methods suffer from poor stability, susceptibility to interference, poor signal integrity under high-frequency testing, and messy wire harness management, affecting heat dissipation and maintenance.

[0005] Structural stability and heat dissipation issues: During testing, the probe generates heat upon contact with the chip. If this heat cannot be dissipated in time, it will affect testing accuracy and equipment lifespan. Simultaneously, if the connecting harness is not securely fixed, it can easily loosen under frequent testing over a long period, leading to poor contact and impacting testing reliability.

[0006] Therefore, there is an urgent need for a chip testing solution that can solve the above problems and achieve high density, high reliability, low cost and easy manufacturing. Summary of the Invention

[0007] The purpose of this invention is to provide a chip detection mechanism and its manufacturing method to solve the problems of high internal wiring cost, poor signal extraction stability, and poor system heat dissipation in the prior art.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] A chip testing mechanism, comprising:

[0010] An integrated ceramic probe assembly consists of a central probe contact and a surrounding annular epitaxial portion. The probe contact contains an array of first vertical conductive channels (first wire groups) for direct connection to the probe. The epitaxial portion contains radially distributed second horizontal conductive channels (third wire groups). A redistribution layer (second wire group) is also integrated within the probe contact, selectively interconnecting specific first vertical conductive channels with specific second horizontal conductive channels.

[0011] PCB board: It is mechanically and electrically connected to the ceramic probe assembly through the epitaxial portion. The PCB board is provided with a ribbon cable groove that matches the contour of the epitaxial portion. The end wire of the third wire group is embedded in the ribbon cable groove and electrically connected to the corresponding contact on the PCB board through the solder pad.

[0012] Preferably, the first vertical conductive channel is formed by laser drilling and filling copper paste into a ceramic green body and then co-firing, or by deep-hole copper plating on a sintered ceramic substrate.

[0013] Preferably, the cable tray is filled with an insulating and thermally conductive adhesive. This adhesive is based on epoxy resin or silicone and doped with high thermally conductive fillers such as aluminum nitride or boron nitride. Its thermal conductivity is not less than 1.5 W / (m·K), and its volume resistivity is not less than 1×10^14 Ω·cm. This adhesive completely covers and cures the end wires, while simultaneously conducting the working heat to the PCB board for dissipation.

[0014] Preferably, the extension portion and the cable tray area together constitute a packaging unit, and the third wire group in the unit is encapsulated by an insulating encapsulating material (such as epoxy molding compound) through transfer molding or injection molding process to form an integrated planar structure.

[0015] Preferably, the third line group is a multilayer flexible circuit board (FPC) with at least two layers, and is joined by a hot-pressing process.

[0016] The present invention also provides a method for preparing the above-mentioned chip detection mechanism, comprising the following steps:

[0017] Ceramic probe fabrication steps: A ceramic probe assembly containing a detection contact and an epitaxial portion is fabricated in one piece using a low-temperature co-fired ceramic (LTCC) or high-temperature co-fired ceramic (HTCC) process, and channels of the first, second, and third wire groups are integrated therein.

[0018] PCB preprocessing steps: Cable trays are machined on the PCB board using mechanical engraving or laser ablation. Assembly and interconnection steps: The epitaxial portion of the ceramic probe assembly is aligned with the cable tray area on the PCB board, and electrical connections are achieved using conductive adhesive, soldering, or anisotropic conductive film (ACF) thermoforming bonding processes.

[0019] Encapsulation and fixing steps: The cable tray area with completed electrical connection is fixed and encapsulated. Specifically, this can be done by pouring in insulating and thermally conductive adhesive and curing it, or by using epoxy molding compound for transfer molding and encapsulation.

[0020] In summary, this application includes at least one of the following beneficial technical effects:

[0021] Innovative structural design: By transferring the complex horizontal wiring from the ceramic probe contact body to an integrated extension portion around it, the vertical interconnect (first wire group) is cleverly separated from the horizontal wiring (third wire group), greatly reducing the difficulty and cost of manufacturing complex wiring within the ceramic body.

[0022] High Reliability and Stability: Utilizing a combination of ribbon cable trays and potting / molding encapsulation for fixation, along with advanced interconnection technologies such as ACF thermoforming, ensures the mechanical stability and electrical connection reliability of the signal lead-out path. This allows the system to withstand long-term, high-frequency testing, effectively avoiding the loosening and interference problems associated with traditional flying wire methods. Excellent Heat Dissipation: Filling the ribbon cable trays with highly thermally conductive insulating material not only provides fixation but also creates an effective heat dissipation path. This allows heat generated at the probe contacts to be promptly conducted to the larger PCB board for dissipation, improving the stability and lifespan of the entire testing system in high-temperature environments.

[0023] Manufacturing flexibility and cost-effectiveness: The structure features a modular design, allowing ceramic probe components to be prefabricated as standard parts and then flexibly combined with PCBs of different specifications. The manufacturing method combines mature ceramic technology with PCB processing and packaging processes, resulting in a clear workflow, easy mass production, and low overall manufacturing costs. Attached Figure Description

[0024] Figure 1 This is a cross-sectional schematic diagram of the overall structure of the present invention.

[0025] Explanation of reference numerals in the attached figures: 1. Chip under test; 2. Probe contact; 21. Epitaxial portion; 3. PCB board; 4. Cable tray; 5. First wire group; 51. Second wire group; 52. Third wire group. Detailed Implementation

[0026] The terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “an,” “the,” “the,” “the,” and “this” are intended to also include expressions such as “one or more,” unless the context clearly indicates otherwise. It should also be understood that in the following embodiments of this application, “at least one” and “one or more” refer to one, two, or more than two. The term “and / or” is used to describe the relationship between related objects, indicating that three relationships may exist; for example, A and / or B can indicate: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character “ / ” generally indicates that the preceding and following related objects are in an “or” relationship.

[0027] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0028] Example 1

[0029] 1. Structure and Materials

[0030] refer to Figure 1 The chip testing mechanism in this embodiment mainly consists of two parts: an integrated ceramic probe assembly and a PCB board 3.

[0031] Ceramic probe assembly:

[0032] Substrate material: Aluminum nitride (AlN) ceramic is selected, which has excellent insulation, high thermal conductivity (approximately 20-30 W / (m·K)) and a coefficient of thermal expansion that matches that of silicon chips. As an alternative, alumina (Al2O3, content above 96%) ceramic can also be used to reduce costs.

[0033] The detection contact part (2) is a cylinder with a diameter of 8 mm and a thickness of 1.5 mm. Inside it, 25 micro-holes with a diameter of 80 μm are formed by laser drilling in a 5×5 array. These micro-holes constitute the channels of the first line group (5).

[0034] The outer extension (21) is an annular structure surrounding the detection contact 2, with an outer diameter of 12 mm, a width of 2 mm, and a thickness consistent with the detection contact. Its interior is pre-designed with 25 radially distributed wiring channels through the cavity design during casting to accommodate the third wire group (52).

[0035] Internal wiring:

[0036] First wire group (5): The micro-orifices are filled with DuPont's LL507 low-temperature copper paste, which is then sintered to form conductive channels. Second wire group (51): Inside the probe contact 2, 20 of the above 25 channels are selectively connected to the 20 wiring channels of the epitaxial portion 21 according to a preset wiring diagram using screen printing technology to form a redistribution layer (RDL). This RDL uses the same LL507 copper paste and is co-fired with the first wire group 5 to ensure the integrity of the connection.

[0037] Third wire group (52): In this embodiment, a double-sided copper-clad polyimide (PI) flexible circuit board (FPC) with a thickness of 50μm is pre-formed and precisely embedded in the wiring channel of the epitaxial portion 21, and fixed with conductive silver paste. The inner end of the FPC is connected to the end point of the second wire group 51, and the outer end extends to the edge of the epitaxial portion 21.

[0038] PCB board (3):

[0039] It is made of FR-4 material with a thickness of 1.6mm.

[0040] Cable tray (4): A ring-shaped groove with a depth of 0.3mm and a shape that precisely matches the contour of the extension 21 is machined on the surface of the PCB board 3 by a CNC milling machine.

[0041] Electrical contacts: The bottom of the cable tray 4 is provided with 20 gold-plated pads corresponding to the end of the third line group 52. These pads are connected to the standard interface on the edge of the board through the internal traces of the PCB.

[0042] Interface connection and encapsulation materials:

[0043] Interconnection material: Anisotropic conductive film (ACF, model AC-8955Y of Hitachi Chemical) is used, with conductive particles having a diameter of 5μm.

[0044] Encapsulation material: Dow Corning TC-5625 thermal conductive gel. This material is based on silicone and filled with boron nitride. Its thermal conductivity is 2.0 W / (m·K), its volume resistivity is >1×10^15 Ω·cm, and it remains elastic in the range of -45℃ to 200℃.

[0045] 2. Preparation method

[0046] Step 1: Ceramic probe fabrication (using LTCC process)

[0047] Casting: Aluminum nitride ceramic powder is mixed with organic binders, plasticizers, etc., and then cast into a green ceramic tape with a thickness of 100μm through a casting machine.

[0048] Drilling and filling: Microholes are drilled on the green ceramic strip in the corresponding detection contact area 2 using an ultraviolet laser, and copper paste is filled in using a vacuum filling machine to form the prototype of the first line group 5.

[0049] Printing: On a specific green ceramic layer, the above-mentioned preset RDL pattern (second line group 51) and the guide lines of the extension portion 21 are printed using a 200-mesh screen.

[0050] Lamination and Isostatic Pressing: Printed and unprinted green ceramic sheets are laminated in the designed order, placed in a mold, and isostatically pressed at 70℃ and 20MPa to firmly bond the layers into a single green body. Co-firing: The green body is placed in a sintering furnace and sintered according to a preset temperature curve (maximum peak temperature 900℃) to finally form a dense, integrated ceramic probe assembly with channels of the first line group 5, the second line group 51, and the third line group 52.

[0051] Post-processing: The sintered components are subjected to surface grinding and leveling treatment.

[0052] Step 2: PCB Preprocessing

[0053] The cable tray 4 is milled out on the FR-4 PCB board 3 using a CNC milling machine, and then an immersion gold process is performed to form a nickel-gold layer with a thickness of 0.05μm on the pads inside the tray.

[0054] Step 3: Assemble the interconnects

[0055] ACF mounting: Precisely attach the ACF film to the area of ​​the ribbon cable slot 4 on the PCB board 3.

[0056] Alignment and pre-compression: Precisely align the extended portion 21 of the ceramic probe assembly (whose FPC end has been cleaned) onto the ACF in the cable tray 4. Using precision mounting equipment, pre-compress at 100°C and 0.5MPa to initially cure and temporarily fix the ACF.

[0057] Primary bonding: The temperature is raised to 180℃, the pressure is increased to 1.5MPa, and the holding time is 20 seconds to complete the primary bonding. At this time, the conductive particles in the ACF are flattened under the action of pressure and temperature, forming a vertical electrical connection between the FPC end lead and the PCB pad, while the resin matrix provides mechanical strength and insulation.

[0058] Step 4: Encapsulation and Fixing

[0059] Using a precision dispensing machine, evenly inject TC-5625 thermal conductive gel into the cable tray 4, ensuring that the gel completely fills all gaps between the FPC leads, the ACF layer and the wall of the cable tray 4, with a slight overflow.

[0060] The entire component is placed in an oven at 100°C and cured for 60 minutes to form a robust, thermally conductive, and insulating encapsulation.

[0061] 3. Performance Testing and Results

[0062] The chip testing mechanism prepared in this embodiment was tested:

[0063] Electrical performance: Tested at 10GHz, the signal insertion loss of all 20 channels is less than -1.5dB, the return loss is better than -15dB, and the crosstalk is less than -40dB, showing excellent high-frequency characteristics.

[0064] Thermal performance: After applying a 5W heat load (simulating probe operation heat) to the detection contact 2 for 30 minutes, the highest temperature of the ceramic probe assembly stabilized at 85℃, and the hot spot temperature of the PCB board 3 was 65℃, indicating that the thermally conductive adhesive effectively established a heat dissipation path.

[0065] Mechanical reliability: Mechanical shock (1500G, 0.5ms) and vibration tests were conducted according to JESD22-B111 standard. After the tests, the change rate of conduction resistance of all channels was less than 2%, and there were no connection failures.

[0066] Comparative experiment: Compared with the same specification testing mechanism using the traditional Pogo Pin flying wire solution, the signal integrity of the present invention is improved by about 30%, and the failure rate in long-term testing is reduced by an order of magnitude.

[0067] Example 2

[0068] As another embodiment of the present invention, its main difference from Embodiment 1 is:

[0069] Ceramic process: High-temperature co-fired ceramics (HTCC) process is adopted, with 92% alumina as the matrix material and tungsten paste as the metallizing material. Sintering is carried out in a reducing atmosphere at 1600℃.

[0070] The third wire group: directly uses gold-plated copper wire with a diameter of 100μm, and uses ultrasonic wedge bonding technology to bond one end to the endpoint of the second wire group 51, and the other end to the PCB pad in the cable tray 4.

[0071] Encapsulation and Fixing: Instead of potting compound, a transfer molding process is used with Sumitomo Bakelite's EME-7320 epoxy molding compound (EMC) to mold the epitaxial portion 21 and the cable tray 4 area under 175°C and 7MPa pressure, forming a 0.5mm thick protective encapsulation layer. This variant embodiment also achieves highly reliable electrical connection and heat dissipation, and is particularly suitable for applications requiring higher mechanical strength of the package.

[0072] In summary, this invention, through innovative structural design and combined with advanced ceramic processing, micro-assembly, and packaging technologies, successfully provides a high-performance, high-reliability chip testing solution. Those skilled in the art can select and adjust materials and process parameters according to actual needs, all of which fall within the scope of protection of this invention.

[0073] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. Any equivalent modifications or variations made by those skilled in the art based on the content disclosed in the present invention should be included within the scope of protection set forth in the claims.

Claims

1. A high-density interconnect chip inspection mechanism, characterized in that, include: An integrated ceramic probe assembly consists of a central probe contact (2) and an outer annular extension (21); The detection contact part (2) is provided with multiple first vertical conductive channels arranged in an array to form a first wire group (5) for direct connection of the probe; The extension portion (21) is provided with a radially distributed second horizontal conductive channel, forming a third wire group (52); the detection contact portion (2) is also integrated with a redistribution layer, which forms a second wire group (51) that selectively interconnects a specific first vertical conductive channel with a specific second horizontal conductive channel; the PCB board (3) is mechanically and electrically connected to the ceramic probe assembly through the extension portion (21), the PCB board (3) is provided with a ribbon cable groove (4) that is connected to the second horizontal conductive channel, and the end wire of the third wire group (52) is buried in the ribbon cable groove (4) and electrically connected to the corresponding contact on the PCB board (3) through the solder pad.

2. The chip testing mechanism according to claim 1, characterized in that, The first vertical conductive channel is formed by laser drilling and filling copper paste into a ceramic green body and then co-firing, or by deep-hole copper plating on a sintered ceramic substrate.

3. The chip testing mechanism according to claim 1, characterized in that, The cable tray (4) is filled with an insulating thermally conductive adhesive with epoxy resin or silicone as the matrix and aluminum nitride or boron nitride as filler. The insulating thermally conductive adhesive completely covers and cures the end wires of the third wire group (52), and at the same time conducts the heat generated during operation to the PCB board (3) for dissipation.

4. The chip testing mechanism according to claim 3, characterized in that, The thermal conductivity of the insulating thermally conductive adhesive is not less than 1.5 W / (m·K), and the volume resistivity is not less than 1×10^14 Ω·cm.

5. The chip testing mechanism according to claim 1, characterized in that, The extension portion (21) and the cable tray (4) together constitute a packaging unit. The third wire group (52) in this unit is encapsulated by an insulating encapsulating material (such as epoxy molding compound) through transfer molding or injection molding processes to form an integrated planar structure.

6. The chip testing mechanism according to claim 1, characterized in that, The third line group (52) is a multilayer flexible circuit board (FPC) with at least two layers, and is bonded to the conductive channels in the epitaxial portion (21) and the pads on the PCB board (3) by a hot pressing process.

7. A method for preparing the chip detection mechanism according to any one of claims 1-6, characterized in that, Includes the following steps: Ceramic probe fabrication steps: A ceramic probe assembly comprising the detection contact (2) and the epitaxial portion (21) is fabricated in an integrated manner using a low-temperature co-fired ceramic (LTCC) or high-temperature co-fired ceramic (HTCC) process, and channels of the first line group (5), the second line group (51) and the third line group (52) are integrated therein; PCB preprocessing steps: The ribbon cable groove (4) matching the contour of the epitaxial part (21) is processed on the PCB board (3) by mechanical engraving or laser ablation process; Assembly and interconnection steps: Align the extension portion (21) of the ceramic probe assembly with the ribbon cable groove (4) area of ​​the PCB board (3), and use conductive adhesive or soldering process to achieve electrical connection between the third wire group (52) and the contacts on the PCB board (3); Encapsulation and fixing steps: The cable tray (4) area where the electrical connection is completed is fixed and encapsulated.

8. The method according to claim 7, characterized in that, The encapsulation and fixing steps are as follows: liquid insulating adhesive mixed with high thermal conductivity filler is injected into the cable tray (4) through dispensing or injection process, and then stepped heating and curing are performed.

9. The method according to claim 7, characterized in that, The encapsulation and fixing step specifically involves using epoxy molding compound (EMC) to mold and encapsulate the mating area of ​​the cable tray (4) and the extension portion (21) under a set temperature and pressure using a transfer molding method.

10. The method according to claim 7, characterized in that, In the assembly interconnection step, anisotropic conductive film (ACF) is used as the interconnection medium, and the electrical connection and mechanical fixation of the third wire group (52) and the PCB board (3) are realized simultaneously through hot pressing bonding process.

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