Coupling method of silicon optical chip and optical fiber array

Abstract

The invention provides a coupling method of a silicon optical chip and an optical fiber array. The coupling method comprises the following steps: preparing the silicon optical chip, the optical fiber array and a carrier chip; performing coarse alignment operation on the silicon optical chip and the carrier chip to realize coupling between the silicon optical chip and the carrier chip; the optical fiber array is installed on the carrier chip, and coupling between the optical fiber array and the carrier chip is achieved; performing fine alignment operation on the carrier chip and the optical fiber array, and performing curing operation on the optical fiber array to obtain a coupling structure of the silicon optical chip and the optical fiber array; performing end face cutting and polishing on the coupling structure, and forming a protective upper cladding on the surface of the coupling structure; and performing performance test and calibration on the coupling structure to obtain a target coupling structure. According to the coupling method provided by the embodiment of the invention, a parallel coupling process with high density, low loss, high consistency and high stability is provided.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a coupling method between a silicon photonic chip and an optical fiber array. Background Technology

[0002] With the exponential growth in demand for transmission bandwidth and energy efficiency in 5G communications, data centers, and high-performance computing, silicon photonics chips have become core components of optical interconnect systems due to their high integration, low power consumption, and compatibility with CMOS processes. The coupling performance between silicon photonics chips and fiber optic arrays, as a critical interface in the optical signal transmission link, directly determines the transmission efficiency, reliability, and industrial feasibility of the entire system.

[0003] Existing coupling technologies between silicon photonic chips and fiber arrays suffer from the following technical problems: Limited channel count expansion: Current coupling technologies are mostly concentrated on single-channel or low-channel-count coupling designs (less than 4 channels). These technologies can only meet the needs of low-bandwidth scenarios and are insufficient for the industrialization of large-scale data interaction scenarios. Lack of multi-channel consistency control: During multi-channel coupling, alignment deviations between channels accumulate, leading to a significant increase in the dispersion of coupling loss. Difficulty in simultaneously achieving optimal coupling loss and structural stability.

[0004] Therefore, providing a parallel coupling process that combines high density, low loss, high consistency, and high stability is a technical problem that needs to be solved in this field. Summary of the Invention

[0005] This application provides a coupling method between a silicon photonic chip and an optical fiber array, aiming to provide a parallel coupling process that combines high density, low loss, high consistency, and high stability.

[0006] In a first aspect, embodiments of this application provide a coupling method between a silicon photonic chip and an optical fiber array, the method comprising:

[0007] Fabrication of silicon photonics chips, fiber arrays, and carrier chips; the fiber array is an 8- to 32-channel single-mode fiber array.

[0008] A coarse alignment operation is performed on the silicon photonics chip and the carrier chip to achieve coupling between the silicon photonics chip and the carrier chip;

[0009] The fiber array is mounted onto the carrier chip to achieve coupling between the fiber array and the carrier chip;

[0010] A fine alignment operation is performed on the carrier chip and the fiber array, and a curing operation is performed on the fiber array to obtain a coupling structure between the silicon photonic chip and the fiber array;

[0011] The coupling structure is subjected to end face cutting and polishing, and a protective cladding layer is formed on the surface of the coupling structure;

[0012] The performance of the coupling structure is tested and calibrated to obtain the target coupling structure.

[0013] Optionally, the silicon photonic chip is fabricated, including:

[0014] Ridge waveguide arrays are fabricated on the wafer surface using an exposure technique;

[0015] A fan-out grating coupler is integrated at the waveguide output end of the ridge waveguide array;

[0016] In the alignment area of ​​the silicon photonic chip, a photolithography operation is performed by spin coating with photoresist to form a spherical dome array.

[0017] Optionally, fabricating an optical fiber array includes:

[0018] Smooth the end face of the fiber array;

[0019] Polish the smoothed fiber array;

[0020] Remove part of the outer sheath of the fiber array to expose the bare fiber portion of each channel of the fiber array;

[0021] The fiber lengths corresponding to each channel of the fiber array are fixed so that the deviation between the fiber lengths corresponding to each channel is less than or equal to a preset deviation value.

[0022] Optionally, the carrier chip is fabricated, including:

[0023] Alignment pit array and mounting vias are fabricated on a wafer substrate using maskless photolithography; the alignment pit array is located in the edge region of the wafer, and the mounting vias are located in the center region of the wafer;

[0024] The area where the alignment pit array is located is etched to form an inverted pyramid alignment pit;

[0025] A micro / nano sleeve was fabricated inside the mounting via using photoresist to obtain a carrier chip.

[0026] Optionally, the coarse alignment operation on the silicon photonics chip and the carrier chip includes:

[0027] The silicon photonic chip is placed on a precision vacuum stage, and the spherical dome array on the surface of the silicon photonic chip is positioned.

[0028] The carrier chip is placed on a three-dimensional fine-tuning platform;

[0029] Adjust the orientation of the three-dimensional fine-tuning platform so that the alignment pit array of the carrier chip is aligned with the spherical dome array of the silicon photonics chip;

[0030] Pressure is applied to the alignment area of ​​the silicon photonic chip so that the spherical dome of the silicon photonic chip is embedded in the inverted pyramid alignment pit of the carrier chip.

[0031] Optionally, mounting the fiber array onto the carrier chip to achieve coupling between the fiber array and the carrier chip includes:

[0032] The fiber array is inserted into the micro / nano sleeve of the carrier chip;

[0033] Curing adhesive is dripped into the U-shaped groove of the carrier chip to achieve coupling between the optical fiber array and the carrier chip.

[0034] Optionally, performing a fine alignment operation on the carrier chip and the fiber array includes:

[0035] A quartz cover plate is placed over the surface of the fiber array and pressure is applied;

[0036] Optical signals are injected into each channel of the optical fiber array, and the transmitted optical power of each channel is collected in real time.

[0037] Based on the acquired optical power of each channel, the carrier chip is adjusted so that the optical power of each channel reaches its maximum value.

[0038] Optionally, the step of performing a curing operation on the fiber array to obtain the coupling structure between the silicon photonic chip and the fiber array includes:

[0039] The coupling region between the fiber array and the carrier chip is irradiated with ultraviolet light for a fixed duration to obtain the coupling structure between the silicon photonic chip and the fiber array.

[0040] Optionally, forming a protective cladding layer on the surface of the coupling structure includes:

[0041] A cladding material is coated onto the surface of the coupling structure using a spin coating process.

[0042] The coupling structure is placed in an oven for baking and curing to form a protective cladding layer on the surface of the coupling structure.

[0043] Optionally, the step of performing performance testing and calibration on the coupling structure to obtain the target coupling structure includes:

[0044] Inject optical signals into each channel of the fiber array and detect the insertion loss of each channel;

[0045] For the target channel, a micro-nano laser fine-tuning device is used to correct the curvature of the microlens in the target channel; the target channel is the channel among the channels whose insertion loss is greater than a first preset loss.

[0046] The coupling structure was subjected to thermal shock cycling and humidity tests, and the insertion loss of each channel was detected.

[0047] If the loss variation of each channel is less than or equal to the second preset loss, the coupling structure is determined to pass the performance test and calibration to obtain the target coupling structure.

[0048] This application provides a coupling method between a silicon photonic chip and an optical fiber array, comprising: fabricating a silicon photonic chip, an optical fiber array, and a carrier chip; the optical fiber array is a 16-channel single-mode optical fiber array; performing a coarse alignment operation on the silicon photonic chip and the carrier chip to achieve coupling between the silicon photonic chip and the carrier chip; mounting the optical fiber array onto the carrier chip to achieve coupling between the optical fiber array and the carrier chip; performing a fine alignment operation on the carrier chip and the optical fiber array, and performing a curing operation on the optical fiber array to obtain a coupling structure between the silicon photonic chip and the optical fiber array; performing end face cutting and polishing on the coupling structure, and forming a protective cladding layer on the surface of the coupling structure; and performing performance testing and calibration on the coupling structure to obtain the target coupling structure. The coupling method provided in this application, through the synergistic effect of a multi-level self-aligned structure and composite processes, can achieve high-density parallel coupling of 8-32 channels with low channel coupling loss, meeting the requirements of high density and low loss. During the coupling process, by performing a coarse alignment operation on the silicon photonic chip and the carrier chip, and a fine alignment operation on the carrier chip and the optical fiber array, a two-level self-alignment mechanism is achieved, ensuring that the positional deviation of each channel is controlled within an ideal range. Performance testing and calibration of the coupling structure reduce the loss of each channel, thus solving the problem of poor consistency across multiple channels. Therefore, embodiments of this application provide a parallel coupling process that combines high density, low loss, high consistency, and high stability. Attached Figure Description

[0049] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is a flowchart of a coupling method between a silicon photonic chip and an optical fiber array provided in an embodiment of this application. Detailed Implementation

[0051] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0052] See Figure 1 , Figure 1 This is a flowchart illustrating a coupling method between a silicon photonic chip and an optical fiber array, as provided in an embodiment of this application. Figure 1 As shown, the method includes the following steps:

[0053] Step 101: Fabricate silicon photonic chip, fiber array and carrier chip; the fiber array is an 8 to 32 channel single-mode fiber array.

[0054] Step 102: Perform a coarse alignment operation on the silicon photonic chip and the carrier chip to achieve coupling between the silicon photonic chip and the carrier chip.

[0055] Step 103: Install the fiber array onto the carrier chip to achieve coupling between the fiber array and the carrier chip.

[0056] Step 104: Perform a fine alignment operation on the carrier chip and the fiber array, and perform a curing operation on the fiber array to obtain the coupling structure of the silicon photonic chip and the fiber array.

[0057] Step 105: The coupling structure is cut and polished at the end face, and a protective cladding is formed on the surface of the coupling structure.

[0058] Step 106: Perform performance testing and calibration on the coupling structure to obtain the target coupling structure.

[0059] In this embodiment, a silicon photonic chip, an optical fiber array, and a carrier chip are first fabricated. The optical fiber array is an 8- to 32-channel single-mode optical fiber array. As a preferred embodiment, the optical fiber array is a 16-channel single-mode optical fiber array.

[0060] A coarse alignment operation is performed on the silicon photonics chip and the carrier chip to achieve coupling between them. After coupling, the fiber optic array is mounted onto the carrier chip to achieve coupling between the fiber optic array and the carrier chip.

[0061] Furthermore, a fine alignment operation is performed on the carrier chip and the fiber array, and a curing operation is performed on the fiber array to obtain the coupling structure of the silicon photonic chip and the fiber array. The coupling structure is then subjected to performance testing and calibration, and the coupling structure that passes the performance test after calibration is determined as the target coupling structure.

[0062] In this embodiment, through the synergistic effect of a multi-stage self-aligned structure and composite process, high-density parallel coupling of 8-32 channels can be achieved with low channel coupling loss, meeting the requirements of high density and low loss. During the coupling process, a two-stage self-alignment mechanism is implemented by performing coarse alignment operations on the silicon photonic chip and the carrier chip, and fine alignment operations on the carrier chip and the fiber array, ensuring that the positional deviation of each channel is controlled within an ideal range. Performance testing and calibration of the coupling structure reduce the loss of each channel, solving the problem of poor consistency among multiple channels. Therefore, this embodiment provides a parallel coupling process that combines high density, low loss, high consistency, and high stability.

[0063] Furthermore, the fabrication processes mentioned in this application are compatible with existing silicon photonics chip wafer-level manufacturing and PCB packaging processes, eliminating the need for specialized and expensive equipment such as femtosecond laser direct writing. Simultaneously, the process parameters are highly standardized, and the yield of each step can be controlled above 95%, facilitating large-scale mass production and rapid conversion into actual productivity, providing a mature and reliable technical solution for the industrialization of high-density optical interconnect systems.

[0064] Optionally, the silicon photonic chip is fabricated, including:

[0065] Ridge waveguide arrays are fabricated on the wafer surface using an exposure technique;

[0066] A fan-out grating coupler is integrated at the waveguide output end of the ridge waveguide array;

[0067] In the alignment area of ​​the silicon photonic chip, a photolithography operation is performed by spin coating with photoresist to form a spherical dome array.

[0068] In this embodiment, a 4-inch screen can be selected. <100> A crystal-oriented wafer serves as the substrate. The substrate thickness is 500 μm, the device layer thickness is 220 nm, and the buried oxide layer thickness is 3 μm. A ridge waveguide array is fabricated on the device layer using electron beam lithography. The waveguide has a width of 500 nm, a height of 220 nm, and 16 channels are arranged at equal intervals with a channel spacing of 127 μm. A fan-out grating coupler is integrated at the waveguide output, with the grating period optimized to 630 nm and a duty cycle of 0.5 using FDTD numerical simulation. Subsequently, in the alignment area of ​​the chip, AZ40 photoresist (5 μm thickness) is spin-coated, photolithographically defined, and then reflowed at 120°C for 60 seconds to form a spherical dome array with a diameter of 5 μm, serving as a coarse alignment reference. Finally, excess photoresist is removed by plasma etching to complete the fabrication of the silicon photonics chip.

[0069] In this embodiment, the photolithography reflow step of the spherical dome can be integrated into the existing CMOS production line, thereby saving manufacturing costs.

[0070] Optionally, fabricating an optical fiber array includes:

[0071] Smooth the end face of the fiber array;

[0072] Polish the smoothed fiber array;

[0073] Remove part of the outer sheath of the fiber array to expose the bare fiber portion of each channel of the fiber array;

[0074] The fiber lengths corresponding to each channel of the fiber array are fixed so that the deviation between the fiber lengths corresponding to each channel is less than or equal to a preset deviation value.

[0075] In this embodiment, a 16-channel single-mode fiber array can be selected, wherein the fiber cladding diameter is 125μm, the core diameter is 9μm, the channel spacing is 127μm, and the fiber length is 1m. The end face of the fiber array is smoothed using a diamond wheel mechanical polishing process, wherein the polishing angle is 0°, and the root mean square roughness of the polished end face is less than or equal to 20nm.

[0076] The outer sheath of the fiber array is stripped to a length of 18mm to expose the bare fiber. The fiber optic cables are then fixed in place by clamps to ensure that the fiber optic cables of each channel are arranged in a coplanar manner with equal lengths. The coplanarity deviation is less than or equal to a preset deviation value. Optionally, the preset deviation value is 0.1mm to avoid coupling deviation caused by inconsistent fiber lengths.

[0077] Optionally, the carrier chip is fabricated, including:

[0078] Alignment pit array and mounting vias are fabricated on a wafer substrate using maskless photolithography; the alignment pit array is located in the edge region of the wafer, and the mounting vias are located in the center region of the wafer;

[0079] The area where the alignment pit array is located is etched to form an inverted pyramid alignment pit;

[0080] A micro / nano sleeve was fabricated inside the mounting via using photoresist to obtain a carrier chip.

[0081] In this embodiment, a 4-inch screen can be selected. <100> A crystal-oriented wafer serves as the substrate for the carrier chip, with a wafer thickness of 300 μm. A 200 nm thick silicon nitride layer is deposited on the substrate surface using PECVD technology as an etch barrier layer. Alignment pit arrays and mounting vias are fabricated on the substrate using maskless photolithography, with the alignment pit arrays located at the edge region of the carrier chip and the mounting vias located at the center region of the carrier chip.

[0082] A silicon substrate was etched using a 90℃ KOH wet etching process to form inverted pyramid alignment pits, with a pit opening side length of 6μm, a depth of 8μm, and a cone angle of 60°. Subsequently, a dry etching process was used to remove the silicon nitride layer in the via region, forming mounting vias with a diameter of 125.2μm. The fabricated carrier chip was fixed onto the stage of a 3D printing machine, and a micro / nano sleeve was fabricated within the mounting via using photoresist. The sleeve had an inner hole diameter of 125.1μm, a length of 100μm, and a hole wall roughness of less than or equal to 50nm. After printing, the chip was cured under 365nm UV light for 10 minutes and developed with isopropanol to complete the carrier chip fabrication.

[0083] In this embodiment, the 3D printing of the micro-nano sleeve can be integrated into the existing CMOS production line, thereby saving manufacturing costs.

[0084] In the above embodiments, a two-level self-alignment mechanism of "spherical dome-inverted pyramid pit coarse alignment + micro-nano sleeve fine alignment" is adopted to construct a full-dimensional alignment system from macro to micro and realize multi-level self-alignment structure design.

[0085] A spherical dome array is fabricated in the alignment area of ​​the silicon photonics chip using thick AZ40 photoresist; correspondingly, an inverted pyramidal alignment pit is fabricated on the fiber array carrier chip by maskless photolithography and 90℃ KOH wet etching; through the elastic interlocking of the spherical dome and the inverted pyramidal pit, rapid correction of macroscopic deviations at the 10μm level is achieved, and the alignment accuracy can reach ±2μm.

[0086] Based on this, a two-photon polymerization 3D-printed micro / nano sleeve is integrated into the fiber mounting area of ​​the carrier chip. Through the synergy of micro / nano fabrication and 3D printing technologies, the radial and axial positional deviations of each channel fiber are constrained to the submicron level (within ±0.3μm), providing a core guarantee for cross-channel consistency of arrays with 8 or more channels from a structural perspective.

[0087] In the above embodiments, to address the coupling loss problem caused by multi-channel mode field mismatch, an innovative composite mode field modulation structure of "gradient refractive index microlens array + refractive index matching layer" is designed to achieve efficient and seamless transition between silicon photonic waveguide and fiber mode field. At the waveguide output end of the silicon photonic chip, a graded refractive index microlens array is integrated using wafer-level electron beam lithography. The radius of curvature of the microlens is precisely matched to that of the single-mode fiber, expanding the mode field size of the silicon photonic waveguide to match that of the fiber mode field. Simultaneously, a customized UV-curable refractive index matching adhesive is filled between the fiber end face and the microlens. The refractive index of this adhesive is continuously adjustable between 1.52 and 1.58, and the difference between its refractive index and that of the silicon photonic waveguide core layer and the fiber core layer is controlled within 0.05, reducing interface reflection loss to below 0.05 dB. This provides key process support for achieving a coupling target of less than 0.5 dB / channel.

[0088] Optionally, the coarse alignment operation on the silicon photonics chip and the carrier chip includes:

[0089] The silicon photonic chip is placed on a precision vacuum stage, and the spherical dome array on the surface of the silicon photonic chip is positioned.

[0090] The carrier chip is placed on a three-dimensional fine-tuning platform;

[0091] Adjust the orientation of the three-dimensional fine-tuning platform so that the alignment pit array of the carrier chip is aligned with the spherical dome array of the silicon photonics chip;

[0092] Pressure is applied to the alignment area of ​​the silicon photonic chip so that the spherical dome of the silicon photonic chip is embedded in the inverted pyramid alignment pit of the carrier chip.

[0093] In this embodiment, the silicon photonics chip is fixed on a precision vacuum stage, and the spherical dome array on the chip surface is positioned using a high-magnification microscope. The carrier chip is placed on a three-dimensional fine-tuning platform, and the orientation of the platform is adjusted to align the alignment pit array of the carrier chip with the spherical dome array of the silicon photonics chip. Pressure is applied to the alignment area of ​​the silicon photonics chip; optionally, this pressure is an axial pressure of 5N, causing the spherical domes to elastically embed into the inverted pyramid pits. Visual monitoring confirms that the alignment deviation is less than or equal to ±2μm, completing the macroscopic coarse alignment.

[0094] Optionally, mounting the fiber array onto the carrier chip to achieve coupling between the fiber array and the carrier chip includes:

[0095] The fiber array is inserted into the micro / nano sleeve of the carrier chip;

[0096] Curing adhesive is dripped into the U-shaped groove of the carrier chip to achieve coupling between the optical fiber array and the carrier chip.

[0097] In this embodiment, the pre-treated 16-channel fiber array is slowly inserted into the micro / nano sleeve of the carrier chip, ensuring that the distance between the fiber end face and the microlens end face of the silicon photonics chip is controlled within 1 to 2 μm. Curing adhesive is dripped into the U-shaped groove of the carrier chip; optionally, 0.1 ml of low-viscosity UV-curable adhesive can be dripped in. The curing agent has a viscosity of 300 mPas and a refractive index of 1.55. The adhesive quickly fills the gaps between the fiber, the sleeve, and the U-shaped groove through capillary action. Excess adhesive is blown away by a nitrogen gas stream to prevent adhesive overflow and contamination of the coupling end face.

[0098] Optionally, performing a fine alignment operation on the carrier chip and the fiber array includes:

[0099] A quartz cover plate is placed over the surface of the fiber array and pressure is applied;

[0100] Optical signals are injected into each channel of the optical fiber array, and the transmitted optical power of each channel is collected in real time.

[0101] Based on the acquired optical power of each channel, the carrier chip is adjusted so that the optical power of each channel reaches its maximum value.

[0102] In this embodiment, the two-stage self-alignment mechanism, combined with dual closed-loop control of "visual positioning + optical power feedback," controls the positional deviation of each channel to the sub-micron level, with inter-channel loss dispersion less than or equal to ±0.08 dB, completely solving the core pain point of poor multi-channel consistency in existing technologies. Simultaneously, the parallel alignment process reduces the coupling time of 16 channels to less than 3 minutes, improving efficiency by over 80% compared to traditional channel-by-channel active alignment processes, significantly reducing time and labor costs for industrial production.

[0103] Optionally, the step of performing a curing operation on the fiber array to obtain the coupling structure between the silicon photonic chip and the fiber array includes:

[0104] The coupling region between the fiber array and the carrier chip is irradiated with ultraviolet light for a fixed duration to obtain the coupling structure between the silicon photonic chip and the fiber array.

[0105] In this embodiment, a quartz cover plate can be placed over the surface of the fiber array and pressure can be applied. Optionally, the pressure is a uniform pressure of 3N to prevent the fiber from floating during the curing process of the adhesive.

[0106] The array-type laser source and photodetector array are turned on, and a TE mode optical signal with a wavelength of 1550nm is injected into each channel. The detector collects the transmitted optical power of each channel in real time. At the same time, the vernier alignment mark on the edge of the carrier chip is read by a high-magnification microscope. Combined with the optical power data, the attitude of the three-dimensional fine-tuning platform is automatically adjusted to adjust the carrier chip until the transmitted optical power of all channels reaches the maximum value, that is, the loss is less than or equal to 0.45dB / channel.

[0107] Furthermore, while keeping the three-dimensional fine-tuning platform in the same position, the coupling area is irradiated with 365nm ultraviolet light for 10 minutes to allow the adhesive to fully cure, thus completing the precise alignment and fixation.

[0108] In this embodiment, a dual-closed-loop parallel alignment control mechanism of "visual positioning + optical power feedback" is established to achieve efficient and consistent alignment of 8 channels or more. A vernier alignment mark is designed on the edge of the carrier chip, and real-time visual monitoring of alignment deviation is achieved using a high-magnification microscope. Simultaneously, an array-type laser source with a wavelength of 1550nm is used to inject optical signals into the silicon photonics chip through an optical fiber array. The photodetector array at the output end of the silicon photonics chip collects the transmitted optical power data of each channel in real time. Based on the visual positioning data and optical power data, a self-developed multi-objective optimization algorithm (based on particle swarm optimization principles) automatically adjusts the X, Y, and Z axis translations and θx, θy, and θz axis rotations of the carrier chip, achieving synchronous alignment optimization of 8 to 32 channels and avoiding the inefficiency and deviation accumulation caused by channel-by-channel calibration. This method reduces the coupling alignment time of 16 channels from 1 to 2 hours in traditional processes to less than 3 minutes, while ensuring that the loss dispersion of all channels is controlled within ±0.08dB.

[0109] In this embodiment, through the synergistic effect of multi-level self-aligned structure and mode field matching composite process, high-density parallel coupling of 8 to 32 channels is successfully achieved, with the channel spacing maintaining the international standard of 127μm, which can be directly adapted to the existing optical module packaging size; the coupling loss of each channel is stably controlled within 0.5dB, which is more than 40% lower than the existing multi-channel coupling technology, and there is no significant accumulation of loss when the number of channels is expanded from 8 to 32, which fully meets the low loss requirements of large-scale data transmission scenarios.

[0110] Optionally, forming a protective cladding layer on the surface of the coupling structure includes:

[0111] A cladding material is coated onto the surface of the coupling structure using a spin coating process.

[0112] The coupling structure is placed in an oven for baking and curing to form a protective cladding layer on the surface of the coupling structure.

[0113] In this embodiment, a coating material is coated onto the surface of the coupling structure using a spin coating process. The coating material can be SU-8 polymer. The spin coating process has a spin coating speed of 3000 rpm and a spin coating time of 30 seconds. The coating material is a coating film with a thickness of 60 μm.

[0114] The coupling structure is placed in an oven and baked and cured according to a stepped temperature increase program of 65℃ / 30 minutes, 95℃ / 30 minutes, and 120℃ / 30 minutes to form a dense protective upper cladding layer, thereby improving the mechanical strength and environmental adaptability of the component.

[0115] In this embodiment, the integrated encapsulation structure of "U-groove-cover plate-upper cladding" effectively isolates the influence of environmental humidity, vibration and temperature fluctuations on the coupling structure. Reliability testing has verified that after 1000 thermal shock cycles from -40℃ to 85℃, the change in coupling loss is less than or equal to 0.03dB / channel. After working in a high humidity environment of 85%RH for 500 hours, there is no significant drift in loss. The UV-curable adhesive and SU-8 cladding material used have excellent chemical stability and mechanical strength, resulting in a long component lifespan and fully meeting the reliability requirements of industrial applications.

[0116] Optionally, the step of performing performance testing and calibration on the coupling structure to obtain the target coupling structure includes:

[0117] Inject optical signals into each channel of the fiber array and detect the insertion loss of each channel;

[0118] For the target channel, a micro-nano laser fine-tuning device is used to correct the curvature of the microlens in the target channel; the target channel is the channel among the channels whose insertion loss is greater than a first preset loss.

[0119] The coupling structure was subjected to thermal shock cycling and humidity tests, and the insertion loss of each channel was detected.

[0120] If the loss variation of each channel is less than or equal to the second preset loss, the coupling structure is determined to pass the performance test and calibration to obtain the target coupling structure.

[0121] In this embodiment, a tunable laser source with a wavelength of 1550nm is used, along with a polarization controller to adjust the TE mode polarization state of the input light. The insertion loss of each channel is tested using an optical power meter. For channels with a loss exceeding 0.45dB / channel, a micro-nano laser fine-tuning device is used to precisely correct the curvature of the microlenses, with each correction amount less than or equal to 0.05μm, until the coupling loss of all channels is less than or equal to 0.5dB / channel, and the loss dispersion between channels is less than or equal to ±0.08dB. The components are subjected to thermal shock cycling from -40℃ to 85℃ (1000 cycles) and high humidity (85℃, 500 hours) reliability tests to ensure that the loss change is less than 0.03dB / channel, thus completing the entire coupling process.

[0122] In this embodiment, an innovative integrated packaging structure of "U-groove - UV transparent cover plate - polymer cladding" is designed, which takes into account mechanical fixation, pattern matching, and environmental protection functions. An integrated U-groove array is fabricated on the carrier chip using dry etching. Low-viscosity UV-curable adhesive is introduced into the U-groove through capillary action. The adhesive not only achieves tight fixation of the optical fiber but also plays a role in secondary refractive index matching. A 1mm thick UV transparent quartz cover plate is used to cover the surface of the optical fiber array, and a uniform pressure of 3N is applied to prevent vertical displacement of the optical fiber due to buoyancy during adhesive curing. After the adhesive is cured by irradiation with 365nm UV light for 10 minutes, a 60μm thick polymer cladding layer is coated on the surface of the packaging structure using a spin-coating process. This is then cured by baking at 120℃ for 30 minutes to form a dense protective layer. This packaging structure effectively isolates the effects of environmental humidity and vibration. After undergoing thermal shock cycling (1000 cycles) from -40℃ to 85℃ and high humidity (85%RH, 85℃, 500 hours) tests, the change in coupling loss of each channel is less than or equal to 0.03dB / channel, significantly improving structural stability and long-term reliability.

[0123] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0124] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0125] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A coupling method between a silicon photonic chip and an optical fiber array, characterized in that, The method includes: Fabrication of silicon photonics chips, fiber arrays, and carrier chips; the fiber array is an 8- to 32-channel single-mode fiber array. A coarse alignment operation is performed on the silicon photonics chip and the carrier chip to achieve coupling between the silicon photonics chip and the carrier chip; The fiber array is mounted onto the carrier chip to achieve coupling between the fiber array and the carrier chip; A fine alignment operation is performed on the carrier chip and the fiber array, and a curing operation is performed on the fiber array to obtain a coupling structure between the silicon photonic chip and the fiber array; The coupling structure is subjected to end face cutting and polishing, and a protective cladding layer is formed on the surface of the coupling structure; The performance of the coupling structure is tested and calibrated to obtain the target coupling structure.

2. The method according to claim 1, characterized in that, Fabrication of silicon photonic chips includes: Ridge waveguide arrays are fabricated on the wafer surface using an exposure technique; A fan-out grating coupler is integrated at the waveguide output end of the ridge waveguide array; In the alignment area of ​​the silicon photonic chip, a photolithography operation is performed by spin coating with photoresist to form a spherical dome array.

3. The method according to claim 1, characterized in that, Fabrication of fiber arrays includes: Smooth the end face of the fiber array; Polish the smoothed fiber array; Remove part of the outer sheath of the fiber array to expose the bare fiber portion of each channel of the fiber array; The fiber lengths corresponding to each channel of the fiber array are fixed so that the deviation between the fiber lengths corresponding to each channel is less than or equal to a preset deviation value.

4. The method according to claim 1, characterized in that, Fabrication of carrier chips includes: Alignment pit array and mounting vias are fabricated on a wafer substrate using maskless photolithography; the alignment pit array is located in the edge region of the wafer, and the mounting vias are located in the center region of the wafer; The area where the alignment pit array is located is etched to form an inverted pyramid alignment pit; A micro / nano sleeve was fabricated inside the mounting via using photoresist to obtain a carrier chip.

5. The method according to claim 1, characterized in that, The coarse alignment operation on the silicon photonics chip and the carrier chip includes: The silicon photonic chip is placed on a precision vacuum stage, and the spherical dome array on the surface of the silicon photonic chip is positioned. The carrier chip is placed on a three-dimensional fine-tuning platform; Adjust the orientation of the three-dimensional fine-tuning platform so that the alignment pit array of the carrier chip is aligned with the spherical dome array of the silicon photonics chip; Pressure is applied to the alignment area of ​​the silicon photonic chip so that the spherical dome of the silicon photonic chip is embedded in the inverted pyramid alignment pit of the carrier chip.

6. The method according to claim 1, characterized in that, The step of mounting the fiber array onto the carrier chip to achieve coupling between the fiber array and the carrier chip includes: The fiber array is inserted into the micro / nano sleeve of the carrier chip; Curing adhesive is dripped into the U-shaped groove of the carrier chip to achieve coupling between the optical fiber array and the carrier chip.

7. The method according to claim 1, characterized in that, The precise alignment operation performed on the carrier chip and the fiber array includes: A quartz cover plate is placed over the surface of the fiber array and pressure is applied; Optical signals are injected into each channel of the optical fiber array, and the transmitted optical power of each channel is collected in real time. Based on the acquired optical power of each channel, the carrier chip is adjusted so that the optical power of each channel reaches its maximum value.

8. The method according to claim 1, characterized in that, The step of performing a curing operation on the fiber array to obtain the coupling structure between the silicon photonic chip and the fiber array includes: The coupling region between the fiber array and the carrier chip is irradiated with ultraviolet light for a fixed duration to obtain the coupling structure between the silicon photonic chip and the fiber array.

9. The method according to claim 1, characterized in that, The formation of a protective cladding layer on the surface of the coupling structure includes: A cladding material is coated onto the surface of the coupling structure using a spin coating process. The coupling structure is placed in an oven for baking and curing to form a protective cladding layer on the surface of the coupling structure.

10. The method according to any one of claims 1-9, characterized in that, The process of performing performance testing and calibration on the coupling structure to obtain the target coupling structure includes: Inject optical signals into each channel of the fiber array and detect the insertion loss of each channel; For the target channel, a micro-nano laser fine-tuning device is used to correct the curvature of the microlens in the target channel; the target channel is the channel among the channels whose insertion loss is greater than a first preset loss. The coupling structure was subjected to thermal shock cycling and humidity tests, and the insertion loss of each channel was detected. If the loss variation of each channel is less than or equal to the second preset loss, the coupling structure is determined to pass the performance test and calibration to obtain the target coupling structure.

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