Multifunctional high-frequency electromagnetic valve driving plate

Abstract

The invention relates to the technical field of electronic control, and discloses a multifunctional high-frequency electromagnetic valve driving board which comprises a logic control board and a pulse sequence power driving board which are connected through a communication interface. The logic control board takes a 32-bit ARM processor as a core, is embedded with a PLC control system and a human-computer interaction interface, and is responsible for upper-layer logic operation, parameter analysis and external communication; the pulse sequence power driving board is provided with a driving microprocessor which operates independently, and the driving microprocessor is used for receiving instructions and generating four groups of cooperative control signals including high-voltage starting, low-voltage holding, current adjusting and protection threshold setting. After the signals are interlocked and shaped by the logic processing circuit, the electromagnetic valve is controlled to act through the power tube driving circuit, and hardware-level real-time monitoring is realized by matching with the output overload protection circuit. According to the invention, a dual-core physical architecture is adopted to separate a logic task from a driving task, so that system scheduling interference is avoided, and microsecond-level time sequence control precision, programmable logic control and high-reliability hardware protection are realized.

Description

Technical Field

[0001] This invention relates to the field of electronic control technology, specifically to a multifunctional high-frequency solenoid valve drive board. Background Technology

[0002] In modern industrial automation control systems, high-frequency solenoid valves, as key actuators, are widely used in textile machinery, dispensing equipment, and spray systems. These applications typically require solenoid valves to have extremely high operating frequencies and precise opening times to ensure accurate fluid control.

[0003] Most existing solenoid valve actuators employ a single microcontroller architecture, utilizing a single microprocessor to handle host computer communication, logic operations, status display, and low-level PWM drive signal generation simultaneously. This architecture is sufficient for low-frequency solenoid valve operation. However, as device operating speeds increase, the interrupt tasks that the microprocessor needs to handle become increasingly heavy. When the amount of communication data is large or the control logic is complex, resource contention within the processor can cause timing jitter in PWM signal generation, leading to deviations in the opening or closing timing of the solenoid valve and affecting the consistency and stability of the device.

[0004] Furthermore, in terms of drive current control, traditional solutions often employ software closed-loop regulation or simple open-loop voltage control. Open-loop control struggles to adapt to changes in load impedance with temperature, easily leading to coil overheating or insufficient pull-in force. Meanwhile, software-based closed-loop control is limited by the ADC sampling rate and CPU processing speed, failing to respond to current surges in real time on a microsecond scale, resulting in large current waveform ripple and increased device losses.

[0005] Regarding circuit protection mechanisms, existing technologies typically employ a resistor divider network with fixed resistance values ​​to set overcurrent protection thresholds. This hardware-based approach lacks flexibility; when the driver board needs to be adapted to different specifications of solenoid valves, hardware components often need to be replaced. While some solutions implement software-set thresholds, they rely on a microprocessor to read sampled values ​​and make judgments. This method introduces processing delays, and in the event of a severe short-circuit fault, the delayed response may damage power devices. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a multifunctional high-frequency solenoid valve driver board, which solves the problems of high-frequency control timing jitter, software current closed-loop response lag, and lack of flexibility and real-time performance of protection mechanisms in existing solenoid valve drivers due to their single-microprocessor architecture.

[0007] To achieve the above objectives, the present invention is implemented through the following technical solution: a multifunctional high-frequency electromagnetic valve drive board, comprising a logic control board and a pulse sequence power drive board that are physically separated and connected by a communication interface circuit; The logic control board includes a logic microprocessor, which is used to receive control logic input by the user and convert it into physical action parameters, and send instructions through the communication interface circuit. The pulse sequence power driver board includes a driver microprocessor, a signal logic processing circuit, and an output power transistor driver circuit, wherein: The drive microprocessor is used to receive the instructions and generate drive control signals according to the instructions; The signal logic processing circuit is connected between the driving microprocessor and the output power transistor driving circuit, and is used to isolate and shape the driving control signal to obtain the processed driving control signal. The output power transistor drive circuit is used to drive the external solenoid valve according to the processed drive control signal.

[0008] Preferably, the drive control signals generated by the drive microprocessor include four sets of independent signals: The high-pressure opening control signal is used to control the high-pressure opening phase of the solenoid valve. The low-pressure holding control signal is used to control the low-pressure holding phase of the solenoid valve. The current adjustment signal is a pulse width modulation signal used to set the target value of the drive current; The protection threshold setting signal is a pulse width modulation signal used to set the trigger threshold for hardware protection.

[0009] Preferably, the signal logic processing circuit includes a logic interlock network; The logic interlock network receives the high-voltage turn-on control signal and the low-voltage hold control signal, and performs mutual exclusion processing on the high-voltage turn-on control signal and the low-voltage hold control signal through logic gate circuits to ensure that the control signals output to the output power transistor drive circuit are not simultaneously in an active state.

[0010] Preferably, the output power transistor drive circuit includes a power switch transistor, a current sampling resistor, and a current negative feedback loop constructed by an operational amplifier; The signal logic processing circuit further includes a first integral filter network for converting the current regulation signal into a DC reference voltage; The first input terminal of the operational amplifier receives the DC reference voltage, and the second input terminal receives the feedback voltage signal from the current sampling resistor; The output terminal of the operational amplifier is connected to the control terminal of the power switch. By comparing the DC reference voltage with the feedback voltage signal, the duty cycle of the power switch is adjusted so that the steady-state current flowing through the solenoid valve corresponds to the duty cycle of the current adjustment signal.

[0011] Preferably, the pulse sequence power drive board further includes an output overload protection circuit; The output overload protection circuit includes a second integral filter network, a hardware comparator, and hardware blocking logic. The second integral filter network is connected to the protection threshold setting signal output terminal of the driving microprocessor, and is used to convert the protection threshold setting signal into a protection reference voltage; The hardware comparator is used to compare the protection reference voltage with a real-time physical state sampling signal from the power circuit; The hardware blocking logic is connected between the output terminal of the hardware comparator and the control terminal of the output power transistor driver circuit, and is used to cut off the power output path of the output power transistor driver circuit when the amplitude of the real-time physical state sampling signal exceeds the protection reference voltage.

[0012] Preferably, the output power transistor drive circuit includes a high-voltage power supply branch and a low-voltage power supply branch; When the drive microprocessor receives an action trigger command, it first sets the high-voltage start control signal to an active level to turn on the high-voltage power supply branch. After a preset start time, it sets the high-voltage start control signal to inactive and, after a dead time, sets the low-voltage hold control signal to an active level to switch to the low-voltage power supply branch.

[0013] Preferably, the logic control board further includes a storage circuit, and the logic microprocessor runs an embedded programmable logic controller system; The logic microprocessor is equipped with a ladder diagram compiler, which is used to parse the ladder diagram program written by the user and send instructions containing the timing of the action to the pulse sequence power drive board according to the ladder diagram logic operation results.

[0014] Preferably, the driving microprocessor has a shadow register internally; The driving microprocessor is used to write the parameters into the shadow register after receiving and verifying the data frame containing physical action parameters sent by the logic microprocessor, and to load the parameters in the shadow register into the activity control register at the end of the currently executed driving pulse cycle.

[0015] Preferably, the logic microprocessor is provided with a parameter mapping module; The parameter mapping module is used to receive the holding current setting value and protection temperature threshold input by the user's physical quantity unit, and convert them into the corresponding duty cycle values ​​of the current adjustment signal and the protection threshold setting signal according to the hardware circuit parameters, and then package them and send them to the drive microprocessor.

[0016] Preferably, the pulse sequence power drive board is provided with a system operating power supply circuit; The system power supply circuit is used to receive external DC power input and convert it into multiple sets of DC power of different voltage levels to power the power devices and digital circuits on the pulse sequence power drive board, and to power the logic control board through the board-level connector.

[0017] This invention provides a multifunctional high-frequency solenoid valve drive board. It has the following beneficial effects: 1. This invention adopts a dual-board architecture with physical separation of the logic control board and the pulse sequence power drive board, decoupling non-real-time tasks such as human-machine interaction and PLC logic scanning from hard real-time tasks such as high-frequency pulse generation; this allows the drive microprocessor to exclusively occupy hardware timer resources, ensuring that the solenoid valve control timing reaches microsecond-level accuracy, avoiding jitter interference caused by the delay of the operating system task scheduling on the output waveform timing, thereby ensuring the consistency of the high-frequency solenoid valve's opening and closing under high-frequency action.

[0018] 2. This invention achieves hardware-level analog closed-loop current control by using a current regulation signal in conjunction with an operational amplifier negative feedback circuit. The driving microprocessor only needs to output a PWM signal with a specific duty cycle to set the target current value, and the high-speed operational amplifier automatically adjusts the conduction state of the power transistor in real time. This eliminates the calculation delay of the software PID algorithm, improves the dynamic response speed of the current loop, and enables the solenoid valve to obtain a stable drive current during the holding phase, thereby reducing coil heat generation and power consumption.

[0019] 3. This invention establishes a dynamic hardware protection mechanism using a protection threshold setting signal; users can flexibly configure protection thresholds for different load characteristics through software, and the thresholds are converted into analog reference voltages after filtering; during system operation, once an overcurrent or overtemperature fault occurs, the hardware comparator will directly trigger the blocking logic to cut off the power output path; it has the flexibility of software parameter settings and the fast response capability of hardware circuits, and can complete the protection of power devices before the microprocessor responds to the interrupt, thus improving the reliability of the system. Attached Figure Description

[0020] Figure 1 This is a block diagram of the overall hardware architecture of the multifunctional high-frequency solenoid valve drive system of the present invention. Figure 2 This is a functional block diagram of the multifunctional high-frequency solenoid valve drive board of the present invention. Figure 3 This is a block diagram of the high-frequency solenoid valve drive circuit of the present invention; Figure 4 This is a diagram of the high-frequency solenoid valve drive pulse sequence of the present invention; Figure 5 This is a diagram showing the control signal input and isolation of the present invention; Figure 6 This is a signal logic processing diagram of the present invention; Figure 7 This is a circuit diagram of the CPU system and memory circuit of the present invention; Figure 8 This is a circuit diagram of the communication interface of the present invention; Figure 9 This is a power drive circuit diagram of the present invention; Figure 10 This is the protection circuit diagram for the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Example: Please see the appendix Figure 1 The present invention provides a multifunctional high-frequency solenoid valve drive board, which mainly consists of two core hardware parts: a logic control board and a pulse sequence power drive board. The logic control board and the pulse sequence power drive board are electrically connected through an internal communication interface circuit to realize data interaction and command transmission.

[0023] The logic control board is mainly responsible for the system's upper-level logic operations, human-machine interaction, and parameter management. The logic control board includes a logic microprocessor, power supply circuit, communication interface circuit, human-machine interface, and storage circuit. The logic microprocessor adopts a 32-bit ARM core architecture and serves as the core computing unit of the logic control board. The power supply circuit is responsible for converting the input power into the 5V and 3.3V voltages required by the logic control board to power the onboard components. The storage circuit is connected to the logic microprocessor and is used to store system firmware, PLC ladder diagram programs, and user-defined control parameters.

[0024] Figure 7 This is a circuit diagram of the CPU system and memory circuit of the present invention.

[0025] like Figure 7As shown, this circuit illustrates the electrical connections between the logic microprocessor and its peripheral core components. The logic microprocessor U2 uses a 32-bit ARM Cortex-M3 core microcontroller (model STM32F103RBT6). Its pins are connected to an external clock oscillation circuit consisting of a 12MHz crystal oscillator X3 and oscillation capacitors (C29, C30), as well as a power-on reset circuit consisting of resistor R2 and capacitor C15, which together maintain the stable operation of the CPU. The core of the FLASH storage circuit is the serial flash memory chip U19 (model W25Q32JVSSIQ). Its chip select terminal CS#, clock terminal CLK, and data terminal DO / DI are connected to the GPIO port of U2 via the SPI bus for storing system programs and user data. In addition, the circuit also has an LED indicator group (POWER, RUN, COM) to indicate the 3.3V power supply, system operation heartbeat, and communication activity status, respectively.

[0026] The logic microprocessor has an embedded PLC control system and ladder diagram compiler; users input control logic or parameters through the human-machine interface, and the logic microprocessor parses and compiles the input information; the communication interface circuit is equipped with RS232 and RS485 interfaces to realize data exchange between the logic control board and the external host computer or factory automation network, and also serves as a channel for issuing instructions to the pulse sequence power drive board.

[0027] The pulse sequence power driver board is mainly responsible for the generation of underlying hardware drive signals and power output. The pulse sequence power driver board includes a driver microprocessor, signal logic processing circuit, output power transistor drive circuit, output overload protection circuit, system power supply circuit and output interface. The driver microprocessor also adopts a 32-bit ARM core architecture, runs independently of the logic microprocessor, and focuses on high-precision timing control.

[0028] The system power supply circuit receives an external 24V DC power supply and converts it into multiple voltages, including DC12V, DC5V, and DC3.3V, to power the power drive section and the digital control section, respectively. The drive microprocessor receives control commands from the logic microprocessor through the inter-board communication interface. The commands include the turn-on time, holding current setting value, and protection threshold setting value.

[0029] Please see the appendix Figure 3 Appendix Figure 4The microprocessor generates four sets of control signals using an internal timer based on the received instructions: VGH, VGL, IGLW, and PGLW. The VGH signal controls the high-pressure opening phase of the solenoid valve, the VGL signal controls the low-pressure holding phase of the solenoid valve, the IGLW signal is a pulse width modulation signal used to adjust the drive current, and the PGLW signal is a pulse width modulation signal used to set the threshold of the protection circuit.

[0030] The signal logic processing circuit is connected between the driver microprocessor and the output power transistor driver circuit. This circuit performs logic interlocking and signal shaping on the VGH and VGL signals output by the driver microprocessor to prevent the high-voltage and low-voltage drive circuits from conducting simultaneously. The processed control signal is then transmitted to the output power transistor driver circuit.

[0031] The output power transistor drive circuit includes a power switching transistor and a driver chip, which is responsible for amplifying the control signal and driving the external solenoid valve connected to the output interface. The output interface includes four independent physical channels, each channel corresponding to an independent drive circuit, which can control four independent high-frequency solenoid valves respectively.

[0032] The output overload protection circuit is connected to the output terminal of the output power transistor driver circuit. The output overload protection circuit monitors the output current and circuit temperature in real time, and feeds back the monitoring results to the driver microprocessor or directly to the control terminal of the output power transistor driver circuit. When the monitored value exceeds the threshold set by the PGLW signal, the output overload protection circuit performs a hardware cut-off operation to stop the power output.

[0033] In the system workflow, the logic microprocessor acts as the main controller, responsible for parsing the user's process requirements and converting physical parameters into digital instructions to send to the pulse sequence power drive board. The drive microprocessor acts as the slave controller, receiving instructions and generating the corresponding pulse sequence with a time accuracy of ±1μs. The signal logic processing circuit ensures the timing logic safety of the signal. The output power transistor drive circuit performs the final power amplification, thereby driving the solenoid valve to operate according to the predetermined curve. The output overload protection circuit provides hardware-level safety monitoring throughout the process.

[0034] Figure 2 This is a functional block diagram of the multifunctional high-frequency solenoid valve drive board of the present invention.

[0035] like Figure 2 As shown, the driver board system is physically divided into a logic control board on the left and a pulse sequence power driver board on the right, which interact with each other through a communication interface circuit.

[0036] In the logic control board section, the core component is a 32-bit CPU system circuit (i.e., a logic microprocessor), which is connected to a FLASH storage circuit for storing programs and data. The logic control board establishes external communication links and communication links with the right-side driver board through a communication interface circuit (supporting RS232 and RS485 protocols). In addition, the board also includes 5V and 3.3V power supply modules and has a reserved HMI human-machine interface for receiving user input.

[0037] In the pulse sequence power driver board section, the core component is the 32-bit CPU system pulse sequence generation circuit (i.e., the driver microprocessor), which is responsible for generating PWM modulation signals and control signals. The onboard system power supply circuit receives the input power and converts it into multiple voltage levels, including DC24V, DC12V, DC5V, and DC3.3V, to power various circuits. The signals generated by the driver microprocessor are transmitted to the signal logic processing module (i.e., the signal logic processing circuit), processed, and then enter the output power transistor driver circuit. The figure also shows the output overload protection circuit and surge suppression circuit, which are connected to the output power transistor driver circuit to monitor the status and provide protection. Finally, the output power transistor and output interfaces (channels 1, 2, 3, and 4 in the figure) are connected to the external output circuit power input to drive external loads.

[0038] Please see the appendix Figure 1 Appendix Figure 2 The multifunctional high-frequency solenoid valve drive system of this invention includes a logic control board and a pulse sequence power drive board in terms of physical architecture. The two are electrically connected and communicate with each other through board-level connectors. The system is built on a dual-core microprocessor architecture. The logic control board is equipped with a logic microprocessor, and the pulse sequence power drive board is equipped with a drive microprocessor. The architecture physically separates non-real-time tasks such as human-computer interaction from hard real-time tasks such as pulse generation at the hardware level, avoiding the interference of operating system task scheduling delay on the microsecond-level control timing accuracy of the solenoid valve.

[0039] The logic control board, as the system's upper-level control node, runs an embedded operating system and an embedded programmable logic controller (PLC) system. The logic microprocessor is connected to a storage circuit, which stores the system firmware and user-written ladder logic programs. The logic microprocessor also includes an instruction parsing module to parse the control logic input by the user through the human-machine interface and convert it into corresponding machine control instructions. These machine control instructions contain physical action parameters for specific channels, including at least the solenoid valve opening time. Hold current setting value and protection temperature threshold .

[0040] The pulse sequence power driver board serves as the lower-level execution node of the system, driving the microprocessor to independently run bare-metal programs or real-time kernels, ensuring exclusive access to hardware timer resources; the system's operating power supply circuit is located on the pulse sequence power driver board, used to convert externally input DC power into various operating voltages.

[0041] Figure 5 This is a diagram showing the control signal input and isolation of the present invention.

[0042] like Figure 5 As shown, this circuit converts externally input industrial-grade switching signals (X0 to X3) into low-voltage logic signals (I0 to I3) recognizable by the logic microprocessor. An RC filter network consisting of resistors (R23-R30) and capacitors (C10-C13) is provided at the external input terminal to filter out high-frequency interference pulses and limit the input current. The filtered signal is connected to a four-channel optocoupler U11. The output collector of the optocoupler is connected to a +5V power supply via a pull-up resistor array RN11, and the emitter is grounded. When the external X terminal signal is effectively turned on, the internal LED of the optocoupler emits light, and the phototransistor conducts, pulling the output I terminal low. This circuit utilizes the optocoupler to achieve electrical isolation between external high-noise signals and the internal logic circuit, preventing external surges from damaging the logic microprocessor.

[0043] The logic microprocessor and the driver microprocessor exchange data via an onboard communication interface (such as UART or SPI). To ensure the accuracy and real-time performance of parameter transmission, the inter-board data exchange process includes the following steps: When the logic microprocessor detects a change in user parameters or a system startup event, it encapsulates the physical action parameters into a communication data frame. The data frame contains the instruction type and parameter data, where the parameter data is a quantized digital value of the physical parameters, and the holding current setting value is mapped to the corresponding duty cycle value.

[0044] The logic microprocessor sends data frames to the pulse sequence power driver board through the communication port.

[0045] The driver microprocessor receives and verifies data frames. Upon successful verification, the driver microprocessor writes the parameter data into its internal shadow register. The shadow register buffers the parameters to be updated and loads them into the activity control register during idle intervals after the currently executing drive pulse cycle ends. This mechanism ensures that parameter update operations do not cause truncation or distortion of the current output waveform.

[0046] The driver microprocessor sends response data, including real-time current values ​​and temperature status of each channel, back to the logic microprocessor.

[0047] Please see the appendix Figure 3In this embodiment, the driving microprocessor adopts a multi-signal collaborative timing generation mechanism to control a single solenoid valve through four collaborative logic signal channels. The four signals are a high-pressure start control signal, a low-pressure hold control signal, a current adjustment signal, and a protection threshold setting signal.

[0048] Figure 4 This is a pulse timing waveform diagram of the high-frequency solenoid valve driven in an embodiment of the present invention.

[0049] like Figure 4 As shown, the horizontal axis represents the time axis, and the vertical axis represents the level state of each control signal. The figure shows the changes of four key signals over two complete action cycles from top to bottom: The first waveform (VGH) is the high-voltage opening control signal; its high-level pulse width corresponds to the "opening time" of the solenoid valve. During this stage, the drive circuit outputs high voltage to generate strong current, causing the valve core to close. The second waveform (VGL) is the low-voltage holding control signal, which intervenes after VGH goes low, controlling the drive circuit to enter the low-current holding stage and reducing power consumption. The third waveform (PGLW) is the protection threshold setting signal, which is a fixed frequency PWM wave. Its duty cycle corresponds to the trigger threshold of the temperature protection or current protection of the hardware protection circuit. The fourth waveform (IGLW) is the current regulation signal, which is a high-frequency dense PWM wave used for the modulation of the working current throughout the process. After being integrated and filtered, this signal serves as the reference for the current negative feedback loop, determining the steady-state value of the load current.

[0050] The driver microprocessor uses its internal high-resolution hardware timer unit to generate the above signals, ensuring the timing control accuracy of the pulse sequence. The generation and execution process of the driver pulse sequence specifically includes the following control logic: During the protection reference establishment phase, before the solenoid valve actuates, the drive microprocessor outputs a PGLW signal. The PGLW signal is a pulse width modulation waveform used to provide an analog reference voltage for the hardware protection circuit. The drive microprocessor adjusts the duty cycle of the PGLW signal to change the amplitude of the filtered DC level, thereby setting the trigger threshold voltage of the hardware protection circuit. The threshold voltage corresponds to the duty cycle of the PGLW signal, so that the physical threshold of over-temperature or over-current protection can be dynamically set by software.

[0051] High-voltage start-up phase; when an action trigger command is received, the drive microprocessor is constantly... The VGH signal is set to an active level, while the VGL signal remains inactive; the VGH signal controls the high-voltage power supply branch in the power stage circuit to conduct, causing the coil current to rise rapidly and engage the valve core.

[0052] The current is limited during the turn-on phase. At the same time, the drive microprocessor outputs the IGLW signal. After hardware filtering, the IGLW signal is converted into a reference voltage for the current loop. The amplitude of the reference voltage is positively correlated with the duty cycle of the IGLW signal. The drive circuit limits the maximum peak current of the output loop according to the reference voltage to prevent excessive current from damaging the device at the moment of turn-on.

[0053] Low-voltage holding phase; when the duration of the VGH signal reaches the preset on-time length. Then, the microprocessor cancels the VGH signal and sets the VGL signal after the dead time, switching to the low-voltage power supply branch or low-power maintenance mode.

[0054] The current regulation during the holding phase; after entering the holding phase, the drive microprocessor adjusts the duty cycle of the IGLW signal, reducing it to the value required to maintain the solenoid valve's engagement; by changing the duty cycle of IGLW, the system changes the given target value of the current closed-loop control system, thereby regulating the average current flowing through the solenoid valve coil to adapt to the load characteristics of different fluid media.

[0055] During the shutdown and reset phase, after the operation is completed, both the VGH and VGL signals are set to invalid.

[0056] Figure 3 This is a block diagram of the high-frequency solenoid valve drive circuit of the present invention.

[0057] like Figure 3 As shown, this circuit mainly consists of a signal logic processing module, an output power transistor drive circuit, and a protection circuit group. The PWM modulation signal and control signal (corresponding to the aforementioned VGH, VGL, IGLW, and PGLW signals) from the drive microprocessor first enter the signal logic processing module. This module is used to perform logic interlocking, integral filtering, and other processing on the signal, and to interact bidirectionally with the output power transistor drive circuit.

[0058] The output power transistor drive circuit is connected to an over-temperature protection circuit and an output overload protection circuit with integrated surge suppression function. These two protection circuits are responsible for real-time monitoring of the temperature of the power device and the current status of the output circuit. When an abnormal physical condition is detected, the protection circuit acts directly on the output power transistor drive circuit through hardware connection or feeds back to the signal logic processing module to trigger a block, thereby forcibly disconnecting the load circuits connected to output interfaces 1 to 4.

[0059] Figure 6 This is a signal logic processing diagram of the present invention.

[0060] like Figure 6As shown, the circuit mainly consists of an AND gate chip U21 (model 74HC08D), a buffer driver chip U12 (model SN74LVC244A), and a Schmitt trigger U32 (model SN74LVC1G14). The AND gate chip U21 receives enable signals (EN0-EN3) and modulation signals (LIW1-LIW4) from the microprocessor, and generates valid drive pulse signals (PLUS0-PLUS3) through hardware logic AND operations, ensuring that the drive waveform is only output when the enable is valid, thus forming the first level of logic interlock. The buffer driver chip U12 is used to enhance the driving capability of the signal. Its output enable terminals (1OE#, 2OE#) are controlled by the internal state signal (INSIDE) and its complementary signal (WITHOUT) after being inverted by U32, respectively. This complementary control logic ensures that control signals in different groups will not be in a low-impedance output state simultaneously at the hardware level, achieving physical isolation and mutual exclusion of the signal transmission path, and preventing the risk of power transistor shoot-through caused by signal interference.

[0061] In this embodiment, the signal logic processing circuit and the output power transistor driving circuit constitute a physical interface layer to achieve signal isolation, interlocking, and power amplification. The specific circuit implementation includes: Electrical isolation and shaping of control signals; the signals output by the drive microprocessor are isolated by optocouplers or digital isolators and then shaped by Schmitt triggers to eliminate signal jitter.

[0062] Hardware-level logic interlocking processing; the shaped VGH and VGL signals are connected to a logic interlocking network composed of logic gate circuits; the interlocking network uses logical AND and NOT operations to ensure that the high-voltage drive channel and the low-voltage drive channel are physically mutually exclusive, preventing power transistor shoot-through short circuits caused by software faults.

[0063] The driving current reference voltage is generated; the signal logic processing circuit uses the first integrating filter network to convert the IGLW pulse signal into a smooth DC reference voltage. .

[0064] Power amplification and closed-loop current control; output power transistor drive circuit receives control signals and reference voltage. The circuit drives a power MOSFET (power switch); a current sampling resistor is connected in series to generate a feedback voltage signal. .

[0065] Current negative feedback regulation; the output power transistor driver circuit integrates a comparator amplifier circuit, which uses the reference voltage... With feedback voltage The comparison is performed, and the duty cycle or gate drive voltage of the power MOSFET is modulated according to the comparison result to form a negative feedback closed loop, so that the steady-state current flowing through the solenoid valve follows the target value set by the IGLW signal.

[0066] Figure 9 This is a power drive circuit diagram of the present invention.

[0067] like Figure 9 As shown, an eight-channel inverting buffer U29 (model SN74HC240) is arranged at the top of the circuit to forcibly organize the weak control commands (HIGH1, YLIW1, etc.) into a signal queue with high drive capability.

[0068] The lower part of the circuit shows the high-voltage drive channel: transistors Q23, Q24 and Q25 form a discrete totem pole drive ladder, amplifying the current layer by layer, and instantly turning on the P-channel MOSFET Q28 at a nanosecond speed, thereby releasing the solenoid valve coil on the OP48V power rail.

[0069] The circuit incorporates an analog current closed loop. Operational amplifier U28 (model AP331) acts as the core, constantly monitoring the voltage across the sampling resistor R96 (0.05Ω) (representing the actual current) and comparing it in real time with the input reference voltage YLIW1 (representing the ideal current). If the actual value deviates from the ideal value, U28 immediately sends a block or adjust command to the gate driver chip U27 (model EG27517) via the SD1 pin, forcibly controlling the gate of power transistor Q30 to keep the load current on a preset trajectory, allowing no deviation whatsoever.

[0070] Please see the appendix Figure 5 - Appendix Figure 10 The dynamic hardware threshold protection mechanism based on PGLW signal in this embodiment achieves fast protection by converting software-defined protection parameters into physical reference voltages of hardware circuits. The mechanism is independent of the microprocessor main program.

[0071] Digital mapping of protection thresholds; driving the microprocessor to convert the user-set protection value into the duty cycle of the PGLW signal according to a preset ratio.

[0072] The analog reference voltage is reconstructed; the output overload protection circuit includes a second integral filter network to perform low-pass filtering on the PGLW signal and extract the DC reference voltage (i.e., the protection reference voltage) corresponding to the duty cycle.

[0073] Figure 10 This is the protection circuit diagram for the present invention.

[0074] like Figure 10As shown, the circuit deploys four precision operational amplifiers U6, U7, U9, and U10 (model LM321), configured in high-impedance differential amplification mode; the input terminals (EI1-EI4) are connected across the sampling resistors of the power loop to capture the weak current drop in the millivolt range; through the precision resistor network constructed by R16 and R5 (100K / 10K), the circuit's gain of 10 times powerfully amplifies these weak signals.

[0075] The amplified signal is not directly fed into the comparator, but must pass through a rectifier filter pool composed of Schottky diodes (D2-D7) and RC networks (such as C43 and R26). This stage of the circuit filters out high-frequency switching noise and extracts a smooth DC envelope signal (EEI1-EEI4) that represents the real load current, providing irrefutable physical evidence for subsequent hardware overload determination.

[0076] Hardware comparison of real-time physical state; the output overload protection circuit uses a hardware comparator (such as an operational amplifier or voltage comparator) to compare the above reference voltage with the real-time physical state signal from the sampling resistor or thermistor.

[0077] Hardware protection trigger: When the amplitude of the real-time physical signal exceeds the reference voltage, the level of the comparator output flips, enabling the subsequent hardware blocking logic.

[0078] Forced power output cut-off; after the hardware blocking logic is turned on, a hardware blocking signal is generated, which directly acts on the enable terminal or gate drive circuit of the power drive chip to forcibly cut off the output path of the power transistor; the cut-off action is executed by the hardware circuit, and the response speed does not depend on the interrupt response time of the microprocessor.

[0079] Please see the appendix Figure 1 Appendix Figure 8 In this embodiment, the logic control board supports user-defined control logic.

[0080] Embedded PLC operating environment: The logic microprocessor runs the PLC instruction interpretation engine and uses a cyclic scanning mechanism to perform input sampling, logic operations and output refresh.

[0081] Graphical logic conversion: The ladder diagram compiler converts the ladder diagram drawn by the user (containing elements such as contacts, coils, and timers) into a sequence of machine instructions, and the logic microprocessor sends action instructions to the driver board according to the instruction sequence.

[0082] Physical parameter mapping; the logic microprocessor is equipped with a parameter mapping module to receive physical parameters (time, current, temperature) input by the user; for the current set value, the parameter mapping module calculates the corresponding IGLW signal duty cycle value based on the sampling ratio and amplification factor of the hardware circuit. The calculation process is completed inside the logic microprocessor, and the calculated control parameters are sent to the driver board.

[0083] Network integration; communication interface circuit supports RS232 / RS485 communication; Figure 8 This is a circuit diagram of the communication interface of the present invention.

[0084] like Figure 8 As shown, the left side of the circuit is the RS232 communication unit. The core chip U14 (model SP232EEN) is tightly surrounded by numerous capacitors (C25, C28, C32, C33). These capacitors form a rapidly operating charge pump, responsible for violently boosting the TTL logic level to the RS232 standard level. The signal input and output terminals are connected in series with ferrite beads L7 and L8, and in parallel with transient suppression diodes D16 and D17 (model SMBJ16CA). This group of devices forms an impregnable dike, used to intercept and absorb the electrostatic surges conducted from the external interface.

[0085] On the right side of the circuit is the RS485 communication unit. U13 (model SP485EEN) acts as a loud driver for differential signals. Its A and B ports are connected by an impedance balancing network composed of R31 (10K), R32 (10K), and R33 (120Ω), which stubbornly clamps the idle potential of the bus. At the same time, diodes D6 and D7 prevent any voltage spikes exceeding the threshold from piercing the chip's protective layer.

[0086] The logic microprocessor maps the status and parameters of the solenoid valve to register addresses via the industrial fieldbus protocol, allowing external systems to read and write remotely.

[0087] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A multi-functional high-frequency solenoid valve drive board, characterized in that, This includes a logic control board and a pulse sequence power drive board that are physically separated but connected by a communication interface circuit. The logic control board includes a logic microprocessor, which is used to receive control logic input by the user and convert it into physical action parameters, and send instructions through the communication interface circuit. The pulse sequence power driver board includes a driver microprocessor, a signal logic processing circuit, and an output power transistor driver circuit, wherein: The drive microprocessor is used to receive the instructions and generate drive control signals according to the instructions; The signal logic processing circuit is connected between the driving microprocessor and the output power transistor driving circuit, and is used to isolate and shape the driving control signal to obtain the processed driving control signal. The output power transistor drive circuit is used to drive the external solenoid valve according to the processed drive control signal.

2. The multifunctional high-frequency solenoid valve drive board according to claim 1, characterized in that, The drive control signals generated by the drive microprocessor include four sets of independent signals: The high-pressure opening control signal is used to control the high-pressure opening phase of the solenoid valve. The low-pressure holding control signal is used to control the low-pressure holding phase of the solenoid valve. The current adjustment signal is a pulse width modulation signal used to set the target value of the drive current; The protection threshold setting signal is a pulse width modulation signal used to set the trigger threshold for hardware protection.

3. The multifunctional high-frequency solenoid valve drive board according to claim 2, characterized in that, The signal logic processing circuit includes a logic interlock network; The logic interlock network receives the high-voltage turn-on control signal and the low-voltage hold control signal, and performs mutual exclusion processing on the high-voltage turn-on control signal and the low-voltage hold control signal through logic gate circuits to ensure that the control signals output to the output power transistor drive circuit are not simultaneously in an active state.

4. The multifunctional high-frequency solenoid valve drive board according to claim 2, characterized in that, The output power transistor drive circuit includes a power switch transistor, a current sampling resistor, and a current negative feedback loop constructed by an operational amplifier. The signal logic processing circuit further includes a first integral filter network for converting the current regulation signal into a DC reference voltage; The first input terminal of the operational amplifier receives the DC reference voltage, and the second input terminal receives the feedback voltage signal from the current sampling resistor; The output terminal of the operational amplifier is connected to the control terminal of the power switch. By comparing the DC reference voltage with the feedback voltage signal, the duty cycle of the power switch is adjusted so that the steady-state current flowing through the solenoid valve corresponds to the duty cycle of the current adjustment signal.

5. The multifunctional high-frequency solenoid valve drive board according to claim 2, characterized in that, The pulse sequence power drive board also includes an output overload protection circuit. The output overload protection circuit includes a second integral filter network, a hardware comparator, and hardware blocking logic. The second integral filter network is connected to the protection threshold setting signal output terminal of the driving microprocessor, and is used to convert the protection threshold setting signal into a protection reference voltage; The hardware comparator is used to compare the protection reference voltage with a real-time physical state sampling signal from the power circuit; The hardware blocking logic is connected between the output terminal of the hardware comparator and the control terminal of the output power transistor driver circuit, and is used to cut off the power output path of the output power transistor driver circuit when the amplitude of the real-time physical state sampling signal exceeds the protection reference voltage.

6. The multifunctional high-frequency solenoid valve drive board according to claim 3, characterized in that, The output power transistor drive circuit includes a high-voltage power supply branch and a low-voltage power supply branch. When the drive microprocessor receives an action trigger command, it first sets the high-voltage start control signal to an active level to turn on the high-voltage power supply branch. After a preset start time, it sets the high-voltage start control signal to inactive and, after a dead time, sets the low-voltage hold control signal to an active level to switch to the low-voltage power supply branch.

7. The multifunctional high-frequency solenoid valve drive board according to claim 1, characterized in that, The logic control board also includes a storage circuit, and the logic microprocessor runs an embedded programmable logic controller system. The logic microprocessor is equipped with a ladder diagram compiler, which is used to parse the ladder diagram program written by the user and send instructions containing the timing of the action to the pulse sequence power drive board according to the ladder diagram logic operation results.

8. The multifunctional high-frequency solenoid valve drive board according to claim 1, characterized in that, The driver microprocessor has a shadow register inside; The driving microprocessor is used to write the parameters into the shadow register after receiving and verifying the data frame containing physical action parameters sent by the logic microprocessor, and to load the parameters in the shadow register into the activity control register at the end of the currently executed driving pulse cycle.

9. The multifunctional high-frequency solenoid valve drive board according to claim 2, characterized in that, The logic microprocessor is equipped with a parameter mapping module; The parameter mapping module is used to receive the holding current setting value and protection temperature threshold input by the user's physical quantity unit, and convert them into the corresponding duty cycle values ​​of the current adjustment signal and the protection threshold setting signal according to the hardware circuit parameters, and then package them and send them to the drive microprocessor.

10. The multifunctional high-frequency solenoid valve drive board according to claim 1, characterized in that, The pulse sequence power driver board is equipped with a system operating power supply circuit. The system power supply circuit is used to receive external DC power input and convert it into multiple sets of DC power of different voltage levels to power the power devices and digital circuits on the pulse sequence power drive board, and to power the logic control board through the board-level connector.

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