Multi-board-card synchronous acquisition method and system

Abstract

The invention belongs to the technical field of signal interleaving acquisition, and particularly relates to a multi-board-card synchronous acquisition method and system, the system comprises a PXIe case and at least two acquisition cards arranged in the PXIe case, one acquisition card is selected as a main acquisition card to generate an acquisition enable signal, the other acquisition cards are selected as sub-acquisition cards, and the acquisition enable signal is transmitted to the PXIe case. The acquisition enabling signals are distributed to the other sub acquisition cards to synchronously acquire at least two preset calibration signals to obtain first sampling data and second sampling data, and the first sampling data and the second sampling data are processed to obtain variable delay parameters between each sub acquisition card and the main acquisition card; and synchronous acquisition between the plurality of sub acquisition cards in each acquisition card and the main acquisition card is carried out according to the variable delay parameters. According to the invention, different types of acquisition cards with different sampling rates can be flexibly configured, the acquisition card is selected as the main acquisition card or the sub-acquisition card for synchronous acquisition of the plurality of acquisition cards, and the method has the characteristics of universality and high precision.

Description

Technical Field

[0001] This invention belongs to the field of signal interleaving acquisition technology, specifically relating to a multi-board synchronous acquisition method and system. Background Technology

[0002] In cutting-edge scientific research and high-end industrial testing applications, synchronous data acquisition is fundamental to obtaining high-quality, high-reliability measurement results. These applications often require the simultaneous monitoring and analysis of signals from a large number of sensors or device nodes, and are extremely sensitive to the temporal relationships between signals, such as phase difference and time difference of arrival. During data exchange between transmitters and receivers, precise synchronization of each transceiver channel is essential to improve signal sampling accuracy.

[0003] PXIe (PCI Express Extensions for Instrumentation) test systems are becoming increasingly widely used due to their standardization, versatility, and maturity. For a PXIe multi-board synchronous sampling system or device, users can use different numbers of PXIe acquisition cards according to their actual needs. However, even PXIe sampling systems using the same model of acquisition cards will inevitably have link latency. Especially in high-speed signal acquisition applications at GHz, this latency can cause significant misalignment of the acquired signals, leading to large errors in subsequent frequency band interleaving sampling and reducing the accuracy of multi-frequency band signal interleaving sampling.

[0004] Link latency originates from a variety of complex sources, primarily including: clock distribution latency between multiple boards, which can exhibit picosecond-level delay differences due to physical variations such as backplane trace length and load; internal clock distribution latency within the boards, introduced by internal trace delays as the reference signal is distributed to each ADC chip via PLLs, clock buffers, and other devices within the acquisition card; and the analog signal path from the signal source to the inputs of each acquisition card, where link latency varies due to cable length, connectors, and analog front-end board conditioning circuits. Existing technologies offer various solutions to address these different sources of link latency, but these processes are complex and have limited calibration accuracy. In applications requiring frequent system reconfigurations and board or cable replacements, achieving a fast, accurate, and automated multi-board synchronous acquisition solution has become a pressing technical challenge. Summary of the Invention

[0005] The purpose of this invention is to provide a method and system for synchronous acquisition of multiple boards, so as to solve one or more technical problems in the background art mentioned above.

[0006] To achieve the above objectives, in a first aspect, the present invention provides a multi-board synchronous acquisition method for synchronously acquiring a measured signal in a multi-board synchronous acquisition system. The multi-board synchronous acquisition system includes a PXIe chassis, at least two acquisition cards disposed within the PXIe chassis, and a clock card. The clock card includes a clock source module and a first trigger module. The method includes:

[0007] Preset the first calibration signal;

[0008] A second calibration signal is preset, and the second calibration signal and the first calibration signal have coprime frequencies.

[0009] The clock source module in the clock card is controlled to simultaneously send clock signals to the acquisition card;

[0010] Select one of the acquisition cards as the main acquisition card, and select the remaining acquisition cards as sub-acquisition cards;

[0011] The first trigger module in the clock card generates a trigger signal and sends the trigger signal to the main acquisition card. The main acquisition card responds to the trigger signal by generating an acquisition enable signal.

[0012] The main acquisition card is controlled to distribute the acquisition enable signal to each of the sub-acquisition cards;

[0013] The main acquisition card responds to the trigger signal to acquire the first calibration signal, and each of the sub-acquisition cards responds to the acquisition enable signal to acquire the first calibration signal, thereby obtaining the first phase delay data of each sub-acquisition card relative to the main acquisition card;

[0014] The main acquisition card responds to the trigger signal to acquire the second calibration signal, and each of the sub-acquisition cards responds to the acquisition enable signal to acquire the second calibration signal, thereby obtaining the second phase delay data of each sub-acquisition card relative to the main acquisition card;

[0015] Defuzzing calculations are performed on the first phase delay data and the second phase delay data to obtain the variable delay parameter between each of the sub-acquisition cards and the main acquisition card;

[0016] Based on the variable delay parameter, each of the sub-acquisition cards is configured to synchronize acquisition with the main acquisition card.

[0017] In some implementations, a third calibration signal is preset that is frequency-coprime with both the first and second calibration signals;

[0018] The main acquisition card responds to the trigger signal to acquire the third calibration signal, and each of the sub-acquisition cards responds to the acquisition enable signal to synchronously acquire the third calibration signal, so as to obtain the third phase delay data of each sub-acquisition card relative to the main acquisition card;

[0019] Defuzzing calculations are performed on the first phase delay data, the second phase delay data, and the third phase delay data to obtain the variable delay parameter between each sub-acquisition card and the main acquisition card.

[0020] In some implementations, the multi-board synchronous acquisition system includes a control card disposed within the PXIe chassis, the control card having a first data processor, each acquisition card including an analog-to-digital converter and a second data processor, and further including: Before acquiring the first phase delay data of each sub-acquisition card relative to the main acquisition card, the system further includes:

[0021] The analog-to-digital converter in the main acquisition card acquires the first calibration signal to obtain the first sampling data;

[0022] The second data processor in the main acquisition card performs a Hilbert transform on the first sampled data to generate a first complex signal.

[0023] The analog-to-digital converter in each of the sub-acquisition cards acquires the first calibration signal to obtain the second sampling data;

[0024] The second data processor within each of the sub-acquisition cards performs a Hilbert transform on the second sampled data to generate a second complex signal;

[0025] The control card acquires a first complex signal from the main acquisition card and a second complex signal from each of the sub-acquisition cards;

[0026] The first data processor in the control card performs conjugate multiplication of the second complex signal in each of the sub-acquisition cards with the first complex signal in the main acquisition card to obtain the first phase delay data of each sub-acquisition card relative to the main acquisition card.

[0027] In some embodiments, the multi-board synchronous acquisition system includes a control card disposed within the PXIe chassis, the control card having a first data processor, each acquisition card including an analog-to-digital converter and a second data processor, and further comprising, before acquiring the first phase delay data of each sub-acquisition card relative to the main acquisition card:

[0028] The analog-to-digital converter in the main acquisition card acquires the first calibration signal to obtain the first sampling data;

[0029] The second data processor in the main acquisition card performs a fast Fourier transform on the first sampled data to obtain the first spectrum;

[0030] The analog-to-digital converter in each of the sub-acquisition cards acquires the first calibration signal to obtain the second sampling data;

[0031] The second data processor within each of the sub-acquisition cards performs a fast Fourier transform on the second sampled data to obtain the second spectrum;

[0032] The control card acquires the first spectrum in the main acquisition card and the second spectrum in each of the sub-acquisition cards;

[0033] The control card extracts the first phase angle information at the first frequency point index according to the first frequency point index of the first spectrum corresponding to the frequency of the first calibration signal.

[0034] The control card extracts the second phase angle information at the second frequency point index according to the second frequency point index of the second spectrum corresponding to the frequency of the first calibration signal;

[0035] The first data processor within the control card calculates the difference between the second phase angle information of each sub-acquisition card and the first phase angle information of the main acquisition card to obtain the first phase delay data of each sub-acquisition card relative to the main acquisition card.

[0036] In some implementations, defuzzification calculations are performed on the first phase delay data and the second phase delay data to obtain a variable delay parameter between each of the sub-acquisition cards and the main acquisition card, including:

[0037] The first data processing module presets a maximum expected time delay parameter;

[0038] Establish a system of linear equations that includes the variable delay parameter, the first fuzzy number, and the second fuzzy number, wherein the first fuzzy number and the second fuzzy number constitute an integer pair of fuzzy numbers;

[0039] The integer search range of the first fuzzy number and the second fuzzy number is determined based on the preset maximum expected time delay parameter;

[0040] Within the integer search range, traverse all pairs of fuzzy integers;

[0041] For each pair of fuzzy integers, two estimated values ​​of delay parameters are calculated based on the linear equations of the first fuzzy number and the second fuzzy number.

[0042] And determine the residual between the two estimated values ​​of the delay parameter;

[0043] Select the pair of fuzzy numbers that minimizes the residual between the estimated values ​​of the two delay parameters, and determine the first target fuzzy number and the second target fuzzy number.

[0044] Furthermore, the first target fuzzy number and the second target fuzzy number are substituted into a system of linear equations containing the delay parameter, the first fuzzy number, and the second fuzzy number to solve for the variable delay parameter.

[0045] In some implementations, before configuring each of the sub-acquisition cards to synchronize acquisition with the main acquisition card according to the variable delay parameter, the process includes:

[0046] The sampling period of the main acquisition card and each of the sub-acquisition cards is obtained, wherein the sampling period of the main acquisition card and each of the sub-acquisition cards is the same;

[0047] Divide the variable delay parameter by the sampling period to obtain the sample delay of each sub-acquisition card relative to the main acquisition card;

[0048] The sampling points of the second sampling data of each of the sub-acquisition cards are extracted according to the sampling point delay, so that each of the sub-acquisition cards can be synchronously acquired with the main acquisition card.

[0049] In some implementations, the acquisition card includes a second trigger module, which presets trigger conditions. When the preset trigger conditions are triggered, the main acquisition card acquires the signal under test.

[0050] In some implementations, the acquisition card includes an external trigger interface that controls the external trigger interface of the main acquisition card to receive the trigger signal.

[0051] And / or, control the external trigger interface of the sub-acquisition card to receive the acquisition enable signal generated by the main acquisition card.

[0052] In some implementations, a PXIe trigger bus and a PXIe star trigger line are also included, wherein the trigger signal generated by the first trigger module in the clock card is injected into the PXIe trigger bus, and the PXIe trigger bus routes the trigger signal to the main acquisition card;

[0053] The acquisition enable signal generated by the main acquisition card is injected into the PXIe star trigger line, and the PXIe star trigger line routes the acquisition enable signal to each of the sub-acquisition cards.

[0054] Secondly, the present invention provides a multi-board synchronous acquisition system for synchronously acquiring the signal under test, including a PXIe chassis, at least two acquisition cards, a clock card, a control card, a PXIe trigger bus, and a PXIe star trigger line disposed within the PXIe chassis; the clock card includes a clock source module and a first trigger module, and the acquisition card includes an analog-to-digital converter, a second data processor, a second trigger module, and / or an external trigger interface; when the multi-board synchronous acquisition system executes a program or instruction, it implements the multi-board synchronous acquisition method as described in any of the foregoing embodiments.

[0055] This application provides a multi-board synchronous data acquisition method and system, including a PXIe chassis and at least two acquisition cards disposed within the PXIe chassis. One acquisition card is selected as the master acquisition card to generate an acquisition enable signal. The remaining acquisition cards are selected as sub-acquisition cards, and the acquisition enable signal is distributed to the remaining sub-acquisition cards to synchronously acquire at least two preset calibration signals to obtain first and second sampled data. The first and second sampled data are processed to obtain a variable delay parameter between each sub-acquisition card and the master acquisition card. Synchronous acquisition between multiple sub-acquisition cards within each acquisition card and the master acquisition card is performed based on the variable delay parameter. This invention can flexibly configure different models of acquisition cards with different sampling rates and select one of them as the master or sub-acquisition card for synchronous acquisition of multiple acquisition cards, featuring versatility and high precision. Attached Figure Description

[0056] Figure 1 This is a schematic diagram of the structure of a multi-board synchronous acquisition system according to an embodiment of the present invention;

[0057] Figure 2 This is a flowchart illustrating a multi-board synchronous acquisition method according to an embodiment of the present invention;

[0058] Figure 3 This is a schematic diagram of the structure of a multi-board synchronous acquisition system according to another embodiment of the present invention;

[0059] Figure 4 This is a flowchart illustrating another embodiment of the multi-board synchronous acquisition method provided by the present invention;

[0060] Figure 5 This is a flowchart illustrating another embodiment of the multi-board synchronous acquisition method provided by the present invention;

[0061] Figure 6 This is a flowchart illustrating another embodiment of the multi-board synchronous acquisition method provided by the present invention;

[0062] Figure 7This is a flowchart illustrating another embodiment of the multi-board synchronous acquisition method provided by the present invention;

[0063] Figure 8 This is a flowchart illustrating another embodiment of the multi-board synchronous acquisition method provided by the present invention;

[0064] Figure 9 This is a schematic diagram of the structure of a multi-board synchronous acquisition system according to another embodiment of the present invention;

[0065] Figure 10 This is a schematic diagram of the structure of a multi-board synchronous acquisition system according to another embodiment of the present invention;

[0066] Figure 11 This is a schematic diagram of the structure of a multi-board synchronous acquisition system according to another embodiment of the present invention;

[0067] Reference numerals in the attached figures: Multi-board synchronous acquisition system 100, PXIe chassis 110, acquisition card 120, analog-to-digital converter 121, second data processor 122, second trigger module 123, external trigger interface 124, control card 130, first data processor 131, PXIe trigger bus 140, clock card 150, clock source module 151, first trigger module 152, PXIe star trigger line 160. Detailed Implementation

[0068] To make the technical solution and beneficial effects of the present invention more apparent and understandable, a detailed description is provided below by listing specific embodiments. The accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application pertains.

[0069] This disclosure of embodiments is not exhaustive, but merely illustrative of some embodiments, and is not intended to limit the scope of protection of this disclosure. Unless contradictory, each step in a particular embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, a solution after removing some steps in a particular embodiment can also be implemented as an independent embodiment, and the order of the steps in a particular embodiment can be arbitrarily interchanged. Furthermore, the optional implementation methods in a particular embodiment can be arbitrarily combined; moreover, the embodiments can be arbitrarily combined, for example, some or all steps of different embodiments can be arbitrarily combined, and a particular embodiment can be arbitrarily combined with the optional implementation methods of other embodiments.

[0070] In each of the disclosed embodiments, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of the embodiments are consistent and can be referenced by each other. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0071] The terminology used in the embodiments of this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure.

[0072] Furthermore, each element, each row, or each column in the table of this disclosure can be implemented as an independent implementation, and any combination of any element, any row, or any column can also be implemented as an independent implementation.

[0073] In systems involving simultaneous sampling of multiple boards, the process is complex and calibration accuracy is limited. In applications requiring frequent system reconfiguration and board or cable replacements, achieving a fast, accurate, and automated simultaneous sampling solution for multiple boards has become a pressing technical challenge. Therefore, this application provides a method and system for simultaneous sampling of multiple boards.

[0074] Figure 1 This is a schematic diagram of the structure of a multi-board synchronous acquisition system according to an embodiment of the present invention.

[0075] Figure 2 This is a flowchart illustrating a multi-board synchronous acquisition method according to an embodiment of the present invention.

[0076] like Figure 1 and Figure 2 As shown, in a first aspect, this application provides a multi-board synchronous acquisition method for synchronously acquiring a measured signal in a multi-board synchronous acquisition system 100, including a PXIe chassis, at least two acquisition cards disposed within the PXIe chassis, and a clock card 150. The clock card 150 includes a clock source module 151 and a first trigger module 152. The multi-board synchronous acquisition method provided in this embodiment includes the following steps:

[0077] Step S210: Preset the first calibration signal;

[0078] Step S220: A second calibration signal is preset, and the frequencies of the second calibration signal and the first calibration signal are coprime;

[0079] Step S230: The clock source module 151 in the control clock card 150 simultaneously sends a clock signal to the acquisition card 120;

[0080] Step S240: Select one of the acquisition cards 120 as the main acquisition card, and select the remaining acquisition cards 120 as sub-acquisition cards;

[0081] In step S250, the first trigger module 152 in the control clock card 150 generates a trigger signal and sends the trigger signal to the main acquisition card. The main acquisition card responds to the trigger signal and generates an acquisition enable signal.

[0082] Step S260: Control the main acquisition card to distribute the acquisition enable signal to each sub-acquisition card;

[0083] In step S270, the main acquisition card responds to the trigger signal to acquire the first calibration signal, and each sub-acquisition card responds to the acquisition enable signal to acquire the first calibration signal, thereby obtaining the first phase delay data of each sub-acquisition card relative to the main acquisition card;

[0084] In step S280, the main acquisition card responds to the trigger signal to acquire the second calibration signal, and each sub-acquisition card responds to the acquisition enable signal to acquire the second calibration signal, thereby obtaining the second phase delay data of each sub-acquisition card relative to the main acquisition card;

[0085] Step S290: Perform defuzzification calculation on the first phase delay data and the second phase delay data to obtain the variable delay parameter between each sub-acquisition card and the main acquisition card;

[0086] Step S300: Configure each sub-acquisition card to synchronize with the main acquisition card according to the variable delay parameter.

[0087] This embodiment selects one of the multiple acquisition cards 120 as the main acquisition card and the remaining acquisition cards 120 as sub-acquisition cards. The first calibration signal and the second calibration signal are acquired synchronously in a time-division manner to obtain the phase delay data of each sub-acquisition card relative to the main acquisition card. By solving the phase delay data of each sub-acquisition card relative to the main acquisition card, the variable delay parameters of each sub-acquisition card relative to the main acquisition card are obtained. These variable delay parameters include one or more of clock allocation delay and link delay. This overcomes the slight time deviation caused by hardware physical differences, such as different cable lengths, differences in internal circuit wiring of the board, component delays, etc. Different models of acquisition cards 120 with the same sampling rate can be flexibly configured. Clock cards, analog front-end cards, etc. can also be flexibly matched according to the usage to form different test links. The variable delay parameters can be obtained by recalibrating with different parameter configurations. It has the characteristics of strong applicability and flexible configuration.

[0088] In this embodiment, a trigger signal is generated by the first trigger module 152 within the clock card 150 to improve the synchronization between the trigger signal and the clock signal, thereby improving the accuracy of system triggering.

[0089] In one possible implementation, the PXIe chassis 110 has 8, 12, or more slots for accommodating 2, 4, or more acquisition cards 120.

[0090] Figure 3 This is a schematic diagram of the structure of a multi-board synchronous acquisition system according to another embodiment of the present invention.

[0091] Figure 4 This is a flowchart illustrating another embodiment of the multi-board synchronous acquisition method provided by the present invention.

[0092] In some implementations, such as Figure 3 and Figure 4 As shown, the multi-board synchronous acquisition system includes a control card 130 housed in a PXIe chassis 110. The control card 130 contains a first data processor 131. Each acquisition card 120 includes an analog-to-digital converter 121 and a second data processor 122. Before acquiring the first phase delay data of each sub-acquisition card relative to the main acquisition card, step S270 further includes:

[0093] Step S2711: The analog-to-digital converter 121 in the main acquisition card acquires the first calibration signal to obtain the first sampled data;

[0094] In step S2712, the second data processor 122 in the main acquisition card performs a Hilbert transform on the first sampled data to generate a first complex signal;

[0095] In step S2713, the analog-to-digital converter 121 in each sub-acquisition card acquires the first calibration signal to obtain the second sampling data;

[0096] In step S2714, the second data processor 122 in each sub-acquisition card performs a Hilbert transform on the second sampled data to generate a second complex signal;

[0097] Step S2715: Control card 130 acquires the first complex signal in the main acquisition card and the second complex signal in each sub-acquisition card;

[0098] In step S2716, the first data processor 131 in the control card 130 performs conjugate multiplication of the second complex signal in each sub-acquisition card with the first complex signal in the main acquisition card to obtain the first phase delay data of each sub-acquisition card relative to the main acquisition card.

[0099] In this embodiment, in steps S2711 and S2713, the main acquisition card and each sub-acquisition card perform calibration on the first calibration signal. Data acquisition is performed, with the second data processor 122 within the main acquisition card and each sub-acquisition card processing the raw sampled data output by the analog-to-digital converter 121. Preliminary processing is performed. For example, the second data processor 122 can perform a digital quadrature downconversion, converting... The signal energy is concentrated near zero, and is then filtered and extracted to obtain the first sampled data from the main acquisition card. The second sampling data of the acquisition card Finally, the first sampled data Second sampling data Send to control card 130.

[0100] In this embodiment, in steps S2712 and S2714, the first data processor 131 processes the first sampled data from the main acquisition card. The second sampling data of the acquisition card Perform Hilbert transforms on the signals to construct the first and second complex signals, respectively. The specific formulas are as follows:

[0101] ;

[0102] in, For the constructed complex signal, The first sampled data Second sampling data The original real number signal, For the real number signal after Hilbert transform, It is the imaginary unit. amplitude The instantaneous envelope of the corresponding sampled data, and its phase The instantaneous phase of the corresponding sampled data.

[0103] Based on the above formula, the first complex signal of the main acquisition card is constructed as follows: The second complex signal for constructing the sub-acquisition card is The relationship between the first and second complex signals with respect to amplitude and phase information is constructed as follows:

[0104] ;

[0105] ;

[0106] in, Indicates the time of data collection The range, Represents an exponential function. The imaginary unit, , Indicates the time of data collection The phase.

[0107] In step S2716, the first complex signal Second complex signal The specific formula for conjugate multiplication is as follows:

[0108] ;

[0109] in, This indicates taking the conjugate.

[0110] Based on the above formula, we obtain:

[0111] ;

[0112] in, phase It is the instantaneous phase difference between two acquired data points. That is, the first phase delay parameter .

[0113] In some implementations, steps S2711 to S2716 are repeated to obtain the second phase delay parameter. .

[0114] In some implementations, steps S2711 to S2716 are repeated to obtain the third phase delay parameter. .

[0115] In this embodiment, the method based on Hilbert transform and conjugate multiplication has higher accuracy and stronger noise resistance compared to other phase detection methods, such as zero-crossing detection.

[0116] Figure 5 This is a flowchart illustrating another embodiment of the multi-board synchronous acquisition method provided by the present invention.

[0117] In some implementations, such as Figure 3 and Figure 5 As shown, the multi-board synchronous acquisition system includes a control card 130 housed in a PXIe chassis 110. The control card 130 contains a first data processor 131. Each acquisition card 120 includes an analog-to-digital converter 121 and a second data processor 122. Before acquiring the first phase delay data of each sub-acquisition card relative to the main acquisition card, step S270 further includes:

[0118] Step S2721: The analog-to-digital converter 121 in the main acquisition card acquires the first calibration signal to obtain the first sampled data;

[0119] Step S2722: The second data processor 122 in the main acquisition card performs a fast Fourier transform on the first sampled data to obtain the first spectrum;

[0120] In step S2723, the analog-to-digital converter 121 in each sub-acquisition card acquires the first calibration signal to obtain the second sampling data;

[0121] In step S2724, the second data processor 122 in each sub-acquisition card performs a fast Fourier transform on the second sampled data to obtain the second spectrum;

[0122] Step S2725: Control card 130 acquires the first spectrum in the main acquisition card and the second spectrum in each sub-acquisition card;

[0123] Step S2726: The control card 130 extracts the first phase angle information at the first frequency point index according to the first frequency point index of the first spectrum corresponding to the frequency of the first calibration signal.

[0124] In step S2727, the control card 130 extracts the second phase angle information at the second frequency point index according to the second frequency point index of the second spectrum corresponding to the frequency of the first calibration signal;

[0125] In step S2728, the first data processor 131 in the control card 130 calculates the difference between the second phase angle information of each sub-acquisition card and the first phase angle information of the main acquisition card to obtain the first phase delay data of each sub-acquisition card relative to the main acquisition card.

[0126] In this embodiment, from steps S2721 to S2725, the second data processor 122 in the main acquisition card performs a fast Fourier transform on the first sampled data to obtain the first spectrum, as shown in the following formula:

[0127] ;

[0128] in: For the sampled data sequence, =0,1,……,N-1, This represents the number of sampling points.

[0129] In steps S2326 and S2327, the frequency of the first calibration signal... The corresponding first frequency index is given by the following formula:

[0130] ;

[0131] ;

[0132] in, The frequency index corresponding to the calibration frequency, The first calibration signal frequency, Sampling frequency, Indicates rounding down. It is the inverse tangent function in the four quadrants. For the first The first frequency point index Phase angle information.

[0133] In step S2728, the first data processor 131 within the control card 130 calculates the difference between the second phase angle information of each sub-acquisition card and the first phase angle information of the main acquisition card, using the following formula:

[0134] ;

[0135] in, This is the first phase angle information. This is the second phase angle information.

[0136] In this embodiment, the phase of a specific frequency is accurately extracted in the frequency domain by using Fast Fourier Transform, which effectively suppresses noise and harmonic interference.

[0137] Figure 6 This is a flowchart illustrating another embodiment of the multi-board synchronous acquisition method provided by the present invention.

[0138] In some implementations, step S290 involves defuzzifying the first phase delay data and the second phase delay data to obtain the variable delay parameter between each sub-acquisition card and the main acquisition card, including:

[0139] Step S291: Preset the maximum expected time delay parameter in the first data processing module;

[0140] Step S292: Establish a system of linear equations containing a variable delay parameter, a first fuzzy number, and a second fuzzy number, wherein the first fuzzy number and the second fuzzy number constitute an integer pair of fuzzy numbers;

[0141] Step S293: Determine the integer search range of the first fuzzy number and the second fuzzy number based on the preset maximum expected time delay parameter;

[0142] Step S294: Within the range of integer search, traverse all possible pairs of fuzzy integers;

[0143] Step S295: For each pair of fuzzy integers, calculate the estimated values ​​of two delay parameters based on the linear equations of the first and second fuzzy numbers.

[0144] Step S296: Determine the residuals of the two delay parameter estimates;

[0145] Step S297: Select the pair of fuzzy integers that minimizes the residual between the estimated values ​​of the two delay parameters, and determine the first target fuzzy number and the second target fuzzy number;

[0146] Step S298: Substitute the first target fuzzy number and the second target fuzzy number into a system of linear equations containing the delay parameter, the first fuzzy number, and the second fuzzy number, and solve to obtain the variable delay parameter.

[0147] In this embodiment, step S292 involves using the first phase delay data. Second phase delay data Construct a system of linear equations concerning the variable delay parameter and the first and second fuzzy numbers:

[0148] ;

[0149] = ;

[0150] = ;

[0151] in and The first calibration signal is respectively Second calibration signal The number of fuzzy periods, This is a variable delay parameter.

[0152] In steps S293 to S298, the maximum expected time delay parameter of the hardware design is used. Sure Within a reasonable physical range. By The expected range and equations (2-1) and (2-2) are derived. and Possible value range and Within this expected range, iterate through all possible pairs of integers. Specifically, construct fuzzy integer pairs:

[0153] based on : 0.5ns, 10.5ns, 20.5ns, ...

[0154] based on :10.05ns,20.15ns,30.25ns,……

[0155] The first data processing module calculates and selects the fuzzy integer pair that minimizes the residuals of the estimated values ​​of the two variable delay parameters, namely 10.5ns and 10.05ns. At this point, the main acquisition card is used as the reference. =1, thus obtaining the variable delay parameter. It is 10.5ns.

[0156] Figure 7 This is a flowchart illustrating another embodiment of the multi-board synchronous acquisition method provided by the present invention.

[0157] In some implementations, such as Figure 7As shown, in step S310, a third calibration signal is preset that is frequency-coprime with both the first and second calibration signals.

[0158] In step S320, the main acquisition card responds to the trigger signal to acquire the third calibration signal, and each sub-acquisition card responds to the acquisition enable signal to synchronously acquire the third calibration signal, so as to obtain the third phase delay data of each sub-acquisition card relative to the main acquisition card.

[0159] Step S330: Perform defuzzification calculation on the first phase delay data, the second phase delay data, and the third phase delay data to obtain the variable delay parameter between each sub-acquisition card and the main acquisition card;

[0160] The third calibration signal is coprime with the first and second calibration signals in terms of frequency.

[0161] In this embodiment, the main acquisition card and each sub-acquisition card respond to the trigger signal to the third calibration signal. Perform synchronous acquisition and obtain the third phase delay parameter. And combined with the first phase delay parameter Second phase delay parameter Construct a system of linear equations containing three equations:

[0162] = ;

[0163] Based on the maximum expected time delay parameters of the hardware design Sure Within a reasonable physical range. By The expected range and equation (2-4) are derived. , and Possible value range , and Within this expected range, iterate through all possible pairs of integers. The first data processing module calculates and selects the fuzzy integer pair that minimizes the residuals of the estimated values ​​of the three variable delay parameters, and substitutes it into one of the equations to obtain the variable delay parameters. .

[0164] In this embodiment, two calibration signals are sufficient for deblurring, but in some scenarios with low signal-to-noise ratios or extremely high reliability requirements, three or more calibration signals can be used to enhance the robustness of deblurring.

[0165] Figure 8 This is a flowchart illustrating another embodiment of the multi-board synchronous acquisition method provided by the present invention.

[0166] In some implementations, such as Figure 8 As shown, in step S300, before configuring the synchronization of each sub-acquisition card with the main acquisition card according to the variable delay parameter, the following steps are included:

[0167] Step S301: Obtain the sampling period of the main acquisition card and each sub-acquisition card. The sampling period of the main acquisition card and each sub-acquisition card is the same.

[0168] Step S302: Divide the variable delay parameter by the sampling period to obtain the sample delay of each sub-acquisition card relative to the main acquisition card;

[0169] Step S303: Extract the second sampling data points of each sub-acquisition card according to the sampling point delay, so that each sub-acquisition card can acquire data synchronously with the main acquisition card.

[0170] In this embodiment, in steps S301 and S302, the control card 130 acquires the sampling period of the main acquisition card and each sub-acquisition card, and obtains the sample delay based on the variable delay parameter of each sub-acquisition card relative to the main acquisition card, as shown in the following formula:

[0171] ;

[0172] ;

[0173] Specifically, in step S303, the data collected by each sub-acquisition card... Before discarding or filling Several sampling points are used to achieve data acquisition with the main acquisition card. Alignment.

[0174] In one possible implementation, digital interpolation is used to smooth the sample alignment portion, including but not limited to linear interpolation, multiple spline interpolation, or Sinc interpolation.

[0175] Figure 9 This is a schematic diagram of the structure of a multi-board synchronous acquisition system according to another embodiment of the present invention.

[0176] In some implementations, such as Figure 9 As shown, the acquisition card 120 includes a second trigger module 123. The second trigger module 123 presets trigger conditions. When the preset trigger conditions are triggered, the main acquisition card acquires the signal under test.

[0177] In this embodiment, by integrating the second trigger module 123 into the acquisition card 120 and specifying the main acquisition card to generate the trigger signal, the external trigger device is eliminated. Compared with the uncertain delay caused by software instruction triggering, the hardware trigger signal generated by the main acquisition card has extremely low jitter and a definite timing relationship. It is distributed to each sub-acquisition card as a unified trigger reference, thereby ensuring the synchronous start-up of the multi-channel acquisition device on the nanosecond time scale.

[0178] Figure 10 This is a schematic diagram of the structure of a multi-board synchronous acquisition system according to another embodiment of the present invention.

[0179] In some implementations, such as Figure 10 As shown, the acquisition card 120 includes an external trigger interface 124, which controls the external trigger interface 124 of the main acquisition card to receive trigger signals.

[0180] And / or, control the external trigger interface 124 of the sub-acquisition card to receive the acquisition enable signal generated by the main acquisition card.

[0181] This implementation enhances the system's compatibility and scalability by configuring an external trigger interface 124; the main acquisition card's ability to receive external trigger signals enables the test system to accurately respond to changes in the status of the external device under test or synchronization commands from other instruments, achieving system-level collaborative work with the external environment and improving the system's flexibility and adaptability in complex test scenarios.

[0182] Figure 11 This is a schematic diagram of the structure of a multi-board synchronous acquisition system according to another embodiment of the present invention.

[0183] In some implementations, such as Figure 11 As shown, it also includes a PXIe trigger bus 140 and a PXIe star trigger line 160, which injects the trigger signal generated by the first trigger module 152 in the clock card 150 into the PXIe trigger bus 140, and the PXIe trigger bus 140 routes the trigger signal to the main acquisition card.

[0184] The acquisition enable signal generated by the main acquisition card is injected into the PXIe star trigger line 160, and the PXIe star trigger line 160 routes the acquisition enable signal to each sub-acquisition card.

[0185] In this embodiment, a PXIe star trigger line 160 is used to ensure that the connection link length between each sub-acquisition card and the main acquisition card is the same, so as to ensure that the link delay is close or equal and the link delay is fixed. Therefore, the trigger delay of the main acquisition card mainly depends on the link length of the PXIe trigger bus.

[0186] Secondly, this application provides a multi-board synchronous acquisition system 100 for synchronously acquiring the signal under test, including a PXIe chassis 110 and at least two acquisition cards 120 disposed within the PXIe chassis 110. Each acquisition card 120 includes a second trigger module 123 and / or an external trigger interface 124. The multi-board synchronous acquisition system also includes a control card 130 disposed within the PXIe chassis 110, which contains a first data processor 131. Each acquisition card 120 includes an analog-to-digital converter 121 and a second data processor 122. When executing programs or instructions, the multi-board synchronous acquisition system 100 implements the multi-board synchronous acquisition method as described in any of the foregoing embodiments.

[0187] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein.

[0188] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A multi-board synchronous data acquisition method, characterized in that, A method for synchronously acquiring a measured signal using a multi-board synchronous acquisition system, the multi-board synchronous acquisition system comprising a PXIe chassis, at least two acquisition cards disposed within the PXIe chassis, and a clock card, the clock card comprising a clock source module and a first trigger module, the method comprising: Preset the first calibration signal; A second calibration signal is preset, and the second calibration signal and the first calibration signal have coprime frequencies. The clock source module in the clock card is controlled to simultaneously send clock signals to the acquisition card; Select one of the acquisition cards as the main acquisition card, and select the remaining acquisition cards as sub-acquisition cards; The first trigger module in the clock card generates a trigger signal and sends the trigger signal to the main acquisition card. The main acquisition card responds to the trigger signal by generating an acquisition enable signal. The main acquisition card is controlled to distribute the acquisition enable signal to each of the sub-acquisition cards; The main acquisition card responds to the trigger signal to acquire the first calibration signal, and each of the sub-acquisition cards responds to the acquisition enable signal to acquire the first calibration signal, thereby obtaining the first phase delay data of each sub-acquisition card relative to the main acquisition card; The main acquisition card responds to the trigger signal to acquire the second calibration signal, and each of the sub-acquisition cards responds to the acquisition enable signal to acquire the second calibration signal, thereby obtaining the second phase delay data of each sub-acquisition card relative to the main acquisition card; Defuzzing calculations are performed on the first phase delay data and the second phase delay data to obtain the variable delay parameter between each of the sub-acquisition cards and the main acquisition card; Based on the variable delay parameter, each of the sub-acquisition cards is configured to synchronize acquisition with the main acquisition card.

2. The multi-board synchronous acquisition method according to claim 1, characterized in that, Also includes: A third calibration signal is preset to be frequency-coprime with both the first and second calibration signals; The main acquisition card responds to the trigger signal to acquire the third calibration signal, and each of the sub-acquisition cards responds to the acquisition enable signal to synchronously acquire the third calibration signal, so as to obtain the third phase delay data of each sub-acquisition card relative to the main acquisition card; Defuzzing calculations are performed on the first phase delay data, the second phase delay data, and the third phase delay data to obtain the variable delay parameter between each sub-acquisition card and the main acquisition card.

3. The multi-board synchronous acquisition method according to claim 1 or 2, characterized in that, The multi-board synchronous acquisition system includes a control card housed within the PXIe chassis. The control card contains a first data processor. Each acquisition card includes an analog-to-digital converter and a second data processor. Before acquiring the first phase delay data of each sub-acquisition card relative to the main acquisition card, the method further includes: The analog-to-digital converter in the main acquisition card acquires the first calibration signal to obtain the first sampling data; The second data processor in the main acquisition card performs a Hilbert transform on the first sampled data to generate a first complex signal. The analog-to-digital converter in each of the sub-acquisition cards acquires the first calibration signal to obtain the second sampling data; The second data processor within each of the sub-acquisition cards performs a Hilbert transform on the second sampled data to generate a second complex signal; The control card acquires a first complex signal from the main acquisition card and a second complex signal from each of the sub-acquisition cards; The first data processor in the control card performs conjugate multiplication of the second complex signal in each of the sub-acquisition cards with the first complex signal in the main acquisition card to obtain the first phase delay data of each sub-acquisition card relative to the main acquisition card.

4. The multi-board synchronous acquisition method according to claim 1 or 2, characterized in that, The multi-board synchronous acquisition system includes a control card housed within the PXIe chassis. The control card contains a first data processor. Each acquisition card includes an analog-to-digital converter and a second data processor. Before acquiring the first phase delay data of each sub-acquisition card relative to the main acquisition card, the method further includes: The analog-to-digital converter in the main acquisition card acquires the first calibration signal to obtain the first sampling data; The second data processor in the main acquisition card performs a fast Fourier transform on the first sampled data to obtain the first spectrum; The analog-to-digital converter in each of the sub-acquisition cards acquires the first calibration signal to obtain the second sampling data; The second data processor within each of the sub-acquisition cards performs a fast Fourier transform on the second sampled data to obtain the second spectrum; The control card acquires the first spectrum in the main acquisition card and the second spectrum in each of the sub-acquisition cards; The control card extracts the first phase angle information at the first frequency point index according to the first frequency point index of the first spectrum corresponding to the frequency of the first calibration signal. The control card extracts the second phase angle information at the second frequency point index according to the second frequency point index of the second spectrum corresponding to the frequency of the first calibration signal; The first data processor within the control card calculates the difference between the second phase angle information of each sub-acquisition card and the first phase angle information of the main acquisition card to obtain the first phase delay data of each sub-acquisition card relative to the main acquisition card.

5. The multi-board synchronous acquisition method according to claim 3, characterized in that, Defuzzing calculations are performed on the first phase delay data and the second phase delay data to obtain the variable delay parameter between each of the sub-acquisition cards and the main acquisition card, including: The first data processing module presets a maximum expected time delay parameter; Establish a system of linear equations that includes the variable delay parameter, the first fuzzy number, and the second fuzzy number, wherein the first fuzzy number and the second fuzzy number constitute an integer pair of fuzzy numbers; The integer search range of the first fuzzy number and the second fuzzy number is determined based on the preset maximum expected time delay parameter; Within the integer search range, traverse all pairs of fuzzy integers; For each pair of fuzzy integers, two estimated values ​​of delay parameters are calculated based on the linear equations of the first fuzzy number and the second fuzzy number. And determine the residual between the two estimated values ​​of the delay parameter; Select the pair of fuzzy integers that minimizes the residual between the estimated values ​​of the two delay parameters to determine the first target fuzzy number and the second target fuzzy number; and Substitute the first target fuzzy number and the second target fuzzy number into a system of linear equations containing the delay parameter, the first fuzzy number, and the second fuzzy number, and solve to obtain the variable delay parameter.

6. The multi-board synchronous acquisition method according to claim 5, characterized in that, Before configuring each of the sub-acquisition cards to synchronize with the main acquisition card according to the variable delay parameter, the process includes: The sampling period of the main acquisition card and each of the sub-acquisition cards is obtained, wherein the sampling period of the main acquisition card and each of the sub-acquisition cards is the same; Divide the variable delay parameter by the sampling period to obtain the sample delay of each sub-acquisition card relative to the main acquisition card; The sampling points of the second sampling data of each of the sub-acquisition cards are extracted according to the sampling point delay, so that each of the sub-acquisition cards can be synchronously acquired with the main acquisition card.

7. The multi-board synchronous acquisition method according to claim 1, characterized in that, The acquisition card includes a second trigger module, which has preset trigger conditions. When the preset trigger conditions are triggered, the main acquisition card acquires the signal under test.

8. The multi-board synchronous acquisition method according to claim 7, characterized in that, The acquisition card includes an external trigger interface, which controls the external trigger interface of the main acquisition card to receive the trigger signal, and / or The external trigger interface of the sub-acquisition card receives the acquisition enable signal generated by the main acquisition card.

9. The multi-board synchronous acquisition method according to claim 8, characterized in that, It also includes a PXIe trigger bus and a PXIe star trigger line, which injects the trigger signal generated by the first trigger module in the clock card into the PXIe trigger bus, and the PXIe trigger bus routes the trigger signal to the main acquisition card; The acquisition enable signal generated by the main acquisition card is injected into the PXIe star trigger line, and the PXIe star trigger line routes the acquisition enable signal to each of the sub-acquisition cards.

10. A multi-board synchronous acquisition system, characterized in that, The system is used for synchronous acquisition of the measured signal, including a PXIe chassis, at least two acquisition cards, a clock card, a control card, a PXIe trigger bus, and a PXIe star trigger line; the clock card includes a clock source module and a first trigger module, and the acquisition card includes an analog-to-digital converter, a second data processor, a second trigger module, and / or an external trigger interface; the multi-board synchronous acquisition system implements the multi-board synchronous acquisition method as described in any one of claims 1-9 when executing programs or instructions.

Images