Method for realizing DSP (Digital Signal Processor) extended external CAN (Controller Area Network) communication by configuring MCBSP (Microprogrammed Control Block Server

Abstract

The invention relates to a method and a device for realizing DSP (Digital Signal Processor) extended external CAN (Controller Area Network) communication for an SPI (Serial Peripheral Interface) host through MCBSP configuration, electronic equipment and a storage medium. The method comprises the steps that a CanA module of a main DSP chip is connected with a Can module of an external device 1, and a CanB module of the main DSP chip is connected with a Can module of an external device 2; the CanA module of the slave DSP chip is connected with the Can module of the external equipment 3, and the CanB module is reserved; the main DSP chip and the slave DSP chip realize SPI (Serial Peripheral Interface) connection through the McBSP module; and the master DSP chip and the slave DSP chip send / receive data to / from the SPI based on a DMA channel, and make a judgment based on a preset judgment condition, so that the master DSP chip communicates with an external device 3 through the CanA module of the slave DSP chip. Under the condition that the SPI module of the main DSP is occupied, the McBSP module and the DMA module are effectively utilized to achieve the SPI function, the DMA module is combined, the hardware design is simple, multi-data and high-speed sending and receiving can be achieved, and stable data transmission can be kept.

Description

Technical Field

[0001] This disclosure relates to the field of intelligent power systems for new energy vehicles. Specifically, it relates to a method, apparatus, electronic device, and computer-readable storage medium for configuring an MCBSP as an SPI host to implement external CAN communication for DSP extension. Background Technology

[0002] The TMS320F28335 digital signal processor (DSP) only has two CAN channels, CanA and CanB. The project requires adding a third backup CAN channel to forward information from the main DSP to this third CAN channel. This necessitates adding an external 28335 chip (as a slave DSP). The main communication methods for information transmission between 28335 DSPs are LAN (CAN), Serial Communication (SCI), and High-Speed ​​Synchronous Serial Input / Output (SPI).

[0003] Option 1: Using CAN communication has the advantages of stable data communication and short software development and porting time. However, its disadvantages are quite obvious in this project. It requires connecting any one of the CAN channels of the two DSPs together to transmit data, resulting in only two CAN channels being available to the outside world, which is no different from the single-chip solution.

[0004] Option 2: Use SCI. By default, the maximum communication rate of SCI is only 1 / 4 of that of SPI. SCI is suitable for long-distance, low-speed communication with other devices.

[0005] Option 3: SPI is suitable for short-distance, high-speed communication on the board. Considering that the distance between the two chips on the board is relatively short and the amount of communication data is relatively large, SPI communication can be selected between the two 28335 chips. However, there is no technical solution in the existing technology to solve this problem.

[0006] Therefore, one or more methods are needed to solve the above problems.

[0007] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0008] The purpose of this disclosure is to provide a method, apparatus, electronic device, and computer-readable storage medium for configuring an MCBSP as an SPI host to implement external CAN communication for DSP extension, thereby overcoming at least to some extent one or more problems caused by the limitations and defects of related technologies.

[0009] According to one aspect of this disclosure, a method is provided for configuring an MCBSP as an SPI master to implement DSP extended external CAN communication, comprising:

[0010] The main DSP chip's CanA module is connected to the Can module of external device 1, and the CanB module is connected to the Can module of external device 2.

[0011] The DSP chip's CanA module is connected to the Can module of external device 3, and the CanB module is reserved.

[0012] The master DSP chip and the slave DSP chip are connected via an SPI interface through a McBSP module.

[0013] The master DSP chip and the slave DSP chip send / receive data to and from the SPI via the DMA channel, and make judgments based on preset conditions, so that the master DSP chip can communicate with the external device 3 through the CanA module of the slave DSP chip.

[0014] In one exemplary embodiment of this disclosure, the method further includes establishing an SPI connection between the master DSP chip and the slave DSP chip via a McBSP module:

[0015] The main DSP chip selects the McBSPB module from the McBSP module and configures the McBSPB module to SPI communication master mode.

[0016] The clock pin MCLKXB of the McBSPB module of the main DSP chip is connected to the clock pin SPICLK of the SPI module of the slave DSP chip.

[0017] The chip select signal pin MFSXB of the McBSPB module of the main DSP chip is connected to the chip select signal pin SPISTE of the SPI module of the slave DSP chip.

[0018] The data transmission pin MDXB of the McBSPB module of the main DSP chip is connected to the data reception pin SPISIMO of the SPI module of the DSP chip.

[0019] The data receive pin MDRB of the McBSPB module of the main DSP chip is connected to the data transmit pin SPISOMI of the SPI module of the DSP chip.

[0020] In one exemplary embodiment of this disclosure, the method further includes:

[0021] The main DSP chip transmits data to external device 1 and external device 2 through its own CanA and CanB modules, respectively.

[0022] The master DSP chip transmits data to the slave DSP chip via SPI, and the slave DSP chip sends the received master DSP data to the external device 3 through its own CanA module.

[0023] External device 3 sends data to the slave DSP chip via its own CAN bus, and the slave DSP chip transmits the received data from external device 3 to the master DSP chip via SPI.

[0024] In one exemplary embodiment of this disclosure, the main DSP chip data transmission and reception control flow in the method further includes:

[0025] Configure the McBSPB module's GPIO ports as clock, chip select, data output, and data input functions for the SPI functionality.

[0026] McBSPB module register configuration;

[0027] DMA module configuration;

[0028] Main DSP chip DMA channel 1 configuration;

[0029] Main DSP chip DMA channel 2 configuration;

[0030] Based on the preset data format, the data format between the master DSP chip and the slave DSP chip is defined;

[0031] Initiate DMA for data transfer;

[0032] SPI communication for bidirectional data transmission;

[0033] After receiving the SPI data from the slave DSP chip, the master DSP chip parses the data and makes a judgment based on preset judgment conditions;

[0034] The data that meets the preset judgment conditions will be saved;

[0035] Data that fails to meet the preset judgment conditions will be removed.

[0036] In one exemplary embodiment of this disclosure, the preset data format in the method further includes:

[0037] Select a preset identifier and place it in bits 12-15 of each SPI transmission data pin;

[0038] Number the data with serial numbers 0-7, and the serial number positions are bit8-bit11;

[0039] Load the data into bits 0-7 of each frame of SPI data;

[0040] Place the 8 data pins to be sent sequentially into the transmit array configured for DMA channel 1.

[0041] In one exemplary embodiment of this disclosure, the preset judgment condition of the method further includes:

[0042] The first preset judgment condition is a data identifier based on a preset data format;

[0043] The second preset judgment condition is the data sequence number based on a preset data format.

[0044] In one exemplary embodiment of this disclosure, the method further includes a data transmission and reception control flow from the DSP chip:

[0045] Configure the SPI module's GPIO ports as corresponding clock input, chip select input, data output, and data input functions;

[0046] SPI module register configuration;

[0047] External device 3 sends a CAN data pin to the DSP chip every 20ms. After receiving the data, the DSP chip saves it and prepares to forward it to the main DSP chip.

[0048] Based on the preset data format, the data format between the master DSP chip and the slave DSP chip is defined;

[0049] When the SPICLK pin receives a clock signal, the data buffered in the serial transmit buffer register SPITXBUF is automatically sent out from the SPISOMI pin.

[0050] When the SPICLK pin receives a clock signal, the data buffered in the serial receive buffer register SPIRXBUF is automatically read from the SPISIMO pin.

[0051] After receiving data from the main DSP chip, the data is placed in the receiving array, ready for parsing and judgment based on preset judgment conditions;

[0052] The data that passes the preset judgment conditions is converted into CAN communication format data;

[0053] Remove data that fails to meet the preset judgment conditions;

[0054] If there is a data error, reinitialize the SPI register and wait for the next clock cycle signal;

[0055] After receiving SPI data from the main DSP chip, the DSP chip converts it into CAN data pins, and then sends the data to the external device from the CAN module of the DSP chip.

[0056] In one aspect of this disclosure, an apparatus is provided for configuring an MCBSP as an SPI master to implement DSP extended external CAN communication, comprising:

[0057] The main DSP chip connection module is used to connect the CanA module of the main DSP chip to the Can module of external device 1, and the CanB module to the Can module of external device 2.

[0058] The DSP chip connection module is used to connect the CanA module of the DSP chip to the Can module of external device 3, and the CanB module is reserved.

[0059] Master / Slave DSP Chip Connection Module, used to enable SPI connection between master and slave DSP chips via McBSP module;

[0060] The master / slave DSP chip communication module is used for the master DSP chip and the slave DSP chip to send / receive data to and from SPI via the DMA channel, and to make judgments based on preset judgment conditions, so that the master DSP chip can communicate with the external device 3 through the slave DSP chip's CanA module.

[0061] In one aspect of this disclosure, an electronic device is provided, comprising:

[0062] Processor; and

[0063] A memory storing computer-readable instructions that, when executed by the processor, implement the method according to any one of the preceding claims.

[0064] In one aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the method according to any one of the preceding claims.

[0065] An exemplary embodiment of this disclosure provides a method for configuring an MCBSP as an SPI master to implement external CAN communication for DSP extension. The method includes: connecting the CanA module of the master DSP chip to the CAN module of external device 1, and connecting the CanB module to the CAN module of external device 2; connecting the CanA module of the slave DSP chip to the CAN module of external device 3, with the CanB module reserved; establishing an SPI connection between the master and slave DSP chips via the McBSP module; sending / receiving data to and from the SPI via a DMA channel, and making judgments based on preset conditions to enable communication between the master DSP chip and external device 3 via the CanA module of the slave DSP chip. This disclosure effectively utilizes the McBSP and DMA modules to implement SPI functionality when the master DSP's SPI module is occupied. Combined with the DMA module, the hardware design is simple, enabling high-speed transmission and reception of multiple data streams while maintaining stable data transmission.

[0066] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0067] The above and other features and advantages of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0068] Figure 1 A flowchart is shown illustrating a method for configuring an MCBSP as an SPI host to implement DSP extended external CAN communication according to an exemplary embodiment of the present disclosure;

[0069] Figure 2 A topology diagram between two DSPs is shown, illustrating a method for configuring an MCBSP as an SPI host to implement DSP extended external CAN communication according to an exemplary embodiment of this disclosure.

[0070] Figures 3A-3B A flowchart illustrating the master / slave DSP data transmission and reception control process for a method of configuring an MCBSP as an SPI master to implement DSP extended external CAN communication according to an exemplary embodiment of the present disclosure is shown.

[0071] Figure 4 A schematic block diagram of an apparatus for configuring an MCBSP as an SPI host to implement DSP extended external CAN communication is shown according to an exemplary embodiment of the present disclosure;

[0072] Figure 5 A block diagram of an electronic device according to an exemplary embodiment of the present disclosure is shown schematically;

[0073] Figure 6 The illustration shows a schematic diagram of a computer-readable storage medium according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0074] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0075] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details described, or other methods, components, materials, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, materials, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0076] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, or in one or more software-hardened modules, or in different network and / or processor devices and / or microcontroller devices.

[0077] In this example embodiment, a method for configuring an MCBSP as an SPI master to implement DSP extended external CAN communication is first provided; see reference. Figure 1 As shown, a method for configuring an MCBSP as an SPI master to implement DSP extended external CAN communication may include the following steps:

[0078] Step S110: The CanA module of the main DSP chip is connected to the Can module of external device 1, and the CanB module is connected to the Can module of external device 2.

[0079] Step S120: Connect the CanA module of the DSP chip to the Can module of the external device 3, and reserve the CanB module;

[0080] In step S130, the master DSP chip and the slave DSP chip are connected via SPI through the McBSP module;

[0081] In step S140, the master DSP chip and the slave DSP chip send / receive data to and from the SPI via the DMA channel, and make judgments based on preset judgment conditions, so that the master DSP chip can communicate with the external device 3 through the CanA module of the slave DSP chip.

[0082] An exemplary embodiment of this disclosure provides a method for configuring an MCBSP as an SPI master to implement external CAN communication for DSP extension. The method includes: connecting the CanA module of the master DSP chip to the CAN module of external device 1, and connecting the CanB module to the CAN module of external device 2; connecting the CanA module of the slave DSP chip to the CAN module of external device 3, with the CanB module reserved; establishing an SPI connection between the master and slave DSP chips via the McBSP module; sending / receiving data to and from the SPI via a DMA channel, and making judgments based on preset conditions to enable communication between the master DSP chip and external device 3 via the CanA module of the slave DSP chip. This disclosure effectively utilizes the McBSP and DMA modules to implement SPI functionality when the master DSP's SPI module is occupied. Combined with the DMA module, the hardware design is simple, enabling high-speed transmission and reception of multiple data streams while maintaining stable data transmission.

[0083] The following will further explain a method for configuring an MCBSP as an SPI host to implement external CAN communication for DSP extension in this example embodiment.

[0084] Example 1:

[0085] In step S110, the CanA module of the main DSP chip can be connected to the Can module of external device 1, and the CanB module can be connected to the Can module of external device 2.

[0086] In this example embodiment, the method further includes establishing an SPI connection between the master DSP chip and the slave DSP chip via the McBSP module:

[0087] The main DSP chip selects the McBSPB module from the McBSP module and configures the McBSPB module to SPI communication master mode.

[0088] The clock pin MCLKXB of the McBSPB module of the main DSP chip is connected to the clock pin SPICLK of the SPI module of the slave DSP chip.

[0089] The chip select signal pin MFSXB of the McBSPB module of the main DSP chip is connected to the chip select signal pin SPISTE of the SPI module of the slave DSP chip.

[0090] The data transmission pin MDXB of the McBSPB module of the main DSP chip is connected to the data reception pin SPISIMO of the SPI module of the DSP chip.

[0091] The data receive pin MDRB of the McBSPB module of the main DSP chip is connected to the data transmit pin SPISOMI of the SPI module of the DSP chip.

[0092] In step S120, the CanA module of the DSP chip is connected to the Can module of the external device 3, and the CanB module is reserved.

[0093] In this example embodiment, the method further includes:

[0094] The main DSP chip transmits data to external device 1 and external device 2 through its own CanA and CanB modules, respectively.

[0095] The master DSP chip transmits data to the slave DSP chip via SPI, and the slave DSP chip sends the received master DSP data to the external device 3 through its own CanA module.

[0096] External device 3 sends data to the slave DSP chip via its own CAN bus, and the slave DSP chip transmits the received data from external device 3 to the master DSP chip via SPI.

[0097] In step S130, the master DSP chip and the slave DSP chip are connected via SPI through the McBSP module.

[0098] In this example embodiment, the main DSP chip data transmission and reception control process in the method further includes:

[0099] Configure the McBSPB module's GPIO ports as clock, chip select, data output, and data input functions for the SPI functionality.

[0100] McBSPB module register configuration;

[0101] DMA module configuration;

[0102] Main DSP chip DMA channel 1 configuration;

[0103] Main DSP chip DMA channel 2 configuration;

[0104] Based on the preset data format, the data format between the master DSP chip and the slave DSP chip is defined;

[0105] Initiate DMA for data transfer;

[0106] SPI communication for bidirectional data transmission;

[0107] After receiving the SPI data from the slave DSP chip, the master DSP chip parses the data and makes a judgment based on preset judgment conditions;

[0108] The data that meets the preset judgment conditions will be saved;

[0109] Data that fails to meet the preset judgment conditions will be removed.

[0110] In this example embodiment, the preset data format in the method further includes:

[0111] Select a preset identifier and place it in bits 12-15 of each SPI transmission data pin;

[0112] Number the data with serial numbers 0-7, and the serial number positions are bit8-bit11;

[0113] Load the data into bits 0-7 of each frame of SPI data;

[0114] Place the 8 data pins to be sent sequentially into the transmit array configured for DMA channel 1.

[0115] In this example embodiment, the preset judgment condition of the method further includes:

[0116] The first preset judgment condition is a data identifier based on a preset data format;

[0117] The second preset judgment condition is the data sequence number based on a preset data format.

[0118] In step S140, the master DSP chip and the slave DSP chip send / receive data to and from the SPI via the DMA channel, and make judgments based on preset judgment conditions, so that the master DSP chip can communicate with the external device 3 through the CanA module of the slave DSP chip.

[0119] In this example embodiment, the method further includes the data transmission and reception control flow from the DSP chip:

[0120] Configure the SPI module's GPIO ports as corresponding clock input, chip select input, data output, and data input functions;

[0121] SPI module register configuration;

[0122] External device 3 sends a CAN data pin to the DSP chip every 20ms. After receiving the data, the DSP chip saves it and prepares to forward it to the main DSP chip.

[0123] Based on the preset data format, the data format between the master DSP chip and the slave DSP chip is defined;

[0124] When the SPICLK pin receives a clock signal, the data buffered in the serial transmit buffer register SPITXBUF is automatically sent out from the SPISOMI pin.

[0125] When the SPICLK pin receives a clock signal, the data buffered in the serial receive buffer register SPIRXBUF is automatically read from the SPISIMO pin.

[0126] After receiving data from the main DSP chip, the data is placed in the receiving array, ready for parsing and judgment based on preset judgment conditions;

[0127] The data that passes the preset judgment conditions is converted into CAN communication format data;

[0128] Remove data that fails to meet the preset judgment conditions;

[0129] If there is a data error, reinitialize the SPI register and wait for the next clock cycle signal;

[0130] After receiving SPI data from the main DSP chip, the DSP chip converts it into CAN data pins, and then sends the data to the external device from the CAN module of the DSP chip.

[0131] In this example embodiment, the 28335 chip has only one SPI module. Since the SPI communication module in the master DSP is already occupied, there is no spare SPI communication module for data transmission with the slave DSP's SPI module. Therefore, it is necessary to develop a module from the existing modules of the 28335 chip that can function as an SPI communication module. The 28335 chip's Multi-Channel Buffered Serial Port (McBSP) module features full-duplex communication, double-buffered data registers allowing continuous data flow, independent framing and clocking for receiving and transmitting, a wide data size selection including 8, 12, 16, 20, 24, or 32 bits, and compatibility with SPI-compatible devices. It can be configured in SPI mode to exchange data with the slave device.

[0132] When McBSP is used for SPI data transmission, its disadvantages are also quite obvious. It does not have internal receive and transmit buffer registers, and can only send and receive a maximum of 32 bits of data at a time. When the data is large, the transmission time is long and the efficiency is low.

[0133] Considering the large amount of data to be transferred, the McBSP module and the Direct Memory Access (DMA) module are used together to improve efficiency. DMA can be used to achieve high-efficiency data transfer between peripherals and memory or between memory devices, without the need for CPU intervention, reducing intermediate steps. Moreover, the modification and transfer of memory addresses are all completed automatically by hardware. In high-speed, large-data-volume scenarios, the DMA transfer method is obviously superior to the CPU interrupt handling method and is more efficient.

[0134] Example 2:

[0135] like Figure 2 As shown in the embodiment of this example:

[0136] 1. The master DSP's CanA module is connected to the Can module of external device 1, and its CanB module is connected to the Can module of external device 2; the slave DSP's CanA module is connected to the Can module of external device 3, and its CanB module is reserved; the master and slave DSPs communicate with the outside world through their respective CAN modules.

[0137] 2. Data exchange between the master and slave DSPs is conducted via SPI. The 28335 chip has two McBSP modules, namely McBSPA and McBSPB. The two modules have the same function. In this invention, the McBSPB module is configured as the SPI communication master mode. The clock pin MCLKXB is connected to the clock SPICLK signal pin in the slave SPI module, the chip select signal pin MFSXB is connected to the chip select SPISTE signal pin in the slave SPI module, the data transmit pin MDXB is connected to the data receive SPISIMO pin in the slave SPI module, and the data receive pin MDRB is connected to the data transmit SPISOMI signal pin in the slave SPI module.

[0138] 3. The clock MCLKXB and chip select signal MFSXB are provided by the master DSP. The master DSP sends data to the slave DSP through the MDXB pin, and the slave DSP sends data to the master DSP through the SPISOMI pin, thereby exchanging data between the two DSPs.

[0139] 4. The overall solution is as follows: The main DSP transmits data to external devices 1 and 2 via its own CanA and CanB modules; the main DSP transmits data to the slave DSP via SPI, and the slave DSP transmits the received main DSP data to external device 3 via its own CanA module; at the same time, external device 3 sends data to the slave DSP via Can, and the slave DSP transmits the received external device 3 data to the main DSP via SPI.

[0140] 5. In this method, the DSP acts as an intermediate transmission, realizing data exchange between the main DSP and external devices 1, 2, and 3. This is equivalent to expanding the main DSP from two external CAN communication channels to four CAN communication channels (one of which is reserved).

[0141] In the embodiments of this example, as Figure 3A As shown, the main DSP data transmission and reception control flow is as follows:

[0142] Procedure 1: Configure the relevant GPIO ports of the McBSPB module according to the 28335 chip manual to perform the corresponding clock, chip select, data output, and data input functions for the SPI function.

[0143] Procedure 2: Main configuration functions of McBSPB module registers: receive frame synchronization mode, transmit frame synchronization mode, McBSPB as SPI master (internal transmit clock driven by SRG), internal receive clock driven by internal transmit clock, select LSPCLK clock source, frequency division is 4, transmit synchronization frame active low, data is transmitted on rising edge and received on falling edge, data length 16 bits.

[0144] Process 3: DMA module configuration. The 28335 chip DMA module has 6 channels. This patent only uses channel 1 for data transmission and channel 2 for data reception.

[0145] The main configurations for Channel 1 are as follows: setting the address corresponding to the McBSPB transmit register to the DMA Channel 1 target address, setting the array address of the data to be transmitted to the source address, setting the burst transfer length register value to 0, the source burst transfer step size register value to 1, the outer loop transfer length register value to 7, the source transfer step size register value to 1, the source / target return length register value to 8, selecting the McBSPB transmit source as the trigger source, enabling the channel interrupt bit, setting the channel interrupt mode selection bit to 1, and selecting the single trigger control bit to 1.

[0146] The main configurations for Channel 2 are as follows: setting the address corresponding to the McBSPB receive register to the source address of DMA Channel 2, setting the array address of the received data to the target address, setting the burst transfer length register value to 0, the source burst transfer step size register value to 0, the target burst transfer step size register value to 1, the outer loop transfer length register value to 7, the target transfer step size register value to 1, the source / target return length register value to 8, selecting the McBSPB receive source as the trigger source, enabling the channel interrupt bit, setting the channel interrupt mode selection bit to 1, and selecting the single trigger control bit to 1.

[0147] Step 4: Data transmission between the DSP and external device 3 is via CAN bus, and data transmission with the host DSP is via SPI. The data format between the master and slave DSPs needs to be agreed upon to better enable the host DSP to send CAN information to external device 3. The specific data parsing method for Step 4 is as follows:

[0148] Configure the SPI communication data format for each frame and the correspondence between the CAN communication identifier and the SPI identifier.

[0149] bit15-bit12 bit11-bit8 Bit7-bit0 Identifier Data sequence number Loading values

[0150] The SPI communication data format for each frame is as follows:

[0151] CAN identifier SPI identifier Send ID0X18F3019C A(1010b) Send ID0X18F3029C B(1011b) Send ID0X18F3039C C(1100b) Send ID0X18F3049C D(1101b) Receive ID0X0CFF9C21 7(0111b)

[0152] Assuming the master DSP needs to send a CAN data identifier (ID) 0X18F3019C with data 1122334455667788 to external device 3, the master DSP needs to send the data to the slave DSP via SPI, and the slave DSP then sends the data to external device 3 via the CAN module. The master DSP needs to first package the SPI data to be sent to the slave device, as follows:

[0153] 1. Select the appropriate identifier and place it in bits 12-15 of each pin of data transmitted by SPI. For example, select the identifier A (1010).

[0154] 2. Number the data from 0 to 7, with the number positions being bits 8 to 11.

[0155] 3. Load the data into bits 0-7. The sequence numbers of the 8 data sent above are derived from the corresponding CAN information forwarded. If the sequence numbers of byte 0-byte 7 of a frame of CAN data are 1122334455667788, then the data sequence number loaded in step 2 with sequence numbers 0-7 is 1122334455667788. Then put the corresponding data into bits 0-bit 7 of each frame of SPI data.

[0156] 4. After the above steps 1, 2, and 3, the format of the 8-pin SPI data sent by the master DSP to the slave DSP is 0xA011, 0xA122, 0xA233, 0xA344, 0xA455, 0xA566, 0xA677, and 0xA788.

[0157] 5. Place the 8 data pins to be sent into the transmit array configured in DMA channel 1 of process 3 in sequence.

[0158] Step 5: After the data is loaded in Step 4, start DMA to transfer the data.

[0159] Procedure 6: SPI communication is bidirectional; the master sends data to the slave while the slave sends data to the master.

[0160] Process 7: After the master DSP receives the SPI data from the slave DSP, it needs to parse each 16-bit data pin to extract the identifier (bit12-bit15), sequence number (bit8-bit11), and data (bit0-bit7) for condition judgment 1 and condition judgment 2.

[0161] Condition 1: The main DSP needs to process the received data and judge the received 8 consecutive pins of data (a group of data). It judges whether the identifier (bit12-bit15) of each pin of data in this group of data is the same. If they are the same, proceed to condition 2; otherwise, discard this group of data.

[0162] Example of condition judgment 1: If 8 consecutive pins (1 group) of 16-bit data are received, namely 0x7001, 0x7101, 0x7201, 0x7301, 0x7401, 0x7501, 0x7601, and 0x7701, and bit 12-bit 15 of the identifier of each frame are all 7, then proceed to condition judgment 2. If any group of identifiers is not 7, it will be discarded.

[0163] Condition 2: Determine the sequence number arrangement in this group of data. Are the sequence numbers of the first pin (bit8-bit11) to the 8th pin (bit8-bit11) arranged in order? If the sequence numbers are arranged in order from 0 to 7, then this group of data is received correctly; otherwise, this group of data is discarded.

[0164] Example of condition judgment 2: If you receive 8 consecutive pins (1 group) of 16-bit data, namely 0x7001, 0x7101, 0x7201, 0x7301, 0x7401, 0x7501, 0x7601, and 0x7701, the data is correct if the sequence number (bit 8-bit 11) of each pin in this group of data is 01234567, otherwise it is incorrect data.

[0165] Process 8: After condition 1 and condition 2 are passed, save each bit of data bit0-bit7 in sequence as valid data.

[0166] Process 9: Data that fails to meet judgment conditions 1 and 2 is removed.

[0167] In the embodiments of this example, as Figure 3B As shown, the data transmission and reception control flow from the DSP is as follows:

[0168] Procedure 1: Configure the relevant GPIO ports of the SPI module as clock input, chip select input, data output, and data input according to the 28335 chip manual.

[0169] Procedure 2: SPI module register main function configuration: data length 16 bits, SPI slave mode, shift clock polarity bit selection 1, SPI clock phase selection 1, enable transmit and receive FIFO register function.

[0170] Process 3: External device 3 sends a CAN data pin to the DSP every 20ms. After receiving the data, the DSP saves it and prepares to forward it to the main DSP.

[0171] Process 4: After the slave DSP receives the CAN information from external device 3, it transmits the data to the master DSP via SPI. The data format between the master and slave DSPs needs to be agreed upon in order to better enable the master DSP to receive information from external device 3.

[0172] For specific data settings in process 4, please refer to [link / reference]. Figure 3A The specific implementation method of process 4 is shown in the following simple example:

[0173] 1. Received one CAN data pin from external device 3 from the DSP. The ID is 0X0CFF9C21, and the data from byte 0 to byte 7 is 0001020304050607.

[0174] 2. The data format needs to be reset. The new data format is 0x7000, 0x7101, 0x7202, 0x7303, 0x7404, 0x7505, 0x7606, 0x7707.

[0175] 3. The data from these 8 pins is buffered in the transmit register, waiting for the signal to arrive before being transmitted.

[0176] Procedure 5: When the SPICLK pin receives a clock signal, the data buffered in SPITXBUF (serial transmit buffer register) is automatically sent out from the SPISOMI pin.

[0177] Procedure 6: When the SPICLK pin receives a clock signal, the data buffered in SPIRXBUF (serial receive buffer register) is automatically read from the SPISIMO pin.

[0178] Step 7: After receiving the main DSP data from the DSP, place it in the receive array, ready for data parsing and judgment.

[0179] Judgment condition 1: The main DSP needs to process the received data and judge the received 8 consecutive pins of data (a group of data). It judges whether the identifier (bit12-bit15) of each pin of data in this group of data is the same. If they are the same, proceed to condition 2; otherwise, discard this group of data.

[0180] Example of condition judgment 1: Receive 8 consecutive pins (1 group) of 16-bit data from the DSP, namely 0xB001, 0xB101, 0xB201, 0xB301, 0xB401, 0xB501, 0xB601, and 0xB701. Bits 12-15 of the identifier of each frame are all B. Proceed to condition judgment 2. If any group of identifiers is not B, it is discarded.

[0181] Condition 2: Determine the sequence number arrangement in this group of data. Are the sequence numbers of the first pin (bit8-bit11) to the 8th pin (bit8-bit11) arranged in order? If the sequence number arrangement is 0-7, then this group of data is received correctly; otherwise, discard this group of data.

[0182] Example of condition judgment 2: If you receive 8 consecutive pins (1 group) of 16-bit data, namely 0xB001, 0xB101, 0xB201, 0xB301, 0xB401, 0xB501, 0xB601, and 0xB701, the data is correct if the sequence number (bit 8-bit 11) of each pin in this group of data is 01234567, otherwise it is incorrect data.

[0183] Step 8: Data that passes both condition 1 and condition 2 is converted into CAN communication format data. The specific method is as follows:

[0184] For specific data format conversion details in step 8, please refer to [link / reference]. Figure 3B The specific implementation method of process 4 is shown in the following simple example:

[0185] 1. For example, the DSP receives a set of data 0xA011, 0xA122, 0xA233, 0xA344, 0xA455, 0xA566, 0xA677, 0xA788 sent by the main DSP via SPI.

[0186] 2. The data format needs to be reset to CAN communication data format ID: 0X18F3019C, with data Bytes 0-7 being 1122334455667788 respectively.

[0187] Process 9: Data that fails to meet judgment conditions 1 and 2 is removed.

[0188] Procedure 10: If there is a data error, reinitialize the SPI register and wait for the next clock cycle signal.

[0189] Process 11: After receiving the SPI data from the main DSP, the data is converted into CAN data and then sent to the external device 3 from the DSP's CAN module.

[0190] In this example embodiment, when the SPI module is occupied, the main DSP of the present invention effectively utilizes the McBSP module and the DMA module to implement the SPI function. Combined with the DMA module, the hardware design is simple, and it can realize multiple data, high-speed transmission and reception, and maintain stable data transmission.

[0191] It should be noted that although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0192] Furthermore, in this example embodiment, an apparatus is also provided for configuring an MCBSP as an SPI host to implement external CAN communication for DSP extension. (See also...) Figure 4 As shown, the device 200, configured as an SPI master to implement external CAN communication for DSP extension, may include: a master DSP chip connection module 210, a slave DSP chip connection module 220, a master / slave DSP chip connection module 230, and a master / slave DSP chip communication module 240. Wherein:

[0193] The main DSP chip connection module 210 is used to connect the CanA module of the main DSP chip to the Can module of external device 1, and the CanB module to the Can module of external device 2.

[0194] The DSP chip connection module 220 is used to connect the CanA module of the DSP chip to the Can module of the external device 3, and the CanB module is reserved.

[0195] Master / Slave DSP Chip Connection Module 230 is used to connect the master DSP chip and the slave DSP chip via the McBSP module through SPI.

[0196] The master / slave DSP chip communication module 240 is used for the master DSP chip and the slave DSP chip to send / receive data to and from SPI via the DMA channel, and to make judgments based on preset judgment conditions, so that the master DSP chip can communicate with the external device 3 through the CanA module of the slave DSP chip.

[0197] The specific details of the device modules for configuring an MCBSP as an SPI host to implement external CAN communication for DSP have been described in detail in the corresponding method for configuring an MCBSP as an SPI host to implement external CAN communication for DSP, so they will not be repeated here.

[0198] It should be noted that although several modules or units of an apparatus 200 configured as an SPI master to implement DSP extended external CAN communication are mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0199] Furthermore, in an exemplary embodiment of this disclosure, an electronic device capable of implementing the above-described method is also provided.

[0200] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented as entirely hardware embodiments, entirely software embodiments (including firmware, microcode, etc.), or embodiments combining hardware and software aspects, collectively referred to herein as “circuit,” “module,” or “system.”

[0201] The following reference Figure 5 To describe an electronic device 500 according to such an embodiment of the present invention. Figure 5 The electronic device 500 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0202] like Figure 5 As shown, the electronic device 500 is manifested in the form of a general-purpose computing device. The components of the electronic device 500 may include, but are not limited to: at least one processing unit 510, at least one storage unit 520, a bus 530 connecting different system components (including storage unit 520 and processing unit 510), and a display unit 540.

[0203] The storage unit stores program code that can be executed by the processing unit 510, causing the processing unit 510 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of the present invention. For example, the processing unit 510 can perform actions such as... Figure 1 Steps S110 to S140 are shown in the diagram.

[0204] Storage unit 520 may include a readable medium in the form of a volatile storage unit, such as random access memory (RAM) 5201 and / or cache memory 5202, and may further include a read-only memory (ROM) 5203.

[0205] Storage unit 520 may also include a program / utility 5204 having a set (at least one) program module 5205, such program module 5205 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0206] Bus 530 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0207] Electronic device 500 can also communicate with one or more external devices 570 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 500, and / or with any device that enables electronic device 500 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 550. Furthermore, electronic device 500 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 560. As shown, network adapter 560 communicates with other modules of electronic device 500 via bus 530. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 500, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0208] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0209] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the methods described above is stored. In some possible embodiments, various aspects of the invention may also be implemented as a program product comprising program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps of the various exemplary embodiments of the invention described in the "Exemplary Methods" section above.

[0210] refer to Figure 6 As shown, a program product 600 for implementing the above-described method according to an embodiment of the present invention is described. It may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, the readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0211] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0212] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0213] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0214] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0215] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0216] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0217] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A method for configuring an McBSP as an SPI master to implement external CAN communication for DSP expansion, characterized in that, The method includes: The main DSP chip's CanA module is connected to the Can module of external device 1, and the CanB module is connected to the Can module of external device 2. The DSP chip's CanA module is connected to the Can module of external device 3, and the CanB module is reserved. The master DSP chip and the slave DSP chip are connected via an SPI interface through a McBSP module. The master DSP chip and the slave DSP chip send / receive data to and from the SPI via the DMA channel, and make judgments based on preset conditions, so that the master DSP chip can communicate with the external device 3 through the CanA module of the slave DSP chip.

2. The method as described in claim 1, characterized in that, The method for establishing an SPI connection between the master DSP chip and the slave DSP chip via the McBSP module also includes: The main DSP chip selects the McBSPB module from the McBSP module and configures the McBSPB module to SPI communication master mode. The clock pin MCLKXB of the McBSPB module of the main DSP chip is connected to the clock pin SPICLK of the SPI module of the slave DSP chip. The chip select signal pin MFSXB of the McBSPB module of the main DSP chip is connected to the chip select signal pin SPISTE of the SPI module of the slave DSP chip. The data transmission pin MDXB of the McBSPB module of the main DSP chip is connected to the data reception pin SPISIMO of the SPI module of the DSP chip. The data receive pin MDRB of the McBSPB module of the main DSP chip is connected to the data transmit pin SPISOMI of the SPI module of the DSP chip.

3. The method as described in claim 1, characterized in that, The method further includes: The main DSP chip transmits data to external device 1 and external device 2 through its own CanA and CanB modules, respectively. The master DSP chip transmits data to the slave DSP chip via SPI, and the slave DSP chip sends the received master DSP data to the external device 3 through its own CanA module. External device 3 sends data to the slave DSP chip via its own CAN bus, and the slave DSP chip transmits the received data from external device 3 to the master DSP chip via SPI.

4. The method as described in claim 1, characterized in that, The main DSP chip data transmission and reception control process in the method also includes: Configure the McBSPB module's GPIO ports as clock, chip select, data output, and data input functions for the SPI functionality. McBSPB module register configuration; DMA module configuration; Main DSP chip DMA channel 1 configuration; Main DSP chip DMA channel 2 configuration; Based on the preset data format, the data format between the master DSP chip and the slave DSP chip is defined; Initiate DMA for data transfer; SPI communication allows for bidirectional data transmission. After receiving the SPI data from the slave DSP chip, the master DSP chip parses the data and makes a judgment based on preset judgment conditions; The data that meets the preset judgment conditions will be saved; Data that fails to meet the preset judgment conditions will be removed.

5. The method as described in claim 4, characterized in that, The preset data format in the method also includes: Select a preset identifier and place it in bits 12-15 of each SPI transmission data pin; Number the data with serial numbers 0-7, and the serial number positions are bit8-bit11; Load the data into bits 0-7 of each frame of SPI data; Place the 8 data pins to be sent sequentially into the transmit array configured for DMA channel 1.

6. The method as described in claim 5, characterized in that, The preset judgment conditions of the method also include: The first preset judgment condition is a data identifier based on a preset data format; The second preset judgment condition is the data sequence number based on a preset data format.

7. The method as described in claim 1, characterized in that, The method further includes the following data transmission and reception control process from the DSP chip: Configure the SPI module's GPIO ports as corresponding clock input, chip select input, data output, and data input functions; SPI module register configuration; External device 3 sends a CAN data pin to the DSP chip every 20ms. After receiving the data, the DSP chip saves it and prepares to forward it to the main DSP chip. Based on the preset data format, the data format between the master DSP chip and the slave DSP chip is defined; When the SPICLK pin receives a clock signal, the data buffered in the serial transmit buffer register SPITXBUF is automatically sent out from the SPISOMI pin. When the SPICLK pin receives a clock signal, the data buffered in the serial receive buffer register SPIRXBUF is automatically read from the SPISIMO pin. After receiving data from the main DSP chip, the data is placed in the receiving array, ready for parsing and judgment based on preset judgment conditions; The data that passes the preset judgment conditions is converted into CAN communication format data; Remove data that fails to meet the preset judgment conditions; If there is a data error, reinitialize the SPI register and wait for the next clock cycle signal; After receiving SPI data from the main DSP chip, the DSP chip converts it into CAN data pins, and then sends the data to the external device from the CAN module of the DSP chip.

8. A device for configuring an McBSP as an SPI host to implement external CAN communication for DSP expansion, characterized in that, The device includes: The main DSP chip connection module is used to connect the CanA module of the main DSP chip to the Can module of external device 1, and the CanB module to the Can module of external device 2. The DSP chip connection module is used to connect the CanA module of the DSP chip to the Can module of external device 3, and the CanB module is reserved. Master / Slave DSP Chip Connection Module, used to enable SPI connection between master and slave DSP chips via McBSP module; The master / slave DSP chip communication module is used for the master DSP chip and the slave DSP chip to send / receive data to and from SPI via the DMA channel, and to make judgments based on preset judgment conditions, so that the master DSP chip can communicate with the external device 3 through the slave DSP chip's CanA module.

9. An electronic device, characterized in that, include Processor; and A memory storing computer-readable instructions that, when executed by the processor, implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements the method according to any one of claims 1 to 7.

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