Seamless fault-tolerant control method for solid-state transformer based on cascaded H-bridge voltage level compensation

Abstract

The invention discloses a solid state transformer (SST) seamless fault-tolerant control method based on cascade H-bridge (CHB) voltage level compensation, and the method comprises the steps: after a fault unit module is bypassed, compensating the missing voltage level of the H bridge of the fault unit module through the H bridges of the remaining unit modules, and maintaining the total voltage of the AC sides of all unit modules of the SST unchanged. According to the invention, the problem of overlarge current impact of the alternating current inductor generated in the process of removing the fault unit module and inserting the redundant unit module in the cascade converter is solved. The method is easy to operate, voltage level compensation of the unit modules can be achieved only by modifying judgment conditions even if the unit modules break down, rapid and smooth switching of the unit modules can be achieved when the faults occur, the voltage and current waveform quality of the system can be maintained, and reliable and stable operation of the whole system is guaranteed.

Description

Technical Field

[0001] This invention belongs to the technical field of medium-voltage power electronic converters for power distribution, and relates to a solid-state transformer control method, particularly a seamless fault-tolerant control method for solid-state transformers based on cascaded H-bridge voltage level compensation. Background Technology

[0002] Solid-state transformers are core devices connecting medium-voltage and low-voltage power grids. Their upstream terminals are directly connected to the medium-voltage grid, converting medium-voltage AC to low-voltage DC power. Solid-state transformer systems integrate numerous power switching devices, which have a high failure rate under high-frequency switching stress, making their failure probability significantly higher than that of traditional power frequency transformers. If a fault occurs in one unit module and is not addressed promptly, the fault can easily spread to other units, causing the solid-state transformer to shut down. In severe cases, it can also affect the operation of the power grid and loads, threatening the safety of the entire medium-voltage power distribution system. Therefore, implementing effective fault-tolerant control for solid-state transformer unit module failures is crucial to ensuring the reliable and stable power supply of the power distribution system.

[0003] For cascaded systems like solid-state transformers, hardware redundancy is a commonly used fault-tolerance solution: when a fault occurs, redundant unit modules are connected to the system to replace the faulty unit modules and maintain the continuous operation of the system.

[0004] Based on whether the redundant unit modules are connected to the system and work together with other unit modules under normal operating conditions, the redundant unit scheme can be divided into two categories: hot standby scheme and cold standby scheme.

[0005] The cold standby scheme maintains the same number of unit modules before and after fault-tolerant control, and the power switching devices experience the same voltage stress without reducing the efficiency of the solid-state transformer. Therefore, theoretically, the cold standby scheme can fully restore normal operation after fault-tolerant switching. However, the disadvantages of the cold standby scheme are: the bus capacitor of the redundant unit module must be charged to the rated bus voltage to operate normally, resulting in a current surge during unit module switching; and during the time between the removal of the faulty unit module and the charging of the redundant unit module's bus capacitor to the rated voltage, the remaining unit modules need to share the original power of the faulty unit module; the charging time of the redundant unit module's bus capacitor is related to the capacitance value, and is usually larger to suppress the ripple of the H-bridge rectified output current, resulting in a longer charging time for the redundant unit module. IEEE Transactions on Power Electronics A fault-tolerant control method for modular multilevel converters is proposed in vol. 30, no. 8, pp. 4052–4057, Aug. 2015. This method can seamlessly bypass faulty modules and insert redundant modules, but it involves a relatively long charging time for the redundant modules. To achieve fast fault-tolerant control, the bus capacitors of the redundant modules can be pre-charged to maintain their rated voltage. When the faulty module is removed, the redundant module can be quickly inserted into the system. (This is from the paper "Improved fault-tolerant method and control strategy based on reverse charging for the power electronic traction transformer") IEEE Transactions on Industrial Electronics , vol. 65, no. 3, pp. 2672–2682, Mar.2018. and "A short-time transition and cost saving redundancy scheme formedium-voltage three-phase cascaded H-bridge electronic power transformer," IEEE Transactions on Power Electronics In , vol. 33, no. 11, pp. 9242–9252, Nov. 2018, the bus capacitor is reverse-charged by the dual active bridge converter after the redundant unit module to ensure fast and smooth fault-tolerant control. However, this method is not suitable for systems with unidirectional power transmission.

[0006] In a hot standby configuration, redundant unit modules operate alongside other unit modules during normal operation, making it less expensive than a cold standby configuration. However, in the event of a fault, the faulty unit module is bypassed, reducing the total number of unit modules. The remaining unit modules require an increase in the bus voltage to avoid overmodulation, which increases voltage stress on the power switching devices. Furthermore, the gain of the downstream isolated DC-DC converter will change, causing it to deviate from its rated operating point. For solid-state transformers with downstream isolated DC-DC converters (such as LLC converters), this hot standby configuration reduces system efficiency. (Efficiency enhancement of DC solid-state transformers by dynamically adjusting active cells) IEEE Transactions on Power Electronics, vol. 38, no.12, pp. 14942-14955, Dec. 2023. For DC solid-state transformer topologies, controlling the duty cycle to change slowly to smoothly bypass and insert unit modules can effectively reduce current overshoot. However, this method is suitable for active switching scenarios and not for fault-tolerant control scenarios. "Fault-tolerant design and control strategy for cascaded H-bridge multilevel converter-based STATCOM," IEEE Transactions on Industrial Electronics , vol. 57, no. 8, pp. 2700–2708, Aug. 2010. By boosting the modulation wave at the switching moment, current surges are avoided. However, after bypassing the faulty module, the bus voltage of the remaining normal modules needs to be increased. Once the bus voltage of the remaining modules rises to a specified value, the modulation wave directly returns to the normal value. (See "Seamless fault-tolerant control for cascaded H-bridge converters based battery energystorage system") IEEE Transactions on Industrial Electronics , vol. 70, no. 4, pp. 3803–3813, Apr. 2023. and "Redistributed pulse width modulation of MMCbattery energy storage system under submodule fault condition," IEEE Transactions on Power Electronics In the article, vol. 35, no. 3, pp. 2284–2294, Mar. 2020, when a submodule fails and is bypassed, the voltage level missing by the faulty submodule is compensated by other normal submodules in the faulty phase. This method does not require modification of the modulation wave or phase shift angle. However, when the number of modules increases, the computational load of this method increases dramatically, and it is also more complicated to operate when multiple submodules fail.

[0007] Therefore, current hot standby solutions cannot simultaneously meet the following requirements: reducing fluctuations caused by unit module switching, not changing the intermediate bus voltage of the unit module, and being easy to operate when facing one or more unit module failures. Summary of the Invention

[0008] The purpose of this invention is to provide a seamless fault-tolerant control method for solid-state transformers (SSTs) based on cascaded H-bridge voltage level compensation. After a faulty unit module is bypassed, the H-bridge of the remaining unit modules compensates for the missing voltage level in the faulty unit module's H-bridge, maintaining the total AC voltage of all SST unit modules unchanged. This invention solves the problem of excessive AC inductor current surges during the removal of faulty unit modules and the insertion of redundant unit modules in cascaded converters. This method is simple to operate; even when multiple unit modules fail, voltage level compensation for multiple unit modules can be achieved simply by modifying the judgment conditions. It enables rapid and smooth switching of unit modules during fault occurrence, and there is no need to raise the intermediate bus voltage of the remaining unit modules after removing the faulty unit module. V busi It can maintain the quality of system voltage and current waveforms and enhance system reliability.

[0009] The technical solution adopted in this invention is as follows: A seamless fault-tolerant control method for solid-state transformers based on cascaded H-bridge voltage level compensation is disclosed. The solid-state transformer includes multiple cascaded unit modules, with the input terminals of each module connected in series and the output terminals connected in parallel to form a cascaded structure. The input terminals of the cascaded unit modules are connected to the AC power grid after being connected in series with a filter inductor. Each cascaded unit module includes a front-stage H-bridge converter and a rear-stage isolated LLC resonant converter. The method is as follows: after a unit module is bypassed due to a fault, in order to keep the total voltage on the AC side of all cascaded unit modules in the solid-state transformer constant, the driving pulses of the H-bridge converters of the remaining unit modules are modified by comparing the relationship between the carrier wave and the modulation wave of the H-bridge converters in each unit module in real time, thereby compensating for the missing positive and negative voltage levels of the H-bridge converter of the faulty unit module.

[0010] The above technical solution further includes the following: When unit module M j The fault was bypassed, in order to ( v tj_1 < v m )&&( v tj_2 < v m ), j =1, 2, ... , n As a logical criterion for requiring positive voltage level compensation, in ( v tj_1 > v m )&&( v tj_2 > v m ), j=1, 2, ... , n As a logical criterion for requiring negative voltage level compensation, when the fault unit module M... j carrier v tj_1 , v tj_2 and modulated wave v m When the relationship between them is in other states, this means that no voltage level compensation is required; where v tj_1 , v tj_2 The fault unit module M is respectively j A pair of carrier signals with complementary phases, v m The signal is a modulated wave, and n is the number of unit modules.

[0011] Furthermore, when multiple unit modules fail, the logical criterion for positive voltage level compensation is that the carrier signal of all faulty unit modules is less than the modulated wave signal, and the logical criterion for negative voltage level compensation is that the carrier signal of all faulty unit modules is greater than the modulated wave signal. In other cases, no compensation is required.

[0012] Furthermore, after determining whether the faulty unit module needs voltage level compensation, the remaining normal unit modules need to be assessed. Compensation can only be performed when the normal unit module itself is at zero voltage. The specific assessment conditions are as follows: When the faulty unit module needs positive voltage level compensation, the normal unit module M... i The logic condition that can be used for positive voltage level compensation is (!(( v ti_1 < v m ) && ( v ti_2 < v m ))), i , j =1, 2, ... , n , i ≠ j When the faulty unit module needs to compensate for the negative voltage level, the normal unit module M... i The logic condition that can be used for negative voltage level compensation is (!(( v ti_1 > v m ) && ( v ti_2 > v m ))),i , j =1, 2, ... , n , i ≠ j .

[0013] Furthermore, after determining whether the faulty unit module needs voltage level compensation, the remaining normal unit modules are judged based on a fixed timing sequence.

[0014] Furthermore, after determining whether the faulty unit module needs voltage level compensation, the remaining normal unit modules are determined based on the module rotation method. That is, the normal unit modules are rotated in the order of voltage level compensation of the faulty unit modules, and the rotation period is based on the carrier period of the faulty unit module, with the order being rotated once every carrier period.

[0015] Furthermore, when a faulty unit module needs to compensate for a voltage level, and it is determined that this compensation is provided by the normal unit module M... i Appropriate voltage level compensation is performed by modifying the drive pulses of the H-bridge converter in the normal unit module using a voltage level compensation logic scheme. Specifically: Switching transistors in the front-end H-bridge converter of a normal unit module S i1 - S i4 The drive signals are respectively g i1 - g i4 , Comp_P_i For normal unit module M i The flag indicating whether positive level compensation is performed is 1 if yes and 0 if no. The positive level drive compensation logic scheme contains two OR gates, and the logical relationship between the drive pulse input and output is as follows: in, g i1 and g i4 They are respectively normal unit modules M i H-bridge switching transistors S i1 and S i4 The driving pulse, g i1P and g i4P Unit module M i H-bridge switching transistors S i1 and S i4The drive pulse after positive voltage level compensation S i1 and S i4 These are the upper and lower switching transistors in the two half-bridges of the H-bridge, respectively. Comp_N_i For normal unit module M i The flag indicating whether the drive signal is subject to negative level compensation is 1 if yes and 0 if no. The negative level compensation logic scheme includes two AND gates, and the logical relationship between the drive pulse input and output is as follows: in, g i1N and g i4N Unit module M i H-bridge switching transistors S i1 and S i4 The drive pulse after being compensated by a negative voltage level.

[0016] This invention addresses the issue of module failures in solid-state transformer (SST) systems by providing a seamless fault-tolerant control method based on cascaded H-bridge voltage level compensation. After a faulty module is bypassed, the H-bridge of the remaining modules compensates for the missing voltage level in the faulty module's H-bridge, maintaining a constant total AC voltage across all SST modules. This invention solves the problem of excessive AC inductor current surges during the removal of faulty modules and the insertion of redundant modules in cascaded converters. The method is simple to operate; even when multiple modules fail, voltage level compensation for multiple modules can be achieved simply by modifying the decision criteria. It enables rapid and smooth switching of modules during fault occurrences, and there is no need to raise the intermediate bus voltage of the remaining modules after removing the faulty module. V busi To maintain the quality of system voltage and current waveforms and enhance system reliability. i =1, 2, … , n ). Attached Figure Description

[0017] Figure 1 In one embodiment of the present invention, by n Circuit diagram of a solid-state transformer composed of individual unit modules.

[0018] Figure 2 This is a circuit diagram of a solid-state transformer composed of four unit modules in one embodiment of the present invention.

[0019] Figure 3 yes Figure 1Example of front-end control block diagram under normal operating conditions.

[0020] Figure 4 yes Figure 1 The block diagram of the downstream control system under normal operating conditions.

[0021] Figure 5 yes Figure 1 A block diagram of the front-end control system using the control method of this invention under an example fault condition.

[0022] Figure 6 Yes Figure 1 In the example, a certain unit module M i Diagram of pre-amplifier H-bridge modulation and AC side voltage level under normal operating conditions.

[0023] Figure 7 Yes Figure 2 The example shows the CPS-SPWM and AC side voltage level diagrams of the CHB under normal operating conditions for all unit modules.

[0024] Figure 8 Yes Figure 2 The CPS-SPWM and drive pulse diagrams of CHB under normal operating conditions for all unit modules in the example.

[0025] Figure 9 Yes Figure 1 In the example, a certain unit module M i The operating state diagram of the front-end H-bridge under normal operating conditions using CPS-SPWM.

[0026] Figure 10 Yes Figure 1 The instance adopts the following in the fault state: Figure 5 The voltage level compensation logic scheme in the control method of the present invention is shown.

[0027] Figure 11 Yes Figure 1 In the example, a certain unit module M j After the failure, use Figure 5 The diagram shows the voltage level compensation judgment strategy based on fixed timing in the control method of the present invention.

[0028] Figure 12 Yes Figure 2 In the example, after unit module M1 fails, it is then used Figure 11 Based on the voltage level compensation judgment strategy with fixed timing shown, the following approach is adopted: Figure 5 The diagram shows the voltage level compensation result of the normal module CHB in the control method of the present invention.

[0029] Figure 13 Yes Figure 2In the example, after unit module M1 fails, it is then used Figure 11 Based on the voltage level compensation judgment strategy with fixed timing shown, the following approach is adopted: Figure 5 The diagram shows the driving pulse compensation result of the normal unit module CHB for voltage level compensation using the control method of the present invention.

[0030] Figure 14 Yes Figure 1 In the example, a certain unit module M j After the failure, use Figure 5 The diagram shows the voltage level compensation judgment strategy based on module rotation in the control method of the present invention.

[0031] Figure 15 Yes Figure 2 In the example, after unit module M1 fails, it is then used Figure 14 Based on the voltage level compensation judgment strategy based on module rotation shown, the following is adopted Figure 5 The diagram shows the voltage level compensation result of the normal module CHB in the control method of the present invention.

[0032] Figure 16 Yes Figure 2 In the example, after unit module M1 fails, it is then used Figure 14 Based on the voltage level compensation judgment strategy based on module rotation shown, the following is adopted Figure 5 The diagram shows the driving pulse compensation result of the normal unit module CHB for voltage level compensation using the control method of the present invention. Detailed Implementation

[0033] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. These embodiments are only used to illustrate and explain the specific implementation and corresponding effects of the present invention, and are not intended to limit the present invention.

[0034] The method of this invention targets solid-state transformers such as Figure 1 As shown: It consists of multiple cascaded unit modules with their input terminals connected in series and their output terminals connected in parallel. The input terminals of each cascaded unit module are connected to the AC power grid after being connected in series with a filter inductor. Each unit module can be used for both the front-end H-bridge converter and the rear-end isolated DC-DC converter, and can also be used for cascaded H-bridge converters.

[0035] According to a specific embodiment of the present invention, Figure 2This is a circuit diagram of a single-phase solid-state transformer composed of four unit modules. The input terminals of each cascaded unit module are connected to the AC power grid in series with a filter inductor, while the output terminals are connected in parallel to maintain a stable DC voltage. Each cascaded unit module consists of a front-stage H-bridge converter and a rear-stage isolated LLC resonant converter. The front-stage H-bridge converter controls the energy of the medium-voltage power grid, reducing the equivalent input voltage of each cascaded unit through series connection and converting it to a lower DC bus voltage. V busi The energy is then fed into the subsequent LLC resonant converter. After high-frequency isolation, the outputs of all cascaded units are connected in parallel to provide energy for the DC load.

[0036] The control circuit can be implemented as follows: it includes a front-stage CHB controller (referred to as the front-stage controller) and a rear-stage LLC controller (referred to as the rear-stage controller). The front-stage controller controls the front-stage H-bridge converter in the cascaded module, while the rear-stage controller controls the rear-stage isolated LLC converter in the cascaded unit module. The front-stage controller controls the output voltage and implements grid-side power factor correction, while the rear-stage controller controls the bus voltage in the middle of the cascaded unit module. V busi ( i =1, 2, … , n ).

[0037] The front-end control block diagram under normal operating conditions is as follows: Figure 3 As shown, the front-end controller includes a voltage control loop (301), a current control loop (302), and a carrier phase-shifted SPWM (303). The voltage control loop (301) is used to control the output voltage of the entire SST system. V o The output signal generated serves as a reference value for the grid current. The current control loop (302) controls the grid current to achieve power factor correction, and its output signal is the duty cycle modulation signal of all cascaded unit front-stage H-bridge converters; carrier phase-shifted SPWM (303) generates the switching pulses of each switch in all front-stage H-bridge converters. Optionally, such as... Figure 4 As shown, the downstream LLC controller includes a bus voltage control loop (401) and a pulse frequency modulation (402). The bus voltage control loop (401) is used to generate the switching frequency of the LLC converter and serves as the input signal for the pulse frequency modulation (402). After pulse frequency modulation, switching pulses are obtained and sent to each switch of the downstream LLC resonant converter.

[0038] exist Figure 3 , Figure 4 Based on conventional control schemes, the control method of this invention employs a front-end control block diagram under fault conditions, as shown below. Figure 5As shown, a voltage level compensation judgment strategy (504) is used to determine when the normal unit module compensates the voltage level of the faulty unit module H bridge, and a voltage level compensation logic scheme (505) is used to modify the driving pulse of the normal unit module H bridge to achieve the purpose of compensating the voltage level.

[0039] Optionally, Figure 5 The specific derivation process of the voltage level compensation logic scheme (505) is as follows: The diagram below shows the pre-amplifier H-bridge modulation and AC side voltage level of a certain unit module under normal operating conditions. Figure 6 As shown, the front-stage CHB of the solid-state transformer employs carrier phase-shifted-sine pulse width modulation (CPS-SPWM), with each H-bridge AC side having three states: zero level, positive level, and negative level. The operating state diagram of the front-stage H-bridge using CPS-SPWM in the normal operation of a certain unit module is shown below. Figure 9 As shown, the individual switches of the cascaded H-bridge can be seen. S i1 - S i4 driving pulse g i1 - g i4 When the value is 1010 and 0101, the AC side voltage is zero. g i1 - g i4 When the value is 1001, its AC side voltage is positive because the switching transistor... S i1 and S i2 As complementary, the switching transistor S i3 and S i4 As they are complementary, it can be known that when g i1 and g i4 When the value is 1, the H-bridge input voltage is positive, which applies to the fault unit module M. i When performing positive level compensation, the fault unit module M is set to... i H-bridge drive pulse g i1 and g i4 A value of 1 is sufficient. g i1 - g i4 When the value is 0110, its AC side voltage is negative because of the switching transistor.S i1 and S i2 As complementary, the switching transistor S i3 and S i4 As they are complementary, it can be known that when g i1 and g i4 When the value is 0, the H-bridge input voltage is negative, which applies to the faulty unit module M. i When performing negative level compensation, the fault unit module M is set to... i The driving pulse of the H-bridge g i1 and g i4 It can be 0 ( i =1, 2, … , n ).

[0040] use Figure 5 The voltage level compensation logic scheme (505) in the normal unit module H-bridge modifies the drive pulse to compensate for the voltage level. Its specific implementation is as follows: Figure 10 The voltage level compensation logic scheme shown is a positive level drive compensation logic scheme (1001) used for the drive signal of the normal module. g i1 - g i4 Compensate for the positive voltage level. Comp_P_i For normal module M i drive signal g i1 - g i4 A flag indicating whether positive level compensation is required. Comp_P_i When the value is 1, the positive level drive compensation logic scheme (1001) is valid, indicating that the normal module M is functioning correctly. i drive signal g i1 - g i4 Positive voltage level compensation is required; the normal module M should be adjusted accordingly. i drive signal g i1 and g i4 Set to 1. Comp_P_i When the value is 0, the positive level drive compensation logic scheme (1001) is invalid, indicating that the normal module M is not working. i drive signal g i1 - g i4No positive level compensation is required. The positive level drive compensation logic scheme (1001) contains two OR gates, and the logical relationship between the drive pulse input and output is as follows: in, g i1 and g i4 Unit module M i H-bridge switching transistors S i1 and S i4 The driving pulse, g i1P and g i4P Unit module M i H-bridge switching transistors S i1 and S i4 The drive pulse after positive voltage level compensation ( i =1, 2, … , n ).

[0041] The negative level drive compensation logic scheme (1002) is used to compensate the negative voltage level of the drive signal of the normal unit module. Comp_N_i For normal unit module M i A flag indicating whether the drive signal is subject to negative level compensation. Comp_N_i When the value is 1, the negative level drive compensation logic scheme (1002) is valid, indicating that the normal module M is functioning correctly. i drive signal g i1P - g i4P Negative voltage level compensation is required. The normal module M after positive voltage level compensation will then... i drive signal g i1P and g i4P Set to 0. Comp_N_i When the value is 0, the negative level drive compensation logic scheme (1002) is invalid, indicating that the normal unit module M i drive signal g i1P - g i4P Negative level compensation is not required. Normal unit modules perform negative level compensation through a negative level compensation logic scheme (1002), which includes two AND gates. The logical relationship between the drive pulse input and output is as follows: in,g i1N and g i4N Unit module M i H-bridge switching transistors S i1 and S i4 Drive pulses compensated for by negative voltage level ( i =1, 2, … , n ).

[0042] Optionally, Figure 5 The specific derivation process of the voltage level compensation judgment strategy (504) is as follows: right Figure 1 The diagram below shows the pre-amplifier H-bridge modulation and AC side voltage level of a certain unit module under normal operating conditions. Figure 6 As shown, v ti_1 and v ti_2 For unit module M i A pair of carrier signals with complementary phases, v m The modulated wave signal of CHB, v si For unit module M i The AC side voltage. i =1, 2, … , n ) Figure 6 Unit module M can be obtained i AC side voltage level v si Its carrier v ti_1 , v ti_2 and modulated wave v m The relationship between them is: in, P Indicates a positive voltage level. N Indicates negative voltage level ( i =1, 2, … , n ).

[0043] When unit module M i carrier v ti_1 , v ti_2 and modulated wave v m The logical relationship between them is ( v ti_1< v m )&&( v ti_2 < v m ), i =1, 2, ... , n At that time, its AC side voltage v si It is at a positive level; when unit module M i carrier v ti_1 , v ti_2 and modulated wave v m The logical relationship between them is ( v ti_1 > v m )&&( v ti_2 > v m ), i =1, 2, ... , n At that time, its AC side voltage v si It is a negative level; when unit module M i carrier v ti_1 , v ti_2 and modulated wave v m When the relationship is in other states, its AC side voltage v si It is at zero level. Therefore, when unit module M j When a fault occurs and the circuit is bypassed, and compensation is needed for the missing voltage level, ( v tj_1 < v m )&&( v tj_2 < v m ), j =1, 2, ... , n As a logical criterion for requiring positive voltage level compensation, in ( v tj_1 > v m )&&( v tj_2 > v m ), j =1, 2, ... , nAs a logical criterion for requiring negative voltage level compensation, when the fault unit module M... j carrier v tj_1 , v tj_2 and modulated wave v m When the relationship is in other states, it means that no voltage level compensation is required. After determining when to compensate the voltage level of the faulty unit, it is then necessary to determine how the remaining normal unit modules should be compensated. This is because the voltage level compensation of a normal unit module cannot contradict its own generated voltage level; therefore, it needs to be compensated when its own voltage level is zero, because in the modulated wave... v m When the value is greater than zero, all unit modules on the AC side will only generate two states: positive level and zero level, in the modulated wave. v m When the voltage is less than zero, all unit modules will only generate two levels on the AC side: negative and zero. Therefore, when a faulty unit needs to be compensated for a positive voltage level, the normal unit module M... i The logical condition for performing positive voltage level compensation is (!(( v ti_1 < v m ) && ( v ti_2 < v m ))), i , j =1, 2, ... , n , i ≠ j When the faulty unit module needs to compensate for the negative voltage level, the normal unit module M... i The logical condition for performing negative voltage level compensation is (!(( v ti_1 > v m ) && ( v ti_2 > v m ))), i , j =1, 2, ..., n , i ≠ j .right Figure 1 In the example, a certain unit module M j After the failure, use Figure 5 The voltage level compensation judgment strategy based on fixed timing in the control method of the present invention is as follows: Figure 11As shown, the voltage level compensation judgment strategy based on fixed timing includes a positive level compensation judgment strategy (1101) and a negative level compensation judgment strategy (1102). The positive level compensation judgment strategy (1101) is used to determine whether to perform positive level compensation, and the negative level compensation judgment strategy (1102) is used to determine whether to perform negative level compensation. The positive level compensation judgment of the fault module (11011) is used as the basis for whether the fault module needs positive level compensation, and the negative level compensation judgment of the fault module (11021) is used as the basis for whether the fault module needs negative level compensation. At the same time, in order not to conflict with the voltage level generated by the normal unit module itself, the judgment strategy (11012) for the normal module to perform positive level compensation and the judgment strategy (11022) for the normal module to perform negative level compensation are used as the basis for whether the normal unit module performs positive voltage level compensation and negative voltage level compensation, respectively.

[0044] For example, normal unit module M i If positive voltage level compensation is possible, then the positive voltage level compensation flag will be set. Comp_P_i Set to 1 otherwise to 0. For example, in a normal unit module M... i If negative voltage level compensation is possible, then the negative voltage level compensation flag will be set. Comp_N_i Set to 1 otherwise to 0. Furthermore, at the very beginning of each compensation determination, the positive level compensation flag needs to be cleared by using compensation flag (1103). Comp_P_i With negative level compensation flag Comp_N_i Clear ( i =1, 2, … , n ).

[0045] Figure 2 The schematic diagram of the CPS-SPWM and AC side voltage levels of the CHB under normal operating conditions of the four unit modules M1, M2, M3, and M4 in the example is shown below. Figure 7 As shown, v t1_1 , v t2_1 , v t3_1 , v t4_1 These are the carrier signals for the four unit modules M1, M2, M3, and M4, respectively. v s1 , v s2 , v s3 , v s4 These are the AC side voltages of four unit modules M1, M2, M3, and M4, respectively. Assume that unit module M1 fails and is bypassed. Figure 12 and Figure 13 They are respectively adopted Figure 11Based on the voltage level compensation judgment strategy shown, the following is adopted Figure 5 The diagram shows the compensation results of the normal unit module voltage level and the compensation results of the normal unit module drive pulse obtained by the control method of the present invention. Figure 12 and Figure 13 middle, v s2C , v s3C , v s4C These are the voltage level compensation flags for the three normal unit modules M2, M3, and M4. A high level indicates that a unit module has performed positive voltage level compensation, a negative level indicates that a unit module has performed negative voltage level compensation, and a zero level indicates that a unit module has not performed voltage level compensation. Figure 12 It can be seen that the voltage level of unit module M1 is missing. v s1 The other three unit modules M2, M3, and M4 respectively generate positive or negative voltage levels during the corresponding time periods for compensation. Figure 12 The shaded areas represent the voltage levels of the three unit modules M2, M3, and M4 that compensate for the missing voltage in the faulty unit module M1. Similarly, Figure 13 The shaded area represents the drive pulses modified by the three unit modules M2, M3, and M4 to compensate for the missing voltage level of the faulty unit module M1.

[0046] Specifically, when multiple unit modules in the system fail, it is only necessary to change the judgment condition for the faulty unit module to require voltage level compensation. For example, for two unit modules M... j M k When a malfunction occurs, ( v tj_1 < v m )&&( v tj_2 < v m )&&( v tk_1 < v m )&&( v tk_2 < v m ), j , k =1, 2, ... , n , j ≠ k As a unit module M j M k The logic criteria for positive voltage level compensation are required, in order to ( vtj_1 > v m )&&( v tj_2 > v m )&&( v tk_1 > v m )&&( v tk_2 > v m ), j , k =1, 2, ... , n , j ≠ k As the logical criterion for requiring negative voltage level compensation, the normal unit module M i The logical condition for performing positive voltage level compensation is (!(( v ti_1 < v m ) && ( v ti_2 < v m ))), i , j , k =1, 2, ... , n , j ≠ i, k ≠ i , k ≠ j When the faulty unit module needs to compensate for the negative voltage level, the normal unit module M... i The logical condition for performing negative voltage level compensation is (!(( v ti_1 > v m ) && ( v ti_2 > v m ))), i , j , k =1, 2, ... , n , j ≠ i, k ≠ i , k ≠ j .

[0047] Optionally, such as Figure 12 As shown, the amount of compensation voltage level of a normal unit module is related to its compensation sequence. Figure 12 The compensation order is M2→M3→M4, which shows that v s2C , v s3C , v s4C The number of high and negative voltage levels decreases sequentially. The unit module at the beginning of the compensation sequence bears the most compensation voltage levels. The further down the compensation sequence, the fewer voltage levels it needs to compensate. This means that the unit module at the beginning of the compensation sequence needs to compensate the most energy, which may exceed its rated capacity and damage the equipment. Therefore, based on the voltage level compensation method proposed in this invention, further, as... Figure 14 As shown, a carrier cycle rotation method is adopted, where the normal unit modules rotate in sequence to compensate for the voltage level of the faulty unit modules. The rotation cycle is based on the carrier cycle of the faulty unit modules, and the sequence is rotated once every carrier cycle. The cycle rotation is performed through carrier cycle update (1403). Positive level compensation judgment strategy (1401) and negative level compensation judgment strategy (1402) are used to determine whether positive or negative voltage level compensation is required. The positive level compensation judgment (14011) of the faulty module is used as the basis for whether the faulty unit module needs positive level compensation, and the negative level compensation judgment (14021) of the faulty module is used as the basis for whether the faulty unit module needs negative level compensation. The judgment strategy (14012) for positive level compensation of the normal module and the judgment strategy (14022) for negative level compensation of the normal module are used as the basis for whether the normal unit modules need positive and negative voltage level compensation, respectively. Figure 14 Zhongyu Figure 11 The judgment logic is the same, only the judgment order for normal unit modules is different.

[0048] Figure 15 Yes Figure 2 In the example, after unit module M1 fails, the following is adopted: Figure 14 The diagram shows the voltage level compensation result of the normal unit module CHB after the voltage level compensation judgment strategy. The shaded part in the diagram is the voltage level of the three unit modules M2, M3, and M4 that compensate for the missing voltage of the faulty unit module M1. Figure 16 Yes Figure 2 In the example, after unit module M1 fails, the following is adopted: Figure 14 The diagram shows the drive pulse compensation results of the normal unit module CHB after the voltage level compensation judgment strategy. The shaded area in the diagram represents the drive pulses modified by the three unit modules M2, M3, and M4 to compensate for the missing voltage level of the faulty unit module M1. It can be seen that when using... Figure 14After the periodic rotation compensation scheme shown, the compensation level required by each normal module is closer, which can balance the energy that each normal module needs to compensate.

[0049] This invention studies a fault-tolerant method for unit modules in solid-state transformers. It addresses the issue of significant current surges in redundant unit modules during traditional hot standby switching processes, necessitating the elevation of the intermediate bus voltage of the unit modules. V busi To address the issue of complex operation, this invention proposes a fault-tolerant control method for voltage level compensation of redundant unit modules. After a faulty unit module is bypassed, the H-bridge of the remaining unit modules compensates for the missing voltage level in the H-bridge of the faulty unit module, maintaining the total AC voltage of all unit modules in the SST constant. This invention solves the problem of excessive AC inductor current surges during the removal of faulty unit modules and the insertion of redundant unit modules in cascaded converters. This method is simple to operate; even when multiple unit modules fail, voltage level compensation for multiple unit modules can be achieved simply by modifying the judgment conditions. It enables rapid and smooth switching of unit modules during fault occurrence, and there is no need to raise the intermediate bus voltage of the remaining unit modules after removing the faulty unit module. V busi To maintain the quality of system voltage and current waveforms and enhance system reliability. i =1, 2,… , n ).

[0050] The embodiments described above are only some solutions of the present invention, and are not intended to limit the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, all technical solutions obtained by equivalent substitution or equivalent transformation fall within the protection scope of the present invention.

Claims

1. A seamless fault-tolerant control method for a solid-state transformer based on cascaded H-bridge voltage level compensation, wherein the solid-state transformer comprises multiple cascaded unit modules, with the input terminals of each module connected in series and the output terminals connected in parallel to form a cascaded structure. The input terminal of each cascaded unit module is connected in series with a filter inductor and then connected to an AC power grid. Each cascaded unit module includes a front-stage H-bridge converter and a rear-stage isolated LLC resonant converter; characterized in that... The method is as follows: after a unit module is bypassed due to a fault, in order to keep the total voltage on the AC side of all cascaded unit modules in the solid-state transformer constant, the driving pulses of the H-bridge converters of the remaining unit modules are modified by comparing the relationship between the carrier wave and the modulation wave of the H-bridge converter in each unit module in real time, thereby compensating for the missing positive and negative voltage levels of the H-bridge converter of the faulty unit module.

2. The seamless fault-tolerant control method for solid-state transformers based on cascaded H-bridge voltage level compensation according to claim 1, characterized in that, Including the following: When unit module M j The fault was bypassed, in order to ( v tj_1 < v m )&&( v tj_2 < v m ), j =1, 2, ... , n As a logical criterion for requiring positive voltage level compensation, in ( v tj_1 > v m )&&( v tj_2 > v m ), j =1, 2, ... , n As a logical criterion for requiring negative voltage level compensation, when the fault unit module M... j carrier v tj_1 , v tj_2 and modulated wave v m When the relationship between them is in other states, this means that no voltage level compensation is required; where v tj_1 , v tj_2 The fault unit module M is respectively j A pair of carrier signals with complementary phases, v m The signal is a modulated wave, and n is the number of unit modules.

3. The seamless fault-tolerant control method for solid-state transformers based on cascaded H-bridge voltage level compensation according to claim 2, characterized in that, When multiple unit modules fail, the logical criterion for positive voltage level compensation is that the carrier signal of all faulty unit modules is less than the modulated wave signal, and the logical criterion for negative voltage level compensation is that the carrier signal of all faulty unit modules is greater than the modulated wave signal. In other cases, no compensation is required.

4. The seamless fault-tolerant control method for solid-state transformers based on cascaded H-bridge voltage level compensation according to claim 1, characterized in that, After determining whether the faulty unit module needs voltage level compensation, the remaining normal unit modules need to be evaluated. Compensation can only be performed when the normal unit module itself is at zero voltage. The specific evaluation criteria are as follows: When the faulty unit module needs positive voltage level compensation, the normal unit module M... i The logic condition that can be used for positive voltage level compensation is (!(( v ti_1 < v m ) && ( v ti_2 < v m ))), i , j =1, 2, ... , n , i ≠ j ; When the faulty unit module needs to compensate for the negative voltage level, the normal unit module M i The logic condition that can be used for negative voltage level compensation is (!(( v ti_1 > v m ) && ( v ti_2 > v m ))), i , j =1, 2, ... , n , i ≠ j .

5. The seamless fault-tolerant control method for solid-state transformers based on cascaded H-bridge voltage level compensation according to claim 4, characterized in that, After determining whether the faulty unit module needs voltage level compensation, the remaining normal unit modules are judged based on a fixed timing sequence.

6. The seamless fault-tolerant control method for solid-state transformers based on cascaded H-bridge voltage level compensation according to claim 4, characterized in that, After determining whether the faulty unit module needs voltage level compensation, the remaining normal unit modules are determined based on the module rotation method. That is, the normal unit modules are rotated in the order of the faulty unit modules to perform voltage level compensation, and the rotation period is based on the carrier period of the faulty unit module, with the order being rotated once every carrier period.

7. The seamless fault-tolerant control method for solid-state transformers based on cascaded H-bridge voltage level compensation according to claim 4, characterized in that, When a faulty unit module needs voltage level compensation, and it is determined that the faulty unit module M is the one that should compensate for the voltage level. i Appropriate voltage level compensation is performed by modifying the drive pulses of the H-bridge converter in the normal unit module using a voltage level compensation logic scheme. Specifically: Switching transistors in the front-end H-bridge converter of a normal unit module S i1 - S i4 The drive signals are respectively g i1 - g i4 , Comp_P_i For normal unit module M i The flag indicating whether positive level compensation is performed is 1 if yes and 0 if no. The positive level drive compensation logic scheme contains two OR gates, and the logical relationship between the drive pulse input and output is as follows: in, g i1 and g i4 They are respectively normal unit modules M i H-bridge switching transistors S i1 and S i4 The driving pulse, g i1P and g i4P Unit module M i H-bridge switching transistors S i1 and S i4 The drive pulse after positive voltage level compensation S i1 and S i4 These are the upper and lower switching transistors in the two half-bridges of the H-bridge, respectively. Comp_N_i For normal unit module M i The flag indicating whether the drive signal is subject to negative level compensation is 1 if yes and 0 if no. The negative level compensation logic scheme includes two AND gates, and the logical relationship between the drive pulse input and output is as follows: in, g i1N and g i4N Unit module M i H-bridge switching transistors S i1 and S i4 The drive pulse after being compensated by a negative voltage level.

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