Clock circuit with adjustable temperature coefficient, charge pump and integrated circuit

Abstract

The invention provides a clock circuit with an adjustable temperature coefficient, and the circuit comprises a reverse module which comprises an odd number of phase inverters, and the odd number is greater than or equal to 3; the time delay module comprises two same time delay circuits, a part of phase inverters in the reverse module are configured between the two time delay circuits, and an output signal of the previous-stage time delay circuit is reversely input into the next-stage time delay circuit; the two time-delay circuits are connected with the phase inverters in the reverse module end to end to form an annular oscillation circuit, and the output ends of the time-delay circuits are provided with current control circuits with positive temperature coefficients; the two delay circuits alternately generate delay signals based on input signals to form clock signals with oscillation periods. The duty ratio is close to or even reaches 50% by adopting complementation of the two time delay circuits, and the problem that transmission of other logic gates in a clock circuit is too fast in a low-temperature environment is solved by controlling the positive temperature coefficient of a current control circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more particularly to a clock circuit, a charge pump, and an integrated circuit. Background Technology

[0002] As an electronic oscillator based on the inverse piezoelectric effect, the crystal oscillator is recognized as the clock signal source with the highest accuracy and best stability in electronic systems.

[0003] For highly integrated chip applications, the use of traditional external crystal oscillators incurs additional cost and space burden. Therefore, on-chip integrated clock generation circuits (such as RC oscillators or ring oscillators) have become a common choice, but their inherent performance limitations often lead to significant deviations in practical applications.

[0004] The core problem with traditional on-chip clock circuits lies in their poor PVT characteristics. The oscillation frequency and timing are easily affected by process variations, power supply voltage fluctuations, and temperature changes. For example, in charge pump applications, the stability of the clock signal directly affects pump efficiency and drive capability, and the clock circuit also has certain temperature requirements. Furthermore, these oscillators typically struggle to achieve a 50% duty cycle, often requiring additional tuning circuitry, which not only increases design complexity but also further exacerbates power consumption and area overhead. Summary of the Invention

[0005] To address the aforementioned problems, this invention provides a clock circuit, charge pump, and integrated circuit with an adjustable temperature coefficient. It employs two complementary delay circuits to achieve a duty cycle close to or even reaching 50%, and solves the problem of excessively fast transmission of other logic gates in the clock circuit under low-temperature conditions by controlling the positive temperature coefficient of the current control circuit.

[0006] The technical solution provided by this invention is as follows: This invention provides a clock circuit with an adjustable temperature coefficient, comprising: The inverting module consists of an odd number of inverters, with the odd number being greater than or equal to 3; The delay module includes two identical delay circuits. A partial inverter from the inverting module is configured between the two delay circuits to invert the output signal of the previous delay circuit and input it into the next delay circuit. The two delay circuits and the first and second ends of each inverter in the inverting module are connected to form a ring oscillation circuit, and the output terminal of the delay circuit is configured with a current control circuit with a positive temperature coefficient. The two delay circuits alternately generate delay signals based on the input signal to form a clock signal with an oscillation period.

[0007] In some preferred embodiments, the inversion module includes: in the delay module, the number of inverters configured between the two delay circuits is odd, and the number of inverters configured between the delay circuits is less than the number of inverters in the inversion module.

[0008] In some preferred embodiments, the reverse module includes: First inverter, second inverter, and third inverter; The delay module includes: a first delay circuit and a second delay circuit; The input terminal of the first delay circuit is connected to the output terminal of the first inverter, the input terminal of the second inverter is connected to the output terminal of the first delay module, the input terminal of the second delay circuit is connected to the output terminal of the second inverter, the input terminal of the third inverter is connected to the output terminal of the second delay module, and the output terminal of the third inverter is connected to the input terminal of the first inverter.

[0009] In some preferred embodiments, the clock circuit further includes an output module configured with at least one inverter, the input of which is connected to the output of the first inverter.

[0010] In some preferred embodiments, the third inverter is implemented based on a NAND gate, which includes a signal input terminal and an enable terminal. The signal input terminal is connected to the output terminal of the second delay circuit, and the enable terminal is used to receive a control signal that controls the start and stop of the clock circuit.

[0011] In some preferred embodiments, the delay circuit further includes: A transmission unit, wherein the input terminal of the transmission unit is connected to the input signal of the delay circuit, and the output terminal of the transmission unit is connected to the input terminal of the RC charging and discharging unit; An RC charging and discharging unit is provided, the output of which is connected to the positive feedback unit and the current control circuit, respectively, and is used to perform charging and discharging operations according to the control signal output by the transmission unit; the current control circuit is used to control the charging and discharging current of the delay circuit output according to the operating temperature. A positive feedback unit, the output of which is connected to the output of the delay circuit, is used to control the output of the delay circuit according to the charging and discharging state of the RC charging unit.

[0012] In some preferred embodiments, the transmission unit includes a first PMOS transistor M1 and a first NMOS transistor M2; The RC charging and discharging unit includes a resistor R, an nmos capacitor M9, and a pmos capacitor M10. The positive feedback unit includes a second PMOS tube M3, a third PMOS tube M4, a second NMOS tube M5, and a third NMOS tube M6. The current control circuit includes a fourth PMOS transistor M7, a fourth NMOS transistor M8, a first bias current source IBIAS1, and a second bias current source IBIAS2. The drain of the first PMOS transistor M1 is connected to the drain of the first NMOS transistor M2, the gate is connected to the gate of the first NMOS transistor M2 and connected to the input signal IN of the delay circuit, and the source is connected to the power supply voltage VCC; the source of the first NMOS transistor M2 is grounded to GND. One end of resistor R is connected to the drain of the first PMOS transistor M1, and the other end is connected to the gate of NMOS capacitor M9, the gate of PMOS capacitor M10, and the drain of the third PMOS transistor M4, respectively; the other end of NMOS capacitor M9 is grounded to GND, and the other end of PMOS capacitor M10 is connected to the power supply voltage VCC. The source of the second PMOS transistor M3 is connected to the power supply voltage VCC, its drain is connected to the source of the third PMOS transistor M4, and its gate is connected to the gate of the third NMOS transistor M6; the gate of the third PMOS transistor M4 is connected to the gate of the second NMOS transistor M5 and connected to the input signal IN of the delay circuit, its drain is connected to the drain of the second NMOS transistor M5; the source of the second NMOS transistor M5 is connected to the drain of the third NMOS transistor M6; the source of the third NMOS transistor M6 is grounded to GND. The source of the fourth PMOS transistor M7 is connected to the first bias current source IBIAS1, the gate is connected to the drain of the first PMOS transistor M1, and the drain is connected to the drain of the fourth NMOS transistor M8; the gate of the fourth NMOS transistor M8 is connected to the drain of the third PMOS transistor M4, and the source is connected to the second bias current source IBIAS2. The output of the clock circuit is connected to the gate of the second PMOS transistor M3 and the drain of the fourth PMOS transistor M7, respectively.

[0013] In some preferred embodiments, the period T of the clock circuit is:

[0014] in, This indicates the rise time of the delay circuit. This indicates the fall-off delay of the delay circuit. This represents the switching voltage of the inverter between the two delay circuits. This indicates the capacitor connected to the output terminal in the delay circuit. This represents the current values ​​of the first bias current source IBIAS1 and the second bias current source IBIAS2.

[0015] On the other hand, the present invention provides a charge pump configured with the aforementioned temperature coefficient adjustable clock circuit.

[0016] In another aspect, the present invention provides an integrated circuit in which the aforementioned temperature coefficient adjustable clock circuit is configured.

[0017] This invention provides a temperature-adjustable clock circuit, charge pump, and integrated circuit. Based on a traditional ring oscillator, it introduces two delay circuits in the delay module to mutually supplement the RC charging and discharging time. This achieves a duty cycle close to or even reaching 50% without the need for additional circuitry, saving chip area and effectively compensating for frequency errors caused by power supply voltage VCC and process technology. Furthermore, a current control circuit with a positive temperature coefficient is configured at the clock circuit output. By controlling the positive temperature coefficient of the current control circuit, the problem of excessively fast transmission of other logic gates in the clock circuit at low temperatures is solved, effectively compensating for the temperature characteristics of the clock circuit. This provides an efficient and reliable solution for generating high-stability on-chip clocks and expands the application scenarios of the clock circuit, such as its application in temperature-sensitive charge pumps VPOS / VNEG in flash circuits. Attached Figure Description

[0018] The preferred embodiments will now be described in a clear and easy-to-understand manner, with reference to the accompanying drawings, to further explain the above-mentioned characteristics, technical features, advantages, and implementation methods.

[0019] Figure 1 This is a schematic diagram of an embodiment of the clock circuit in this invention; Figure 2 This is a clock circuit diagram according to one embodiment of the present invention; Figure 3 This is a circuit diagram of the delay circuit in this invention; Figure 4 This is a frequency deviation diagram of the clock signal output by the clock circuit when the power supply voltage is between 2V and 5V in this invention. Figure 5 This is a frequency deviation diagram of the clock signal output by the clock circuit when the operating temperature is between -45℃ and 130℃ in this invention.

[0020] Figure label: 11-First inverter, 12-Second inverter, 13-Third inverter, 21-First delay circuit, 22-Second delay circuit. Detailed Implementation

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.

[0022] According to a first embodiment of the present invention, a clock circuit with an adjustable temperature coefficient includes: an inverting module comprising an odd number of inverters, wherein the odd number is greater than or equal to 3; a delay module comprising two identical delay circuits, wherein a portion of the inverters in the inverting module are disposed between the two delay circuits to invert the output signal of the preceding delay circuit and input it into the following delay circuit; the two delay circuits are connected to the first and second ends of each inverter in the inverting module to form a ring oscillation circuit, and the output terminal of the delay circuit is configured with a current control circuit having a positive temperature coefficient; the two delay circuits alternately generate delay signals based on the input signal to form a clock signal with an oscillation period.

[0023] A traditional ring oscillator is a closed-loop circuit formed by connecting an odd number (N≥3) of inverters (NOT gates) end-to-end. It suffers from poor PVT characteristics and a duty cycle that is not 50%. Therefore, this embodiment improves upon this by introducing a delay module to replace the unstable gate delay in the traditional ring oscillator. A pair of precise delay circuits, insensitive to process, voltage, and temperature variations, is designed, fundamentally improving the clock circuit's performance. The number of inverters in the inverting module can be designed according to the actual application, such as including 3, 5, or even more; no specific limitation is made here. The inverters mentioned can be implemented using conventional inverters or other logic gates.

[0024] The delay module includes two identical delay circuits. One delay circuit creates a delay of half a cycle (e.g., high level) of the clock signal, and the other delay circuit creates a delay of the other half cycle (e.g., low level) of the clock signal. The two delay circuits are symmetrically designed and can output a clock signal with a 50% duty cycle without additional correction circuitry.

[0025] To achieve the function of the delay module, an odd number of inverters from the inverting module should be configured between the two delay circuits, with the number of inverters between the delay circuits being less than the number of inverters in the inverting module. This inverts (flips) the output of the previous delay circuit before inputting it into the next delay circuit. In other words, some inverters from the inverting module are configured between the two delay circuits, and each inverter and the two delay circuits are cross-connected to form a ring oscillator. The specific number of inverters configured between the two delay circuits is not limited here; preferably, one inverter is configured between the two delay circuits.

[0026] To achieve temperature compensation for the clock circuit, a current control circuit with a positive temperature coefficient is configured in the delay circuit and connected to the output. This allows the current control circuit to provide a larger charging and discharging current at lower operating temperatures, increasing the oscillation frequency and offsetting the excessively fast transmission of other logic gates in the clock circuit, thus achieving temperature compensation. In applications, the oscillation frequency of the clock circuit can be adjusted by changing the current in the current control circuit as needed.

[0027] This embodiment is obtained by improving the above embodiments. In this embodiment, as follows: Figure 1 As shown, the inverting module includes a first inverter 11, a second inverter 12, and a third inverter 13; the delay module includes a first delay circuit 21 and a second delay circuit 22; wherein, the input terminal of the first delay circuit 21 is connected to the output terminal of the first inverter 11, the input terminal of the second inverter 12 is connected to the output terminal of the first delay module, the input terminal of the second delay circuit 22 is connected to the output terminal of the second inverter 12, the input terminal of the third inverter 13 is connected to the output terminal of the second delay module, and the output terminal of the third inverter is connected to the input terminal of the first inverter 11; the output terminal of the first inverter 11 serves as the output terminal OUT of the clock circuit.

[0028] In this embodiment, the clock circuit consists of three inverters and two delay circuits. Based on the combination of the first delay circuit, the second inverter, and the second delay circuit, the two delay circuits work alternately based on the input signal to form a complete and balanced clock waveform.

[0029] This embodiment is obtained by improving the above embodiment. In this embodiment, the clock circuit further includes an output module configured with at least one inverter, and the input terminal of the output module is connected to the output terminal of the first inverter.

[0030] In this embodiment, to stabilize the output, an output module including at least one inverter is further configured at the output terminal of the clock circuit. The number of inverters in the output module is not specifically limited here; it can include one, two, or even more, depending on the actual application.

[0031] This embodiment is obtained by improving the above embodiment. In this embodiment, the third inverter is implemented based on a NAND gate. The NAND gate includes a signal input terminal and an enable terminal. The signal input terminal is connected to the output terminal of the second delay circuit, and the enable terminal is used to receive the control signal for controlling the start and stop of the clock circuit.

[0032] In one embodiment, such as Figure 2As shown, the clock circuit consists of two delay modules (delay1, delay2), four inverters (INV1, INV2, INV3, INV4), and a NAND gate (NAND3). Inverter INV1 (corresponding to the first inverter), delay circuit delay1 (corresponding to the first delay circuit), inverter INV2 (corresponding to the second inverter), delay circuit delay2 (corresponding to the second delay circuit), and NAND gate (corresponding to the third inverter) are connected end-to-end. The input of inverter INV3 is connected to the output of inverter INV1, and its output is connected to the input of inverter INV4. The output of inverter INV4 serves as the clock circuit's output (OUT). During operation, inverter INV1, delay circuit delay1, inverter INV2, delay circuit delay2, and NAND gate (NAND3) form a ring oscillation circuit, outputting a clock signal with an oscillation period, which is ultimately output through inverters INV3 and INV4.

[0033] This embodiment is an improvement on the above embodiments. In this embodiment, the delay circuit (first delay circuit / second delay circuit) further includes: a transmission unit, the input terminal of which is connected to the input signal of the delay circuit, and the output terminal of which is connected to the input terminal of the RC charging and discharging unit; an RC charging and discharging unit, the output terminal of which is connected to the positive feedback unit and the current control circuit respectively, for performing charging and discharging operations according to the control signal output by the transmission unit; the current control circuit for controlling the charging and discharging current of the delay circuit output terminal according to the operating temperature; and a positive feedback unit, the output terminal of which is connected to the output terminal of the delay circuit, for controlling the output of the delay circuit according to the charging and discharging state of the RC charging unit.

[0034] Specifically, such as Figure 3As shown, the transmission unit includes a first PMOS transistor M1 and a first NMOS transistor M2; the RC charging and discharging unit includes a resistor R, an NMOS capacitor M9, and a PMOS capacitor M10; the positive feedback unit includes a second PMOS transistor M3, a third PMOS transistor M4, a second NMOS transistor M5, and a third NMOS transistor M6; the current control circuit includes a fourth PMOS transistor M7, a fourth NMOS transistor M8, a first bias current source IBIAS1, and a second bias current source IBIAS2; wherein, the drain of the first PMOS transistor M1 is connected to the drain of the first NMOS transistor M2, the gate is connected to the gate of the first NMOS transistor M2 and connected to the input signal IN of the delay circuit, and the source is connected to the power supply voltage VCC; the source of the first NMOS transistor M2 is grounded to GND; one end of the resistor R is connected to the drain of the first PMOS transistor M1, and the other end is connected to the gate of the NMOS capacitor M9, the gate of the PMOS capacitor M10, and the drain of the third PMOS transistor M4 respectively; the other end of the NMOS capacitor M9 is connected to... The other end of the PMOS capacitor M10 is connected to the power supply voltage VCC; the source of the second PMOS transistor M3 is connected to the power supply voltage VCC, its drain is connected to the source of the third PMOS transistor M4, and its gate is connected to the gate of the third NMOS transistor M6; the gate of the third PMOS transistor M4 is connected to the gate of the second NMOS transistor M5 and connected to the input signal IN of the delay circuit, and its drain is connected to the drain of the second NMOS transistor M5; the source of the second NMOS transistor M5 is connected to the drain of the third NMOS transistor M6; the source of the third NMOS transistor M6 is grounded to GND; the source of the fourth PMOS transistor M7 is connected to the first bias current source IBIAS1, its gate is connected to the drain of the first PMOS transistor M1, and its drain is connected to the drain of the fourth NMOS transistor M8; the gate of the fourth NMOS transistor M8 is connected to the drain of the third PMOS transistor M4, and its source is connected to the second bias current source IBIAS2; the output of the clock circuit is connected to the gate of the second PMOS transistor M3 and the drain of the fourth PMOS transistor M7, respectively.

[0035] During operation, as the input signal IN1 of the first delay circuit changes from high to low (1→0), the input signal IN1 (corresponding to...) Figure 3 When IN in the circuit goes low, the gate of the first PMOS transistor M1 goes low and enters the on state; the gate of the first NMOS transistor M2 goes low and enters the off state; the first PMOS transistor M1 conducts and charges the NMOS capacitor M9 and the PMOS capacitor M10 through the resistor R, and node delb1 (corresponding to Figure 3The voltage at node delb1 gradually increases from low to high. When it reaches the threshold voltage Vth of the fourth NMOS transistor M8, the output terminal OUT'1 (corresponding to OUT' in the diagram) is pulled low through the second bias current source IBIAS2, meaning that the output terminal OUT'1 begins to decrease. At the same time, the second PMOS transistor M3 begins to conduct and draws current from the power supply voltage VCC, accelerating the rise of node delb1. The accelerated rise of node delb1 causes the third PMOS transistor M4 to turn off more quickly, and the second NMOS transistor M5 to turn on more quickly, further accelerating the pull-down of the output terminal OUT'1 together with the fourth NMOS transistor M8, forming a positive feedback loop.

[0036] After passing through the inverter between the first and second delay circuits, the input signal IN2 of the second delay circuit is quickly pulled from low to high (0→1). The first PMOS transistor M1 enters the off state, and the first NMOS transistor M2 enters the on state. The delb2 node discharges the NMOS capacitors M9 and MMOS capacitors M10 through the resistor R, slowly lowering the power supply voltage VCC. When it drops to the threshold voltage Vth of the fourth NMOS transistor M8, the output terminal OUT'2 (corresponding to OUT' in the figure) is charged through the first bias current source IBIAS1, that is, the output terminal OUT'2 begins to rise. When it rises to the flip point (logic threshold voltage) of the next logic gate, the third NMOS transistor M6 turns on, and the second PMOS transistor M3 turns off. The conduction of the third NMOS transistor M6 further pulls the delb2 node low, accelerating the charging of the output terminal OUT'2, thus forming a half-cycle clock signal. The formation of the second half-cycle clock signal is the same as the above process, the difference being that the charging and discharging processes of the two delay circuits are reversed, which will not be elaborated here.

[0037] The clock circuit provided in the above embodiments, if the delay of the logic gates (inverters, NAND gates) is ignored, the period T can be expressed as:

[0038] in, The rise delay of the delay circuit can be determined by the RC charging and discharging unit; The fall delay of the delay circuit can be determined by the RC charging and discharging unit; This represents the switching voltage of the inverter between two delay circuits. Figure 2 In the example shown, it refers to the switching voltage of inverter INV2; This indicates the capacitor connected to the output terminal in the delay circuit, which can be obtained through simulation; This represents the current values ​​of the first bias current source IBIAS1 and the second bias current source IBIAS2.

[0039] In the above embodiments, in the delay module, when the resistor R and capacitor C (the capacitance of nmos capacitor M9 and pmos capacitor M10) remain unchanged, the delay time is mainly determined by the threshold voltage Vth of the fourth nmos transistor M8. Since the threshold voltage is affected by the corner (process corner), and the larger the power supply voltage VCC, the shorter the time it takes for the delb node to charge to the threshold voltage Vth; during discharge, the longer the time it takes for the delb node to discharge from the power supply voltage VCC to the threshold voltage Vth. Therefore, in practical applications, the characteristics of the process and voltage can be adjusted by controlling an appropriate ratio. Furthermore, regarding temperature, the positive temperature coefficient of the current control circuit (first bias current source IBIAS1 and second bias current source IBIAS2) can be controlled to compensate for the excessively fast transmission of other logic gates INV1~INV2 and NAND3 at low temperatures in the ring oscillator, thus achieving temperature compensation. Moreover, the delay module uses two delay circuits to complement each other's discharge time, achieving a duty cycle close to or even reaching 50% without additional circuitry, generating a stable clock signal.

[0040] Based on Figure 2 and Figure 3 In the example shown, when the power supply voltage is between 2V and 5V, the frequency deviation of the clock signal output by the clock circuit is as follows: Figure 4 (The horizontal axis represents the power supply voltage VCC, and the middle axis represents the frequency.) As shown, the deviation is within 5%, and the duty cycle is between 45% and 55%. When the chip's operating temperature is between -45℃ and 130℃, the frequency deviation of the clock signal output by the clock circuit is as follows: Figure 5 (The horizontal axis represents the operating temperature (temp), and the middle axis represents the frequency.) As shown, the deviation is within 10%, and the duty cycle is between 45% and 55%. It can be seen that the clock circuit provided by this invention can effectively achieve its purpose, providing a stable clock signal.

[0041] In another embodiment of the present invention, a charge pump is configured with the aforementioned temperature coefficient adjustable clock circuit.

[0042] In flash circuit design, the main function of the clock circuit is to provide an oscillation waveform for the charge pump VPOS / VNEG, and the charge pump's capability is related to the frequency of the clock signal. Furthermore, the charge pump VPOS / VNEG requires greater driving capability at higher temperatures, thus necessitating a higher clock frequency. Therefore, a clock circuit with a positive temperature coefficient can fully meet the requirements of the charge pump VPOS / VNEG. The clock circuit provided in the above embodiment can adjust the output frequency of the clock circuit by controlling the positive temperature coefficient of the current control circuit (first bias current source IBIAS1 and second bias current source IBIAS2), enabling the charge pump VPOS / VNEG to utilize its functional characteristics more effectively.

[0043] In another embodiment of the present invention, an integrated circuit is provided, wherein the integrated circuit is configured with the above-mentioned temperature coefficient adjustable clock circuit. It should be noted that the above embodiments can be freely combined as needed. The above are merely preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A clock circuit with an adjustable temperature coefficient, characterized in that, include: The inverting module comprises an odd number of inverters, wherein the odd number is greater than or equal to 3; The delay module includes two identical delay circuits, with a partial inverter from the inverting module configured between the two delay circuits to invert the output signal of the previous delay circuit and input it into the next delay circuit. Two delay circuits are connected to the first and second terminals of each inverter in the inverting module to form a ring oscillation circuit, and the output terminal of the delay circuit is equipped with a current control circuit with a positive temperature coefficient. Two delay circuits alternately generate delay signals based on the input signal to form a clock signal with an oscillation period.

2. The clock circuit as described in claim 1, characterized in that, In the delay module, the number of inverters configured between the two delay circuits is odd, and the number of inverters configured between the delay circuits is less than the number of inverters in the inversion module.

3. The clock circuit as described in claim 1 or 2, characterized in that, The inverting module includes: a first inverter, a second inverter, and a third inverter; The delay module includes: a first delay circuit and a second delay circuit; The input terminal of the first delay circuit is connected to the output terminal of the first inverter, the input terminal of the second inverter is connected to the output terminal of the first delay module, the input terminal of the second delay circuit is connected to the output terminal of the second inverter, the input terminal of the third inverter is connected to the output terminal of the second delay module, and the output terminal of the third inverter is connected to the input terminal of the first inverter.

4. The clock circuit as described in claim 3, characterized in that, The clock circuit also includes an output module configured with at least one inverter, the input terminal of which is connected to the output terminal of the first inverter.

5. The clock circuit as described in claim 3, characterized in that, The third inverter is implemented based on a NAND gate, which includes a signal input terminal and an enable terminal. The signal input terminal is connected to the output terminal of the second delay circuit, and the enable terminal is used to receive a control signal that controls the start and stop of the clock circuit.

6. The clock circuit as described in claim 1 or 2, characterized in that, The delay circuit also includes: A transmission unit, wherein the input terminal of the transmission unit is connected to the input signal of the delay circuit, and the output terminal of the transmission unit is connected to the input terminal of the RC charging and discharging unit; An RC charging and discharging unit is provided, the output of which is connected to the positive feedback unit and the current control circuit respectively, and is used to perform charging and discharging operations according to the control signal output by the transmission unit; the current control circuit is used to control the charging and discharging current of the delay circuit output according to the operating temperature. A positive feedback unit, the output of which is connected to the output of the delay circuit, is used to control the output of the delay circuit according to the charging and discharging state of the RC charging unit.

7. The clock circuit as described in claim 6, characterized in that, The transmission unit includes a first PMOS transistor M1 and a first NMOS transistor M2; The RC charging and discharging unit includes a resistor R, an nmos capacitor M9, and a pmos capacitor M10. The positive feedback unit includes a second PMOS tube M3, a third PMOS tube M4, a second NMOS tube M5, and a third NMOS tube M6. The current control circuit includes a fourth PMOS transistor M7, a fourth NMOS transistor M8, a first bias current source IBIAS1, and a second bias current source IBIAS2. The drain of the first PMOS transistor M1 is connected to the drain of the first NMOS transistor M2, the gate is connected to the gate of the first NMOS transistor M2 and connected to the input signal IN of the delay circuit, and the source is connected to the power supply voltage VCC; the source of the first NMOS transistor M2 is grounded to GND. One end of resistor R is connected to the drain of the first PMOS transistor M1, and the other end is connected to the gate of NMOS capacitor M9, the gate of PMOS capacitor M10, and the drain of the third PMOS transistor M4, respectively; the other end of NMOS capacitor M9 is grounded to GND, and the other end of PMOS capacitor M10 is connected to the power supply voltage VCC. The source of the second PMOS transistor M3 is connected to the power supply voltage VCC, its drain is connected to the source of the third PMOS transistor M4, and its gate is connected to the gate of the third NMOS transistor M6; the gate of the third PMOS transistor M4 is connected to the gate of the second NMOS transistor M5 and connected to the input signal IN of the delay circuit, and its drain is connected to the drain of the second NMOS transistor M5; the source of the second NMOS transistor M5 is connected to the drain of the third NMOS transistor M6; the source of the third NMOS transistor M6 is grounded to GND. The source of the fourth PMOS transistor M7 is connected to the first bias current source IBIAS1, the gate is connected to the drain of the first PMOS transistor M1, and the drain is connected to the drain of the fourth NMOS transistor M8; the gate of the fourth NMOS transistor M8 is connected to the drain of the third PMOS transistor M4, and the source is connected to the second bias current source IBIAS2. The output of the clock circuit is connected to the gate of the second PMOS transistor M3 and the drain of the fourth PMOS transistor M7, respectively.

8. The clock circuit as described in claim 7, characterized in that, The period T of the clock circuit is: ； in, This indicates the rise time of the delay circuit. This indicates the fall-off delay of the delay circuit. This represents the switching voltage of the inverter between the two delay circuits. This indicates the capacitor connected to the output terminal in the delay circuit. This represents the current values ​​of the first bias current source IBIAS1 and the second bias current source IBIAS2.

9. A charge pump, characterized in that, The charge pump is equipped with a temperature coefficient adjustable clock circuit as described in any one of claims 1-8.

10. An integrated circuit, characterized in that, The integrated circuit is configured with a temperature coefficient adjustable clock circuit as described in any one of claims 1-8.

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