Information transmission method and device based on label bit delay distribution

Abstract

The invention discloses an information transmission method and device based on label bit delay distribution, which are applied to a sending end, and comprises the following steps: carrying out coding interleaving on an original information bit sequence to generate an interleaved bit sequence, and carrying out rearrangement based on a variable node degree of a protograph to obtain a rearranged bit sequence; constructing a label bit set based on a constellation diagram order, performing reliability sorting according to mutual information of each label bit in the set, dividing the label bit set into a plurality of label bit subsets, and allocating delay time slots; mapping the rearranged bit sequence to tag bits corresponding to the tag bit subsets in a blocking manner, converting the rearranged bit sequence into modulation symbols, modulating the modulation symbols and then performing transmission pretreatment to generate transmission signals, and transmitting the transmission signals to a receiving end through a visible light communication channel; and decoding the transmission signal through a receiving end, generating a decoding bit sequence, and outputting the decoding bit sequence. Therefore, through division of tag bit subsets and bit sequence rearrangement, delay time slot distribution accuracy is guaranteed, and visible light communication transmission reliability is effectively improved.

Description

Technical Field

[0001] This invention relates to the field of information encoding and transmission technology, and in particular to an information transmission method and apparatus based on tag bit delay allocation. Background Technology

[0002] Visible light communication (VLC) is a novel communication technology that integrates lighting and wireless data transmission using light-emitting diodes (LEDs). With the rapid development of solid-state lighting technology and semiconductor devices, LEDs have been widely deployed in indoor lighting, intelligent transportation, and display systems. Compared to traditional radio frequency communication, VLC offers advantages such as abundant available spectrum resources, low electromagnetic interference, strong security, and the ability to work seamlessly with lighting systems.

[0003] In the intensity modulation / direct detection (IM / DD) architecture of VLC, traditional bipolar orthogonal frequency division multiplexing (OFDM) signals cannot satisfy the constraint of non-negative real values ​​for optical signals. However, asymmetrically clipped optical orthogonal frequency division multiplexing (ACO-OFDM) systems achieve non-negative signal transmission without additional DC bias by loading data only on odd-numbered subcarriers, generating real-valued time-domain signals using a Hermitian symmetry structure, and performing asymmetrical clipping.

[0004] To further improve the reliability of the ACO-OFDM system under the constraints of limited optical power and low latency, delayed bit-interleaved coded modulation (DBICM) was introduced. However, in the above scheme, the allocation of delay slots is usually a preset value and the mapping relationship between tag bits and coded bits is not optimized, which restricts the bit error rate performance of the system. Summary of the Invention

[0005] This invention provides an information transmission method and apparatus based on tag bit delay allocation, which solves the technical problem that in traditional multi-carrier modulation schemes based on visible light communication, the allocation of delay slots is usually a preset value and the mapping relationship between tag bits and coded bits is not optimized, thus restricting the bit error rate performance of the system.

[0006] This invention provides an information transmission method based on tag bit delay allocation, applied at the sending end, the method comprising:

[0007] When the original information bit sequence is received, it is encoded by the original pattern encoder and then interleaved by the interleaver to generate an interleaved bit sequence.

[0008] Based on the variable node degree of the original model graph in the original model graph encoder, the interleaved bit sequence is rearranged to obtain the rearranged bit sequence;

[0009] A set of tag bits is constructed based on the order of the constellation diagram, and after reliability sorting according to the mutual information of each tag bit in the set, it is divided into multiple subsets of tag bits.

[0010] Distribute delay time slots to the tag bits within each of the aforementioned subsets of tag bits;

[0011] The rearranged bit sequence is divided into blocks and mapped to the tag bits corresponding to each subset of tag bits, and then converted into modulation symbols according to the constellation diagram;

[0012] The modulation symbol is modulated and then preprocessed before transmission to generate a transmission signal, which is transmitted to the receiving end through a visible light communication channel. The receiving end is used to decode the transmission signal, generate a decoded bit sequence, and output it.

[0013] Optionally, the step of rearranging the interleaved bit sequence according to the variable node degree of the original pattern graph in the original pattern graph encoder to obtain the rearranged bit sequence includes:

[0014] According to the variable node degree of the original model graph in the original model graph encoder, sort the multiple variable nodes of the original model graph to obtain the variable node index sequence;

[0015] The interleaved bit sequence is rearranged according to the variable node index sequence to obtain the rearranged bit sequence.

[0016] Optionally, the step of constructing a set of tag bits based on the order of the constellation diagram, and then dividing it into multiple subsets of tag bits after reliability sorting according to the mutual information of each tag bit in the set, includes:

[0017] The number of bits in the set is obtained by calculating the binary logarithm based on the order of the constellation diagram.

[0018] Create a tag bit set according to the number of bits in the set;

[0019] Calculate the mutual information of each tag bit within the tag bit set;

[0020] Sort each tag bit in the tag bit set in descending order according to the mutual information to obtain the tag bit update set;

[0021] The tag bit update set is divided into multiple tag bit subsets based on the number of bits in the set.

[0022] Optionally, the step of dividing the tag bit update set into multiple tag bit subsets based on the number of set bits includes:

[0023] The first ratio between the number of bits in the set and the first value is calculated using a floor function;

[0024] The second ratio between the number of bits in the set and the second value is calculated using a floor function;

[0025] The tag bit update set is divided according to the first ratio to obtain a first tag bit subset and a tag bit subset to be split;

[0026] The subset of tag bits to be split is divided according to the second ratio to obtain a second subset of tag bits and a third subset of tag bits.

[0027] Optionally, the step of allocating delay time slots to tag bits within each subset of tag bits includes:

[0028] Obtain the number of bit reliability levels corresponding to the subset of third tag bits;

[0029] The third tag bit subset is split into multiple fourth tag bit subsets, the number of which is equal to the number of the bit reliability levels; each fourth tag bit subset is assigned a reliability index.

[0030] Calculate the difference between the number of reliability levels of the bit and each reliability sequence number;

[0031] Allocate a delay slot equal to the difference to the corresponding subset of fourth tag bits;

[0032] Calculate the first sum of the number of bit reliability levels and the first preset value;

[0033] Allocate delay slots equal to the number of the bit reliability levels to the tag bits within the second tag bit subset;

[0034] Allocate a delay slot equal to the first sum to the tag bits within the first tag bit subset.

[0035] Optionally, the step of mapping the rearranged bit sequence into blocks corresponding to the tag bits of each of the tag bit subsets, and converting them into modulation symbols according to the constellation diagram, includes:

[0036] Calculate the second sum of the number of bit reliability levels corresponding to the third tag bit subset and the second preset value;

[0037] Divide the rearranged bit sequence to obtain multiple coded bit sub-blocks that are equal to the second sum;

[0038] Each of the coded bit sub-blocks is mapped to the tag bit corresponding to the first tag bit subset, the tag bit corresponding to the second tag bit subset, and the tag bit corresponding to each of the fourth tag bit subsets to obtain a tag bit sequence;

[0039] The tag bit sequence is converted into modulation symbols according to the constellation diagram.

[0040] Optionally, the step of modulating the modulation symbol, performing pre-transmission processing, generating a transmission signal, and transmitting it to the receiving end via a visible light communication channel includes:

[0041] The modulation symbol is loaded onto the odd subcarriers in the first half, the conjugate signal of the modulation symbol is loaded onto the odd subcarriers in the second half, and the even subcarriers are set to zero to generate a frequency domain signal.

[0042] Perform an inverse fast Fourier transform on the frequency domain signal to generate a time domain signal;

[0043] After clipping the time-domain signal, a cyclic prefix is ​​added to generate the transmission signal;

[0044] The transmitted signal is transmitted to the receiving end via a visible light communication channel.

[0045] Optionally, the receiving end is specifically used for:

[0046] When the transmitted signal is received, the cyclic prefix of the transmitted signal is removed to obtain the signal to be transformed;

[0047] Perform a Fast Fourier Transform on the signal to be transformed to obtain the frequency domain signal to be extracted;

[0048] The frequency domain signal within the odd-numbered subcarriers in the first half of the frequency domain signal to be extracted is extracted to obtain the frequency domain signal to be demodulated.

[0049] The frequency domain signal to be demodulated is demodulated by a demodulator to obtain the log-likelihood ratio sequence corresponding to the frequency domain signal to be demodulated.

[0050] The log-likelihood ratio sequence is subjected to inverse bit delay to obtain the uninterleaved log-likelihood ratio sequence;

[0051] The uninterleaved log-likelihood ratio sequence is deinterleaved to obtain the log-likelihood ratio sequence to be decoded;

[0052] The log-likelihood ratio sequence to be decoded is decoded using a primitive model decoder to generate and output a decoded bit sequence.

[0053] Optionally, the receiving end is further configured to:

[0054] The log-likelihood ratio sequence to be decoded is decoded by the original model diagram decoder to generate a decoded bit sequence and an external log-likelihood ratio sequence.

[0055] The external log-likelihood ratio sequence is input to the demodulator to assist in demodulating the frequency domain signal to be demodulated under different time slot delays.

[0056] The present invention also provides an information transmission device based on tag bit delay allocation, applied at the transmitting end, the device comprising:

[0057] The bit sequence preprocessing module is used to encode the original information bit sequence by the original pattern encoder when the original information bit sequence is received, and then interleave it by the interleaver to generate an interleaved bit sequence.

[0058] The bit sequence rearrangement module is used to rearrange the interleaved bit sequence according to the variable node degree of the original pattern in the original pattern encoder to obtain a rearranged bit sequence.

[0059] The tag bit subset partitioning module is used to construct a tag bit set based on the order of the constellation diagram, and then divide it into multiple tag bit subsets after sorting the reliability according to the mutual information of each tag bit in the tag bit set.

[0060] The delay time slot allocation module is used to allocate delay time slots to tag bits within each of the said tag bit subsets;

[0061] The bit sequence block mapping module is used to map the rearranged bit sequence blocks to the tag bits corresponding to each of the tag bit subsets, and convert them into modulation symbols according to the constellation diagram;

[0062] The signal transmission module is used to modulate the modulation symbol and perform pre-transmission processing to generate a transmission signal and transmit it to the receiving end through a visible light communication channel; the receiving end is used to decode the transmission signal, generate a decoded bit sequence and output it.

[0063] As can be seen from the above technical solutions, the present invention has the following advantages:

[0064] This invention generates an interleaved bit sequence by encoding and interleaving the original information bit sequence, and then rearranges it based on the variable node degree of the original modulus graph to obtain a rearranged bit sequence. A set of tag bits is constructed based on the constellation graph order, and after reliability sorting according to the mutual information of each tag bit within the set, it is divided into multiple tag bit subsets and allocated delay slots. The rearranged bit sequence is block-mapped to the tag bits corresponding to each tag bit subset, then converted into modulation symbols, modulated, and pre-processed for transmission to generate a transmission signal, which is transmitted to the receiving end through a visible light communication channel. The receiving end decodes the transmission signal to generate a decoded bit sequence and outputs it. Thus, through the partitioning of tag bit subsets and the rearrangement of the bit sequence, the accuracy of delay slot allocation is ensured, effectively improving the reliability of visible light communication transmission. Attached Figure Description

[0065] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0066] Figure 1 A flowchart illustrating the steps of an information transmission method based on tag bit delay allocation provided in an embodiment of the present invention;

[0067] Figure 2 A schematic diagram illustrating a tag bit-constrained delay allocation process provided in an embodiment of the present invention;

[0068] Figure 3 This is a schematic diagram of the average mutual information of tag bits provided in an embodiment of the present invention;

[0069] Figure 4 A block diagram of a DACO-OFDM system based on original model graph encoding is provided for an embodiment of the present invention;

[0070] Figure 5 This is a schematic diagram illustrating the comparison of bit error rates across multiple schemes, provided in an embodiment of the present invention.

[0071] Figure 6 This is a structural block diagram of an information transmission device based on tag bit delay allocation provided in an embodiment of the present invention. Detailed Implementation

[0072] This invention provides an information transmission method and apparatus based on tag bit delay allocation, which addresses the technical problem in traditional visible light communication-based multicarrier modulation schemes where the allocation of delay slots is usually a preset value and the mapping relationship between tag bits and coded bits is not optimized, thus restricting the system's bit error rate performance and channel reliability.

[0073] To make the objectives, features, and advantages of this invention more apparent and understandable, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0074] Please see Figure 1 , Figure 1 A flowchart illustrating the steps of an information transmission method based on tag bit delay allocation provided in an embodiment of the present invention.

[0075] This invention provides an information transmission method based on tag bit delay allocation, applied at the sending end, the method comprising:

[0076] Step 101: When the original information bit sequence is received, the original information bit sequence is encoded by the original pattern encoder and then interleaved by the interleaver to generate an interleaved bit sequence.

[0077] The raw information bit sequence refers to the binary data sequence that is to be transmitted through a visible light communication system without any encoding or processing.

[0078] A protograph encoder is an encoding system designed based on a protograph structure, which achieves encoding by defining the connection relationship between variable nodes and check nodes.

[0079] An interleaver is a system used to shuffle the order of encoded bit sequences. Its core function is to disperse burst errors into random errors, reduce the impact of channel fading on the transmission of consecutive bits, and improve the fault tolerance of decoding.

[0080] In this embodiment of the invention, after receiving the original information bit sequence, the transmitting end inputs it into the original pattern graph encoder, completes the encoding process according to the preset original pattern graph connection rules, and generates an encoded bit sequence. Then, the encoded bit sequence is sent to an interleaver, which rearranges the bit positions of the encoded bit sequence according to a preset interleaving mode, breaking the correlation between consecutive bits, and finally outputs an interleaved bit sequence, laying the foundation for subsequent bit rearrangement and mapping. Specifically, time slots... In, the original information bit sequence The bits are fed into the original pattern encoder for encoding, generating an encoded bit sequence. , The length of the original information bit sequence. This represents the number of coded bits transmitted. Subsequently, the coded bit sequence is interleaved to obtain the interleaved bit sequence.

[0081] It should be noted that the original model encoder can adopt an adaptive structure, which can dynamically adjust the node connection density of the original model according to the real-time fading characteristics of the visible light communication channel. The interleaver can adopt a dynamic interleaving depth design to fuse signal state information.

[0082] In traditional bit delay schemes, the interleaved coded bit sequence is divided into... Each sub-block, that is ,in, as well as That's the modulation order. Next, the sub-block... Delayed Each time slot ( , (For the delay scheme), to generate delayed sub-blocks. ,in, Indicates the first Sub-block The number of delay slots, delay The coded bits in a sub-block of a time slot are called delay-free coded bits, and the delay... The coded bits in a sub-block of a time slot are called delayed coded bits. Delay plan Given that both the transmitter and receiver are known, in the delay scheme In the above, the maximum number of delay time slots and the minimum number of delay time slots are respectively and ,and , However, the above process does not take into account the reasonable allocation of delay slots for tag bits in a Delayed Asymmetrically Clipped Optical Orthogonal Frequency Division Multiplexing (DACO-OFDM) system, nor does it consider the mapping relationship between encoded bits and tag bits with and without delay. Therefore, this embodiment of the invention allocates delay slots for tag bits through the process of steps 102-105, and optimizes the mapping relationship between encoded bits and tag bits with and without delay.

[0083] Step 102: Based on the variable node degree of the original model graph in the original model graph encoder, rearrange the interleaved bit sequence to obtain the rearranged bit sequence;

[0084] Variable node degree refers to the number of connections between each variable node and the check node in the original model diagram, and is used to measure the importance of variable nodes.

[0085] In this embodiment, after obtaining the interleaved bit sequence, the degree information of each variable node in the original model graph encoder is extracted from each variable node. The variable nodes are sorted according to a preset sorting rule (such as descending or ascending degree) to determine the positional relationship of the encoded bits corresponding to each variable node in the interleaved bit sequence. Based on this positional relationship, the interleaved bit sequence is rearranged so that the encoded bits from variable nodes of different degrees form an ordered rearranged bit sequence.

[0086] In one example of the present invention, step 102 may include the following sub-steps:

[0087] Based on the variable node degree of the original model graph in the original model graph encoder, sort the multiple variable nodes of the original model graph to obtain the variable node index sequence;

[0088] The interleaved bit sequence is rearranged according to the variable node index sequence to obtain the rearranged bit sequence.

[0089] In this embodiment, the degree information of all variable nodes in the original model graph of the original model graph encoder is extracted to determine the number of connections for each variable node. Then, according to the degree of the variable nodes, a preset sorting rule (such as descending or ascending degree) is used to arrange all variable nodes in order, generating a variable node index sequence containing the indexes of each variable node. The indexes at the beginning of the index sequence correspond to variable nodes with larger or smaller degrees, realizing the classification and sorting of variable nodes according to their reliability association attributes. Next, based on the variable node index sequence, the source of the variable node corresponding to each bit in the interleaved bit sequence is traced, and the bits in the interleaved bit sequence are rearranged according to the order of the index sequence. The encoded bits from the same variable node or variable nodes of the same degree are grouped together, and finally, the rearranged bit sequence is obtained.

[0090] Specifically, interleaved bit sequences It can be represented as:

[0091] ;

[0092] in, This represents a subsequence of encoded bits generated from nodes of the same type of variable. The number of times a variable node is promoted (i.e., the number of encoded bits generated by the same type of variable node). The number of encoded bits transmitted. , This represents the number of variable nodes in the original model graph.

[0093] In the original model diagram, The degree of each variable node is often different. After obtaining the degree of each variable node, sort them in descending order according to their degree to obtain the variable node index sequence. for:

[0094] ;

[0095] in, Sort by degree in descending order, and then rank 1st. The index value corresponding to the variable node, .

[0096] According to the variable node index sequence The interleaved bit sequence is rearranged to obtain the rearranged bit sequence. .

[0097] Step 103: Construct a set of tag bits based on the order of the constellation diagram, and then sort the tags according to their mutual information within the set, dividing them into multiple subsets of tag bits.

[0098] A constellation diagram is a graphic used in digital modulation to represent the amplitude and phase combinations corresponding to different symbols. Its order determines the number of bits that a single symbol can carry.

[0099] The tag bit set refers to the set of all bits corresponding to a single modulation symbol, determined by the constellation order. Each bit is used to distinguish different modulation symbols.

[0100] Mutual information refers to the degree of correlation between each tag bit and the received original information bit sequence. The greater the mutual information, the higher the reliability of tag bit transmission.

[0101] A tag bit subset refers to several subsets obtained by splitting the sorted tag bit set according to a preset rule. Each subset contains tag bits with similar reliability.

[0102] In this embodiment, the number of tag bits required for a single modulation symbol is determined according to the constellation order corresponding to the selected modulation scheme, thereby constructing a complete tag bit set. By calculating the average mutual information between each tag bit and its received bit sequence, all bits in the tag bit set are reliably sorted according to the average mutual information. The sorted tag bit set is then divided according to the ratio between the number of tag bits for a single modulation symbol and a preset value, thereby dividing the tag bit set into multiple tag bit subsets.

[0103] It should be noted that, in addition to directly calculating the average mutual information, a weighted mutual information calculation method can also be used when calculating mutual information. This method introduces the position weight of the tag bit in the constellation diagram and assigns higher weight coefficients to tag bits that are easily disturbed, such as those at the edge.

[0104] In one example of the present invention, step 103 may include the following sub-steps S11-S15:

[0105] S11. Calculate the binary logarithm based on the order of the constellation diagram to obtain the number of bits in the set;

[0106] S12. Create a tag bit set according to the number of bits in the set;

[0107] S13. Calculate the mutual information of each tag bit in the tag bit set;

[0108] S14. Sort each tag bit in the tag bit set in descending order according to the mutual information to obtain the tag bit update set;

[0109] In this embodiment, after selecting the modulation scheme and the constellation diagram used by the modulation scheme, the total number of tag bits that a single modulation symbol can carry, i.e., the set of bits, is obtained by calculating the binary logarithm of the order of the constellation diagram. Based on this set of bits, a tag bit set containing all tag bits is created, ensuring that the set covers all bit identification requirements of a single modulation symbol. This tag bit set can be represented as:

[0110] ;

[0111] Represent a Constellation The set of all tag bits in the set. This represents the i-th tag bit in a single modulation symbol. , m is the number of bits in the set. .

[0112] After obtaining the tag bit set, the mutual information between each tag bit in the tag bit set and the received signal is calculated using the average mutual information formula to determine the reliability of each tag bit. That is, the greater the mutual information, the higher the reliability.

[0113] Then, based on the mutual information of the tag bits in descending order, the set of tags is updated assuming the rearranged tags are used. for:

[0114] ;

[0115] in, The reliability of each tag bit is That is, the first The first tag bit has the highest reliability; the second... The reliability of the first tag bit is the second highest; and so on, the reliability of the second... The reliability of each tag bit is the lowest. , .

[0116] S15. Divide the tag bit update set into multiple tag bit subsets according to the number of set bits.

[0117] Furthermore, S15 may include the following sub-steps:

[0118] The first ratio between the number of bits in the set and the first value is calculated using a floor function;

[0119] The second ratio between the number of bits in the set and the second value is calculated using a floor function;

[0120] The tag bit update set is divided according to the first ratio to obtain the first tag bit subset and the tag bit subset to be split;

[0121] The tag bit subset to be split is divided according to the second ratio to obtain the second tag bit subset and the third tag bit subset.

[0122] In this embodiment, a floor function is used to calculate the first ratio between the number of bits in the set and a first value, and a floor function is used to calculate the second ratio between the number of bits in the set and a second value, ensuring that the ratio is an integer to satisfy the integer constraint of the number of bits.

[0123] ;

[0124] ;

[0125] in, This represents the floor function. The first ratio, This is the second ratio.

[0126] like Figure 2 As shown, the set is updated from the tag bits according to the first ratio. Extract the corresponding number of tag bits from the beginning (highest reliability level) to form the first tag bit subset. The remaining tag bits form a subset of tag bits to be split. .

[0127] Since the tag bits corresponding to the subset of tag bits to be split have lower reliability, and low-reliability tag bits are more sensitive to delay slot allocation, therefore, the second ratio is used to further split the subset of tag bits to be split. The corresponding number of tag bits are truncated from the beginning (relatively high end of the low reliability bits) to form a second subset of tag bits. The remaining bits of the subset of tag bits to be split constitute the third subset of tag bits. By using two-level quantization to achieve precise separation of bits with different reliability levels, this approach not only aligns with the characteristic that low-reliability bits are more sensitive to delay allocation, but also provides a clear bit classification basis for subsequent delay slot allocation strategies that combine local and global allocation, effectively improving the matching accuracy between delay allocation and bit reliability.

[0128] Furthermore, after obtaining the subset of third-label bits, it can be further split according to a third ratio, which can be... In this embodiment, there is no limit to the specific number of divisions, and the maximum number of divisions is m. The first and second values ​​can also be dynamically optimized in combination with real-time channel quality (such as signal-to-noise ratio and interference intensity): when the channel quality is poor, the first value is increased to expand the proportion of high-reliability bits, and the second value is decreased to refine the division of low-reliability bits; when the channel quality is good, the parameters are adjusted in reverse to balance transmission performance and processing efficiency.

[0129] Step 104: Allocate delay time slots to tag bits within each tag bit subset;

[0130] Delayed time slots refer to the time intervals allocated for tag bits to be transmitted across time slots. By delaying the transmission of different tag bits, the reliability of bit detection is improved by utilizing the prior information of the receiver.

[0131] In this embodiment, for each subset of tag bits based on its reliability level, a strategy combining local and global allocation is employed to allocate delay slots for each tag bit within that subset. For subsets of tag bits with lower reliability, local allocation is performed based on the detailed reliability levels of the bits within the subset, assigning differentiated delay slots to different detailed levels. For subsets of tag bits with higher reliability, a globally unified allocation rule is used to allocate fixed or optimized delay slots, ensuring that the delay allocation adapts to the differences in bit reliability while also meeting the overall system delay constraints.

[0132] In one example of the present invention, step 104 may include the following sub-steps:

[0133] Obtain the number of bit reliability levels corresponding to the third tag bit subset;

[0134] The third tag bit subset is split into multiple fourth tag bit subsets, the number of which is equal to the number of bit reliability levels; each fourth tag bit subset is assigned a reliability index.

[0135] Calculate the difference between the number of bit reliability levels and each reliability index;

[0136] Allocate a delay slot equal to the difference to the corresponding subset of fourth tag bits;

[0137] Calculate the first sum of the number of bit reliability levels and the first preset value;

[0138] Allocate delay slots equal to the number of bit reliability levels to tag bits within the second tag bit subset;

[0139] Allocate a delay slot equal to the first sum to the tag bits within the first tag bit subset.

[0140] In this embodiment, the reliability differences of all tag bits within the third tag bit subset are identified, and the corresponding number of bit reliability levels is statistically obtained. correspond Each tag bit Each tag bit has Different levels of reliability, The number of bit reliability levels is preset to 1. Based on this number, the third tag bit subset is split into an equal number of fourth tag bit subsets, and a unique reliability sequence number is assigned to each fourth tag bit subset, making the sequence number negatively correlated with the reliability level, i.e., the k-th fourth tag bit subset... ( ) corresponding Each tag bit has the same level of reliability, among which, , , , , k is the reliability index.

[0141] For example, such as Figure 2 As shown, when At that time, the fourth tag bit subset ( ) corresponding Each tag bit has the same level of reliability; when At that time, the fourth tag bit subset ( ) corresponding Each tag bit has the same level of reliability; and so on, when At that time, the fourth tag bit subset ( ) corresponding Each tag bit has the same level of reliability.

[0142] For each subset of fourth-label bits, the difference between the number of bit reliability levels and the reliability index of that subset is calculated. This difference is then used as the number of delay slots allocated to the corresponding subset of fourth-label bits, achieving fine-grained delay allocation within low-reliability bits. Specifically, for the k-th subset of fourth-label bits... The corresponding tag bits are assigned a delay. Each time slot.

[0143] For example, when At that time, the fourth tag bit subset The corresponding tag bits are assigned a delay. Each time slot, i.e. ;when At that time, the fourth tag bit subset The corresponding tag bits are assigned a delay. Each time slot, i.e. ; and so on, when At that time, the fourth tag bit subset The corresponding tag bits are assigned a delay. Each time slot, i.e. .

[0144] Subsequently, based on the first preset value preset by the system, a first sum of the number of bit reliability levels and the first preset value is calculated; a number of delay slots equal to the number of bit reliability levels is allocated to all tag bits within the second tag bit subset, and a number of delay slots equal to the first sum is also allocated to all tag bits within the first tag bit subset, completing the global delay slot allocation. Specifically, for the second tag bit subset... The corresponding tag bits are assigned a delay. Each time slot, i.e. First tag bit subset The corresponding tag bits are assigned a delay. Each time slot, i.e. At this point, the number of maximum delay time slots is .

[0145] By combining the aforementioned local allocation with global allocation strategy for delay slot allocation, the total number of delay slots for all tag bits is obtained, thus forming a delay slot allocation scheme. And synchronized to the receiving end, Indicates the first The number of delay slots for each tag bit. By allocating delay slots locally to accommodate differences in low-reliability bits, and combining this with global allocation to ensure the performance of high-reliability bits, the delay sensitivity of different subsets of tag bits is precisely matched. This makes the delay slot allocation highly compatible with the bit reliability, effectively improving the anti-interference capability of low-reliability bits, while avoiding system performance loss caused by excessive delay of high-reliability bits.

[0146] Step 105: Map the rearranged bit sequence into blocks and assign them to the tag bits corresponding to each subset of tag bits, and convert them into modulation symbols according to the constellation diagram;

[0147] Modulation symbols refer to signal units that convert the binary information corresponding to the tag bits into a specific combination of amplitude and phase in a constellation diagram.

[0148] In this embodiment, the rearranged bit sequence is divided into corresponding coded bit sub-blocks according to the number of tag bits contained in each tag bit subset, ensuring that the number of bits in each coded bit sub-block matches the number of bits in the corresponding tag bit subset. After being divided into coded bit sub-blocks, they are mapped one by one to the tag bits in the corresponding tag bit subset. Finally, according to the definition of the constellation diagram, the mapped combination of tag bits and coded bit sub-blocks is converted into the corresponding modulation symbol, thereby realizing the initial conversion from binary information to analog modulation signal.

[0149] In one example of the present invention, step 105 may include the following sub-steps:

[0150] Calculate the number of bit reliability levels corresponding to the third tag bit subset and the second sum of the second preset value;

[0151] Divide and rearrange the bit sequence to obtain multiple coded bit sub-blocks with the same second sum;

[0152] Each encoded bit sub-block is mapped to the tag bit corresponding to the first tag bit subset, the tag bit corresponding to the second tag bit subset, and the tag bit corresponding to each fourth tag bit subset to obtain the tag bit sequence;

[0153] The tag bit sequence is converted into modulation symbols according to the constellation diagram.

[0154] In this embodiment, the obtained rearranged bit sequence is divided into encoded bit sub-blocks. First, the number of bit reliability levels corresponding to the third tag bit subset and the second sum of the second preset value are calculated. , or can be expressed as The second preset value is 2. Based on this second sum, the rearranged bit sequence is divided evenly or adaptively according to the bit allocation ratio corresponding to each tag bit subset (first, second, and fourth tag bit subsets), resulting in coded bit sub-blocks with the same number as the second sum, ensuring that the number of bits in each coded bit sub-block precisely matches the number of bits in the corresponding tag bit subset. Then, following the mapping principle of high-reliability coded bits to high-reliability tag bits, each coded bit sub-block is mapped one by one to the tag bits corresponding to the first tag bit subset, the second tag bit subset, and the third tag bit subset, and combined according to the arrangement order of the tag bits to form a complete tag bit sequence.

[0155] like Figure 2 As shown, rearrange the bit sequence The encoded bits are mapped to tag bits with and without delay. Specifically, the bit sequence is first rearranged... The tag bits within are sorted and divided into Each encoded bit sub-block, i.e. , , , , Among them, encoded bit sub-blocks For the new encoded bit sequence The Middle To the One encoded bit, , For example, when At that time, encode bit sub-blocks For rearranging bit sequences The Middle To the One encoded bit; when At that time, encode bit sub-blocks For rearranging bit sequences The Middle To the One encoded bit; and so on, when At that time, encode bit sub-blocks For rearranging bit sequences The Middle To the One encoded bit.

[0156] Subsequently, the bit sub-blocks are encoded. Mapped to the first tag bit subset The corresponding tag bits (i.e.) ), Encoded bit sub-blocks Mapped to a subset of second-label bits The corresponding tag bits (i.e.) ).when At that time, encode bit sub-blocks Mapped to the fourth tag bit subset The corresponding tag bits (i.e.) ), that is, when At that time, encode bit sub-blocks Mapped to the fourth tag bit subset The corresponding tag bits (i.e.) );when At that time, encode bit sub-blocks Mapped to the fourth tag bit subset The corresponding tag bits (i.e.) ), and so on.

[0157] The scheme summarized in steps 102-105 above forms a novel labeling bit constrained delayed allocation (LBCDA) scheme, which can reasonably allocate delay time slots to label bits and optimize the mapping relationship between encoded bits and label bits with and without delay.

[0158] Finally, based on the selected constellation diagram definition, each corresponding bit combination in the tag bit sequence is converted into the corresponding modulation symbol, completing the conversion from binary coded bits to analog modulated signals.

[0159] For example, with Taking the structured quadrant (SQ) constellation diagram as an example (i.e.) The reliability of different tag bits is as follows: Figure 3 As shown. The set of tag bits arranged according to reliability is as follows. ,therefore, It can be divided into a subset of the first tag bits. and the subset of tag bits to be split Next, the subset of tag bits to be split... Further processing can divide it into a subset of third-label bits. and the fourth tag bit subset Subsequently, the subset of tag bits. , ,and Allocate delay time slots.

[0160] Specifically, firstly, the subset of third tag bits... The corresponding tag bits are allocated a delay time slot. At this time, The corresponding tag bits have only one reliability level, that is, the subset of the fourth tag bits is Therefore, the fourth tag bit subset The corresponding tag bits are assigned a delay. Each time slot. Next, the subset of second tag bits... and the first tag bit subset Allocate delay time slots. Specifically, the subset of second tag bits. The corresponding tag bits are assigned a delay. One time slot; first tag bit subset The corresponding tag bits are assigned a delay. (Right now ( ) time slots.

[0161] Next, the coded bits are rearranged and mapped. If the Accumulate Repeat-4-Jagged Accumulate (AR4JA) code is used as the encoding scheme, it has 4 transmitted variable nodes, and 1024 coded bits are transmitted in each frame. , AR4JA code variable node degree size sequence Therefore, according to After rearranging, the rearranged bit sequence is obtained. .Will They were divided into order Three coded bit sub-blocks (at this time) ),Right now , and .

[0162] Encoded bit sub-blocks For sequence The first to the 512th encoded bits will Mapped to the first tag bit subset The corresponding tag bits, namely the 1st and 2nd tag bits;

[0163] Encoded bit sub-blocks For sequence The 513th to 768th encoded bits will Mapped to a subset of second-label bits The corresponding tag bit, i.e., the 3rd tag bit;

[0164] Finally, encode the bit sub-blocks. For sequence The 769th to 1024th encoded bits will Mapped to the fourth tag bit subset The corresponding tag bit, namely the 4th tag bit.

[0165] Step 106: After modulating the modulation symbol, preprocessing is performed to generate a transmission signal and transmit it to the receiving end through a visible light communication channel; the receiving end is used to decode the transmission signal, generate a decoded bit sequence and output it.

[0166] Visible light communication channels refer to communication channels that use LEDs as the emission light source and visible light as the transmission medium.

[0167] Decoded bit sequence refers to the binary data sequence recovered by the receiving end after demodulating and decoding the transmitted signal sent by the transmitting end.

[0168] In this embodiment, the converted modulation symbols undergo inverse fast Fourier transform, clipping, and cyclic prefix addition to satisfy the intensity modulation constraints of the LED light source, generating a transmission signal. This transmission signal is transmitted to the receiving end via a visible light communication channel. The receiving end sequentially performs cyclic prefix removal, fast Fourier transform, demodulation, deinterleaving, and decoding to generate and output a decoded bit sequence.

[0169] In one example of the present invention, step 106 may include the following sub-steps:

[0170] The modulation symbol is loaded onto the odd subcarriers in the first half, the conjugate signal of the modulation symbol is loaded onto the odd subcarriers in the second half, and the even subcarriers are set to zero to generate a frequency domain signal.

[0171] Perform an inverse fast Fourier transform on the frequency domain signal to generate a time domain signal;

[0172] After clipping the time-domain signal, a cyclic prefix is ​​added to generate the transmission signal;

[0173] The signal is transmitted to the receiving end via a visible light communication channel.

[0174] like Figure 4 As shown, in this embodiment, the generated modulation symbols are sequentially loaded onto the odd-numbered subcarriers of the first half of the OFDM system. Simultaneously, a complex conjugation operation is performed on the modulation symbols to obtain a conjugate signal, which is then loaded onto the corresponding odd-numbered subcarriers of the second half to ensure the frequency domain signal satisfies Hermitian symmetry. The amplitude of all even-numbered subcarriers is set to zero to avoid interference with the effective signal transmission, ultimately forming a frequency domain signal that meets the requirements of the VLC system. Subsequently, the frequency domain signal is input into the inverse fast Fourier transform module to perform an inverse fast Fourier transform operation, synthesizing the multi-carrier signals distributed in the frequency domain into a time domain signal. For the negative components present in the time domain signal, an asymmetric clipping method is used to remove the negative parts, ensuring the signal satisfies the non-negative intensity modulation constraint of the LED, resulting in a non-negative time domain signal. A cyclic prefix of a preset length is added to the beginning of the non-negative time domain signal to cancel inter-symbol interference caused by multipath propagation in the VLC channel. Finally, the transmitted signal with the added cyclic prefix is ​​transmitted to the receiving end through the VLC channel, completing the signal transmission process. This process ensures signal non-negativity through Hermitian symmetric design and asymmetric clipping, while the addition of a cyclic prefix enhances the signal's resistance to multipath interference. This enables the transmitted signal to accurately adapt to the transmission characteristics of the VLC channel, effectively solving the problem that traditional bipolar OFDM signals cannot be directly used in VLC systems, and improving the reliability and stability of signal transmission.

[0175] Specifically, after allocating delay slots for each coded bit sub-block, each coded bit sub-block is mapped to a slot of length [length missing]. of Quadrature amplitude modulation (QAM) symbol sequence, Subsequently, the modulation symbol is loaded onto the first half of the odd-numbered subcarriers, while the second half of the odd-numbered subcarriers carries the conjugate signal of the modulation symbol. It is fed into the Inverse Fast Fourier Transform (IFFT) module. Point IFFT transform, where, , It is the number of OFDM symbols in a frame of signal. Frequency domain signal. It satisfies the Hermitian symmetry property, that is ,in, It is the number of subcarriers. It is an odd number and The asterisk (*) represents the conjugate operation on complex numbers. The time-domain signal obtained after IFFT is... A non-negative clipped signal is generated after clipping processing. ,in,

[0176] ;

[0177] Subsequently, a length of The cyclic prefix (CP) is inserted into the clipped signal. The header. The clipped signal with CP is sent into the VLC channel for transmission. In the VLC channel, the channel impulse response is... ,in, It is the coefficient of the generalized Lambertian radiator. It is the scattering component. It is the Dirac function. This is the delay between the line-of-sight signal and the scattered signal. In a VLC scenario, considering the influence of LED bandwidth, the equivalent channel impulse response is... ,in, It refers to the responsivity of the photodetector (PD). It's a convolution operation. It is the pulse response of the LED. It refers to the LED bandwidth.

[0178] In one example of the present invention, the receiving end is specifically used for:

[0179] When a transmitted signal is received, the cyclic prefix of the transmitted signal is removed to obtain the signal to be transformed;

[0180] Perform a Fast Fourier Transform on the signal to be transformed to obtain the frequency domain signal to be extracted;

[0181] Extract the frequency domain signal within the odd-numbered subcarriers in the first half of the frequency domain signal to be extracted to obtain the frequency domain signal to be demodulated.

[0182] The demodulator demodulates the frequency domain signal to be demodulated, and obtains the log-likelihood ratio sequence corresponding to the frequency domain signal to be demodulated.

[0183] The log-likelihood ratio sequence is subjected to inverse bit delay to obtain the uninterrupted log-likelihood ratio sequence;

[0184] The log-likelihood ratio sequence to be decoded is de-interleaved to obtain the log-likelihood ratio sequence to be decoded.

[0185] The original model diagram decoder decodes the log-likelihood ratio sequence to be decoded, generates a decoded bit sequence, and outputs it.

[0186] Furthermore, the receiving end is specifically used for:

[0187] The original model decoder decodes the log-likelihood ratio sequence to be decoded, generating a decoded bit sequence and an external log-likelihood ratio sequence.

[0188] An external log-likelihood ratio sequence is input to the demodulator to assist in demodulating the frequency domain signal to be demodulated under different time slot delays.

[0189] The Log-Likelihood Ratio (LLR) sequence refers to the sequence of probabilities of the quantization tag bit being 0 or 1 output by the demodulator. The sign and magnitude of the value directly reflect the confidence level of the bit value.

[0190] The uninterleaved log-likelihood ratio sequence refers to the LLR sequence obtained after inverse bit delay processing, which still retains the bit position scrambling state caused by the interleaving operation at the transmitter.

[0191] The log-likelihood ratio sequence to be decoded refers to the LLR sequence after deinterleaving, in which both timing and position are restored to the original encoded state. It is the direct input of the original pattern diagram decoder.

[0192] The external log-likelihood ratio sequence refers to the auxiliary sequence generated by the original modulus decoder during the decoding process, which reflects the correlation information between coded bits and can be used to improve the demodulation accuracy of signals with different time slot delays.

[0193] In this embodiment, in time slot , No. The received time-domain OFDM signal, i.e., the transmitted signal The discrete form can be expressed as:

[0194] ;

[0195] in, yes Discrete form ( , ), The mean is 0 and the variance is Additive white Gaussian noise, This is the one-sided power spectral density. Furthermore, the signal-to-noise ratio formula for an electrical signal is... ,in, , ,as well as These are the number of odd subcarriers used, the average energy of each subcarrier, and the coding rate, respectively. Then, from the... The CP is removed from the received OFDM time-domain signal, and the signal to be transformed is fed into the Fast Fourier Transform (FFT) module for processing. The frequency domain signal to be extracted is obtained after point FFT transformation. Since only the first half of the odd-numbered subcarriers carry the modulation signal, the frequency domain signal, i.e., the frequency domain signal to be demodulated, is extracted from the corresponding subcarriers. The signal is then sent to a demodulator for demodulation. Assuming perfect channel state information, for the signal... Demodulation can be divided into two parts: demodulation of the coded bit with the maximum delay and demodulation of other coded bits. Specifically, for the coded bit with the maximum delay (i.e., demodulation of the coded bit with the maximum delay...) The LLR of () is calculated as shown in the following formula:

[0196] ;

[0197] in, Indicates the first The signal received on each subcarrier Indicates the first Frequency domain channel fading coefficients on each subcarrier Indicates in time slot Time The estimated symbols on each subcarrier, Indicates the first Each tag bit is ( A subset of symbols. For other coded bits (i.e. The LLR of () is calculated as shown in the following formula:

[0198] ;

[0199] in, Indicates encoded bits for External information and , , When all signals After the associated sub-blocks are demodulated, the LLR is fed into the inverse bit delay module and the deinterleaver to obtain the codeword. The LLR of all encoded bits is generated. The LLR is then fed into the original pattern decoder for decoding to obtain the decoded bit sequence. Simultaneously, the codeword is output. The external LLR is used to assist in demodulating the coded bits in other time slots. Finally, all codewords are recovered by repeating the above operation, generating the decoded bit sequence and outputting it.

[0200] In the specific implementation, the bit error rate performance of AR4JA code under different delay allocation schemes was simulated based on the DACO-OFDM system. The simulation parameters of VLC channel under the DACO-OFDM system are shown in Table 1.

[0201] Table 1

[0202]

[0203] As can be seen from Table 1 above, the modulation bandwidth... The highest frequency at which signals can be transmitted in a DACO-OFDM system is defined as 100MHz. LED bandwidth. This is used to limit the maximum modulation frequency of the LED, the core signal transmitting device at the transmitting end, in visible light communication; specifically, it limits the maximum modulation frequency of the LED to 40MHz. (Subcarrier spacing...) Based on modulation bandwidth and total number of subcarriers The calculated value represents the frequency spacing between adjacent subcarriers. A smaller spacing results in a larger number of subcarriers and higher spectral efficiency, but also greater sensitivity to frequency shifts. PD detection area. The photosensitive area of ​​the photodetector; the larger the area, the more optical power it can receive, thus improving the receiving sensitivity. PD responsivity This represents the efficiency of the PD in converting received optical power into electrical signal current. In this embodiment, a normalized ideal value is used, but its specific value can also be set to less than 1. PD half-power field of view. This refers to the maximum angular range within which a PD can effectively receive optical signals. LED half-power angle. The emission angle used to describe the light intensity distribution characteristics of an LED, i.e., the emission angle at which the light intensity attenuates to half of its maximum value. In this embodiment, a 60° half-power angle means that the LED's light signal attenuates by no more than 3dB within a 60° range, making it suitable for scenarios where indoor uniform lighting and communication are integrated, balancing coverage and signal strength. PD optical filter gain The transmittance of optical components used to filter out ambient light (such as sunlight) and stray light. A gain of 1 represents ideal filtering (no additional attenuation). In practice, different filter coefficients are selected depending on the scenario to improve the system's signal-to-noise ratio. PD concentrator gain. This refers to the gain achieved by focusing incident light onto the photosensitive surface of the PD through structures such as optical lenses. A value of 1 indicates no additional gain; its main function is to enhance received optical power, thereby increasing the system's communication range and anti-interference capability. The delay between the line-of-sight signal and the scattered signal. This refers to the time difference between the arrival of a line-of-sight direct signal and a non-line-of-sight scattered (reflected) signal at the receiver. Spatial reflection coefficient. This represents the light reflectivity of reflective surfaces such as walls and ceilings. A value of 0.4 indicates that 40% of the incident light is reflected.

[0204] The AR4JA code has a bit length of 2560 and a code rate of The detector uses the maximum a posteriori probability algorithm, and the decoder uses the belief propagation (BP) algorithm with 50 BP iterations. Simulation results are as follows: Figure 5 As shown, the bit error rates of the traditional no-delay allocation scheme, the random delay allocation scheme, and the proposed LBCDA scheme are illustrated. It can be seen that compared with the traditional no-delay allocation scheme and the random delay allocation scheme, the novel LBCDA scheme proposed in this embodiment of the invention has a very significant advantage in bit error rate performance.

[0205] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0206] The following describes the information transmission device based on tag bit delay allocation provided in the embodiments of the present invention. The information transmission device based on tag bit delay allocation described below can be referred to in correspondence with the information transmission method based on tag bit delay allocation described above.

[0207] Please see Figure 6 , Figure 6 This invention illustrates an information transmission device based on tag bit delay allocation, applied at a transmitting end. The device includes:

[0208] The bit sequence preprocessing module 601 is used to encode the original information bit sequence by the original pattern encoder when the original information bit sequence is received, and then interleave it by the interleaver to generate an interleaved bit sequence.

[0209] The bit sequence rearrangement module 602 is used to rearrange the interleaved bit sequence according to the variable node degree of the original model in the original model encoder to obtain the rearranged bit sequence.

[0210] The tag bit subset partitioning module 603 is used to construct a tag bit set based on the order of the constellation diagram, and then divide it into multiple tag bit subsets after sorting the reliability according to the mutual information of each tag bit in the tag bit set.

[0211] The delay time slot allocation module 604 is used to allocate delay time slots to tag bits within each tag bit subset;

[0212] The bit sequence block mapping module 605 is used to map the rearranged bit sequence blocks to the tag bits corresponding to each tag bit subset, and convert them into modulation symbols according to the constellation diagram;

[0213] The signal transmission module 606 is used to modulate the modulation symbol and perform pre-transmission processing to generate a transmission signal and transmit it to the receiving end through a visible light communication channel; the receiving end is used to decode the transmission signal, generate a decoded bit sequence and output it.

[0214] Optionally, the bit sequence rearrangement module 602 is specifically used for:

[0215] Based on the variable node degree of the original model graph in the original model graph encoder, sort the multiple variable nodes of the original model graph to obtain the variable node index sequence;

[0216] The interleaved bit sequence is rearranged according to the variable node index sequence to obtain the rearranged bit sequence.

[0217] Optionally, the tag bit subset partitioning module 603 includes:

[0218] The quantity calculation submodule is used to calculate the binary logarithm based on the order of the constellation diagram to obtain the number of bits in the set;

[0219] The tag bit set creation submodule is used to create tag bit sets according to the number of bits in the set;

[0220] The mutual information calculation submodule is used to calculate the mutual information of each tag bit within the tag bit set;

[0221] The tag bit sorting submodule is used to sort each tag bit in the tag bit set in descending order according to each mutual information to obtain the updated tag bit set.

[0222] The subset partitioning submodule is used to divide the tag bit update set into multiple tag bit subsets based on the number of set bits.

[0223] Optionally, the subset partitioning submodule is specifically used for:

[0224] The first ratio between the number of bits in the set and the first value is calculated using a floor function;

[0225] The second ratio between the number of bits in the set and the second value is calculated using a floor function;

[0226] The tag bit update set is divided according to the first ratio to obtain the first tag bit subset and the tag bit subset to be split;

[0227] The tag bit subset to be split is divided according to the second ratio to obtain the second tag bit subset and the third tag bit subset.

[0228] Optionally, the delay time slot allocation module 604 is specifically used for:

[0229] Obtain the number of bit reliability levels corresponding to the third tag bit subset;

[0230] The third tag bit subset is split into multiple fourth tag bit subsets, the number of which is equal to the number of bit reliability levels; each fourth tag bit subset is assigned a reliability index.

[0231] Calculate the difference between the number of bit reliability levels and each reliability index;

[0232] Allocate a delay slot equal to the difference to the corresponding subset of fourth tag bits;

[0233] Calculate the first sum of the number of bit reliability levels and the first preset value;

[0234] Allocate delay slots equal to the number of bit reliability levels to tag bits within the second tag bit subset;

[0235] Allocate a delay slot equal to the first sum to the tag bits within the first tag bit subset.

[0236] Optionally, the bit sequence block mapping module 605 is specifically used for:

[0237] Calculate the number of bit reliability levels corresponding to the third tag bit subset and the second sum of the second preset value;

[0238] Divide and rearrange the bit sequence to obtain multiple coded bit sub-blocks with the same second sum;

[0239] Each encoded bit sub-block is mapped to the tag bit corresponding to the first tag bit subset, the tag bit corresponding to the second tag bit subset, and the tag bit corresponding to each fourth tag bit subset to obtain the tag bit sequence;

[0240] The tag bit sequence is converted into modulation symbols according to the constellation diagram.

[0241] Optionally, the signal transmission module 606 is specifically used for:

[0242] The modulation symbol is loaded onto the odd subcarriers in the first half, the conjugate signal of the modulation symbol is loaded onto the odd subcarriers in the second half, and the even subcarriers are set to zero to generate a frequency domain signal.

[0243] Perform an inverse fast Fourier transform on the frequency domain signal to generate a time domain signal;

[0244] After clipping the time-domain signal, a cyclic prefix is ​​added to generate the transmission signal;

[0245] The signal is transmitted to the receiving end via a visible light communication channel.

[0246] Optionally, the receiving end is specifically used for:

[0247] When a transmitted signal is received, the cyclic prefix of the transmitted signal is removed to obtain the signal to be transformed;

[0248] Perform a Fast Fourier Transform on the signal to be transformed to obtain the frequency domain signal to be extracted;

[0249] Extract the frequency domain signal within the odd-numbered subcarriers in the first half of the frequency domain signal to be extracted to obtain the frequency domain signal to be demodulated.

[0250] The demodulator demodulates the frequency domain signal to be demodulated, and obtains the log-likelihood ratio sequence corresponding to the frequency domain signal to be demodulated.

[0251] The log-likelihood ratio sequence is subjected to inverse bit delay to obtain the uninterrupted log-likelihood ratio sequence;

[0252] The log-likelihood ratio sequence to be decoded is de-interleaved to obtain the log-likelihood ratio sequence to be decoded.

[0253] The original model diagram decoder decodes the log-likelihood ratio sequence to be decoded, generates a decoded bit sequence, and outputs it.

[0254] Optionally, the receiving end is also specifically used for:

[0255] The original model decoder decodes the log-likelihood ratio sequence to be decoded, generating a decoded bit sequence and an external log-likelihood ratio sequence.

[0256] An external log-likelihood ratio sequence is input to the demodulator to assist in demodulating the frequency domain signal to be demodulated under different time slot delays.

[0257] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or modules may be electrical, mechanical, or other forms.

[0258] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0259] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0260] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An information transmission method based on tag bit delay allocation, characterized in that, Applied to the sending end, the method includes: When the original information bit sequence is received, it is encoded by the original pattern encoder and then interleaved by the interleaver to generate an interleaved bit sequence. Based on the variable node degree of the original model graph in the original model graph encoder, the interleaved bit sequence is rearranged to obtain the rearranged bit sequence; A set of tag bits is constructed based on the order of the constellation diagram, and after reliability sorting according to the mutual information of each tag bit in the set, it is divided into multiple subsets of tag bits. Distribute delay time slots to the tag bits within each of the aforementioned subsets of tag bits; The rearranged bit sequence is divided into blocks and mapped to the tag bits corresponding to each subset of tag bits, and then converted into modulation symbols according to the constellation diagram; The modulation symbol is modulated and then preprocessed before transmission to generate a transmission signal, which is transmitted to the receiving end through a visible light communication channel. The receiving end is used to decode the transmission signal, generate a decoded bit sequence, and output it.

2. The information transmission method based on tag bit delay allocation according to claim 1, characterized in that, The step of rearranging the interleaved bit sequence according to the variable node degree of the original pattern graph in the original pattern graph encoder to obtain the rearranged bit sequence includes: According to the variable node degree of the original model graph in the original model graph encoder, sort the multiple variable nodes of the original model graph to obtain the variable node index sequence; The interleaved bit sequence is rearranged according to the variable node index sequence to obtain the rearranged bit sequence.

3. The information transmission method based on tag bit delay allocation according to claim 1, characterized in that, The step of constructing a tag bit set based on the order of the constellation diagram, and then dividing it into multiple tag bit subsets after reliability sorting according to the mutual information of each tag bit in the tag bit set, includes: The number of bits in the set is obtained by calculating the binary logarithm based on the order of the constellation diagram. Create a tag bit set according to the number of bits in the set; Calculate the mutual information of each tag bit within the tag bit set; Sort each tag bit in the tag bit set in descending order according to the mutual information to obtain the tag bit update set; The tag bit update set is divided into multiple tag bit subsets based on the number of bits in the set.

4. The information transmission method based on tag bit delay allocation according to claim 3, characterized in that, The step of dividing the tag bit update set into multiple tag bit subsets based on the number of bits in the set includes: The first ratio between the number of bits in the set and the first value is calculated using a floor function; The second ratio between the number of bits in the set and the second value is calculated using a floor function; The tag bit update set is divided according to the first ratio to obtain a first tag bit subset and a tag bit subset to be split; The subset of tag bits to be split is divided according to the second ratio to obtain a second subset of tag bits and a third subset of tag bits.

5. The information transmission method based on tag bit delay allocation according to claim 4, characterized in that, The step of allocating delay time slots to tag bits within each subset of tag bits includes: Obtain the number of bit reliability levels corresponding to the subset of third tag bits; The third tag bit subset is split into multiple fourth tag bit subsets, the number of which is equal to the number of the bit reliability levels; each fourth tag bit subset is assigned a reliability index. Calculate the difference between the number of reliability levels of the bit and each reliability sequence number; Allocate a delay slot equal to the difference to the corresponding subset of fourth tag bits; Calculate the first sum of the number of bit reliability levels and the first preset value; Allocate delay slots equal to the number of the bit reliability levels to the tag bits within the second tag bit subset; Allocate a delay slot equal to the first sum to the tag bits within the first tag bit subset.

6. The information transmission method based on tag bit delay allocation according to claim 5, characterized in that, The step of mapping the rearranged bit sequence into blocks corresponding to the tag bits of each subset of tag bits, and converting it into modulation symbols according to the constellation diagram, includes: Calculate the second sum of the number of bit reliability levels corresponding to the third tag bit subset and the second preset value; Divide the rearranged bit sequence to obtain multiple coded bit sub-blocks that are equal to the second sum; Each of the coded bit sub-blocks is mapped to the tag bit corresponding to the first tag bit subset, the tag bit corresponding to the second tag bit subset, and the tag bit corresponding to each of the fourth tag bit subsets to obtain a tag bit sequence; The tag bit sequence is converted into modulation symbols according to the constellation diagram.

7. The information transmission method based on tag bit delay allocation according to claim 1, characterized in that, The step of modulating the modulation symbol, performing pre-transmission processing, generating a transmission signal, and transmitting it to the receiving end through a visible light communication channel includes: The modulation symbol is loaded onto the odd subcarriers in the first half, the conjugate signal of the modulation symbol is loaded onto the odd subcarriers in the second half, and the even subcarriers are set to zero to generate a frequency domain signal. Perform an inverse fast Fourier transform on the frequency domain signal to generate a time domain signal; After clipping the time-domain signal, a cyclic prefix is ​​added to generate the transmission signal; The transmitted signal is transmitted to the receiving end via a visible light communication channel.

8. The information transmission method based on tag bit delay allocation according to claim 1, characterized in that, The receiving end is specifically used for: When the transmitted signal is received, the cyclic prefix of the transmitted signal is removed to obtain the signal to be transformed; Perform a Fast Fourier Transform on the signal to be transformed to obtain the frequency domain signal to be extracted; The frequency domain signal within the odd-numbered subcarriers in the first half of the frequency domain signal to be extracted is extracted to obtain the frequency domain signal to be demodulated. The frequency domain signal to be demodulated is demodulated by a demodulator to obtain the log-likelihood ratio sequence corresponding to the frequency domain signal to be demodulated. The log-likelihood ratio sequence is subjected to inverse bit delay to obtain the uninterleaved log-likelihood ratio sequence; The uninterleaved log-likelihood ratio sequence is deinterleaved to obtain the log-likelihood ratio sequence to be decoded; The log-likelihood ratio sequence to be decoded is decoded using a primitive model decoder to generate and output a decoded bit sequence.

9. The information transmission method based on tag bit delay allocation according to claim 8, characterized in that, The receiving end is further used for: The log-likelihood ratio sequence to be decoded is decoded by the original model diagram decoder to generate a decoded bit sequence and an external log-likelihood ratio sequence. The external log-likelihood ratio sequence is input to the demodulator to assist in demodulating the frequency domain signal to be demodulated under different time slot delays.

10. An information transmission device based on tag bit delay allocation, characterized in that, Applied to the transmitting end, the device includes: The bit sequence preprocessing module is used to encode the original information bit sequence by the original pattern encoder when the original information bit sequence is received, and then interleave it by the interleaver to generate an interleaved bit sequence. The bit sequence rearrangement module is used to rearrange the interleaved bit sequence according to the variable node degree of the original pattern in the original pattern encoder to obtain a rearranged bit sequence. The tag bit subset partitioning module is used to construct a tag bit set based on the order of the constellation diagram, and then divide it into multiple tag bit subsets after sorting the reliability according to the mutual information of each tag bit in the tag bit set. The delay time slot allocation module is used to allocate delay time slots to tag bits within each of the said tag bit subsets; The bit sequence block mapping module is used to map the rearranged bit sequence blocks to the tag bits corresponding to each of the tag bit subsets, and convert them into modulation symbols according to the constellation diagram; The signal transmission module is used to modulate the modulation symbol and perform pre-transmission processing to generate a transmission signal and transmit it to the receiving end through a visible light communication channel; the receiving end is used to decode the transmission signal, generate a decoded bit sequence and output it.

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