Automatic address allocation method, device and system for bus device and medium
By using a cascading response mechanism between bus devices and a hardware bias circuit, automatic address configuration of bus devices is achieved, solving the problems of errors and timing issues caused by manual operation, and improving the success rate and efficiency of addressing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN XBROTHER TECH
- Filing Date
- 2025-12-04
- Publication Date
- 2026-04-21
AI Technical Summary
The existing bus device address allocation method relies on manual operation, which is prone to errors. Furthermore, it cannot automatically address devices when there is no host or the device fails, resulting in timing issues and high maintenance costs.
A cascading response mechanism between bus devices is adopted. The device status is determined by the level status of the cascading input port. Automatic address configuration between devices is achieved by using response messages, eliminating timing dependencies, reducing host interaction, and using hardware bias circuits to ensure that the initial state is determined.
It achieves automatic addressing without host intervention, improves the success rate and efficiency of addressing, reduces human error and timing mismatch, and is suitable for efficient addressing in both hostless and host-based scenarios.
Smart Images
Figure CN121907818A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of industrial communication technology, and in particular to a method, device, system and medium for automatic address allocation of bus devices. Background Technology
[0002] In fields such as data center monitoring and industrial control, bus communication is primarily represented by RS485. RS485 bus is widely used due to its simple wiring and long transmission distance. In RS485 bus systems, a master-slave communication mode is typically used. To achieve accurate communication between the master and a specific slave device, each slave device must have a unique communication address within the bus.
[0003] Traditional address allocation methods rely primarily on manual operation, such as setting addresses via DIP switches before equipment installation or writing addresses one by one using a handheld programmer. This method is not only time-consuming and labor-intensive due to the large number of devices, but also prone to address conflicts due to human error when devices are replaced or added, resulting in high maintenance costs.
[0004] To address the issue of manual addressing, some automatic addressing technologies have emerged in related technical solutions. For example, a master-slave cascading method is used. The master sends the first address setting command, the first enabled device responds and sets its address, then enables the next device, and the master sends the second address setting command after receiving the response, and so on, to complete the master's addressing of multiple slave devices.
[0005] However, the existing automatic addressing schemes still have the following significant drawbacks: the entire addressing process must be controlled by the host, which needs to send independent address setting commands to each slave device and wait for a response. If the host fails or the system is in a hostless network debugging mode, the automatic addressing function will be unusable. Furthermore, in the existing scheme, the address allocation command for the next-level device is issued by the host, while the enable signal for the next-level device to enter the receiving state is sent by the previous-level slave device. Since these are two independent devices, the host's address allocation command arrives before the previous-level slave device has completed its enable action, causing the next-level device to be unable to recognize a valid command, resulting in addressing failure or address loss due to timing issues.
[0006] Therefore, this application aims to provide a method that can achieve stable and timing-free addressing between multiple slave devices by utilizing an inter-device cascading response mechanism, without host intervention in addressing. Summary of the Invention
[0007] The main objective of this invention is to provide a method, device, system, and medium for automatic address allocation of bus devices. The aim is to provide an automatic addressing mechanism that can be implemented without timing issues, independent of the host and utilizing inter-device cascading response mechanisms, while also reducing the total addressing time of bus devices.
[0008] To achieve the above objectives, this invention proposes an automatic address allocation method for bus devices, comprising applying to multiple cascaded bus devices, wherein the multiple bus devices are connected in parallel via a communication bus, and between adjacent bus devices, the cascaded output port of the preceding bus device is connected to the cascaded input port of the following bus device, the method comprising: The bus device currently in the addressing enabled state is determined based on the level state of the cascaded input port. The first bus device is initially in the addressing enabled state, and the remaining bus devices are initially in the addressing masked state. Bus devices in the addressing enabled state listen for trigger messages on the communication bus; Configure its own address according to the address information in the trigger message; After configuring its own address, the bus device in the addressing enabled state drives its own cascaded output port to switch the level state, so that the next-level bus device is in the addressing enabled state, and sends a response message carrying its own address information to the communication bus. The response message serves as a trigger message used by the next-level bus device to configure its own address, until all bus devices have completed their configuration.
[0009] Furthermore, the trigger message includes a start message and a recursive message; The startup message is initiated by the host on the communication bus or any of the bus devices, and is used to trigger the bus device in the first position; The recursive message is the response message sent by the previous bus device, which is used to trigger the next bus device to complete the configuration of its own address information.
[0010] Furthermore, configuring its own communication address based on the address information of the trigger message includes: Extract the reference address value from the trigger message; When the trigger message is the start message, the reference address value is reset to the initial value as its own communication address; When the trigger message is the recursive message, the reference address value is incremented, and the incremented reference address value is used as its own communication address.
[0011] Furthermore, the cascaded input port of the bus device is configured with a first impedance element to maintain it in the addressing enabled state, and the cascaded output port is configured with a second impedance element to maintain it in the addressing shielded state. The resistance of the first impedance element is greater than the resistance of the second impedance element; The cascade input port of the bus device is in the addressing enabled state when the signal is valid, and in the addressing masked state when the signal is invalid. The first cascaded input port of the bus device is maintained to the valid signal by the first impedance element, while the cascaded input ports of the remaining bus devices are clamped to the invalid signal by the second impedance element of the preceding bus device, and driven to the valid signal when the cascaded output port of the preceding bus device switches its level.
[0012] Furthermore, bus devices in the addressing enabled state initiate a shielding protection period after completing address configuration; During the shielding protection period, bus devices in the addressing enabled state shield the address information of the trigger message on the communication bus to prevent duplicate addressing.
[0013] Furthermore, it also includes: The bus device initiates a response time after sending a trigger message or receiving a response message. If no new response message is detected on the communication bus within the response time, the address allocation process is determined to be over, and the address information in the last received response message is recorded as the total number of bus devices.
[0014] This application also discloses a bus device, including: The status detection module is used to determine the bus device currently in the addressing enabled state based on the level status of the cascaded input ports. The first bus device is initially in the addressing enabled state, and the remaining bus devices are initially in the addressing masked state. A communication interaction module is used to listen to the trigger messages of the communication bus through a bus device in the addressing enabled state; The address configuration module is used to configure its own address according to the address information in the trigger message; The cascading driver module is used to, after configuring its own address, drive the cascading output port of the bus device in the addressing enabled state to switch the level state, so that the bus device in the next stage is in the addressing enabled state, and send a response message carrying its own address information to the communication bus. The communication interaction module is also used to send a response message carrying its own address information to the communication bus, and the response message is configured as the trigger message of the subsequent bus device.
[0015] Furthermore, it also includes a hardware bias circuit, which includes a first impedance element and a second impedance element. The first end of the first impedance element is electrically connected to the cascaded input port, and the second end of the first impedance element is electrically connected to the first reference potential; The first end of the second impedance element is electrically connected to the cascaded output port, and the second end of the second impedance element is electrically connected to the second reference potential; The resistance of the first impedance element is greater than the resistance of the second impedance element; The cascaded input port and cascaded output port are respectively connected to the status detection module and the cascaded drive module through electrical isolation devices.
[0016] This application also discloses an automatic bus address allocation system, including multiple bus devices as described above; Multiple bus devices are connected in parallel via a communication bus, and between adjacent bus devices, the cascade output port of the previous stage bus device is connected to the cascade input port of the next stage bus device; The first bus device or the host connected to the bus device sends a startup message. The first bus device configures its own address based on the startup message and sends a response message to the bus. Subsequent bus devices configure their own addresses in turn using the response messages of the previous bus device.
[0017] This application also discloses a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the above-described method for automatic address allocation of bus devices.
[0018] The above technical solution has the following advantages: This application solves the problem of repeated interaction between the master and slave in traditional solutions by using the response message sent by the bus device as the trigger message for the subsequent bus device. The response message sent by the preceding bus device after configuration is directly captured by the subsequent device and used as the trigger message, realizing automatic cascading addressing between bus devices. Only one start message needs to be sent on the bus; subsequent processes are completed autonomously between the bus devices. This is not only suitable for masterless scenarios, achieving decentralization, but also eliminates timing errors caused by response delays between the master and slave by eliminating the cascading input ports and trigger messages from the preceding bus device, greatly improving the addressing success rate.
[0019] This application also applies to the addressing state of the host. The response message on the bus is used to inform the host that the configuration is complete. On the other hand, the response message directly serves as the trigger message for the next level bus device. The host only needs to send a start message once in the whole process. After that, the host only needs to passively receive the response message on the bus. There is no need to repeatedly send allocation instructions, which reduces the number of data packets on the bus and the interaction waiting time, and improves the addressing efficiency of the bus device.
[0020] By using the level states of the cascaded input ports and hardware bias circuits, the system ensures that the first bus device and the subsequent bus device have a definite initial state at the physical level, avoiding ambiguity in software logic judgments, solving the problem of the first bus device being prone to malfunction or having an uncertain state, improving the system's anti-interference capability and reliability, and also ensuring that the cascaded input ports of the first bus device are always at an effective level, which helps to facilitate the smooth implementation of decentralization.
[0021] This application sets a shielding protection period during which bus devices will not respond to subsequent trigger messages, thus preventing bus devices from continuously receiving trigger messages and re-addressing after the initial addressing is completed, and ensuring the uniqueness and accuracy of address allocation for multiple bus devices. Attached Figure Description
[0022] The present invention will now be described in detail with reference to specific embodiments and accompanying drawings, wherein: Figure 1 This is a flowchart of the automatic address allocation method of the present invention; Figure 2 This is a schematic diagram of the hostless structure of the present invention; Figure 3 This is a schematic diagram of the structure of the host computer of the present invention; Figure 4 This is a schematic diagram of the hardware bias circuit of the present invention; Figure 5 This is a structural block diagram of the bus device of the present invention.
[0023] In the diagram: 100, bus device; 200, first impedance element; 300, second impedance element; 400, host; 500, first optocoupler; 600, second optocoupler. Detailed Implementation
[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the following specific embodiments are only used to explain the invention and do not constitute a limitation thereof.
[0025] like Figures 1 to 3As shown, this application includes a communication bus and multiple bus devices 100 mounted on the bus, namely the slave devices mentioned in the background art. Hereinafter, they will be referred to as bus devices 100. The communication bus can adopt the A and B lines of an RS485 bus. Multiple bus devices 100 are connected in parallel through the communication bus to realize data interaction. RS485 is only one type of bus communication method. Other methods can also be used, such as CAN bus.
[0026] This embodiment provides an automatic address allocation method for bus devices, applied to multiple cascaded bus devices 100. The multiple bus devices 100 are connected in parallel via a communication bus, and between adjacent bus devices 100, the cascade output port of the previous stage bus device 100 is connected to the cascade input port of the next stage bus device 100. The method includes the following steps: Step S1: Determine the bus device 100 currently in the addressing enabled state based on the level state of the cascaded input port. The first bus device 100 is initially in the addressing enabled state, and the remaining bus devices 100 are initially in the addressing masked state.
[0027] In this embodiment, the bus device 100 determines whether it is in the addressing state by detecting the level of its own cascade input port. Due to the configuration of the hardware bias circuit described below, the cascade input port of the first bus device 100 in the cascade link is in a floating state and is not connected to the previous level device. It is preferably pulled low to a low level by the hardware bias circuit, so as to be identified as a valid signal. The bus device 100 determines that it is in the addressing enabled state.
[0028] For the remaining bus devices 100, their cascade input ports are connected to the cascade output ports of the preceding bus device 100 and are pulled up by the cascade output ports of the preceding bus device 100. The cascade input ports of the remaining bus devices 100 are maintained at a high level, i.e., an invalid signal, thus determining that they are in an addressable masked state. Based on the initial state determination of the hardware bias circuit, the uncertainty of traditional software logic is avoided. In addition, the low level as a valid signal and the high level as an invalid signal in this embodiment is only one implementation method. It is also possible to use the high level as a valid signal and the low level as an invalid signal. This embodiment does not limit this, but by choosing the method of using the low level as a valid signal, the first bus device 100 can always be in the addressable enabled state, so that the subsequent host 400 does not need to perform the addressing startup operation, which is conducive to achieving decentralization.
[0029] Step S2: The bus device 100 in the addressing enabled state listens for trigger messages on the communication bus. When the bus device 100 confirms that it is in the addressing enabled state, it starts listening to the communication bus and waits to receive trigger messages that conform to the preset protocol format. The bus device 100 in the addressing disabled state, although also connected to the communication bus, will logically ignore the address configuration instructions in the trigger messages.
[0030] This embodiment further explains the trigger message, which includes the start message and the recursive message. In order to adapt to different application scenarios, the system defines a unified message format, such as using an 8-byte instruction structure.
[0031] The startup message is initiated by the host 400 or any bus device 100 on the communication bus, and is used to trigger the first bus device 100. The startup message has a specific identifier. For example, the first byte of the message is set to FF, indicating that it is an actively initiated addressing packet. The second byte can be written with the address function code, such as 05. The third and fourth bytes can be a specific code, such as F0 03. The fifth and sixth bytes are the starting address of the address information, with values from 0000 to 00FE. The seventh and eighth bytes are the CRC checksum of the first six bytes. The first addressing packet is like this: FF 05 F0 03 00 00 1B 14.
[0032] Step S3: Configure its own address according to the address information in the trigger message. The bus device 100 in the addressing enabled state parses the received trigger message, extracts the reference address information contained therein, and generates and writes its own communication address according to the reference address information. The written communication address is stored in its own memory, thereby realizing the addressing of the bus device 100.
[0033] Step S4: After configuring its own address, the bus device 100 in the addressing enabled state drives its cascade output port to switch its level, enabling the next-level bus device 100 to be in the addressing enabled state, and sends a response message carrying its own address information to the communication bus. Specifically, after the current bus device 100 completes the address writing, it controls the internal circuit to drive the cascade output port from high level to low level. Because the cascade output port of the bus device 100 is connected to the cascade input port of the next-level bus device 100, the cascade input port of the next-level bus device 100 becomes low, causing the next-level bus device 100 to switch from the address masking state to the address enable state. At the same time, the bus device 100 broadcasts a response message carrying its own address information to the communication bus. When the bus device 100 sends the response message to the communication bus and the cascade output port of the bus device 100 outputs a low level, the two can be sent simultaneously. Preferably, the cascade output port of the bus device 100 outputs a low level first, so that the next-level bus device 100 switches to the address enable state and the next-level bus device 100 is in a state of waiting to receive the response message in advance.
[0034] It is particularly important to note that this embodiment solves the timing race problem in traditional solutions. In the prior art, address allocation instructions are typically issued by the host 400, while the enable signal is executed by the preceding bus device 100. These two signals originate from different devices, leading to the risk of timing errors in the arrival of the host 400's address allocation instructions and enable signal, resulting in addressing failure. In this application, however, the enable action and the transmission of the trigger message are independently controlled by the preceding bus device 100. The bus device 100 prioritizes driving the cascaded output port OUT low to ensure that the cascaded input port IN of the subsequent device is physically stable at a valid level before sending a response message to the bus. Thus, relying solely on a single bus device 100 to enable and send trigger messages for the subsequent bus device 100 eliminates the timing coordination errors caused by response delays between the host 400 and the bus device 100, greatly improving the addressing success rate.
[0035] The response message serves as the trigger message for the subsequent bus device 100 to configure its own address, until all bus devices 100 have completed configuration. Upon detecting a low cascading input port, the subsequent bus device 100 switches to the addressing enable state and captures the response message sent by the preceding bus device 100. When the subsequent bus device 100 receives the response message and the cascading input port is low, it uses the preceding bus device 100's response message as its own addressing trigger message and repeats the above configuration, driving, and sending process, forming a cascading automatic addressing flow until the last bus device 100 completes addressing.
[0036] In scenarios without a master 400, such as field debugging or self-organizing network applications, any bus device 100 can send the start message through human-machine interaction. In this application, the first bus device 100 is initially in an enabled state, and it does not need to use the addressing instruction of the master 400 to send the trigger message. It only needs to broadcast the trigger message on the communication bus. Any bus device 100 can broadcast the trigger message to the communication bus, such as through human-machine interaction buttons, human-machine interaction pages, etc. The first bus device 100 is always in the addressing enabled state. When the first bus device 100 receives the trigger message and the cascade input terminal is low, it configures its own address through the address information of the trigger message, thus achieving decentralization without the participation of the master 400. It can perform automatic slave addressing without the master 400.
[0037] Specifically, if the cascade input port of the bus device 100 is at a valid level, the bus device 100 directly sets itself to address 01 and sends a response message; if the cascade input port of the bus device 100 is at an invalid level, the bus device 100 will broadcast a start message through the communication bus, thereby waking up the bus device 100 whose cascade input port is at a valid level, i.e., the first bus device 100 as indicated in this embodiment. Regardless of who sends the message, since the input port of the first bus device 100 is always physically at a valid level, the first bus device 100 will be the first bus device 100 to respond to the start message.
[0038] In a scenario with a host 400, the host 400 sends a startup message to the communication bus. Bus devices 100 with active input ports begin responding to the startup message, i.e., responding with a trigger message. This application improves the communication efficiency of the bus devices 100. In the traditional master-slave interaction mode, the host 400 needs to send allocation instructions to each bus device 100 individually and wait for a reply. The number of interactions is twice the number of bus devices 100, and includes a significant amount of processing and waiting time for the host 400. In this embodiment, the response message sent by the bus device 100 serves two purposes: firstly, it informs the host 400 that the configuration is complete, i.e., the enabled bus device 100 returns a response message to the host 400 via the communication bus; secondly, the response message directly serves as the trigger message for the next-level bus device 100. Throughout the entire process, the host 400 only needs to send a startup message once, and subsequently only needs to passively receive response messages on the communication bus, without needing to repeatedly send allocation instructions. The amount of data packet interaction on the communication bus has been reduced by nearly 50%. Taking the addressing of 254 bus devices as an example, the total time has been shortened from the traditional 7-8 seconds to less than 5 seconds, which greatly reduces the impact of interruption on business data transmission.
[0039] The recursive message is a response message sent by the preceding bus device 100 to trigger the following bus device 100 to complete its own address information configuration. The first byte of the message sent by the preceding bus device 100 after configuration is its own slave address (e.g., 01 to FE). This message is a response message for the preceding bus device 100, but it acts as a trigger message for the following device, realizing the automatic transmission of the addressing trigger source.
[0040] like Figure 1 As shown, this embodiment describes in detail the specific logic of address generation, as follows: The process of configuring its own communication address based on the address information of the trigger message includes extraction, reset, or increment operations.
[0041] First, bus device 100 extracts the reference address value from the trigger message. For example, the protocol specifies that the 5th and 6th bytes of the message store address information.
[0042] When the trigger message is a startup message, the reference address value is reset to an initial value (such as 0000) as its own communication address. For example, if the reference address field in the startup message is 0000, and the first bus device 100 recognizes that this is a startup message (type code FF), it will not directly use the reference value, but will reset it to the system's starting address, or add 1 to the reference value 0000 to get 0001, and write 0001 into its own memory.
[0043] When the trigger message is a recursive message, the reference address value is incremented, and the incremented reference address value is used as its own communication address. For example, the second-level bus device 100 receives a message from the first-level bus device 100, which carries the address 0001. The second-level bus device 100 recognizes this as a recursive message (type code 01), so it adds 1 to 0001 to get 0002, and uses 0002 as its own address for configuration. Similarly, the Nth-level bus device 100 uses the address of the N-1 minus-1th-level bus device 100 to increment, achieving continuous automatic address allocation.
[0044] like Figures 2 to 4 As shown, the cascaded input port of the bus device 100 is configured with a first impedance element 200 to maintain it in an addressing enabled state, and the cascaded output port is configured with a second impedance element 300 to maintain it in an addressing masked state. The resistance value of the first impedance element 200 is greater than the resistance value of the second impedance element 300.
[0045] In actual products, the first impedance element 200 is selected with a large resistance value and is connected as a pull-down resistor between the cascade input port and ground. The second impedance element 300 is selected with a small resistance value and is connected as a pull-up resistor between the cascade output port and the power supply. The first impedance element 200 is much larger than the second impedance element 300. For example, the resistance value of the first impedance element 200 is 15 to 25 times that of the second impedance element 300.
[0046] When the cascading input port of bus device 100 is active, it is in an addressing enabled state; when the cascading input port is inactive, it is in an addressing masked state. In this embodiment, a low level is defined as an active signal, and a high level is defined as an inactive signal.
[0047] The cascaded input port of the first bus device 100 is maintained as a valid signal by the first impedance element 200. Since the input port of the first bus device 100 is floating, the first impedance element 200 acts as a pull-down resistor, which stably pulls the level of the cascaded input port of the bus device 100 low, ensuring that it is in the addressing enabled state upon power-up, and can trigger automatic addressing operation without the host 400.
[0048] The cascaded input ports of the remaining bus devices 100 are clamped to invalid signals by the second impedance element 300 of the preceding bus device 100, and driven to valid signals when the cascaded output port of the preceding bus device 100 switches its level. When the bus devices 100 are cascaded, the second impedance element 300 of the preceding stage and the first impedance element 200 of the following stage form a series circuit. Since the resistance of the first impedance element 200 is much greater than that of the second impedance element 300, according to the voltage divider principle, the voltage at the cascade connection point is mainly determined by the second impedance element 300, which is close to the power supply voltage, i.e., it presents a high level. Therefore, as long as the cascaded output port of the preceding bus device 100 has no output, the input port of the following bus device 100 is clamped to invalid signals. Only when the preceding bus device 100 drives its output port to a low level can the effect of the second impedance element 300 be overcome, and the cascaded input port of the following bus device 100 be pulled low, thereby putting the following bus device 100 into the addressing enabled state.
[0049] After address configuration is completed, the bus device 100 in the address-enabled state initiates a shielding protection period. Since the cascading input port of the first bus device 100 is always at a low level through a hardware bias circuit, the first bus device 100 is always in the address-enabled state. To prevent subsequent recursive messages sent by the bus device 100 from erroneously triggering the first bus device 100 to re-address, this embodiment introduces a shielding protection period.
[0050] During the shielding protection period, the bus device 100 in the addressing enabled state shields the address information of trigger messages on the communication bus to prevent duplicate addressing. For example, the shielding protection period can be set to 5 seconds using a timer. After completing the first address write, the bus device 100 starts a 5-second timer. If the timer does not exceed the shielding protection period (i.e., 5 seconds), and the bus device 100 detects a trigger message on the bus with its own input port at a valid level, it will be forced to ignore the trigger message and not perform its own address update operation, thus preventing the first bus device 100 from being mistakenly triggered by messages from subsequent bus devices 100.
[0051] After sending a trigger message or receiving a response message, the bus device 100 starts the response time. The start of the response time can be initiated by the host 400 or by the bus device 100 that initiates the addressing command. A timer can be used to start the timing. The response time is reset every time a trigger message and a response message are exchanged on the communication bus.
[0052] If no new response message is detected on the communication bus within the response time, the address allocation process is considered complete, and the address information in the last received response message is recorded as the total number of bus devices 100. For example, the response time is set to 100 milliseconds. Whenever the host 400 or the bus device 100 that initiated the addressing command receives a response message indicating successful configuration of a bus device 100, the timer is reset to zero. If no new response message is received on the bus within 100 milliseconds, it indicates that there are no more bus devices 100 to be addressed on the cascaded link, and the process terminates. At this point, the address information in the last received response message represents the total number of bus devices 100 on the bus. Alternatively, if no new response message is received on the bus within 100 milliseconds, it may also indicate an interruption in the bus device 100 on the cascaded link, such as a broken line. In this case, after troubleshooting, the host 400 or the bus device 100 that initiated the addressing command should resend the trigger message to the communication bus, and the address information of the preceding bus device 100 should be overwritten.
[0053] When bus device 100 sends a response message, its cascade output port will be at an active level (low level) and a response time of 100 milliseconds will be enabled. When bus device 100 detects a new response message from the next-level bus device 100, or when the bus device 100 exceeds the response time during the listening process, the cascade output port of bus device 100 will return to an inactive level (high level), thereby making the cascade input port of the next-level bus device 100 inactive and indicating that the next-level bus device 100 has responded to the trigger message.
[0054] like Figure 5As shown, the application also provides a bus device 100, which includes a status detection module, a communication interaction module, an address configuration module, and a cascading driver module.
[0055] The status detection module determines the bus device 100 currently in the addressing enabled state based on the voltage level of the cascaded input ports. The first bus device 100 is initially in the addressing enabled state, while the remaining bus devices 100 are initially in the addressing disabled state. The status detection module achieves this by reading the input pin states of the microcontroller, whose pins are connected to the cascaded input ports, thereby obtaining the voltage level of the cascaded input ports of the bus device 100 and determining whether the bus device 100 is in the addressing enabled or addressing disabled state.
[0056] The communication interaction module is used to listen for trigger messages on the communication bus through the bus device 100, which is in the address-enabled state. Preferably, the communication interaction module utilizes the microcontroller's serial communication peripheral to connect to an RS485 transceiver to transmit and receive data.
[0057] The address configuration module is used to configure its own address based on the address information in the trigger message. The address configuration module is responsible for performing address resolution, increment operations, and writing the new address to non-volatile memory.
[0058] The cascading driver module, after configuring its own address, enables a bus device 100 in the address-enabled state to switch the level of its cascading output port, thus enabling the next-level bus device 100 to also be in the address-enabled state and sending a response message carrying its own address information to the communication bus. The cascading driver module controls the general-purpose output pins of the microcontroller, changing the level of the cascading output port by driving external circuitry.
[0059] The communication interaction module is also used to send a response message carrying its own address information to the communication bus. The response message is configured as a trigger message for the next-level bus device 100.
[0060] like Figure 2 and Figure 3 As shown, in terms of physical connection logic, adjacent bus devices 100 are connected in a cascade manner. That is, the cascade output port OUT of the previous stage bus device 100 is connected to the cascade input port IN of the next stage bus device 100. For the bus device 100 at the first position of the cascade link, its cascade input port IN is in a floating state, and it does not have a previous stage bus device 100 and cannot be connected to the previous stage bus device 100. For the bus device 100 at the last position of the cascade link, its cascade output port OUT is floating, and it does not have a next stage bus device 100 and cannot be connected to the next stage bus device 100.
[0061] To address the problem of uncertain microcontroller pin states during the initial power-up phase of a device in existing technologies, leading to addressing confusion, this embodiment incorporates a hardware bias circuit in each bus device 100. For example... Figure 4 As shown, the hardware bias circuit includes a first impedance element 200 and a second impedance element 300.
[0062] This embodiment describes in detail the hardware circuit structure of the bus device 100. The bus device 100 also includes a hardware bias circuit, which includes a first impedance element 200 and a second impedance element 300.
[0063] The first terminal of the first impedance element 200 is electrically connected to the cascaded input port, and the second terminal of the first impedance element 200 is electrically connected to the first reference potential. In this embodiment, the first impedance element 200 is a 20K ohm resistor, and the first reference potential is circuit ground.
[0064] The first terminal of the second impedance element 300 is electrically connected to the cascaded output port, and the second terminal of the second impedance element 300 is electrically connected to the second reference potential. In this embodiment, the second impedance element 300 is a 1K ohm resistor, and the second reference potential is the positive terminal of the power supply.
[0065] The resistance of the first impedance element 200 is greater than the resistance of the second impedance element 300.
[0066] Since the cascade input port IN of the first bus device 100 is floating and only affected by the first impedance element 200, the input level is stably pulled low. Therefore, the first bus device 100 determines that it is in the addressable enabled state upon power-up. The cascade input ports IN of the remaining bus devices 100 are connected to the cascade output ports OUT of the previous stage device. Since the OUT terminal of the previous stage bus device 100 is connected to the power supply through the second impedance element 300, and this resistance is much smaller than the pull-down resistor of the subsequent stage bus device 100 (i.e., the first impedance element 200), according to the series voltage divider principle, the voltage at the connection point is close to VCC, i.e., a high level, ensuring that the subsequent stage device is stably in the addressable shielded state initially or when not driven.
[0067] like Figure 4 As shown, the cascaded input port and cascaded output port are connected to the status detection module and the cascaded drive module, respectively, through electrical isolation devices. Specifically, the electrical isolation device can be an optocoupler (hereinafter referred to as an optocoupler). The cascaded input port is connected to the input terminal of the first optocoupler 500, and the output terminal of the first optocoupler 500 is connected to the input pin of the microcontroller. The output pin of the microcontroller is connected to the input terminal of the second optocoupler 600, and the output terminal of the second optocoupler 600 is connected to the cascaded output port. Through the design of the electrical isolation device, electrical interference between the bus devices 100 is effectively blocked, improving the stability of the system in complex industrial environments.
[0068] The first optocoupler 500 and the second optocoupler 600 can be BPC-817SC. In bus device 100, when IN is low, optocoupler U1 is turned on, and the signal is transmitted to the MCU's GP1 pin. The MCU's GP0 pin controls optocoupler U3. When the next stage needs to be driven, the MCU outputs a signal to turn on optocoupler U3, forcibly pulling the OUT port low to ground. The optocouplers achieve electrical isolation between the cascaded input port IN and the cascaded output port OUT and the MCU. Combined with the first impedance element 200 and the second impedance element 300, this ensures the anti-interference capability and common-mode rejection capability when devices from different power systems are cascaded.
[0069] As a variation of the embodiment, the resistance values of the first impedance element 200 and the second impedance element 300 can be adjusted according to the actual circuit, as long as the resistance value of the first impedance element 200 is much greater than the resistance value of the second impedance element 300 (e.g., more than 15 times), it can be ensured that the voltage level after voltage division is recognized as a high level by the logic circuit.
[0070] This embodiment provides an automatic bus address allocation system, which includes multiple bus devices 100 as described above. The multiple bus devices 100 are connected in parallel through a communication bus, and between adjacent bus devices 100, the cascade output port of the previous stage bus device 100 is connected to the cascade input port of the next stage bus device 100.
[0071] The first bus device 100 or the host 400 connected to the bus device 100 sends a startup message. The first bus device 100 configures its own address based on the startup message and sends a response message to the bus. Subsequent bus devices 100 configure their own addresses in turn using the response messages of the previous bus device 100.
[0072] This system has two addressing modes: The first addressing mode is initiated by the host 400. That is, the system contains a host 400. After the host 400 is powered on, it sends a start message, which can also be called a trigger message. The first bus device 100 responds to the start message because its input port is pulled low. After the first bus device 100 configures its address, it pulls its output port low and sends a response message, triggering the next level bus device 100, and so on, until all bus devices 100 are addressed.
[0073] The second mode is the hostless 400 mode, which means that the system does not contain a host 400 or the host 400 is offline. In this case, the user operates any bus device 100, causing that bus device 100 to send a start message. Although this message may be sent by a bus device 100 in the middle of the cascaded link, since the bus is broadcast in parallel and only the input port of the first bus device 100 is in a valid low-level state, the first bus device 100 will capture and respond to the start message, thereby starting the automatic addressing process of the entire cascaded link, thus realizing slave self-organizing network addressing in the absence of a host 400 environment.
[0074] This embodiment provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the automatic address allocation method of the bus device 100 described above. The storage medium may be flash memory or read-only memory inside the microcontroller of the bus device 100, and the stored code includes a sequence of instructions for implementing the aforementioned status detection, message parsing, address configuration, and port driving logic.
[0075] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.
Claims
1. A method for automatic address allocation of a bus device, characterized in that, A method applicable to multiple cascaded bus devices, wherein the multiple bus devices are connected in parallel via a communication bus, and between adjacent bus devices, the cascaded output port of the preceding bus device is connected to the cascaded input port of the following bus device, the method includes: The bus device currently in the addressing enabled state is determined based on the level state of the cascaded input port. The first bus device is initially in the addressing enabled state, and the remaining bus devices are initially in the addressing masked state. Bus devices in the addressing enabled state listen for trigger messages on the communication bus; Configure its own address according to the address information in the trigger message; After configuring its own address, the bus device in the addressing enabled state drives its own cascaded output port to switch the level state, so that the next-level bus device is in the addressing enabled state, and sends a response message carrying its own address information to the communication bus. The response message serves as a trigger message used by the next-level bus device to configure its own address, until all bus devices have completed their configuration.
2. The automatic address allocation method for bus devices as described in claim 1, characterized in that, The trigger message includes a start message and a recursive message; The startup message is initiated by the host on the communication bus or any of the bus devices, and is used to trigger the bus device in the first position; The recursive message is the response message sent by the previous bus device, which is used to trigger the next bus device to complete the configuration of its own address information.
3. The automatic address allocation method for bus devices as described in claim 2, characterized in that, The step of configuring its own communication address according to the address information of the trigger message includes: Extract the reference address value from the trigger message; When the trigger message is the start message, the reference address value is reset to the initial value as its own communication address; When the trigger message is the recursive message, the reference address value is incremented, and the incremented reference address value is used as its own communication address.
4. The automatic address allocation method for bus devices as described in claim 1, characterized in that, The cascaded input port of the bus device is configured with a first impedance element to maintain it in the addressing enabled state, and the cascaded output port of the bus device is configured with a second impedance element to maintain it in the addressing shielded state. The resistance of the first impedance element is greater than the resistance of the second impedance element; The cascade input port of the bus device is in the addressing enabled state when the signal is valid, and in the addressing masked state when the signal is invalid. The first cascaded input port of the bus device is maintained to the valid signal by the first impedance element, while the cascaded input ports of the remaining bus devices are clamped to the invalid signal by the second impedance element of the preceding bus device, and driven to the valid signal when the cascaded output port of the preceding bus device switches its level.
5. The automatic address allocation method for bus devices as described in claim 4, characterized in that, Bus devices in the addressing enabled state initiate a shield protection period after completing address configuration; During the shielding protection period, bus devices in the addressing enabled state shield the address information of the trigger message on the communication bus to prevent duplicate addressing.
6. The automatic address allocation method for bus devices as described in claim 1, characterized in that, Also includes: The bus device initiates a response time after sending a trigger message or receiving a response message. If no new response message is detected on the communication bus within the response time, the address allocation process is determined to be over, and the address information in the last received response message is recorded as the total number of bus devices.
7. A bus device, characterized in that, include: The status detection module is used to determine the bus device currently in the addressing enabled state based on the level status of the cascaded input ports. The first bus device is initially in the addressing enabled state, and the remaining bus devices are initially in the addressing masked state. The communication interaction module is used to listen for trigger messages on the communication bus through bus devices in the addressing enabled state; The address configuration module is used to configure its own address according to the address information in the trigger message; The cascading driver module is used to, after configuring its own address, drive the cascading output port of the bus device in the addressing enabled state to switch the level state, so that the bus device in the next stage is in the addressing enabled state, and send a response message carrying its own address information to the communication bus. The communication interaction module is also used to send a response message carrying its own address information to the communication bus, and the response message is configured as the trigger message of the subsequent bus device.
8. The bus device as described in claim 7, characterized in that, It also includes a hardware bias circuit, which includes a first impedance element and a second impedance element. The first end of the first impedance element is electrically connected to the cascaded input port, and the second end of the first impedance element is electrically connected to the first reference potential; The first end of the second impedance element is electrically connected to the cascaded output port, and the second end of the second impedance element is electrically connected to the second reference potential; The resistance of the first impedance element is greater than the resistance of the second impedance element; The cascaded input port and cascaded output port are respectively connected to the status detection module and the cascaded drive module through electrical isolation devices.
9. A bus address automatic allocation system, characterized in that, Includes multiple bus devices as described in claim 7 or 8; Multiple bus devices are connected in parallel via a communication bus, and between adjacent bus devices, the cascade output port of the previous stage bus device is connected to the cascade input port of the next stage bus device; The first bus device or the host connected to the bus device sends a start message. The first bus device configures its own address based on the trigger message and sends a response message to the bus. Subsequent bus devices configure their own addresses in turn using the response messages of the previous bus device.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the automatic address allocation method for the bus device as described in any one of claims 1 to 6.