Buffer dynamic adjustment method and device, electronic equipment and storage medium
By splitting the buffer into multiple configurable sub-buffers and dynamically adjusting their capacity according to the working status of the IFPU and the scene, the problem of buffer overflow in multi-camera scenarios is solved, achieving data caching balance and ensuring camera system performance under limited hardware resources.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SPREADTRUM COMM (TIANJIN) INC
- Filing Date
- 2026-01-20
- Publication Date
- 2026-04-21
AI Technical Summary
In multi-camera scenarios, the buffer of electronic devices is prone to overflow due to data accumulation, which can cause camera malfunctions and affect the user's experience of taking photos, recording videos, or previewing in real time.
A fixed-size buffer is divided into multiple independent, configurable sub-buffers, and the capacity of each sub-buffer is dynamically adjusted according to the working status and scenario of the IFPU to balance data caching capacity and DDR bandwidth requirements and avoid buffer overflow.
With limited hardware resources, effectively avoid buffer overflows, ensure the overall performance of the camera system, and improve the user experience.
Smart Images
Figure CN121907975A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic equipment technology, and in particular to a method, apparatus, electronic device and storage medium for dynamic adjustment of buffers. Background Technology
[0002] With the upgrading of electronic devices' camera functions, multi-camera configurations are gradually becoming mainstream, such as dual-camera, triple-camera, and even quad-camera systems.
[0003] In multi-camera scenarios, the raw image data from multiple cameras needs to be processed. The processed data needs to be transmitted to the Double Data Rate Synchronous Dynamic Random Access Memory (DDR) of the electronic device for subsequent image processing or display.
[0004] However, when multiple cameras output data simultaneously, a large amount of temporary data is generated. If the DDR bandwidth cannot meet the instantaneous data output requirements, the buffer may overflow due to data accumulation. If an overflow occurs, it will cause the camera function to be interrupted, directly affecting the user's experience of taking photos, recording videos, or real-time previewing. Summary of the Invention
[0005] This application provides a method, apparatus, electronic device, and storage medium for dynamic adjustment of a buffer, which can solve the technical problem in the related art that the buffer is prone to overflow due to data accumulation when multiple cameras output data at the same time.
[0006] In a first aspect, embodiments of this application provide a method for dynamically adjusting a buffer, applied in an electronic device, the electronic device including at least two image front processing units (IFPUs), the method comprising:
[0007] Multiple sub-buffers are established based on the buffers in the image processing pipeline corresponding to each IFPU;
[0008] Select the target configuration mode based on the working parameters of each IFPU; these working parameters include the working status and / or working scenario of each IFPU.
[0009] Adjust the capacity ratio of each sub-buffer according to the target configuration mode.
[0010] In one possible implementation, the electronic device includes a first IFPU and a second IFPU; the above-mentioned establishment of multiple sub-buffers based on the buffers in the image processing pipeline corresponding to each IFPU includes:
[0011] The first buffer in the image processing pipeline corresponding to the first IFPU is split into a first sub-buffer and a second sub-buffer; the first sub-buffer is located at the head of the image processing pipeline corresponding to the first IFPU, and the second sub-buffer is located at the tail of the image processing pipeline corresponding to the first IFPU.
[0012] The second buffer in the image processing pipeline corresponding to the second IFPU is split into a third sub-buffer and a fourth sub-buffer; the third sub-buffer is located at the head of the image processing pipeline corresponding to the second IFPU, and the fourth sub-buffer is located at the tail of the image processing pipeline corresponding to the second IFPU.
[0013] In one possible implementation, the selection of the target configuration mode based on the operating parameters of each IFPU includes:
[0014] Obtain a list of pre-configured configuration modes for each IFPU under different working states and / or working scenarios;
[0015] Select the target configuration mode based on the configuration mode list and the working status and / or working scenario of each IFPU.
[0016] In one possible implementation, the IFPU's working state includes an on state and an off state; the IFPU's working scenarios include online working scenarios and offline working scenarios.
[0017] In one possible implementation, the selection of the target configuration mode based on the operating parameters of each IFPU includes:
[0018] Select the first configuration mode when the first IFPU is enabled and online, and the second IFPU is disabled.
[0019] Select the second configuration mode when both the first IFPU and the second IFPU are enabled and in an online working scenario.
[0020] Select the third configuration mode when the first IFPU is enabled and in an online working scenario, and when the second IFPU is enabled and in an offline working scenario.
[0021] When the first IFPU is in a closed state and the second IFPU is in a closed state and is in an online working scenario, select the fourth configuration mode;
[0022] Select the fifth configuration mode when the first IFPU is enabled and operating offline, and when the second IFPU is enabled and operating online.
[0023] In one possible implementation, the above method further includes:
[0024] In response to user configuration operations, the capacity ratio of each sub-buffer is adjusted according to the user configuration operations; the aforementioned user configuration operations include configuration operations for multiple sub-buffers.
[0025] Secondly, embodiments of this application provide a buffer dynamic adjustment device applied in an electronic device, the electronic device including at least two IFPUs, the device comprising:
[0026] The preprocessing module is used to create multiple sub-buffers based on the buffers in the image processing pipeline corresponding to each IFPU;
[0027] The selection module is used to select the target configuration mode based on the working parameters of each IFPU; these working parameters include the working status and / or working scenario of each IFPU.
[0028] The adjustment module is used to adjust the capacity ratio of each sub-buffer according to the target configuration mode.
[0029] Thirdly, embodiments of this application provide an electronic device, including: a memory and a processor;
[0030] The memory stores the instructions that the computer executes;
[0031] The processor executes computer execution instructions stored in memory, causing the processor to perform the first aspect and / or various possible implementations of the first aspect as described above.
[0032] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the first aspect and / or various possible implementations of the first aspect.
[0033] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the first aspect and / or various possible implementations of the first aspect.
[0034] Sixthly, embodiments of this application provide a chip including at least one processor for executing program instructions to perform the above-described buffer dynamic adjustment method.
[0035] The buffer dynamic adjustment method, apparatus, electronic device, and storage medium provided in this application divide the originally fixed-size buffer into multiple independent configurable sub-buffers and dynamically adjust the capacity of each sub-buffer according to the actual operating scenario (such as the working state and / or working scenario of the IFPU), thereby balancing data caching capacity and DDR bandwidth requirements under limited hardware resources, avoiding buffer overflow, and ensuring the overall performance of the camera system. Attached Figure Description
[0036] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0037] Figure 1 This is a flowchart illustrating a method for dynamically adjusting a buffer provided in an embodiment of this application.
[0038] Figure 2 This is a schematic diagram of buffer splitting provided in an embodiment of this application;
[0039] Figure 3 This is a schematic diagram of the structure of a buffer dynamic adjustment device provided in the embodiments of this application;
[0040] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.
[0041] The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation
[0042] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0043] In this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.
[0044] In the embodiments of this application, terms such as "first" and "second" are used to distinguish identical or similar items with essentially the same function and purpose. For example, the first sub-buffer and the second sub-buffer are merely used to distinguish different sub-buffers and do not limit their order. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or execution order, and that "first" and "second" do not necessarily imply that they are different.
[0045] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.
[0046] The technical solutions provided in this application can be applied to camera systems of electronic devices (such as smartphones and tablets), especially image processing pipelines in multi-camera scenarios (dual-camera, triple-camera).
[0047] Camera systems typically include:
[0048] Front-end acquisition layer: This layer includes the lens, image sensor, serializer, and power supply module, and is responsible for optical imaging and electrical signal conversion. Some modules integrate an image signal processor (ISP), which can directly perform processing such as noise reduction and color correction.
[0049] Transmission link layer: Low Voltage Differential Signaling (LVDS) or Mobile Industry Processor Interface (MIPI) protocols are used for high-speed data transmission.
[0050] Backend processing layer: The domain controller performs image scaling, stitching, and other processing.
[0051] Electronic devices typically carry many systems, such as communication systems, camera systems, and audio-visual systems. These systems all need to access DDR, which leads to different systems competing for DDR.
[0052] For example, in a multi-camera scenario, the IFPU needs to process the raw image data from multiple cameras, performing operations such as color correction, noise suppression, and dynamic range adjustment. The processed data needs to be transmitted to the DDR of the electronic device via a high-speed interface (such as the AXI bus) for subsequent image processing or display.
[0053] However, since the system resources (such as DDR bandwidth) inside electronic devices need to be shared by multiple systems such as communication modules and audio and video processing modules, the camera system will face the problem of instantaneous bandwidth competition in multi-camera scenarios.
[0054] When multiple cameras output high-resolution data simultaneously, the IFPU image processing pipeline generates a large amount of temporary data. If the DDR bandwidth cannot meet the instantaneous data output requirements, the IFPU's First-In-First-Out (FIFO) buffer may overflow due to data accumulation. Once an overflow occurs, it cannot be recovered, causing the camera system to stop and directly affecting the user's experience of taking photos, recording videos, or performing live previews.
[0055] In related technologies, the following two solutions are typically used to address the data overflow problem in multi-camera scenarios:
[0056] (1) Frame dropping: When insufficient DDR bandwidth is detected, some of the data output by the Camera system is directly dropped to avoid buffer overflow.
[0057] This solution is simple and easy to implement, but it has a significant drawback: discarding the data output by the camera system will cause the preview to be discontinuous, and users will perceive the screen as lagging.
[0058] (2) Increase the priority of the Camera system: By adjusting the DDR bandwidth allocation strategy, the data transmission needs of the Camera system are given priority.
[0059] However, mobile devices have limited DDR bandwidth. Increasing the camera priority may crowd out resources of other systems such as communication modules and audio / video processing modules, leading to a decline in overall system performance or even malfunction.
[0060] For example, increased latency in the communication module may affect call quality, and insufficient resources in the audio and video modules may cause audio stuttering or abnormal video playback.
[0061] Therefore, how to balance bandwidth requirements and data caching capabilities in multi-camera scenarios through dynamic resource allocation mechanisms without increasing hardware costs has become a technical problem that needs to be solved in the design of camera systems for electronic devices.
[0062] To address the aforementioned technical issues, this application provides a method for dynamically allocating and optimizing buffer resources in a camera image processing pipeline by dynamically splitting and configuring these resources, taking into account the differences in data processing requirements across different camera scenarios.
[0063] The technical concept of this application embodiment is to divide the originally fixed-size buffer into multiple independent and configurable sub-buffers, and dynamically adjust the capacity of each sub-buffer according to the actual operating scenario (such as the working state and / or working scenario of the IFPU), thereby balancing data caching capacity and DDR bandwidth requirements under limited hardware resources, avoiding buffer overflow, and ensuring the overall performance of the Camera system.
[0064] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.
[0065] In this application embodiment, the device used to implement the function of the electronic device can be the electronic device itself; or it can be a device that enables the electronic device to implement the function, such as a chip system, which can be installed in the electronic device.
[0066] Optionally, the aforementioned electronic devices include at least two IFPUs. In a Camera IP system, the IFPU, as a key module, is responsible for image data preprocessing (such as noise reduction, color correction, format conversion, etc.). Its pipeline design employs a FIFO buffer, which uses a "first-in, first-out" mechanism to cache temporary data, and this is crucial for system performance and stability.
[0067] When the IFPU processes image data, the input (such as sensor output) and output (such as subsequent processing modules) rates may not match. The FIFO, acting as an intermediate buffer, can absorb rate differences and prevent data loss or processing blockage.
[0068] For example, if an image sensor outputs data at 60fps, but subsequent modules can only process 30fps, a FIFO can buffer the extra frames to ensure data continuity.
[0069] The IFPU can contain multiple pipeline stages (such as noise reduction → color correction → format conversion). Each stage has a different processing time, and FIFO can balance the latency between stages to maintain efficient pipeline operation.
[0070] The size (depth) of a FIFO directly determines its buffering capacity. A larger capacity allows for the storage of more temporary data, and the system becomes more tolerant of sudden rate fluctuations. If the FIFO depth is insufficient, data will overflow when the input rate consistently exceeds the output rate.
[0071] like Figure 1 As shown, Figure 1 This is a flowchart illustrating a method for dynamically adjusting a buffer provided in an embodiment of this application.
[0072] In some embodiments, the above-described dynamic buffer adjustment method includes:
[0073] S101. Based on the buffers in the image processing pipeline corresponding to each IFPU, establish multiple sub-buffers.
[0074] In some implementations, the buffer structure within the image processing pipeline corresponding to each IFPU can be analyzed to determine which sub-buffers it can be divided into. These sub-buffers can correspond to different processing stages or data types.
[0075] Based on the analysis results, the buffer of each IFPU is divided into multiple sub-buffers. Each sub-buffer can have a specific purpose and its capacity can be dynamically adjusted.
[0076] S102. Select the target configuration mode based on the working parameters of each IFPU.
[0077] Optionally, the above operating parameters include the operating status and / or operating scenario of each IFPU.
[0078] In some implementations, the current requirements and processing capabilities of each IFPU can be analyzed based on its operating parameters. For example, in high-resolution mode, an IFPU may require a larger buffer to store more image data.
[0079] Based on the analysis results, select the target configuration mode that is suitable for the current working state and scenario. Multiple configuration modes can be predefined, each corresponding to a different sub-buffer capacity ratio.
[0080] S103. Adjust the capacity ratio of each sub-buffer according to the target configuration mode.
[0081] In some implementations, the capacity ratio of each sub-buffer can be determined based on the target configuration pattern. For example, the capacity of some sub-buffers can be increased while the capacity of others can be decreased.
[0082] In some implementations, the capacity of each sub-buffer can be actually adjusted according to a defined adjustment strategy.
[0083] In some implementations, after adjustments are made, it can be verified whether the adjustment effect meets expectations. For example, the adjustment effect can be evaluated by monitoring indicators such as buffer usage and processing latency.
[0084] The buffer dynamic adjustment method provided in this application splits the originally fixed-size buffer into multiple independent configurable sub-buffers and dynamically adjusts the capacity of each sub-buffer according to the actual operating scenario (such as the working status and / or working scenario of the IFPU), thereby balancing data caching capacity and DDR bandwidth requirements under limited hardware resources, avoiding buffer overflow, and ensuring the overall performance of the Camera system.
[0085] In some embodiments, the electronic device includes a first IFPU and a second IFPU; the establishment of multiple sub-buffers based on the buffers in the image processing pipeline corresponding to each IFPU includes:
[0086] The first buffer in the image processing pipeline corresponding to the first IFPU is split into a first sub-buffer and a second sub-buffer; the first sub-buffer is located at the head of the image processing pipeline corresponding to the first IFPU, and the second sub-buffer is located at the tail of the image processing pipeline corresponding to the first IFPU.
[0087] The second buffer in the image processing pipeline corresponding to the second IFPU is split into a third sub-buffer and a fourth sub-buffer; the third sub-buffer is located at the head of the image processing pipeline corresponding to the second IFPU, and the fourth sub-buffer is located at the tail of the image processing pipeline corresponding to the second IFPU.
[0088] For example, refer to Figure 2 , Figure 2 This is a schematic diagram of buffer splitting provided in an embodiment of this application.
[0089] In some implementations, the image processing pipeline corresponding to the first IFPU includes first sensor input data (sensor-1 input) and acquired input data 1 (fetch input-1); the image processing pipeline corresponding to the second IFPU includes second sensor input data (sensor-2 input) and acquired input data 2 (fetch input-2).
[0090] Here, Sensor Input can refer to data input directly from the image sensor. The image sensor is responsible for capturing optical images and converting them into electrical signals, which are then converted into digital data to form the original image information.
[0091] Sensor Input is characterized by: large data volume, containing all the original information of the image; and existing in RAW format, requiring processing to be converted into a usable image format.
[0092] Sensor Input is the starting point of the IFPU processing flow. Data enters the IFPU from here for preprocessing operations such as noise reduction, color correction, and format conversion.
[0093] IFPU processes the sensor input in real time to ensure the continuity and stability of image data.
[0094] Fetch Input can refer to data input obtained from other processing units, memory, or external interfaces. This data has already undergone some processing or storage and needs to be further processed by the IFPU or merged with other data.
[0095] The characteristics of Fetch Input include: the data format and content vary depending on the source, and it can include pre-processed image data, metadata, control information, etc. The data volume may be small, and real-time processing is not necessarily required.
[0096] Fetch Input provides IFPU with additional data sources, enabling IFPU to process data from different sources.
[0097] IFPU can perform further processing on the Fetch Input, such as merging, synchronizing, or analyzing data with the Sensor Input, to meet specific application needs.
[0098] In one possible implementation, the selection of the target configuration mode based on the operating parameters of each IFPU includes:
[0099] Obtain a list of pre-configured configuration modes for each IFPU under different working states and / or working scenarios; select the target configuration mode based on the configuration mode list and the working states and / or working scenarios of each IFPU.
[0100] In one possible implementation, the IFPU's working state includes an on state and an off state; the IFPU's working scenarios include online working scenarios and offline working scenarios.
[0101] In online work scenarios, the input data for IFPU mode is Sensor Input; in offline work scenarios, the input data for IFPU mode is Fetch Input.
[0102] For example, refer to Table 1, which is a list of configuration modes provided in the embodiments of this application.
[0103] Table 1: Configuration Mode List
[0104]
[0105] Among them, IFPU1 Clock represents the working state of the first IFPU, IFPU2 Clock represents the working state of the second IFPU, "on" means it is in the on state, and "off" means it is in the off state.
[0106] In some implementations, the selection of the target configuration mode based on the operating parameters of each IFPU includes:
[0107] Select the first configuration mode when the first IFPU is enabled and in an online working scenario, and the second IFPU is disabled; select the second configuration mode when both the first and second IFPUs are enabled and in an online working scenario; select the third configuration mode when both the first and second IFPUs are enabled and in an offline working scenario; select the fourth configuration mode when both the first and second IFPUs are disabled and in an online working scenario; and select the fifth configuration mode when both the first and second IFPUs are enabled and in an offline working scenario.
[0108] For example, in the first configuration mode, the cache resources of the first buffer and the second buffer can be allocated to the first sub-buffer and the second sub-buffer, and the capacity of the third sub-buffer and the fourth sub-buffer can be zero.
[0109] In the second configuration mode, the total capacity of the first and second sub-buffers can account for 50% of the total buffer capacity; similarly, the total capacity of the third and fourth sub-buffers can also account for 50% of the total buffer capacity. Optionally, the capacity of the first sub-buffer can be smaller than the capacity of the second sub-buffer. For example, the capacity of the first sub-buffer can account for 20% of the total buffer capacity, and the capacity of the second sub-buffer can account for 30% of the total buffer capacity; similarly, the capacity of the third sub-buffer can account for 20% of the total buffer capacity, and the capacity of the fourth sub-buffer can account for 30% of the total buffer capacity.
[0110] In the third configuration mode, the total capacity of the first and second sub-buffers can account for 60% of the total buffer capacity; the total capacity of the third and fourth sub-buffers can account for 40% of the total buffer capacity. Optionally, the capacity of the first sub-buffer can account for 25% of the total buffer capacity, and the capacity of the second sub-buffer can account for 35% of the total buffer capacity.
[0111] In the fourth configuration mode, the cache resources of the first and second buffers can be allocated to the third and fourth sub-buffers, and the capacity of the first and second sub-buffers can be zero.
[0112] In the fifth configuration mode, the total capacity of the first and second sub-buffers can account for 40% of the total buffer capacity; the total capacity of the third and fourth sub-buffers can account for 60% of the total buffer capacity.
[0113] The buffer dynamic adjustment method provided in this application solves the overflow problem caused by insufficient instantaneous bandwidth in multi-camera scenarios by splitting and dynamically configuring the FIFO buffer.
[0114] In some embodiments, the above method further includes:
[0115] In response to user configuration operations, the capacity ratio of each sub-buffer is adjusted according to the user configuration operations; the aforementioned user configuration operations include configuration operations for multiple sub-buffers.
[0116] In some implementations, after resetting the IFPU, the capacity ratio of each sub-buffer can be adjusted according to user-configured operations.
[0117] For example, refer to Table 2, which is a list of configuration modes provided in the embodiments of this application.
[0118] Table 2: Configuration Mode List 2
[0119]
[0120] In the single-camera scenario 1, the first IFPU is on and the second IFPU is off; in the single-camera scenario 2, the second IFPU is off and the first IFPU is on; in the dual-camera scenario, both the first and second IFPUs are on.
[0121] The buffer dynamic adjustment method provided in this application allows users to flexibly choose the configuration mode according to actual needs, avoiding resource waste or overflow risks caused by fixed allocation.
[0122] In some embodiments, this application also provides a buffer dynamic adjustment device. (See reference...) Figure 3 , Figure 3 This is a schematic diagram of a buffer dynamic adjustment device provided in an embodiment of this application. The buffer dynamic adjustment device 30 can be applied to the above-mentioned electronic device and includes:
[0123] The preprocessing module 301 is used to establish multiple sub-buffers based on the buffers in the image processing pipeline corresponding to each IFPU.
[0124] Selection module 302 is used to select the target configuration mode based on the working parameters of each IFPU; these working parameters include the working status and / or working scenario of each IFPU.
[0125] Adjustment module 303 is used to adjust the capacity ratio of each sub-buffer according to the target configuration mode.
[0126] In one possible implementation, the above-mentioned electronic device includes a first IFPU and a second IFPU; the preprocessing module 301 is used for:
[0127] The first buffer in the image processing pipeline corresponding to the first IFPU is split into a first sub-buffer and a second sub-buffer; the first sub-buffer is located at the head of the image processing pipeline corresponding to the first IFPU, and the second sub-buffer is located at the tail of the image processing pipeline corresponding to the first IFPU.
[0128] The second buffer in the image processing pipeline corresponding to the second IFPU is split into a third sub-buffer and a fourth sub-buffer; the third sub-buffer is located at the head of the image processing pipeline corresponding to the second IFPU, and the fourth sub-buffer is located at the tail of the image processing pipeline corresponding to the second IFPU.
[0129] In one possible implementation, the selection module 302 is used for:
[0130] Obtain a list of pre-configured configuration modes for each IFPU under different working states and / or working scenarios;
[0131] Select the target configuration mode based on the configuration mode list and the working status and / or working scenario of each IFPU.
[0132] In one possible implementation, the IFPU's working state includes an on state and an off state; the IFPU's working scenarios include online working scenarios and offline working scenarios.
[0133] In one possible implementation, the selection module 302 is used for:
[0134] Select the first configuration mode when the first IFPU is enabled and online, and the second IFPU is disabled.
[0135] Select the second configuration mode when both the first IFPU and the second IFPU are enabled and in an online working scenario.
[0136] Select the third configuration mode when the first IFPU is enabled and in an online working scenario, and when the second IFPU is enabled and in an offline working scenario.
[0137] When the first IFPU is in a closed state and the second IFPU is in a closed state and is in an online working scenario, select the fourth configuration mode;
[0138] Select the fifth configuration mode when the first IFPU is enabled and operating offline, and when the second IFPU is enabled and operating online.
[0139] In one possible implementation, the above-described apparatus further includes a configuration module for:
[0140] In response to user configuration operations, the capacity ratio of each sub-buffer is adjusted according to the user configuration operations; the aforementioned user configuration operations include configuration operations for multiple sub-buffers.
[0141] The buffer dynamic adjustment device provided in this embodiment can execute the buffer dynamic adjustment method provided in the above method embodiment. Its implementation principle and technical effect are similar, and will not be described in detail here.
[0142] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 4 As shown, the electronic device 40 provided in this embodiment includes at least one processor 401 and a memory 402. Optionally, the electronic device 40 further includes a communication interface 403. The processor 401, memory 402, and communication interface 403 are connected via a bus.
[0143] In the specific implementation process, at least one processor 401 executes computer execution instructions stored in memory 402, causing at least one processor 401 to execute the above-mentioned buffer dynamic adjustment method.
[0144] The specific implementation process of processor 401 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.
[0145] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.
[0146] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.
[0147] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.
[0148] This application also provides a chip including at least one processor for executing program instructions to perform the above-described buffer dynamic adjustment method.
[0149] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described dynamic buffer adjustment method.
[0150] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described dynamic buffer adjustment method.
[0151] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.
[0152] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an application-specific integrated circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.
[0153] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0154] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.
Claims
1. A method for dynamically adjusting a buffer zone, characterized in that, Applied in an electronic device, the electronic device including at least two image front-end processing units (IFPUs), the method includes: Based on the buffers in the image processing pipeline corresponding to each IFPU, multiple sub-buffers are established; Select the target configuration mode based on the working parameters of each IFPU; the working parameters include the working status and / or working scenario of each IFPU. Adjust the capacity ratio of each sub-buffer according to the target configuration mode.
2. The method according to claim 1, characterized in that, The electronic device includes a first IFPU and a second IFPU; the establishment of multiple sub-buffers based on the buffers in the image processing pipeline corresponding to each IFPU includes: The first buffer in the image processing pipeline corresponding to the first IFPU is split into a first sub-buffer and a second sub-buffer; the first sub-buffer is located at the head of the image processing pipeline corresponding to the first IFPU, and the second sub-buffer is located at the tail of the image processing pipeline corresponding to the first IFPU. The second buffer in the image processing pipeline corresponding to the second IFPU is split into a third sub-buffer and a fourth sub-buffer; the third sub-buffer is located at the head of the image processing pipeline corresponding to the second IFPU, and the fourth sub-buffer is located at the tail of the image processing pipeline corresponding to the second IFPU.
3. The method according to claim 2, characterized in that, The step of selecting the target configuration mode based on the operating parameters of each IFPU includes: Obtain a list of pre-configured configuration modes for each of the IFPUs under different working states and / or working scenarios; Based on the configuration mode list and the working status and / or working scenario of each IFPU, select the target configuration mode.
4. The method according to claim 3, characterized in that, The working state of the IFPU includes an on state and a off state; the working scenario of the IFPU includes an online working scenario and an offline working scenario.
5. The method according to claim 4, characterized in that, The step of selecting the target configuration mode based on the operating parameters of each IFPU includes: When the first IFPU is enabled and in an online working scenario, and the second IFPU is disabled, select the first configuration mode; When the first IFPU is enabled and in an online working scenario, and the second IFPU is enabled and in an online working scenario, select the second configuration mode; Select the third configuration mode when the first IFPU is enabled and in an online working scenario, and when the second IFPU is enabled and in an offline working scenario. When the first IFPU is in a closed state and the second IFPU is in a closed state and is in an online working scenario, select the fourth configuration mode; Select the fifth configuration mode when the first IFPU is enabled and operating offline, and when the second IFPU is enabled and operating online.
6. The method according to claim 1, characterized in that, The method further includes: In response to a user configuration operation, the capacity ratio of each of the sub-buffers is adjusted according to the user configuration operation; the user configuration operation includes configuration operations for the plurality of sub-buffers.
7. A buffer dynamic adjustment device, characterized in that, Applied in an electronic device, the electronic device includes at least two image front-end processing units (IFPUs), the device comprising: The preprocessing module is used to establish multiple sub-buffers based on the buffers in the image processing pipeline corresponding to each IFPU; The selection module is used to select a target configuration mode based on the working parameters of each IFPU; the working parameters include the working status and / or working scenario of each IFPU. An adjustment module is used to adjust the capacity ratio of each of the sub-buffers according to the target configuration mode.
8. An electronic device, characterized in that, include: Memory, processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory, causing the processor to perform the buffer dynamic adjustment method as described in any one of claims 1-6.
9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the buffer dynamic adjustment method as described in any one of claims 1-6.
10. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the buffer dynamic adjustment method as described in any one of claims 1-6.