Preparation method of fin type tunneling field effect transistor

Abstract

The invention provides a preparation method of a fin type tunneling field effect transistor, and belongs to the technical field of micro-nano electronics. A traditional planar TFET device and a FinFET structure are combined, the advantage of low off-state current can be kept while on-state current can be improved, bipolar current is restrained, namely, an expansion region is prepared in a source region in a self-alignment mode, so that a tunneling junction is formed at the gate-source overlapping position, tunneling current is improved, and meanwhile, through a thick side wall prepared before source-drain epitaxy, the tunneling efficiency is improved. An under-coverage area structure is formed at the drain terminal to suppress bipolar current; meanwhile, the main body of the substrate region of the device is still lightly doped high-resistance silicon, so that the advantage of low off-state current of the tunneling field effect transistor is maintained. Besides, the preparation method is based on a standard fin type tunneling field effect transistor process flow of an advanced node, only one photoetching plate is additionally arranged on the premise of not changing a basic process flow, and the potential of realizing large-scale production is maintained.

Description

Technical Field

[0001] This invention belongs to the field of micro-nano electronics technology, specifically relating to a method for fabricating a fin tunneling field-effect transistor. Background Technology

[0002] With Moore's Law continuously evolving, chip power consumption has become a core issue in the development of integrated circuit technology. For traditional FinFET devices, due to their short-channel effect and the theoretical limit of their subthreshold swing (minimum 60mV / dec at room temperature), the off-state current of a FinFET increases with decreasing operating voltage and channel length at the same on-state current. This makes the power consumption problem of FinFETs even more pronounced at advanced nodes. Therefore, to solve the power consumption problem of integrated circuits, innovation at the basic device level is needed. A tunneling field-effect transistor (TFET), based on a band-to-band tunneling conduction mechanism and a gate-controlled pin device structure, has emerged as one solution to overcome the power consumption problem of traditional devices. TFET devices have lower off-state current, lower operating voltage, and better scalability than MOSFETs. Introducing TFET devices at the FinFET node can also leverage the strong gate control capability of the fin structure to optimize the subthreshold characteristics of TFET devices, further facilitating their miniaturization. However, the low on-state current and high bipolar current limit the large-scale circuit application of Fin-TFETs. Therefore, increasing the current switching ratio of Fin-TFETs is a key issue to promote their practical circuit applications. Summary of the Invention

[0003] The purpose of this invention is to propose a method for fabricating a Fin-TFET device, which can increase the on-state current of the Fin-TFET device and reduce its bipolar current, thereby improving its current switching ratio.

[0004] The technical solution of the present invention is as follows: A method for fabricating a fin-tunneling field-effect transistor (Fin-TFET) is characterized by the following steps: During fabrication, an extended region is fabricated only in the source region using self-alignment, thereby forming a tunneling junction at the gate-source overlap to increase the source tunneling probability and the device's on-state current. Simultaneously, a sub-covered region structure is formed at the drain end using the thick sidewalls fabricated before source-drain epitaxy to suppress bipolar current and the device's off-state current. The proposed method for fabricating the fin-tunneling field-effect transistor includes the following steps: Step 1: Provide a lightly doped silicon substrate with either N-type or P-type doping. Step 2: Perform fin etching using self-aligned double exposure technology; Step 3: Perform shallow trench isolation (STI) process. The specific method is to deposit an oxide layer on the entire wafer and then form shallow trench isolation by etching back. Step 4: The N-well and P-well regions are exposed by photolithography etching, and the N-well and P-well are formed by ion implantation and annealing. Step 5: Deposit polysilicon across the entire wafer and create a hard mask to define the polysilicon gate; Step 6: Apply thin sidewall construction techniques; Step 7: Photolithography and etching expose the source window of the Fin-TFET device, ion implantation is performed on the source extension region, followed by annealing, thereby forming the gate-source overlap region and the gate-drain undercover region of the Fin-TFET. Step 8: Deposit silicon nitride across the entire wafer and anisotropically etch to form thick sidewalls; Step 9: Create a hard mask to define the source region of the Fin-TFET, etch the fins of the source region, and then perform source region epitaxy; Step 10: Create a hard mask to define the drain region of the Fin-TFET, etch the fins of the drain region, and then perform drain region epitaxy; Step 11: After removing the polysilicon gate, deposit multiple layers of gate dielectric, then deposit a gate metal stack to adjust the work function, and then deposit metal to form a metal gate; Step 12: Form the rear-end vias and interconnects; Furthermore, the thickness range of STI in step 3 is 60nm-100nm.

[0005] Furthermore, the dose range of ion implantation in step 4 is 1e11-1e13 cm⁻¹. -2 The energy range is 10-50 keV, and the ion implantation angle is 0° to 90°.

[0006] Furthermore, step 6 specifically involves forming a 1nm silicon dioxide layer on the polycrystalline silicon surface through thermal oxidation, followed by chemical vapor deposition (CVD) of a 1-2nm silicon dioxide layer. These two silicon dioxide layers together serve as thin sidewalls.

[0007] Furthermore, the dose range of ion implantation in step 7 is 1e13-5e15cm. -2 The energy range is 0.1-10keV, and the ion implantation angle is 0° to 90°. If it is an N-type Fin-TFET device, the implanted impurities are P-type impurities such as boron and boron fluoride. If it is a P-type Fin-TFET device, the implanted impurities are N-type impurities such as phosphorus and arsenic.

[0008] Furthermore, in steps 9 and 10, when it is necessary to integrate P-type and N-type devices on a single chip, the fins of the source region of the N-type device and the drain region of the P-type device are etched simultaneously, and epitaxy is performed simultaneously; then the fins of the drain region of the N-type device and the source region of the P-type device are etched simultaneously, and epitaxy is performed simultaneously.

[0009] Furthermore, steps 9 and 10 employ in-situ doping or ion implantation for impurity doping. For N-type Fin-TFET devices, the doping concentration in the source region ranges from 1e17 to 1e20 cm⁻¹. -3 The doping concentration of the P-type impurity in the drain region ranges from 1e17 to 1e20 cm⁻¹. -3 The doping concentration in the source region is 1e17-1e20 cm⁻¹ for N-type impurities; for P-type Fin-T FET devices, the doping concentration is 1e17-1e20 cm⁻¹. -3 The N-type impurity, with a doping concentration ranging from 1e17 to 1e20 cm⁻¹, is epitaxially distributed in the drain region. -3 P-type impurities.

[0010] Furthermore, in step 11, the gate dielectric material can be a dielectric material such as silicon dioxide or hafnium oxide, and the gate metal stack material includes metal materials such as titanium nitride, tantalum nitride, and aluminum titanium nitride.

[0011] Furthermore, in step 12, the electrode material filling the through hole can be one of metals such as aluminum, copper, or tungsten.

[0012] Furthermore, the three-dimensional structure of the fin tunneling field-effect transistor after the drain region epitaxial process in step 10 is as follows: Figure 1 As shown: The device is based on a silicon substrate (7), with a well (6) existing in a fin-like structure on the upper part of the substrate, and its channel located below the polysilicon gate (2). The source region (11) and drain region (12) are located at both ends of the fin and are asymmetrically doped with impurities. The polysilicon gate (2) is arranged in a three-sided surrounding manner in the fin-like channel, realizing strong electrostatic control of the channel potential. The gate structure is electrically isolated and physically spaced from the source and drain regions (12) by thick sidewalls (10) and thin sidewalls (1). In addition, shallow trench isolation (5) is used to isolate adjacent fins.

[0013] Technical effects of the present invention: This invention proposes a method for fabricating a fin-type tunneling field-effect transistor (FET), combining a traditional planar TFET device with a FinFET structure. This method improves the on-state current while maintaining the advantage of low off-state current, and simultaneously suppresses bipolar current. Specifically, it involves self-aligning the extended region in the source region to form a tunneling junction at the gate-source overlap, increasing the tunneling current. Furthermore, the thick sidewalls fabricated before the source-drain epitaxy create an under-covered region structure at the drain, suppressing bipolar current. Meanwhile, the substrate remains primarily lightly doped, high-resistivity silicon, thus preserving the low off-state current advantage of the FET. Moreover, this fabrication method is based on the standard fin-type tunneling field-effect transistor process flow at advanced nodes. Without altering the basic process flow, it only requires an additional photolithography plate, maintaining the potential for large-scale production. Attached Figure Description

[0014] Figure 1 This is a three-dimensional schematic diagram and a cross-sectional schematic diagram of a fin tunneling field-effect transistor after the source-drain epitaxial process according to the method of the present invention. In the figure, 1 is a thin sidewall, 2 is a polysilicon gate, 5 is a shallow trench isolation, 6 is a well, 7 is a silicon substrate, 10 is a thick sidewall, 11 is the source region, 12 is the drain region, AA' is a cross-section along the fin direction, and BB' is a cross-section along the gate direction. Figure 2 This is a cross-sectional view of a fin tunneling field-effect transistor prepared according to the method of the present invention along the AA' direction (fin direction); Figures 3 to 12 This is a cross-sectional view of the process for fabricating a finned tunneling field-effect transistor according to the method of the present invention, wherein... Figures 3 to 7 This is a cross-sectional view along the BB' direction (gate direction). Figures 8 to 12 It is a cross-sectional view along the AA' direction (fin direction).

[0015] In the picture: 1 — Thin sidewall 2 — Polysilicon gate 3 — Fin protective oxide layer 4 — Fin-shaped channel area 5 — Shallow trench isolation 6 — Trap 7 — Silicon substrate 8 — Source region extension 9 — Photoresist 10 — Thick sidewall 11 — Source Region 12 — Drain Region 13 — Interlayer dielectric 14 — Gate oxide layer 15 — Gate high dielectric constant material layer 16 — Gate metal stack 17 — Metal gate 18 — Insulating material above the gate 19 — Metal Electrode Detailed Implementation

[0016] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0017] A cross-sectional view along the fin direction of the fin-type tunneling field-effect transistor prepared by the method of the present invention is shown below. Figure 2 As shown, its structure is as follows: the device is disposed on a silicon substrate (7) and a well (6) structure is formed on it. The well layer can be used to isolate the leakage current between devices; shallow trench isolation (STI) structure (5) is used to isolate different fins; the active region of the device is a fin-shaped channel region (4) located above the well (6), and the source region (11) and drain region (12) are connected on both sides of the channel region (4). At the junction of the finned channel region (4) and the source region (12), a source region extension region (8) is provided. The doping concentration in this region is precisely controlled by optimizing the injection conditions, which is the key to improving the tunneling current in this scheme. Considering the process compatibility with the existing reference platform, the source region (11) and the drain region (12) can be made of SiGe material with a narrow bandgap. The gate structure is arranged around the channel region. The material above the channel region is first a gate oxide layer (14) of silicon dioxide, then a gate high-k material layer (15) (such as hafnium oxide), and then a gate metal stack (16) for adjusting the threshold voltage of the device, which includes titanium nitride, tantalum nitride, TiAl alloy, etc. The metal gate (17) is used to apply the control voltage, and the top is provided with an insulating material (18) for protection; the thick sidewall (10) of the gate is located on the side of the gate oxide layer (14) and is made of an insulating material (such as silicon nitride) to precisely separate the gate structure from the heavily doped regions of the source region (11) / drain region (12), thereby preventing the diffusion of impurities from the source and drain regions to the channel below, preventing short-channel effects and unwanted parasitic capacitance; (13) is the interlayer dielectric to provide electrical isolation and mechanical support; the source region, drain region and gate are led out through the metal electrode (19).

[0018] Figures 3 to 12 The following describes a process of one embodiment of the fabrication method of the fin tunneling field-effect transistor provided by the present invention, with the following steps: First, a heavily boron-doped low-resistivity silicon substrate with a resistivity of 0.01 Ω-cm is prepared. Then, an almost intrinsically doped substrate (resistivity of 10 Ω-cm) is obtained through epitaxy as the substrate region of the Fin-TFET device (7), as shown below. Figure 3 As shown; Next, a fin etching process was performed using self-aligned double exposure technology to form Fin(4), with a Fin strip height of 110 nm, as shown. Figure 4 As shown; Next, shallow trench isolation (STI) is performed with a depth of 60-70 nm. The STI isolation region is formed by first depositing and then etching back (5), as shown in the example. Figure 5 As shown; Next, the trap implantation process will be performed, with the ion implantation dose range being 1e11-1e13 cm⁻¹. -2 The energy range is 30-50 keV, the ion implantation angle is 0° to 90°, and the doping concentration range is 1E15-1E18 cm⁻¹. -3 To form an N-well, the injected impurities are N-type impurities such as phosphorus and arsenic; to form a P-well, the injected impurities are P-type impurities such as boron and boron fluoride. The injected dose range is 1e11-1e13 cm⁻¹. -2 The energy range is 10-50 keV, the ion implantation angle is 0° to 90°, followed by annealing to form a trap (6), such as Figure 6 As shown; Next, the polysilicon gate is fabricated. Specifically, a 1nm silicon dioxide layer is first formed on the fin surface using thermal oxidation (3) to protect the channel. Then, 120nm-200nm of polysilicon is deposited across the entire wafer. After being smoothed to the target gate height using chemical mechanical polishing (CMP), a 10-20nm layer of amorphous carbon is deposited as a hard mask. The gate pattern is then transferred to the hard mask using photolithography. Finally, the hard mask is used to define the polysilicon gate (2). Figure 7 As shown; Next, the thin sidewall and source region extension ion implantation process is performed. Specifically, after defining the polysilicon gate, a 1nm silicon dioxide layer is formed on the polysilicon using thermal oxidation, followed by chemical vapor deposition (CVD) of a 1-2nm silicon dioxide layer. These two silicon dioxide layers together serve as the thin sidewall (1). Then, a hard mask and photoresist (9) are used to define the source region of the Fin-TFET device. Boron (N-type Fin-TFET) or arsenic (P-type Fin-TFET) is implanted via ion implantation, with an implantation dose range of 1e13-5e15cm. -2 The energy range is 0.1-10 keV, the ion implantation angle is 0° to 90°, and the doping concentration is 1E19-5E20 cm⁻¹. -3 This forms a highly doped source region extension region (8), such as Figure 8 As shown; Next, the photoresist (9) is removed, and the impurities injected into the source region extension region are annealed to form the gate-source overlap region and gate-drain undercover region of Fin-TFET; Next, a thick silicon nitride sidewall is deposited on both sides of the gate (10). Then, a SiCN hard mask is deposited. Then, the source region of the Fin-TFET is defined by photolithography etching, and the remaining area is covered by photoresist. After that, SiCN is etched with fluorine plasma to expose the source fins of the Fin-TFET. Then, excess photoresist is cleaned, and then the exposed fins are etched to make room for epitaxial growth. Next, the source region SiGe is epitaxially grown to form the source region of the Fin-TFET (11). If an N-type Fin-TFET is prepared, the source region is doped with P-type boron impurity. If a P-type Fin-TFET is prepared, the source region is doped with N-type phosphorus impurity. The doping concentration is 1E20cm³. -3 Then, repeat the above steps, using SiCN as a hard mask, to etch away the fins (Fin) of the Fin-TFET drain region and perform epitaxy of the drain region SiGe to form the drain region of the Fin-TFET (12). If an N-type Fin-TFET is fabricated, the drain region is doped with N-type phosphorus impurity; if a P-type Fin-TFET is fabricated, the drain region is doped with P-type boron impurity, with a doping concentration of 1E20cm⁻¹. -3 ,like Figure 9 As shown; Next, annealing activates the impurities injected into the source / drain region; Next, 150-250nm insulating phosphosilicate glass is deposited across the entire wafer as an interlayer dielectric (13), and chemical mechanical polishing (CMP) is performed using polycrystalline silicon as a stop layer. Figure 10 As shown; Next, polysilicon is removed using isotropic etching with highly selective materials. Since there is a layer of silicon dioxide material above the fins (4) in the channel region as a protective oxide layer (3), the fins (4) in the channel region will not be damaged. Then, silicon dioxide under the gate is etched by isotropic etching, at which time silicon dioxide (3) under the polysilicon and thin sidewalls (1) are removed simultaneously. Next, a thin (less than 1 nm) layer of silicon dioxide is deposited as the gate oxide layer (14) using atomic layer deposition technology, and then a 2.2 nm layer of hafnium oxide is deposited as the gate high-k material (15). Then, the work function is adjusted by depositing different metal layers as gate metal stacks (16) multiple times, including titanium nitride, tantalum nitride, TiAl alloy, etc. Finally, a 100 nm thick layer of tungsten metal is deposited using chemical vapor deposition technology, and the insulating material phosphosilicate glass (13) is ground flat to form a metal gate (17). Figure 11 As shown; Next, the metal gate is etched back, and after etching, a layer of insulating material silicon oxynitride is deposited (18). Then, the insulating material phosphosilicate glass is used as a stop layer and polished flat. The purpose of this is to prevent the metal gate from short-circuiting with the source and drain electrodes. Next, the insulating material phosphosilicate glass is deposited over the entire wafer. Then, the source region, drain region, and source electrode vias, drain electrode vias, and gate electrode vias on the gate metal stack region are etched by exposure. The vias are then filled with tungsten metal to form metal electrodes (19). Figure 12 As shown.

[0019] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the scope of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A method for fabricating a Fin-TFET, characterized in that, Includes the following steps: Step 1: Provide a lightly doped silicon substrate with either N-type or P-type doping. Step 2: Perform fin etching using self-aligned double exposure technology; Step 3: Perform shallow trench isolation process. The specific method is to deposit an oxide layer on the entire wafer and then form shallow trench isolation by etching back. Step 4: The N-well and P-well regions are exposed by photolithography etching, and the N-well and P-well are formed by ion implantation and annealing. Step 5: Deposit polysilicon across the entire wafer and create a hard mask to define the polysilicon gate; Step 6: Apply thin sidewall construction techniques; Step 7: Photolithography and etching expose the source window of the Fin-TFET device, ion implantation is performed on the source extension region, followed by annealing, thereby forming the gate-source overlap region and the gate-drain undercover region of the Fin-TFET. Step 8: Deposit silicon nitride across the entire wafer and anisotropically etch to form thick sidewalls; Step 9: Create a hard mask to define the source region of the Fin-TFET, etch the fins of the source region, and then perform source region epitaxy; Step 10: Create a hard mask to define the drain region of the Fin-TFET, etch the fins of the drain region, and then perform drain region epitaxy; Step 11: After removing the polysilicon gate, deposit multiple layers of gate dielectric, then deposit a gate metal stack to adjust the work function, and then deposit metal to form a metal gate; Step 12: Form the back-end vias and interconnects.

2. The preparation method according to claim 1, characterized in that, The thickness range of the shallow trench isolation in step 3 is 60nm-100nm.

3. The preparation method according to claim 1, characterized in that, In step 4, the ion implantation dose range is 1e11-1e13 cm⁻¹. -2 The energy range is 10-50 keV, and the ion implantation angle is 0° to 90°.

4. The preparation method according to claim 1, characterized in that, Step 6 specifically involves forming a 1nm silicon dioxide layer on the polycrystalline silicon surface through thermal oxidation, followed by chemical vapor deposition of a 1-2nm silicon dioxide layer. These two silicon dioxide layers together serve as thin sidewalls.

5. The preparation method according to claim 1, characterized in that, The dose range for ion implantation in step 7 is 1e13-5e15cm. -2 The energy range is 0.1-10keV, and the ion implantation angle is 0° to 90°. If it is an N-type Fin-TFET device, the implanted impurity is a P-type impurity, and if it is a P-type Fin-TFET device, the implanted impurity is an N-type impurity.

6. The preparation method according to claim 1, characterized in that, In steps 9 and 10, when it is necessary to integrate P-type and N-type devices on a single chip, the fins of the source region of the N-type device and the drain region of the P-type device are etched simultaneously, and epitaxy is performed simultaneously; then the fins of the drain region of the N-type device and the source region of the P-type device are etched simultaneously, and epitaxy is performed simultaneously.

7. The preparation method according to claim 1, characterized in that, Steps 9 and 10 employ in-situ doping or ion implantation for impurity doping. For N-type Fin-TFET devices, the doping concentration range in the source region is 1e17-1e20 cm⁻¹. -3 The doping concentration of the P-type impurity in the drain region ranges from 1e17 to 1e20 cm⁻¹. -3 N-type impurities; For P-type Fin-T FET devices, the doping concentration in the source region is 1e17-1e20 cm⁻¹. -3 The N-type impurity, with a doping concentration ranging from 1e17 to 1e20 cm⁻¹, is epitaxially distributed in the drain region. -3 P-type impurities.

8. The preparation method according to claim 1, characterized in that, In step 11, the gate dielectric material is a dielectric material: silicon dioxide and hafnium oxide, and the gate metal stack material is a metal material, including titanium nitride, tantalum nitride and aluminum titanium nitride.

9. The preparation method according to claim 1, characterized in that, In step 12, the electrode material used to fill the through hole is one of aluminum, copper, or tungsten metal.

10. The preparation method according to claim 1, characterized in that, After the drain region epitaxial process in step 10, the three-dimensional structure of the fin tunneling field-effect transistor is as follows: the device is based on a silicon substrate (7), the well (6) exists in the upper part of the substrate in a fin-like structure, its channel is located below the polysilicon gate (2), the source region (11) and the drain region (12) are located at both ends of the fin and are asymmetrically doped with impurities, the polysilicon gate (2) is arranged in a three-sided surrounding manner in the fin-like channel, the gate structure is electrically isolated and physically separated from the source region and the drain region (12) through thick sidewalls (10) and thin sidewalls (1), and shallow trench isolation (5) is used to isolate adjacent fins.

Images