Near-full-grid-control FinFET structure and preparation method and application thereof

Abstract

The invention discloses a near-full-grid-control FinFET (FinFET) structure and a preparation method and an application of the near-full-grid-control FinFET structure. The near-full-grid-control FinFET structure comprises an epitaxial structure, an ohmic contact layer, a source electrode, a drain electrode and a grid electrode, the epitaxial structure comprises a heterostructure and a cap layer, the epitaxial structure is provided with a protruding fin-shaped part, a carrier channel in the heterostructure is located in the fin-shaped part, and the cap layer is located on the topmost layer of the fin-shaped part; the ohmic contact layer is arranged on the two sides of the fin-shaped part in the first direction, the source electrode and the drain electrode are arranged on the ohmic contact layer, the grid electrode is arranged between the source electrode and the drain electrode in the first direction, the grid electrode comprises a top grid and side grids, the side grids are distributed on the two sides of the fin-shaped part in the second direction, and the top grid is arranged on the top of the cap layer and connected with the side grids into a whole. According to the invention, access areas between gate-source and gate-drain do not exist, the whole Fin channel is almost regulated and controlled by the side gate by using the thick GaN cap layer, and the current linearity can be effectively improved on the basis of increasing the current density, so that the output power density, gain and the like are increased.

Description

Technical Field

[0001] This invention specifically relates to a near-full-gate controlled FinFET structure, its fabrication method, and its application, belonging to the field of electronic device technology. Background Technology

[0002] Gallium nitride (GaN) materials possess a wide bandgap (3.4 eV), high breakdown voltage (3.1 MV / cm), and high electron mobility (~1800 cm⁻¹). 2 GaN boasts advantages such as high current density, high voltage, and high power, making it a representative material capable of simultaneously achieving high frequency, high voltage, and high power. Based on spontaneous polarization and piezoelectric polarization effects, GaN-based heterostructures (such as AlGaN / GaN, AlInGaN / GaN, AlN / GaN, etc.) can form 2DEG (Two-dimensional electron gas) channels with both high electron mobility and high electron concentration without deliberate doping, making them an ideal choice for next-generation HEMT (High-electron-mobility transistor) devices. GaN HEMTs offer significant advantages such as high current density, high breakdown voltage, and high frequency. As a power amplifier (PA), they have been successfully applied to 5G core infrastructure such as base stations, gradually replacing traditional silicon-based LDMOS (Lateral Double-diffused Metal-Oxide-Semiconductor) devices, and will continue to play a crucial role in the entire 5G communication technology. In the consumer electronics sector, which boasts a broader market prospect, silicon-based GaN HEMTs for RF (Radio Frequency) / MM Wave (Millimeter Wave) applications, with their low-cost advantage, are equally attractive. Compared to traditional gallium arsenide (GaAs) HBTs (Heterojunction Bipolar Transistors), GaN HEMTs exhibit stronger power output capabilities and superior heat dissipation performance. Therefore, they can highlight their inherent advantages in 5G communication services, which place higher demands on power, and are expected to be applied to the transmitter PA in mobile phone RF front-end modules.

[0003] To simplify circuit design and reduce static power consumption, mobile RF power amplifiers (PAs) in devices such as smartphones require devices to be off at 0V gate voltage, i.e., to achieve enhancement-mode design. Furthermore, constrained by the actual operating voltage requirements of mobile RF PAs (≤10V), increasing device current density has become the primary means of improving output power density. Multi-channel GaN-based heterojunction materials have lower sheet resistance, providing higher current density for devices. However, conventional planar gates cannot fully deplete multi-layer channels, making multi-channel planar devices difficult to turn off. Therefore, by combining the effective control of multi-layer channels using Fin structures, multi-channel Fin structures overcome the problem of difficult turn-off of multi-channel devices while increasing current density. Figure 1a , Figure 1b , Figure 1c This diagram illustrates a conventional GaN-based multi-channel FinFET. To improve the device's current density and output power density, the AlGaN layer is typically n-type doped to increase the 2DEG concentration within the channel. However, while a higher 2DEG concentration helps reduce the series resistance of the access region and achieve a larger current density, it makes enhancement-mode designs more difficult to implement. On the other hand, reducing the 2DEG concentration makes enhancement-mode multi-channel FinFET designs easier to implement, but it simultaneously increases the source-drain access region resistance and reduces the device current density.

[0004] To address these issues, numerous research institutions worldwide have conducted a series of studies on enhancement-mode GaN-based multi-channel FinFETs. Among them: the Swiss Federal Institute of Technology in Lausanne (EPFL) enhanced the gate's control over the channel by reducing the width of the multi-channel Fin structure to below 20 nm, achieving an enhancement-mode design; Virginia Polytechnic Institute and State University (VT) successfully fabricated an enhancement-mode FinFET by depleting electrons in the channel using p-NiO gate technology; and HRL Laboratories, using sidewall technology to achieve an enhancement-mode FinFET with an ultra-thin AlGaN barrier and a 100 nm wide Fin structure, experienced a sharp decrease in transconductance after reaching its maximum value as the gate voltage increased, resulting in low current linearity. Improving current linearity helps to enhance device output current density and power gain, which is an important aspect of evaluating PA performance. Teledyne Scientific Company (TSI) designed and fabricated a Buried Dual Gate (BRIDGE) FET, which significantly improved the device's current linearity by utilizing the control mechanism of the Fin structure sidewall gate, but the device is a depletion-type design.

[0005] However, FinFETs fabricated using the EPFL method face significant challenges in achieving enhancement-mode design due to the high 2DEG concentration in the multi-channel heterostructure, requiring extremely small Fin widths (less than 20 nm). VT successfully fabricated enhancement-mode FinFETs using p-NiO gate technology, but p-NiO growth is technically difficult and exhibits poor thermal stability. HRL's FinFETs, fabricated using sidewall technology, achieved enhancement-mode design through an ultra-thin AlGaN barrier and a 100 nm wide Fin structure, but their transconductance drops sharply after reaching approximately 50% of its maximum value, exhibiting low current linearity. Furthermore, due to the absence of a gate dielectric, their gate voltage operating range is extremely small (0–1.5 V). Summary of the Invention

[0006] The main objective of this invention is to provide a near-full-gate controlled FinFET structure, its fabrication method, and its application, thereby overcoming the shortcomings of the prior art.

[0007] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:

[0008] A first aspect of the present invention provides a near-full-gate controlled FinFET structure, comprising:

[0009] An epitaxial structure, comprising a heterostructure and a capping layer, wherein the epitaxial structure has a protruding fin-like portion, a carrier channel within the heterostructure is located within the fin-like portion, and the capping layer is located at the top layer of the fin-like portion;

[0010] An ohmic contact layer is disposed on both sides of the fin along a first direction, and the ohmic contact layer is electrically connected to the carrier channel.

[0011] The fin comprises a source, a drain, and a gate. The source and the drain are disposed on and electrically connected to the ohmic contact layer. The gate is disposed between the source and the drain along a first direction. The gate includes a top gate and a side gate. The side gates are distributed on both sides of the fin along a second direction. The top gate is disposed on the top of the capping layer and is integrally connected to the side gates. The capping layer ensures that the unit capacitance between the top gate and the carrier channel is less than the unit capacitance between the side gate and the carrier channel. The top gate has less control over the current of the carrier channel than the side gate has. The first direction intersects the second direction.

[0012] A second aspect of the present invention provides an electronic device comprising the aforementioned near-full-gate FinFET structure.

[0013] A third aspect of this invention provides a method for fabricating a near-fully-gate controlled FinFET structure, comprising:

[0014] An epitaxial structure is provided, the epitaxial structure including a heterostructure and a capping layer disposed on the heterostructure, wherein a carrier channel is formed within the heterostructure;

[0015] The capping layer and part of the heterostructure located in the source and drain ohmic regions are removed, and part of the capping layer and part of the heterostructure located in the gate region are removed, thereby forming a raised fin in the gate region. The carrier channel is retained only in the fin, and the remaining capping layer is located on the top layer of the fin. The source and drain ohmic regions are located on both sides of the gate region along the first direction.

[0016] An ohmic contact layer is formed in the source and drain ohmic regions of the epitaxial structure, and the ohmic contact layer is electrically connected to the carrier channel in the fin.

[0017] A gate is formed in the gate region of the epitaxial structure. The gate includes a top gate and a side gate. The side gate is located on both sides of the fin along a second direction. The top gate is disposed on top of the capping layer and is integrally connected with the side gate. The capping layer at least makes the unit capacitance between the top gate and the carrier channel smaller than the unit capacitance between the side gate and the carrier channel. The control force of the top gate on the current of the carrier channel is smaller than the control force of the side gate on the current of the carrier channel. The first direction intersects the second direction.

[0018] Compared with the prior art, the advantages of the present invention include:

[0019] This invention proposes a novel near-full-gate multi-channel FinFET structure with a thick GaN capping layer. Based on a multi-channel GaN-based heterostructure with low Al composition and a thin AlGaN barrier layer, the near-full-gate multi-channel FinFET with a thick GaN capping layer is fabricated using a thick GaN capping layer and secondary epitaxial growth ohmic technology. This enables the design of enhancement-mode devices with high current density and high current linearity, thus meeting the needs of mobile PA applications.

[0020] This invention proposes a novel near-full-gate controlled multi-channel FinFET structure with a thick GaN capping layer. This structure eliminates the gate-source and gate-drain junction regions. The thick GaN capping layer allows for near-side-gate control of the entire Fin channel, effectively improving current linearity while increasing current density, thereby enhancing output power density and gain.

[0021] The present invention proposes a novel near-full-gate multi-channel FinFET structure with a thick GaN capping layer. In terms of enhancement-mode design, since the GaN-based multi-channel heterostructure uses a low Al composition and a thin AlGaN barrier layer, enhancement-mode FinFETs can be fabricated without the need to fabricate extremely small Fin structure widths, thereby significantly improving the reliability and stability of device fabrication. Attached Figure Description

[0022] Figure 1a , Figure 1b , Figure 1c This is a schematic diagram of a conventional GaN-based multichannel FinFET structure.

[0023] Figure 2a , Figure 2b , Figure 2c This is a schematic diagram of a near-full-gate controlled FinFET structure provided in a typical embodiment of the present invention;

[0024] Figure 3a , Figure 3b , Figure 3cThis is a schematic diagram of a GaN-based multi-channel epitaxial structure provided in Embodiment 1 of the present invention;

[0025] Figure 4a , Figure 4b , Figure 4c This is a schematic diagram of the structure after depositing the silicon oxide mask layer in Embodiment 1 of the present invention;

[0026] Figure 5a , Figure 5b , Figure 5c This is a schematic diagram of the structure after the gate region electron beam photoresist patterning in Example 1;

[0027] Figure 6a , Figure 6b , Figure 6c This is a schematic diagram of the structure after the electron beam photoresist pattern is transferred to the silicon oxide mask layer in Embodiment 1 of the present invention;

[0028] Figure 7a , Figure 7b , Figure 7c This is a schematic diagram of the structure after etching the thick capping layer and multi-layer channel in the source and drain ohmic regions in Embodiment 1 of the present invention;

[0029] Figure 8a , Figure 8b , Figure 8c This is a schematic diagram of the structure after the secondary epitaxial ohmic contact layer in Embodiment 1 of the present invention;

[0030] Figure 9a , Figure 9b , Figure 9c This is a schematic diagram of the structure of the patterned AR-P-6200 electron beam photoresist formed in Embodiment 1 of the present invention;

[0031] Figure 10a , Figure 10b , Figure 10c This is a schematic diagram of the structure after etching to form the Fin structure in Embodiment 1 of the present invention;

[0032] Figure 11a , Figure 11b , Figure 11c This is a schematic diagram of the structure after active region isolation in Embodiment 1 of the present invention;

[0033] Figure 12a , Figure 12b , Figure 12c This is a schematic diagram of the structure after the gate dielectric is formed in Embodiment 1 of the present invention;

[0034] Figure 13a , Figure 13b , Figure 13c This is a schematic diagram of the structure after the source and drain ohmic contact electrodes are formed in Embodiment 1 of the present invention;

[0035] Figure 14a , Figure 14b , Figure 14c This is a schematic diagram of the structure after the T-shaped gate is formed in Embodiment 1 of the present invention;

[0036] Figure 15a , Figure 15b , Figure 15c This is a schematic diagram of a GaN-based multi-channel epitaxial structure provided in Embodiment 2 of the present invention;

[0037] Figure 16a , Figure 16b , Figure 16c This is a schematic diagram of the structure after forming the patterned AR-P-6200 electron beam photoresist in Embodiment 2 of the present invention;

[0038] Figure 17a , Figure 17b , Figure 17c This is a schematic diagram of the structure after etching to form the Fin structure in Embodiment 2 of the present invention;

[0039] Figure 18a , Figure 18b , Figure 18c This is a schematic diagram of the structure after the silicon oxide mask layer is formed in Embodiment 2 of the present invention;

[0040] Figure 19a , Figure 19b , Figure 19c This is a schematic diagram of the structure after the gate region electron beam photoresist patterning is completed in Embodiment 2 of the present invention;

[0041] Figure 20a , Figure 20b , Figure 20c This is a schematic diagram of the structure after the electron beam photoresist pattern is transferred to the silicon oxide mask layer in Embodiment 2 of the present invention;

[0042] Figure 21a , Figure 21b , Figure 21c This is a schematic diagram of the structure after etching the thick capping layer and multi-layer channel in the source and drain ohmic regions in a typical embodiment of the present invention.

[0043] Figure 22a , Figure 22b , Figure 22c This is a schematic diagram of the structure after secondary epitaxy to form an ohmic contact layer in Embodiment 2 of the present invention;

[0044] Figure 23a , Figure 23b These are the local structure and conduction band diagram of a conventional FinFET;

[0045] Figure 24a , Figure 24bThese are partial structures and conduction band diagrams of a near-full-gate FinFET structure provided in a typical embodiment of the present invention. Detailed Implementation

[0046] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate the technical solution, its implementation process, and its principles.

[0047] A first aspect of the present invention provides a near-full-gate controlled FinFET structure, comprising:

[0048] An epitaxial structure, comprising a heterostructure and a capping layer, wherein the epitaxial structure has a protruding fin-like portion, a carrier channel within the heterostructure is located within the fin-like portion, and the capping layer is located at the top layer of the fin-like portion;

[0049] An ohmic contact layer is disposed on both sides of the fin along a first direction, and the ohmic contact layer is electrically connected to the carrier channel.

[0050] The fin comprises a source, a drain, and a gate. The source and the drain are disposed on and electrically connected to the ohmic contact layer. The gate is disposed between the source and the drain along a first direction. The gate includes a top gate and a side gate. The side gates are distributed on both sides of the fin along a second direction. The top gate is disposed on the top of the capping layer and is integrally connected to the side gates. The capping layer ensures that the unit capacitance between the top gate and the carrier channel is less than the unit capacitance between the side gate and the carrier channel. The top gate has less control over the current of the carrier channel than the side gate has. The first direction intersects the second direction.

[0051] Furthermore, the heterostructure includes at least one channel layer and at least one barrier layer stacked together, the carrier channel is formed at the interface between the channel layer and the barrier layer, the capping layer is located on the topmost channel layer or barrier layer, and the capping layer satisfies specific conditions.

[0052] In a more specific implementation, the heterostructure includes multiple channel layers and multiple barrier layers stacked together, and the heterostructure has multiple carrier channels.

[0053] Furthermore, the capping layer is formed of a material with a relative permittivity between 1 and 50, and / or the thickness of the capping layer does not exceed 500 nm.

[0054] Furthermore, the thickness of the capping layer is 100nm-500nm. For example, the thickness of the capping layer can be 10nm, 50nm, 100nm, 120nm, 210nm, 320nm, 350nm, 400nm, 450nm, 500nm, etc.

[0055] Furthermore, the material of the capping layer includes III-V group compounds, metal oxides, non-metal oxides, or non-metal nitrides.

[0056] Furthermore, the material of the capping layer includes, but is not limited to, any one of gallium nitride, aluminum nitride, aluminum gallium nitride, aluminum oxide, hafnium oxide, silicon oxide, and silicon nitride.

[0057] Furthermore, the thickness of the barrier layer does not exceed 200 nm, and the Al content in the barrier layer does not exceed 60%. For example, the thickness of the barrier layer can be 10 nm, 15 nm, 30 nm, 55 nm, 80 nm, 115 nm, 155 nm, 178 nm, 200 nm, etc., and the Al content in the barrier layer can be 5%, 8%, 10%, 15%, 20%, 25%, 28%, 30%, 45%, 52%, 54%, 60%, etc.

[0058] Furthermore, the material of the barrier layer includes at least one of AlGaN, AlN, AlInN, and AlInGaN, but is not limited thereto.

[0059] Furthermore, the material of the channel layer includes GaN, but is not limited to this.

[0060] Furthermore, the gate is generally a T-shaped gate, a strip gate, or a screw gate.

[0061] Furthermore, in the first direction, the width of the fin portion does not exceed 1000nm, preferably 80nm-1000nm. For example, the width of the fin portion can be 80nm, 100nm, 200nm, 350nm, 500nm, 850nm, 1000nm, etc.

[0062] Furthermore, the ohmic contact layer includes an n-type heavily doped layer, the top surface of which is flush with the top surface of the capping layer.

[0063] Furthermore, the n-type heavily doped layer includes n++GaN layers, etc.

[0064] In a more specific implementation, the near-full-gate FinFET structure further includes a gate dielectric layer, which is continuously disposed between the top gate, the side gate, the epitaxial structure, and the ohmic contact layer.

[0065] Furthermore, the material of the gate dielectric layer includes Al2O3, SiO2, HfO2, HfO2, AlON, AlN, and SiN. x At least one of them, but not limited to this.

[0066] Furthermore, the near-full-gate FinFET structure is either an enhancement-mode device structure or a depletion-mode device structure.

[0067] A second aspect of the present invention provides an electronic device comprising the aforementioned near-full-gate FinFET structure.

[0068] Furthermore, the electronic device includes a power amplifier for use in 5G communication bands, millimeter wave bands, or terahertz bands.

[0069] A third aspect of this invention provides a method for fabricating a near-fully-gate controlled FinFET structure, comprising:

[0070] An epitaxial structure is provided, the epitaxial structure including a heterostructure and a capping layer disposed on the heterostructure, wherein a carrier channel is formed within the heterostructure;

[0071] The capping layer and part of the heterostructure located in the source and drain ohmic regions are removed, and part of the capping layer and part of the heterostructure located in the gate region are removed, thereby forming a raised fin in the gate region. The carrier channel is retained only in the fin, and the remaining capping layer is located on the top layer of the fin. The source and drain ohmic regions are located on both sides of the gate region along the first direction.

[0072] An ohmic contact layer is formed in the source and drain ohmic regions of the epitaxial structure, and the ohmic contact layer is electrically connected to the carrier channel in the fin.

[0073] A gate is formed in the gate region of the epitaxial structure. The gate includes a top gate and a side gate. The side gate is located on both sides of the fin along a second direction. The top gate is disposed on top of the capping layer and is integrally connected with the side gate. The capping layer at least makes the unit capacitance between the top gate and the carrier channel smaller than the unit capacitance between the side gate and the carrier channel. The control force of the top gate on the current of the carrier channel is smaller than the control force of the side gate on the current of the carrier channel. The first direction intersects the second direction.

[0074] In a more specific implementation, the fabrication method of the near-full-gate FinFET structure further includes: first forming a gate dielectric layer on the surface of the epitaxial structure and the ohmic contact layer, and then forming the gate on the gate dielectric layer.

[0075] Furthermore, the gate dielectric layer can be an Al2O3 layer deposited using ALD (Atomic Layer Deposition), or it can be a gate dielectric deposited using various other methods, such as SiO2, HfO2, AlON, or SiN. x The dielectric material can be a single dielectric, or a composite gate dielectric such as Al2O3 / AlN or Al2O3 / HfO2. Furthermore, the dielectric sidewall material used in the embodiments of this invention is not limited to ALD-deposited SiN. x It is also applicable to various other media layers and media layers deposited by various other methods.

[0076] The following will further explain the technical solution, its implementation process and principle in conjunction with the accompanying drawings and specific implementation examples. Unless otherwise specified, the various semiconductor materials, semiconductor processing technologies and equipment used in the embodiments of the present invention are all known in the art, and are not specifically limited or described here.

[0077] Please see Figure 2a , Figure 2b and Figure 2c A near-full-gate controlled multi-channel FinFET structure with a thick GaN capping layer, comprising:

[0078] The epitaxial structure comprises a substrate, an epitaxial structure formed on the substrate, an n++ GaN ohmic contact layer disposed on the epitaxial structure, and a source electrode (i.e., source electrode, hereinafter the same), a drain electrode (i.e., drain electrode, hereinafter the same) and a gate electrode matched with the epitaxial structure. The epitaxial structure includes a buffer layer, at least one GaN / AlGaN heterojunction, and a GaN capping layer sequentially stacked on the substrate. The GaN / AlGaN heterojunction includes a GaN channel layer and an AlGaN barrier layer stacked on the substrate. A carrier channel (e.g., a two-dimensional electron gas) is formed at the interface between the GaN channel layer and the AlGaN barrier layer. Furthermore, the gate region of the epitaxial structure has a fin-like portion, the bottom of which is located in the bottommost GaN channel layer. All carrier channels inside the epitaxial structure are... Located in the fin, a GaN capping layer is located on the top layer of the fin. An n++ GaN ohmic contact layer is stacked on the bottom GaN channel layer and distributed along the first direction on both sides of the fin. The n++ GaN ohmic contact layer is electrically connected to the carrier channel in the fin. The source and drain are disposed on the n++ GaN ohmic contact layer and electrically connected to the n++ GaN ohmic contact layer. The gate is disposed between the source and drain along the first direction. The gate includes a top gate and a side gate. The top gate is disposed above the GaN capping layer. The side gate is disposed on both sides of the fin along the second direction and is integrated with the top gate. In addition, a gate dielectric layer is disposed between the gate, the epitaxial structure, and the n++ GaN ohmic contact layer. The first direction and the second direction intersect perpendicularly.

[0079] Specifically, the substrate material can be silicon, sapphire, silicon carbide, gallium nitride, aluminum nitride, etc., and the buffer layer material can be a group III nitride, such as GaN. The thickness of the substrate and the buffer layer can be set according to specific requirements, and no specific limitation is made here.

[0080] Specifically, the epitaxial structure can be a single-channel structure comprising only one GaN / AlGaN heterojunction, or a dual-channel or multi-channel structure comprising multiple stacked GaN / AlGaN heterojunctions. Specifically, the thickness of the AlGaN barrier layer does not exceed 200 nm, and the Al content in the AlGaN barrier layer does not exceed 60%. It should be noted that the material of the barrier layer is not limited to AlGaN-based materials; it can also be applied to materials with other barrier layers, such as AlN-based, AlInN-based, and AlInGaN-based materials.

[0081] It should be noted that the GaN / AlGaN heterojunction in this epitaxial structure can also be a back barrier structure.

[0082] Specifically, the thickness of the GaN capping layer does not exceed 1000nm.

[0083] Specifically, the gate is generally a T-shaped gate, a strip gate, or a screw gate.

[0084] Specifically, by reducing the Al composition and thinning the AlGaN barrier layer, a lower electron concentration is achieved, enabling enhancement-mode FinFET designs using a wider (~80nm) Fin structure, significantly reducing the fabrication difficulty of the Fin structure. Furthermore, a short-channel FinFET was fabricated using secondary epitaxial growth ohmic technology, with almost the entire channel effectively controlled by the gate (i.e., gate length LG ≈ source-drain distance LDS, e.g.) Figure 2b (As shown). Because there are no access regions between the gate and source, or between the gate and drain, the knee voltage of the device can be significantly reduced while increasing the device current density. Furthermore, the presence of a thick GaN capping layer weakens the influence of the top gate on the carrier channel, causing the carrier channel to be mainly controlled by the side gate (e.g., Figure 2c (As shown). As the gate voltage increases, electrons extend laterally from the center of the Fin structure to both sides along the first direction. This unique channel-opening mechanism causes the transconductance to increase continuously with the gate voltage, improving current linearity and thus increasing the power gain of the PA.

[0085] Specifically, according to the capacitance calculation formula, unit capacitance = absolute permittivity multiplied by the relative permittivity of the material divided by the electrode spacing. For example, given that the relative permittivity of both gallium nitride (GaN) and aluminum oxide (ACO) gate dielectrics is around 9, when the GaN capping layer thickness is 90 nm and the ACO gate dielectric thickness is 10 nm, the unit capacitance formed between the side gate and the channel is approximately 10 times that between the top gate and the channel. According to the formula charge density (Q) = unit capacitance (C) multiplied by gate voltage (V), with the same gate voltage increment, the side gate can induce more charge carriers compared to the top gate; that is, the charge carriers in the channel are mainly controlled by the side gate. Furthermore, if a material with a lower relative permittivity (such as silicon dioxide, with a relative permittivity of 3.9) is used as the capping layer material, and the material thickness is increased, the capacitance between the top gate and the channel will be even smaller, meaning the top gate's control over the channel will be weaker. This structure allows the charge carriers in the channel to be mainly controlled by the side gate, which alleviates the inter-electron scattering in the two-dimensional electron gas channel caused by the increase in gate voltage, thereby suppressing the decrease in transconductance and increasing the current linearity of the device.

[0086] Example 1

[0087] A method for fabricating a near-full-gate controlled multi-channel FinFET structure with a thick GaN capping layer (first defining the gate region with negative adhesive, then defining the Fin structure with positive adhesive), specifically includes the following steps:

[0088] 1) Multi-channel AlGaN / GaN epitaxial structures with thick GaN capping layers are epitaxially grown on a substrate using MOCVD (Metal-organic Vapor Deposition) technology, such as... Figure 3a , Figure 3b , Figure 3c As shown in the figure. The thickness of the GaN capping layer is 100 nm, the thickness of the AlGaN barrier layer is 10 nm, the Al content is 10%, the thickness of the GaN channel layer is 10 nm, the substrate material can be silicon, sapphire, silicon carbide, gallium nitride, aluminum nitride, etc., and the buffer layer material can be GaN, etc.

[0089] 2) A silicon oxide layer is formed on the thick GaN capping layer as a mask layer, with a thickness of 200 nm, such as... Figure 4a , Figure 4b , Figure 4c As shown.

[0090] 3) AR-N-7520 electron beam photoresist is applied to the gate region on the mask layer to define the T-gate foot size of the device, i.e., gate length LG ≈ 50nm-800nm, such as... Figure 5a , Figure 5b , Figure 5c As shown.

[0091] 4) Fluorine-based ICP (Inductively Coupled Plasma) etching technology was used, with AR-N-7520 electron beam photoresist as a mask, to etch the silicon oxide mask layer in the source and drain ohmic regions. The etching rate was controlled at 1–20 nm / min. After etching, the AR-N-7520 electron beam photoresist was removed. Figure 6a , Figure 6b , Figure 6c As shown.

[0092] 5) Etching of source and drain ohmic regions: Using chlorine-based ICP etching technology, the thick GaN capping layer and multi-channel AlGaN / GaN heterojunction located in the source and drain ohmic regions are etched. The etching rate is controlled at 1–20 nm / min, stopping when the etching reaches the bottommost GaN channel layer. Figure 7a , Figure 7b , Figure 7c As shown.

[0093] 6) Secondary epitaxial ohmic contact layer: Using MOCVD, n++GaN is epitaxially grown on the bottom GaN channel layer exposed in the source and drain ohmic regions as an ohmic contact layer. The doping concentration and thickness of n++GaN ensure good ohmic contact with the channel electrons in the multi-channel AlGaN / GaN epitaxial structure. Afterwards, the silicon oxide mask layer is removed, such as... Figure 8a , Figure 8b , Figure 8c As shown.

[0094] 7) A patterned AR-P-6200 (α-methyl styrene-co-α-chloroacrylate methylester) electron beam photoresist is formed on the top surface of the thick GaN capping layer and the n++ GaN ohmic contact layer as a mask layer for etching to form the Fin structure, such as... Figure 9a , Figure 9b , Figure 9c As shown.

[0095] 8) Etching of the thick capping layer and multi-channel heterojunction in the Fin structure region: Chlorine-based ICP etching technology was used, with AR-P-6200 electron beam photoresist as a mask, to etch the thick GaN capping layer and multi-channel AlGaN / GaN heterojunction in the Fin structure region. The etching rate was controlled between 1 nm / min and 20 nm / min, and etching was stopped at the bottom GaN channel layer. After etching, the photoresist was removed. Figure 10a , Figure 10b , Figure 10c As shown.

[0096] 9) Active region isolation: Active region isolation is performed using N-ion implantation technology, with an implantation energy of 150 keV to 400 keV and an implantation ion dose of 10. 12 / cm 2 ~10 14 / cm 2 The injection depth is approximately 50nm to 250nm beyond the buffer layer, such as... Figure 11a , Figure 11b , Figure 11c As shown.

[0097] 10) Deposited gate dielectric layer: Al2O3 is deposited as the gate dielectric layer using ALD (Atom Layer Deposition) technology. The thickness of Al2O3 is 5–20 nm. Figure 12a , Figure 12b , Figure 12c As shown.

[0098] 11) Fabrication of source and drain electrodes: After the source-drain ohmic contact windowing process, Ti / Au metal was fabricated on the n++GaN ohmic contact layer as the source and drain electrodes using electron beam evaporation technology. The thickness of the Ti / Au metal was 50nm / 250nm. Figure 13a , Figure 13b , Figure 13c As shown.

[0099] 12) Fabrication of the T-type gate: A double-layer electron beam photoresist process and electron beam evaporation technology are used to deposit Ni / Au metal as a T-type gate in the gate region. The Ni / Au metal thickness is 250nm / 250nm. The gate includes a top gate and a side gate. The side gate is located on the sidewall of the Fin structure, and the top gate is located on top of the thick GaN capping layer. Figure 14a , Figure 14b , Figure 14c As shown.

[0100] Example 2

[0101] The fabrication method of a near-full-gate controlled multi-channel FinFET structure with a thick GaN capping layer in this embodiment is basically the same as that in Embodiment 1. The difference is that in this embodiment, the Fin structure is first defined with positive adhesive and then the gate region is defined with negative adhesive. The specific differences mainly include the following steps:

[0102] 1) Multi-channel AlGaN / GaN epitaxial structures with thick GaN capping layers are epitaxially grown on a substrate using MOCVD (Metal-organic Vapor Deposition) technology, such as... Figure 15a , Figure 15b , Figure 15cAs shown in the figure. The thickness of the GaN capping layer is 100 nm, the thickness of the AlGaN barrier layer is 10 nm, the Al content is 15%, the thickness of the GaN channel layer is 10 nm, the substrate material can be silicon, sapphire, silicon carbide, gallium nitride, aluminum nitride, etc., and the buffer layer material can be GaN, etc.

[0103] 2) A patterned AR-P-6200 (α-methyl styrene-co-α-chloroacrylate methylester) electron beam photoresist is formed on the top surface of the thick GaN capping layer as a mask layer for etching the Fin structure, such as... Figure 16a , Figure 16b , Figure 16c As shown.

[0104] 3) Etching of the thick GaN capping layer and multi-channel AlGaN / GaN heterojunction in the Fin structure region: Chlorine-based ICP etching technology was used, with AR-P-6200 electron beam photoresist as a mask, to etch the thick GaN capping layer and multi-channel AlGaN / GaN heterojunction in the Fin structure region. The etching rate was controlled between 1 and 20 nm / min, and etching was stopped at the bottom GaN channel layer. After etching, the photoresist was removed. Figure 17a , Figure 17b , Figure 17c As shown.

[0105] 4) A silicon oxide mask layer with a thickness of 200 nm is formed on the surface of the multi-channel AlGaN / GaN epitaxial structure, such as... Figure 18a , Figure 18b , Figure 18c As shown.

[0106] 5) Using AR-N-7520 electron beam photoresist, define the gate foot dimensions of the T-gate, i.e., gate length LG ≈ 50nm-800nm. For example... Figure 19a , Figure 19b , Figure 19c As shown.

[0107] 6) Etching of the silicon oxide mask layer in the source and drain ohmic regions: Fluorine-based ICP etching technology was used, with AR-N-7520 electron beam photoresist as the mask, to etch the silicon oxide mask layer in the source and drain ohmic regions. The etching rate was controlled at 1–20 nm / min. After etching, the 7520 electron beam photoresist was removed. Figure 20a , Figure 20b , Figure 20c As shown.

[0108] 7) Etching of the thick GaN capping layer and multi-channel AlGaN / GaN heterojunction in the source and drain ohmic regions: Using chlorine-based ICP etching technology with silicon oxide as a mask, the thick GaN capping layer and multi-channel AlGaN / GaN heterojunction in the source and drain ohmic regions are etched. The etching rate is controlled at 1–20 nm / min, stopping when the etching reaches the bottommost GaN channel layer. Figure 21a , Figure 21b , Figure 21c As shown.

[0109] 8) Secondary epitaxial n++ GaN ohmic contact layer: Using silicon oxide as a mask, an n++ GaN layer is epitaxially grown on the bottom GaN channel layer in the source and drain ohmic regions using MOCVD. The doping concentration and thickness ensure good ohmic contact with the channel electrons in the multi-channel AlGaN / GaN heterojunction. The silicon oxide mask layer is then removed. Figure 22a , Figure 22b , Figure 22c As shown.

[0110] After testing, please refer to Figure 23a , Figure 23b In conventional FinFETs, the conduction band of the two-dimensional electron gas channel is below the Fermi level. As the gate voltage increases, the electric field generated by the top gate perpendicular to the AlGaN / GaN interface intensifies. While this increases the number of electrons in the channel, it also causes these electrons to be closer to the AlGaN / GaN surface, leading to increased inter-electron scattering and consequently reducing transconductance and device current linearity. (See also: [link to relevant documentation]) Figure 24a , Figure 24b In the FinFET provided by the present invention, the charge carriers in the channel are mainly controlled by the side gate. As the gate voltage increases, the electrons in the two-dimensional electron gas channel extend from the center of the Fin structure to both ends, which increases the number of electrons in the two-dimensional electron gas channel. However, the electric field generated by the side gate is parallel to the AlGaN / GaN interface direction, so the electrons do not get closer and closer to the AlGaN / GaN surface as the gate voltage increases, thereby alleviating inter-electron scattering, suppressing the reduction of transconductance, and improving the current linearity of the device.

[0111] This invention proposes a novel near-full-gate controlled multi-channel FinFET structure with a thick GaN capping layer and its fabrication method. This technical solution employs a multi-channel GaN-based heterostructure with a low Al composition and a thin AlGaN barrier layer. Utilizing a thick GaN capping layer and secondary epitaxial growth ohmic technology, a near-full-gate controlled multi-channel FinFET with a thick GaN capping layer is fabricated. This enables enhancement-mode device designs with high current density and high current linearity, thus meeting the needs of mobile power amplifier (PA) applications. Compared to conventional GaN-based multi-channel FinFETs, this invention eliminates the access regions between the gate and source, and the thick GaN capping layer allows the entire Fin channel to be almost entirely controlled by the side gate. This effectively improves current linearity while increasing current density, thereby increasing output power density and gain. Regarding enhancement-mode design, because the GaN-based multi-channel heterostructure uses a low Al composition and a thin AlGaN barrier layer, enhancement-mode FinFETs can be fabricated without requiring extremely small Fin structure widths, thus significantly improving the reliability and stability of device fabrication.

[0112] This invention proposes a novel near-full-gate controlled multi-channel FinFET structure with a thick GaN capping layer and its fabrication method. Reducing the Al composition and the thickness of the AlGaN barrier layer decreases the two-dimensional electron gas concentration, while reducing the Fin structure width enhances the control of the side gate over the channel, facilitating enhancement-mode design. Increasing the thickness of the GaN capping layer weakens the control of the top gate over the channel, thus making the channel primarily controlled by the side gate. Compared to conventional FinFETs, FinFETs with a thick capping layer help mitigate inter-electron scattering within the channel, suppress transconductance degradation, and improve device current linearity as the gate voltage increases.

[0113] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A near-fully-gate controlled FinFET structure, characterized in that, include: An epitaxial structure, comprising a heterostructure and a capping layer, wherein the epitaxial structure has a protruding fin-like portion, a carrier channel within the heterostructure is located within the fin-like portion, and the capping layer is located at the top layer of the fin-like portion; An ohmic contact layer is disposed on both sides of the fin along a first direction, and the ohmic contact layer is electrically connected to the carrier channel. The device comprises a source, a drain, and a gate. The source and the drain are disposed on and electrically connected to the ohmic contact layer. The gate is disposed between the source and the drain along a first direction. The gate includes a top gate and a side gate. The side gates are distributed on both sides of the fin along a second direction. The top gate is disposed on the top of the capping layer and is integrally connected to the side gates. The capping layer ensures that the unit capacitance between the top gate and the carrier channel is less than the unit capacitance between the side gate and the carrier channel. The top gate has less control over the current of the carrier channel than the side gate has. The first direction intersects the second direction.

2. The near-fully-gate controlled FinFET structure according to claim 1, characterized in that: The heterostructure includes at least one channel layer and at least one barrier layer stacked together, wherein the carrier channel is formed at the interface between the channel layer and the barrier layer, and the capping layer is located on the topmost channel layer or barrier layer. Preferably, the heterostructure includes multiple channel layers and multiple barrier layers stacked together, and the heterostructure has multiple carrier channels.

3. The near-fully-gate controlled FinFET structure according to claim 2, characterized in that: The capping layer is formed of a material with a relative permittivity between 1 and 50, and / or the thickness of the capping layer does not exceed 500 nm; Preferably, the thickness of the capping layer is 100nm-500nm; Preferably, the material of the capping layer includes III-V group compounds, metal oxides, non-metal oxides, or non-metal nitrides; Preferably, the material of the capping layer includes any one of gallium nitride, aluminum nitride, aluminum gallium nitride, aluminum oxide, hafnium oxide, silicon oxide, and silicon nitride; And / or, the thickness of the barrier layer is no more than 200 nm, and the Al content in the barrier layer is no more than 60%; Preferably, the material of the barrier layer includes at least one of AlGaN, AlN, AlInN, and AlInGaN; Preferably, the channel layer is made of GaN.

4. The near-fully-gate controlled FinFET structure according to claim 1, characterized in that: The gate is generally a T-shaped gate, a strip gate, or a screw gate.

5. The near-fully-gate controlled FinFET structure according to claim 1, characterized in that: In the first direction, the width of the fin does not exceed 1000 nm.

6. The near-fully-gate controlled FinFET structure according to claim 1, characterized in that: The ohmic contact layer includes an n-type heavily doped layer, the top surface of which is flush with the top surface of the capping layer; Preferably, the n-type heavily doped layer includes an n++GaN layer.

7. The near-full-gate controlled FinFET structure according to claim 1, characterized in that, Also includes: A gate dielectric layer is continuously disposed between the top gate, the side gate, the epitaxial structure, and the ohmic contact layer; Preferably, the material of the gate dielectric layer includes Al2O3, SiO2, HfO2, HfO2, AlON, AlN, and SiN. x At least one of them; And / or, the near-full-gate FinFET structure is an enhancement-mode device structure or a depletion-mode device structure.

8. An electronic device, characterized in that, Includes the near-full-gate FinFET structure according to any one of claims 1-7; Preferably, the electronic device includes a power amplifier for use in 5G communication bands, millimeter wave bands, or terahertz bands.

9. The method for fabricating a near-fully-gate controlled FinFET structure as described in any one of claims 1-7, characterized in that, include: An epitaxial structure is provided, the epitaxial structure including a heterostructure and a capping layer disposed on the heterostructure, wherein a carrier channel is formed within the heterostructure; Remove the capping layer and part of the heterostructure located in the source and drain ohmic regions, and remove part of the capping layer and part of the heterostructure located in the gate region, thereby forming a raised fin in the gate region. The carrier channel is retained only in the fin, and the remaining capping layer is located on the top layer of the fin. The source and drain ohmic regions are located on both sides of the gate region along the first direction. An ohmic contact layer is formed in the source and drain ohmic regions of the epitaxial structure, and the ohmic contact layer is electrically connected to the carrier channel in the fin. A gate is formed in the gate region of the epitaxial structure. The gate includes a top gate and a side gate. The side gate is located on both sides of the fin along a second direction. The top gate is disposed on top of the capping layer and is integrally connected with the side gate. The capping layer at least makes the unit capacitance between the top gate and the carrier channel smaller than the unit capacitance between the side gate and the carrier channel. The control force of the top gate on the current of the carrier channel is smaller than the control force of the side gate on the current of the carrier channel. The first direction intersects the second direction.

10. The method for fabricating a near-fully-gate controlled FinFET structure according to claim 9, characterized in that, Also includes: First, a gate dielectric layer is formed on the surface of the epitaxial structure and the ohmic contact layer, and then the gate is formed on the gate dielectric layer.

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