Display panel and electronic device including the same

Abstract

A display panel and an electronic device including the same are provided, in which the display panel includes: first and second driving voltage lines alternately arranged in a first direction in a display area and extending in a second direction crossing the first direction; a first color pixel circuit and a third color pixel circuit alternately arranged along the second driving voltage line; and a second color pixel circuit arranged along the first driving voltage line, in which the first color pixel circuit and the second color pixel circuit are electrically connected to the first driving voltage line, and the third color pixel circuit is electrically connected to the second driving voltage line.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0144315, filed on October 21, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to a display panel and an electronic device including the display panel, and more specifically, to a display panel capable of displaying high-quality images and an electronic device including the display panel. Background Technology

[0004] Display panels are used in a variety of electronic devices. In order to display higher quality images at higher resolutions, pixel sizes have been reduced, and therefore, various electronic components need to be placed in small areas. Summary of the Invention

[0005] In display panels and electronic devices including display panels according to related technologies, as the size of pixels decreases, it becomes impossible to adequately guarantee the area of ​​pixels of a specific color.

[0006] One or more embodiments include a display panel capable of displaying high-quality images and an electronic device including the display panel. However, such technical objectives are merely examples, and this disclosure is not limited thereto.

[0007] Other aspects will be set forth in part in the description which follows and will be apparent in part from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0008] According to one or more embodiments, a display panel may include: a first driving voltage line and a second driving voltage line, which are alternately arranged in a first direction in a display area and extend in a second direction intersecting the first direction; a first color pixel circuit and a third color pixel circuit, which are alternately arranged along the second driving voltage line; and a second color pixel circuit, which is arranged along the first driving voltage line, wherein the first color pixel circuit and the second color pixel circuit are electrically connected to the first driving voltage line, and the third color pixel circuit is electrically connected to the second driving voltage line.

[0009] The potential of the second driving voltage supplied through the second driving voltage line may be different from the potential of the first driving voltage supplied through the first driving voltage line.

[0010] The potential of the second driving voltage supplied through the second driving voltage line can be greater than the potential of the first driving voltage supplied through the first driving voltage line.

[0011] Each of the first color pixel circuits in the first color pixel circuit can be electrically connected to a corresponding first driving voltage line in the first driving voltage line through an adjacent second color pixel circuit in the second color pixel circuits arranged in the same row.

[0012] A group of pixel circuits arranged in a first direction in the order of a third color pixel circuit, a second color pixel circuit, a first color pixel circuit, and a second color pixel circuit can be arranged repeatedly in the first direction, wherein the first color pixel circuit in the group can be electrically connected to a corresponding first driving voltage line in the first driving voltage line through a second color pixel circuit that is set away from the third color pixel circuit relative to the first color pixel circuit in the group.

[0013] The operation control transistors of the first color pixel circuit and the second color pixel circuit can be electrically connected to the first driving voltage line, and the operation control transistor of the third color pixel circuit can be electrically connected to the second driving voltage line.

[0014] The operation control transistor of each of the first color pixel circuits can be electrically connected to the operation control transistor of an adjacent second color pixel circuit in the same row, and correspondingly, electrically connected to a corresponding drive voltage line in the first drive voltage line.

[0015] A group of pixel circuits arranged in a first direction in the order of a third color pixel circuit, a second color pixel circuit, a first color pixel circuit, and a second color pixel circuit can be arranged repeatedly in the first direction. The operation control transistor of the first color pixel circuit in the group can be electrically connected to the operation control transistor of the second color pixel circuit, which is set to be away from the third color pixel circuit relative to the first color pixel circuit in the group, and correspondingly, electrically connected to a corresponding first drive voltage line in the first drive voltage line.

[0016] The driving transistors of the first color pixel circuit and the second color pixel circuit can be electrically connected to the first driving voltage line, and the driving transistor of the third color pixel circuit can be electrically connected to the second driving voltage line.

[0017] The driving transistor of each first color pixel circuit in the first color pixel circuit can be electrically connected to the driving transistor of an adjacent second color pixel circuit in the second color pixel circuit arranged in the same row, and correspondingly, electrically connected to a corresponding first driving voltage line in the first driving voltage line.

[0018] A group of pixel circuits arranged in a first direction in the order of a third color pixel circuit, a second color pixel circuit, a first color pixel circuit, and a second color pixel circuit can be arranged repeatedly in the first direction. The driving transistor of the first color pixel circuit in the group can be electrically connected to the driving transistor of the second color pixel circuit which is set away from the third color pixel circuit relative to the first color pixel circuit in the group, and correspondingly, electrically connected to a corresponding first driving voltage line in the first driving voltage line.

[0019] The display panel may further include: first connecting lines and second connecting lines, which are alternately arranged in a second direction and extend in a first direction, wherein each of the first connecting lines can be electrically connected to a first driving voltage line and each of the second connecting lines can be electrically connected to a second driving voltage line.

[0020] The first connecting line and the second connecting line can be set on the first driving voltage line and the second driving voltage line.

[0021] Each of the first connecting lines may have a group of repeating arrangements in a first direction, wherein each of the groups includes an extension portion arranged in the first direction in the order of a first extension portion corresponding to a first color pixel electrode, a second extension portion corresponding to a second color pixel electrode, a third extension portion corresponding to a third color pixel electrode, and a second extension portion corresponding to a second color pixel electrode; and each of the second connecting lines may have a group of repeating arrangements in the first direction, wherein each of the groups includes an extension portion arranged in the first direction in the order of a third extension portion corresponding to a third color pixel electrode, a second extension portion corresponding to a second color pixel electrode, a first extension portion corresponding to a first color pixel electrode, and a second extension portion corresponding to a second color pixel electrode.

[0022] The first connecting line and the second connecting line can be located below the first driving voltage line and the second driving voltage line.

[0023] Each third color pixel circuit in the third color pixel circuit may include: an initialization transistor having one end electrically connected to a pixel electrode; and a connection electrode that electrically connects the other end of the initialization transistor to an initialization voltage line and is disposed below the first connection line and the second connection line.

[0024] Each of the first color pixel circuits in the first color pixel circuit can be electrically connected to a corresponding first connection line in the first connection line.

[0025] Each of the first color pixel circuits may include an emission control transistor and a connection electrode that electrically connects the emission control transistor to a corresponding first connection line in the first connection line, and the connection electrode, the first driving voltage line and the second driving voltage line are disposed on the same layer.

[0026] The display panel may further include: a first color pixel electrode electrically connected to each of the first color pixel circuits; a second color pixel electrode electrically connected to each of the second color pixel circuits; a third color pixel electrode electrically connected to each of the third color pixel circuits; and a common electrode disposed on the first color pixel electrode, the second color pixel electrode, and the third color pixel electrode, wherein the common electrode is integrally formed into a single unit, wherein a first color emitting layer may be disposed between the first color pixel electrode and the common electrode, a second color emitting layer may be disposed between the second color pixel electrode and the common electrode, and a plurality of third color emitting layers and a charge generation layer disposed between the plurality of third color emitting layers may be disposed between the third color pixel electrode and the common electrode.

[0027] According to one or more embodiments, an electronic device may include: a display panel; and a lower cover forming the appearance of the electronic device and having an opening exposing a portion of the display panel, wherein the display panel includes: a first driving voltage line and a second driving voltage line, alternately arranged in a display area in a first direction and extending in a second direction intersecting the first direction; a first color pixel circuit and a third color pixel circuit, alternately arranged along the second driving voltage line; and a second color pixel circuit, arranged along the first driving voltage line, wherein the first color pixel circuit and the second color pixel circuit are electrically connected to the first driving voltage line, and the third color pixel circuit is electrically connected to the second driving voltage line.

[0028] The potential of the second driving voltage supplied through the second driving voltage line may be different from the potential of the first driving voltage supplied through the first driving voltage line.

[0029] These and / or other aspects will become apparent and more readily understood through the following description of embodiments, the accompanying drawings, and the claims. Attached Figure Description

[0030] The above and other aspects, features, and advantages of certain embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0031] Figure 1 This is a schematic perspective view of an electronic device according to an embodiment;

[0032] Figure 2 yes Figure 1 An exploded schematic perspective view of an electronic device;

[0033] Figure 3 yes Figure 1 A schematic diagram of an electronic device;

[0034] Figure 4 This is a schematic plan view of the display panel according to an embodiment;

[0035] Figure 5 yes Figure 4 A schematic side view of the display panel;

[0036] Figure 6 yes Figure 4 A schematic floor plan of the display panel;

[0037] Figure 7 yes Figure 6 An enlarged schematic diagram of area A of the display panel;

[0038] Figure 8 This is an enlarged schematic diagram of a portion of the display panel according to an embodiment;

[0039] Figure 9 It is a schematic arrangement diagram including the emission areas of a plurality of pixels in a display panel according to an embodiment;

[0040] Figure 10 yes Figure 9 A schematic diagram of the structure of the light-emitting elements in the display panel;

[0041] Figure 11 yes Figure 9 A schematic diagram of the structure of another light-emitting element of the display panel;

[0042] Figure 12 It can be electrically connected Figure 10 A schematic diagram of the equivalent circuit of the light-emitting element;

[0043] Figure 13 It can be electrically connected Figure 11 A schematic diagram of the equivalent circuit of the light-emitting element;

[0044] Figure 14 It is shown that it includes Figure 9 A schematic diagram showing the arrangement of transistors and capacitors in the pixels of a display panel;

[0045] Figures 15 to 22 yes Figure 14 The diagram shows a schematic arrangement of components such as transistors and capacitors in each layer of the display panel.

[0046] Figure 23 yes Figure 9A schematic diagram of the pixel electrode arrangement of the display panel;

[0047] Figure 24 It is along Figure 14 A schematic cross-sectional view of the display panel taken by lines A-A' and B-B';

[0048] Figures 25 to 29 This is a schematic arrangement of elements such as transistors and capacitors in each layer of the display panel according to an embodiment;

[0049] Figure 30 This is a schematic arrangement diagram of the second source / drain layer of the display panel according to an embodiment;

[0050] Figure 31 and Figure 32 This is a schematic diagram of an equivalent circuit that can be electrically connected to the light-emitting element of the display panel according to the embodiment;

[0051] Figure 33 It is shown that it includes those with Figure 31 and Figure 32 A schematic diagram showing the arrangement of transistors, capacitors, etc., in the pixels of a display panel of a pixel circuit.

[0052] Figures 34 to 37 yes Figure 33 The diagram shows a schematic arrangement of components such as transistors and capacitors in each layer of the display panel.

[0053] Figure 38 It has Figure 33 A schematic diagram of the pixel electrode arrangement of the display panel;

[0054] Figure 39 and Figure 40 This is a schematic diagram of an equivalent circuit that can be electrically connected to the light-emitting element of the display panel according to the embodiment; and

[0055] Figure 41 and Figure 42 This is a schematic diagram of an equivalent circuit that can be electrically connected to the light-emitting element of the display panel according to the embodiment. Detailed Implementation

[0056] In the following description, numerous specific details are set forth for illustrative purposes in order to provide a thorough understanding of various embodiments or implementations of this disclosure. As used herein, “embodiment” and “implementation” are interchangeable terms used as non-limiting examples of the devices or methods disclosed herein. However, it will be apparent, however, that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. These various embodiments are not necessarily exclusive, nor are they intended to limit this disclosure. For example, a particular shape, construction, and characteristic of an embodiment may be used or implemented in another embodiment.

[0057] Unless otherwise stated, the illustrated embodiments should be understood as providing features of this disclosure. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, areas and / or aspects of various embodiments (hereinafter individually or collectively referred to as “elements”) may be combined, separated, interchanged and / or rearranged in other ways without departing from the scope of this disclosure.

[0058] The use of crosshairs and / or shading in accompanying drawings is typically provided to clarify boundaries between adjacent elements. Therefore, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for a particular material, material properties, size, scale, commonality between illustrated elements, and / or any other characteristic, attribute, property, etc. Furthermore, in the drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. A particular process sequence may be performed differently than the described sequence when embodiments can be implemented differently. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Moreover, the same reference numerals and / or reference characters denote the same elements.

[0059] When an element or layer is referred to as being “on,” “connected to,” or “linked to” another element or layer, it can be directly on, directly connected to, or directly linked to the other element or layer, or an intermediary element or layer may be present. However, when an element or layer is referred to as being “directly” on, directly connected to, or directly linked to the other element or layer, an intermediary element or layer is not present. Therefore, the term “connection” can refer to a physical, electrical, and / or fluid connection with or without an intermediary element. For the purposes of this disclosure, “at least one of A and B” can be interpreted as only A, only B, or any combination of A and B. Furthermore, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0060] Although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0061] Spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side” (e.g., in “sidewall”) may be used herein for descriptive purposes and thus to describe the relationship of one element to another as illustrated in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are intended to cover different orientations of the apparatus in use, operation, and / or manufacture. For example, if the apparatus in the drawings is flipped, an element described as being “below” or “under” other elements or features will subsequently be oriented “above” other elements or features. Thus, the term “below” can encompass both above and below orientations. Furthermore, the apparatus may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatial relative descriptive terms used herein should be interpreted accordingly.

[0062] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the / said” are intended to also include the plural forms. Furthermore, when used in this specification, the terms “comprising,” “including,” and / or variations thereof specify the presence of stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than terms of degree, and therefore to explain the inherent deviations of measured, calculated, and / or provided values ​​that would be recognized by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±20%, ±10%, or ±5% of the stated value.

[0063] Various embodiments are described herein with reference to schematic cross-sectional and / or exploded views that are schematic illustrations of embodiments and / or intermediate structures. Therefore, variations in the shape of the illustrations are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments disclosed herein are not necessarily to be construed as limited to a specific illustrated shape of the area, but are to include deviations in shape caused, for example, by manufacturing processes. In this way, the areas illustrated in the figures may be schematic in nature, and the shapes of these areas may not reflect the actual shapes of the areas of the device, and therefore are not intended to be limiting.

[0064] In accordance with the conventions of the art, some embodiments are described and illustrated in the accompanying drawings based on functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits, such as logic circuits, discrete components, microprocessors, hardwired circuits, storage elements, and wiring connections, which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. It is also contemplated that each block, unit, and / or module may be implemented by dedicated hardware, or may be implemented as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions. Furthermore, without departing from the scope of this disclosure, each block, unit, and / or module of some embodiments may be physically separated into two or more interactive and discrete blocks, units, and / or modules. Furthermore, without departing from the scope of this disclosure, blocks, units, and / or modules of some embodiments may be physically combined into more complex blocks, units, and / or modules.

[0065] Figure 1 This is a schematic perspective view of the electronic device 1 according to an embodiment. Figure 2 yes Figure 1 An exploded schematic perspective view of electronic device 1, and Figure 3 yes Figure 1 A schematic diagram of electronic device 1.

[0066] refer to Figure 1 and Figure 2 Electronic device 1 may include a device for displaying moving or still images, and may be a television, laptop computer, monitor, billboard, Internet of Things (IoT) device, and portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, or ultra-mobile personal computers (UMPCs). Electronic device 1 may be a wearable device such as a smartwatch, watch phone, glasses display, or head-mounted display (HMD). Electronic device 1 may be a vehicle's dashboard, a vehicle's central dashboard or a central information display (CID) arranged on the dashboard, an interior rearview mirror display replacing the vehicle's side mirrors, or a display arranged behind the front seats as entertainment for the rear seats.

[0067] For ease of description, Figure 1 and Figure 2 The electronic device 1 shown in the illustration can be a smartphone. The electronic device 1 may include a cover window 70, a display panel 10, a data driver 20, a display circuit board 30, a component 40, a bracket 60, a main circuit board 50, a battery 80, and / or a bottom cover 90.

[0068] Electronic device 1 may include computing systems that provide image display capabilities, such as smartwatches, mobile phones, smartphones, portable computers, tablet PCs, watch phones, car displays, smart glasses, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs). Electronic device 1 may include at least one of head-mounted display (HMD) devices, virtual reality (VR) devices, mixed reality (MR) devices, and augmented reality (AR) devices.

[0069] In the plan view, "left", "right", "up" and "down" indicate the direction when viewing the display panel 10 in a direction perpendicular to the display panel 10 (or in the plan view). For example, "left" represents the -x direction, "right" represents the +x direction, "up" represents the +y direction, and "down" represents the -y direction.

[0070] Electronic device 1 can have a roughly rectangular shape in a plan view. For example, as shown... Figure 1 As shown, electronic device 1 may have a generally rectangular shape, having a shorter side in the x-axis direction and a longer side in the y-axis direction in the xy-plane. For example, the corner where the shorter side in the x-axis direction intersects the longer side in the y-axis direction may form a right angle or a circular shape with a predetermined curvature. In the plan view, the shape of electronic device 1 is not limited to a rectangle and may include other polygonal, elliptical, or irregular shapes.

[0071] The cover window 70 can be disposed above the display panel 10 to cover the upper surface of the display panel 10. The cover window 70 can protect the upper surface of the display panel 10.

[0072] The cover window 70 may include a transparent cover unit DA 70 corresponding to the display panel 10 and a light-shielding cover unit NDA 70 surrounding the transparent cover unit DA 70. The light-shielding cover unit NDA 70 may include an opaque material (e.g., a colored opaque material) that blocks light. The light-shielding cover unit NDA 70 may include a pattern that is visible to the user when no image is displayed.

[0073] The display panel 10 may be disposed below the cover window 70. The display panel 10 may overlap with the transparent cover unit DA 70 of the cover window 70. The display panel 10 may include a display area DA. The display area DA, which is the area for displaying images, may include the area through which light emitted from a component 40 disposed below the display panel 10 passes (hereinafter referred to as the "component area"). The component 40 may include a camera and sensors using visible light, infrared light, and sound, etc.

[0074] Display panel 10 can be a light-emitting display panel including light-emitting diodes (LEDs). The LEDs can be organic light-emitting diodes (OLEDs) including an organic light-emitting layer or inorganic light-emitting diodes including inorganic materials. Inorganic LEDs can include PN junction diodes containing materials based on inorganic semiconductors. When a forward voltage is applied to the PN junction diode, holes and electrons are injected, and the energy generated by the recombination of holes and electrons is converted into light energy, thus emitting light of a predetermined color. Inorganic LEDs can have widths ranging from a few micrometers to several hundred micrometers. Inorganic LEDs can be referred to as miniature light-emitting diodes (LEDs).

[0075] The display panel 10 can be a rigid display panel that is rigid and therefore not easily bent, or a flexible display panel that is flexible and therefore easily bent, folded, or rolled up. For example, the display panel 10 can include a foldable display panel that can be folded and unfolded, a curved display panel that has a curved display surface, a curved display panel in which areas other than the display surface are bent, a rollable display panel that can be rolled up and unfolded, and a stretchable display panel.

[0076] The display panel 10 can be implemented as a transparent display panel, such that objects or backgrounds disposed below the display panel 10 can be viewed from the upper surface of the display panel 10. In another embodiment, the display panel 10 can be a reflective display panel that can reflect objects or backgrounds above the upper surface of the display panel 10.

[0077] The data driver 20 may be mounted on the display panel 10 as an integrated circuit (IC). However, this disclosure is not limited thereto. For example, the data driver 20 may be mounted on the display circuit board 30.

[0078] The display circuit board 30 can be attached to one side of the display panel 10. The display circuit board 30 can be a flexible printed circuit board (FPCB), a rigid printed circuit board (PCB) that cannot be easily bent, or a composite printed circuit board including both FPCB and rigid PCB. A touch sensor driver can be mounted on the display circuit board 30. The touch sensor driver can include an IC. The touch sensor driver can be electrically connected via the display circuit board 30 to the touch electrodes of the touchscreen layer of the display panel 10.

[0079] The touchscreen layer of the display panel 10 can sense user touch input using at least one of various touch methods, such as resistive layer methods and capacitive methods. For example, when the touchscreen layer of the display panel 10 senses user touch input using a capacitive method, the touch sensor driver can determine whether the user has touched the touchscreen layer by applying a drive signal to the drive electrode in the touch electrode and sensing the voltage charged in the mutual capacitance between the drive electrode and the sensing electrode through the sensing electrode in the touch electrode.

[0080] User touches can include contact touches and proximity touches. A contact touch can mean that an object, such as a user's finger or a pen, is in direct contact with the overlay window 70 disposed on the touchscreen layer. A proximity touch, like a hover, means that an object, such as a user's finger or a pen, is positioned above or near the overlay window 70 and then moves away from it. The touch sensor driver can transmit sensor data to the main processor 510 based on the sensed voltage, and the main processor 510 can calculate the touch coordinates at which the touch input occurred by analyzing the sensor data.

[0081] The controller can be mounted on the display circuit board 30, wherein the controller can supply driving voltage for driving the pixels, gate drivers and / or data drivers 20 of the display panel 10.

[0082] A bracket 60 for supporting the display panel 10 may be disposed below the display panel 10. The bracket 60 may include plastic, metal, or both. The bracket 60 may have a first camera hole CMH1 into which a camera device 531 is inserted, a battery hole BH into which a battery 80 is disposed, a cable hole CAH through which cables connected to the display circuit board 30 pass, and a component hole CPH corresponding to component 40. The component hole CPH may overlap with component 40 of the main circuit board 50 in a plan view. For reference, the display area DA of the display panel 10 may overlap with component 40 of the main circuit board 50 in a plan view. The bracket 60 may not have the component hole CPH when necessary.

[0083] Component 40 of electronic device 1 may include a first component 41, a second component 42, a third component 43, and a fourth component 44 overlapping with display panel 10. Each of the first component 41, the second component 42, the third component 43, and the fourth component 44 may include at least one of a proximity sensor, an illumination sensor, an iris sensor, a facial recognition sensor, and a camera (or image sensor). The proximity sensor, using infrared light, can detect objects positioned near the upper surface of electronic device 1, and the illumination sensor can detect the brightness of light incident on the upper surface of electronic device 1. The iris sensor can capture the iris of a person positioned above the upper surface of electronic device 1, and the camera can receive image data of objects positioned on the upper surface of electronic device 1. Component 40 is not limited to proximity sensors, illumination sensors, iris sensors, facial recognition sensors, and cameras, and may include other sensors.

[0084] The main circuit board 50 and the battery 80 can be disposed below the bracket 60. The main circuit board 50 can be a printed circuit board or a flexible printed circuit board.

[0085] The main circuit board 50 may include a main processor 510, a camera device 531, a main connector 50a, and a component 40. The main processor 510 may include an integrated circuit. When needed, the electronic device 1 may include not only the camera device 531 disposed on the upper surface of the main circuit board 50, but also a camera device disposed on the lower surface of the main circuit board 50. Each of the main processor 510 and the main connector 50a may be disposed on one of the upper and lower surfaces of the main circuit board 50. The main circuit board 50 may be electrically connected to the display circuit board 30 via the main connector 50a, etc.

[0086] The main processor 510 can control all functions of the electronic device 1. For example, the main processor 510 can output digital video data to the data driver 20 via the display circuit board 30, causing the display panel 10 to display an image. The main processor 510 can receive sensed data from the touch sensor driver. The main processor 510 can determine whether the user is directly touching the touchscreen based on the sensed data, and perform operations corresponding to the user's direct touch or proximity touch. The main processor 510 can be an application processor including an integrated circuit, a central processing unit, or a system-on-a-chip.

[0087] Camera device 531 processes image frames, such as still images or moving images, acquired by an image sensor in camera mode, and outputs the image frames to main processor 510. Camera device 531 may include at least one of a camera sensor (e.g., a charge-coupled device (CCD) and complementary metal-oxide-semiconductor (CMOS), a light sensor (or image sensor), and a laser sensor.

[0088] A cable passing through the cable hole CAH of the bracket 60 can be connected to the main connector 50a, and the main circuit board 50 can be electrically connected to the display circuit board 30 through the cable.

[0089] Electronic device 1 can be made of, for example Figure 3 The block diagram shown illustrates this. Besides the main processor 510, the electronic device 1 can be represented as including... Figure 3 The wireless communication unit 520, input unit 530, sensor unit 540, output unit 550, interface unit 560, memory 570 and / or power supply unit 580 are shown.

[0090] The wireless communication unit 520 may include at least one of the following: a broadcast receiving module 521, a mobile communication module 522, a wireless internet module 523, a short-range communication module 524, and a location information module 525.

[0091] The broadcast receiving module 521 can receive broadcast signals and / or broadcast-related information from an external broadcast management server via a broadcast channel. The broadcast channel may include a satellite channel or a ground wave channel.

[0092] The mobile communication module 522 can transmit / receive radio signals to / from at least one of a base station, an external terminal, and a server on a mobile communication network established according to mobile communication technical standards or communication schemes (e.g., Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), Code Division Multiple Access 2000 (CDMA2000), Enhanced Voice Data Optimized or Enhanced Voice Data Only (EV-DO), Wideband CDMA (WCDMA), High-Speed ​​Downlink Packet Access (HSDPA), High-Speed ​​Uplink Packet Access (HSUPA), Long Term Evolution (LTE), and LTE-A Advanced, etc.). The radio signals may include voice call signals, image communication call signals, or various types of data corresponding to text / multimedia message transmission / reception.

[0093] Wireless Internet module 523 represents a module for wireless Internet access. Wireless Internet module 523 can transmit / receive wireless signals on a communication network according to wireless Internet technologies. Examples of wireless Internet technologies may include Wireless Local Area Network (WLAN), Wi-Fi, Wi-Fi Direct, and / or Digital Living Network Alliance (DLNA).

[0094] The short-range communication module 524 is used for short-range communication and can be used via Bluetooth. ® The short-range communication module 524 supports at least one of the following technologies: Radio Frequency Identification (RFID), Infrared Data Association IrDA (IrDA), Ultra Wideband (UWB), ZigBee, Near Field Communication (NFC), Wi-Fi, Wi-Fi Direct, and Wireless Universal Serial Bus (Wireless USB). The short-range communication module 524 can support wireless communication between electronic device 1 and a wireless communication system, between electronic device 1 and another electronic device, or between electronic device 1 and a network in which another electronic device (or an external server) is located via a short-range wireless local area network (WLAN). The short-range WLAN can be a wireless personal area network (WLAN). The other electronic device can be a wearable device that can exchange data with or operate alongside electronic device 1.

[0095] The location information module 525, which is used to obtain the location of the electronic device 1, may include a Global Positioning System (GPS) module or a Wi-Fi module.

[0096] The input unit 530 may include an image input unit, such as a camera device 531, for inputting image signals; an audio input unit, such as a microphone 532, for inputting audio signals; and an input unit 533 for receiving information from a user. The camera device 531 processes image frames, such as still images or moving images, acquired by the image sensor in image communication mode or capture mode. The processed image frames may be displayed on the display panel 10 or stored in the memory 570. The microphone 532 processes external audio signals into electronic voice data. The processed voice data may be utilized in various ways depending on the function being performed (or the application being executed) in the electronic device 1.

[0097] The main processor 510 can control the operation of the electronic device 1 to correspond to the information input through the input unit 533. The input unit 533 may include mechanical input devices such as buttons, dome switches, micro-wheels, and micro-switches, or touch input devices disposed on the lower or side surface of the electronic device 1. The touch input device may include the touch screen layer of the display panel 10.

[0098] Sensor unit 540 may include at least one sensor that senses at least one of the following: information inside electronic device 1, information about the surrounding environment of electronic device 1, and user information, and generates a corresponding sensing signal. Main processor 510 may control the driving or operation of electronic device 1 based on the sensing signal, or perform data processing, functions, or operations related to applications installed in electronic device 1. Sensor unit 540 may be a proximity sensor, illumination sensor, or facial recognition sensor as described above with respect to component 40. Sensor unit 540 may include an accelerometer, magnetic sensor, gravity sensor, gyroscope sensor, motion sensor, RGB sensor, infrared (IR) sensor, finger scanning sensor, ultrasonic sensor, optical sensor, and / or battery level sensor. Sensor unit 540 may include an environmental sensor or a chemical sensor. Environmental sensors may include, for example, a barometer, hygrometer, thermometer, radiation detection sensor, thermal detection sensor, and / or gas detection sensor. Chemical sensors may include, for example, an electronic nose, health sensor, and / or biometric sensor.

[0099] The output unit 550 is used to generate outputs related to vision, hearing or touch, and may include at least one of the display panel 10, sound output unit 551, tactile module 552 and light output unit 553.

[0100] Display panel 10 displays (outputs) information processed by electronic device 1. For example, display panel 10 may display execution screen information of an application driven by electronic device 1, user interface (UI), or graphical user interface (GUI) information corresponding to the execution screen information. Display panel 10 may include a display layer and a touch screen layer, wherein the display layer displays images and the touch screen layer senses user touch input. Accordingly, display panel 10 may act as one of the input units 533 providing an input interface between electronic device 1 and the user, and simultaneously act as one of the output units 550 providing an output interface between electronic device 1 and the user.

[0101] The sound output unit 551 can output sound data received by the wireless communication unit 520 or stored in the memory 570 in call receiving mode, communication mode, recording mode, voice recognition mode, and broadcast receiving mode, etc. The sound output unit 551 can output sound signals related to the functions performed by the electronic device 1 (e.g., call signal receiving tone and message receiving tone, etc.). The sound output unit 551 may include a receiver and a speaker. At least one of the receiver and speaker may be a sound generator attached to the display panel 10 and vibrating the display panel 10 to output sound. The sound generator may be a piezoelectric element or piezoelectric actuator that contacts and expands according to an electrical signal, or an exciter that generates magnetic force to vibrate the display panel 10 by using a voice coil.

[0102] The haptic module 552 generates various haptic effects that can be felt by the user. The haptic module 552 can provide vibrations as haptic effects to the user. The haptic module 552 can not only transmit haptic effects through direct contact, but also realize haptic effects, allowing the user to perceive haptic effects through the muscles in their fingers or arms.

[0103] The light output unit 553 outputs a signal to notify of an event by using light from a light source. Examples of events generated in the electronic device 1 may include message reception, call signal reception, missed call, alarm, calendar notification, email reception, and / or information reception via an application. The signal output by the light output unit 553 is implemented when the electronic device 1 emits monochromatic or multicolor light to its front or rear surface. The signal output may end when the electronic device 1 detects that the user has acknowledged the event.

[0104] Interface unit 560 serves as a path for connecting to various external devices of electronic device 1. Interface unit 560 may include at least one of a wired / wireless headphone port, an external charger port, a wired / wireless data port, a memory card section, a port for connecting a device with an identification module, an audio input / output (I / O) port, a video I / O port, and a headphone port. When an external device is connected to interface unit 560, electronic device 1 can perform appropriate control related to the connected external device.

[0105] Memory 570 stores data supporting various functions of electronic device 1. Memory 570 may store multiple applications driven in electronic device 1, data and / or commands for the operation of electronic device 1. At least some of the multiple applications can be downloaded from an external server via wireless communication. Memory 570 may store applications for the operation of main processor 510 and temporarily store data input / output (e.g., data such as phone books, messages, still images and / or moving images). Memory 570 may store tactile data of various vibration modes provided to tactile module 552 and audio data regarding various sounds provided to sound output unit 551.

[0106] The memory 570 may include at least one type of storage medium selected from flash memory, hard disk, solid-state drive (SSD), silicon disk drive (SDD), multimedia card micro, card memory (e.g., secure digital (SD) or extreme digital (XD) memory), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic storage, magnetic disk, and optical disk.

[0107] The power supply unit 580, under the control of the main processor 510, receives external and / or internal power and supplies power to various components included in the electronic device 1. The power supply unit 580 may include a battery 80. The power supply unit 580 may include a connection port. The connection port may be an example of an interface unit 560 to which an external charger is electrically connected, wherein the external charger is powered to charge the battery 80. In another embodiment, the power supply unit 580 may wirelessly charge the battery 80. Figure 2 As shown, the battery 80 can be configured not to overlap with the main circuit board 50 in a third direction (e.g., the z-axis direction). The battery 80 can overlap with the battery hole BH of the bracket 60.

[0108] like Figure 2As shown, the lower cover 90 can form the exterior of the electronic device 1 and may have an opening that exposes a portion of the display panel 10. The lower cover 90 can be fastened to the display panel 10 such that its surface corresponding to the display panel 10 is exposed. The lower cover 90 can be positioned on the opposite side of the cover window 70, with the display panel 10 located between the lower cover 90 and the cover window 70. The lower cover 90 can be positioned below the main circuit board 50 and the battery 80. The lower cover 90 can be fastened and secured to the bracket 60. The lower cover 90 can form the lower exterior of the electronic device 1. The lower cover 90 may comprise plastic, metal, or both plastic and metal.

[0109] A second camera hole CMH2, which exposes the lower surface of the camera device 531, can be formed in the lower cover 90. The positions of the camera device 531 and the corresponding first camera hole CMH1 and second camera hole CMH2 are not limited to... Figure 1 and Figure 2 The embodiments shown are not applicable and can be modified in various ways.

[0110] Figure 4 This is a schematic plan view of the display panel 10 according to an embodiment, and Figure 5 yes Figure 4 A schematic side view of the display panel 10. The electronic device 1 may include... Figure 4 and Figure 5 The display panel 10 shown in the image.

[0111] Display panel 10 may include a display area DA and a peripheral area PA outside the display area DA. The display area DA is the area where an image is displayed and can be set with multiple pixels. The display area DA can have various shapes, such as circular, elliptical, polygonal, or specific graphic shapes. Figure 4 The image shows that the display area DA has a roughly rectangular shape with rounded corners.

[0112] The peripheral region PA can be disposed outside (or around) the display region DA. The peripheral region PA can include a first peripheral region PA1 and a second peripheral region PA2, wherein the first peripheral region PA1 can surround at least a portion of the display region DA, and the second peripheral region PA2 is disposed at the lower end of the display region DA and extends in a first direction (e.g., the x-axis direction). The width of the second peripheral region PA2 in the first direction (e.g., the x-axis direction) can be smaller than the width of the display region DA. With this structure, at least a portion of the second peripheral region PA2 can be easily bent.

[0113] Figure 4 The planar shape of the display panel 10 shown can be consistent with that of the substrate 100 included in the display panel 10 (see [reference]). Figure 6The shapes are basically the same. In the case where the display panel 10 includes a display area DA and a peripheral area PA disposed outside the display area DA, this can represent the substrate 100 (see...). Figure 6 This includes the display area DA and the peripheral area PA outside the display area DA. In the following text, for convenience, the designation is based on substrate 100 (see [link to substrate 100]). Figure 6 The description includes the assumptions of the display area DA and the peripheral area PA.

[0114] The display panel 10 may include a main area MR, a bent area BR outside the main area MR, and a sub-area SR separated from the main area MR but located between the bent area BR. The main area MR may be located on one side of the bent area BR, and the sub-area SR may be located on the other side of the bent area BR. Figure 5 As shown, the display panel 10 can be bent within the bending region BR, and in the plan view, at least a portion of the sub-region SR can overlap with the main region MR. Although in Figure 5 The illustration shows the display panel 10 being bent, but this disclosure is not limited thereto. For example, the display panel 10 may be a foldable display panel, and for example, the display panel 10 may be bent inside the display area DA about a bending axis intersecting the display area DA. The display panel 10 may not be bent when needed. The sub-area SR may be a non-display area.

[0115] The data driver 20 can be arranged in the sub-region SR of the display panel 10. The data driver 20 can be disposed on the display panel 10 in the form of an integrated circuit (IC). For example, the data driver 20 can be a data driver integrated circuit that generates data signals.

[0116] The display circuit board 30 can be attached to the end of the sub-area SR of the display panel 10. The display circuit board 30 can be electrically connected to the data driver 20, etc., through the pads of the sub-area SR of the display panel 10.

[0117] Figure 6 yes Figure 4 A schematic plan view of the display panel 10. (Reference) Figure 6 The display panel 10 may include a substrate 100. Various components forming the display panel 10 may be disposed on the substrate 100.

[0118] Substrate 100 may comprise glass, ceramic, metal, or polymer resin. Substrate 100 may comprise polymer resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. Substrate 100 may have a multilayer structure comprising two layers containing the aforementioned polymer resin and an inorganic material layer disposed between the two layers. In another embodiment, substrate 100 may have a structure in which layers comprising polymer resin and inorganic material layers are alternately stacked. The inorganic material layer may comprise silicon oxide, silicon nitride, or silicon oxynitride.

[0119] Pixels can be disposed in a display area DA, and the display area DA can display an image using light emitted from the pixels. Each pixel may include a light-emitting diode (LED), and the LED may be electrically connected to the pixel circuitry PC. The pixel circuitry PC and the LED may be disposed in the display area DA. For convenience, although... Figure 6 The diagram shows a pixel circuit PC and a light-emitting diode (LED) arranged side by side, but the pixel circuit PC can actually overlap the LED at least partially. For example, the LED can be positioned on the pixel circuit PC.

[0120] The gate drive circuit, pad 14, power line 15, and common voltage supply line 16 can be located in the peripheral area PA. The gate drive circuit may include, for example, a first scan drive circuit 11, a second scan drive circuit 12, and / or an emit control drive circuit 13.

[0121] The first scan drive circuit 11 can provide a scan signal to the pixel circuit PC via the gate line SL. The second scan drive circuit 12 can be disposed opposite to the first scan drive circuit 11, with the display area DA located between the first scan drive circuit 11 and the second scan drive circuit 12. Some pixel circuits PCs disposed in the display area DA can be electrically connected to the first scan drive circuit 11, and other pixel circuits PCs can be electrically connected to the second scan drive circuit 12. Depending on the situation, the second scan drive circuit 12 can be omitted.

[0122] Like the first scan drive circuit 11, the emission control drive circuit 13 can be located on one side of the display area DA. The emission control drive circuit 13 can provide an emission control signal to the pixel circuit PC via the emission control line EL. Although in Figure 6The illustration shows that the emission control drive circuit 13 is disposed on only one side of the display area DA, but this disclosure is not limited thereto. For example, the display panel 10 may include emission control drive circuits 13 disposed on one side and the other side of the display area DA. In another embodiment, the display panel 10 may include a first scan drive circuit 11 disposed on one side of the display area DA and an emission control drive circuit 13 disposed on the other side of the display area DA.

[0123] The pad 14 can be disposed in the second peripheral region PA2 of the substrate 100. The pad 14 can be exposed without being covered by an insulating layer and can be electrically connected to the display circuit board 30. The pad 34 of the display circuit board 30 can be electrically connected to the pad 14 of the display panel 10.

[0124] The display circuit board 30 can transmit signals or power from the controller to the display panel 10. Control signals generated by the controller can be transmitted to the gate drive circuit via the display circuit board 30. The controller can separately apply the drive voltage ELVDD (in...) Figure 12 and Figure 13 (as shown in) and common voltage ELVSS (in Figure 12 and Figure 13 (As shown in the diagram) Power supply line 15 and common voltage supply line 16 are provided. A drive voltage ELVDD can be provided to each pixel circuit PC via a drive voltage line PL electrically connected to power supply line 15, and a common voltage ELVSS can be provided to the common electrode of the light-emitting diode (LED) electrically connected to the common voltage supply line 16. Power supply line 15 may extend in a first direction (x-axis direction). Common voltage supply line 16 may have a loop with an open side and partially surround the display area DA.

[0125] The data signal of the data driver 20 can be transmitted to the pixel circuit PC, which is electrically connected to the input line IL via the data line DL.

[0126] Figure 7 yes Figure 6 An enlarged schematic diagram of area A of the display panel 10. (See attached diagram.) Figure 7 As shown, the data line DL extending in the second direction (e.g., the y-axis direction) can be positioned in the display area DA, and the input line IL can be positioned in the peripheral area PA. The input line IL can transmit the data signal from the data driver 20 to the data line DL. For ease of illustration, although... Figure 7The diagram shows that the data lines DL include a first data line DL1, a second data line DL2, a third data line DL3, a fourth data line DL4, a fifth data line DL5, and a sixth data line DL6, and the input lines IL include a first input line IL1, a second input line IL2, a third input line IL3, a fourth input line IL4, a fifth input line IL5, and a sixth input line IL6. However, the number of data lines DL and the number of input lines IL can be varied.

[0127] Some data lines DL can be directly connected to their corresponding input lines IL, but other data lines DL can be electrically connected to their corresponding input lines IL via data transmission lines DTL.

[0128] The first data line DL1, the third data line DL3, and the fifth data line DL5 can receive data signals from the first input line IL1, the third input line IL3, and the fifth input line IL5. For example, the first data line DL1, the third data line DL3, and the fifth data line DL5 can be electrically connected to the first input line IL1, the third input line IL3, and the fifth input line IL5. Each of the first data line DL1, the third data line DL3, and the fifth data line DL5 can be integrally formed into a single unit with its corresponding counterpart among the first input line IL1, the third input line IL3, and the fifth input line IL5. In another embodiment, such as... Figure 7 As shown, each of the first data line DL1, the third data line DL3, and the fifth data line DL5 can be electrically connected to a corresponding one of the first input lines IL1, IL3, and IL5 through the first contact hole CNT1.

[0129] The second data line DL2, the fourth data line DL4, and the sixth data line DL6 can be electrically connected to the second input line IL2, the fourth input line IL4, and the sixth input line IL6 via the first data transmission line DTL1, the second data transmission line DTL2, and the third data transmission line DTL3. For example, the second input line IL2 can be electrically connected to the second data line DL2 via the first data transmission line DTL1, the fourth input line IL4 can be electrically connected to the fourth data line DL4 via the second data transmission line DTL2, and the sixth input line IL6 can be electrically connected to the sixth data line DL6 via the third data transmission line DTL3.

[0130] A large portion of each of the first data transmission lines DTL1, DTL2, and DTL3 can be located in the display area DA. One end of each of the first data transmission lines DTL1, DTL2, and DTL3 can be electrically connected via the second contact hole CNT2 to a corresponding one of the second input lines IL2, IL4, and IL6. The other end of each of the first data transmission lines DTL1, DTL2, and DTL3 can be electrically connected via the third contact hole CNT3 to a corresponding one of the second data lines DL2, DL4, and DL6. For reference, although in Figure 7 The diagram shows that the second contact hole CNT2 and the third contact hole CNT3 are disposed in the peripheral area PA, but this disclosure is not limited thereto. For example, the second contact hole CNT2 and / or the third contact hole CNT3 may be disposed in the display area DA.

[0131] The first data transmission line DTL1 may include a first horizontal connector DHL1, a first vertical connector DVL1, and a first additional vertical connector DVL1'; the second data transmission line DTL2 may include a second horizontal connector DHL2, a second vertical connector DVL2, and a second additional vertical connector DVL2'; and the third data transmission line DTL3 may include a third horizontal connector DHL3, a third vertical connector DVL3, and a third additional vertical connector DVL3'. The first horizontal connector DHL1, the second horizontal connector DHL2, and the third horizontal connector DHL3 may extend in a first direction (x-axis direction). The first vertical connector DVL1, the second vertical connector DVL2, the third vertical connector DVL3, the first additional vertical connector DVL1', the second additional vertical connector DVL2', and the third additional vertical connector DVL3' may extend in a second direction (e.g., y-axis direction) and may be substantially parallel to the data line DL.

[0132] Each of the second input line IL2, the fourth input line IL4, and the sixth input line IL6 can be electrically connected via the second contact hole CNT2 to a corresponding one of the first vertical connection lines DVL1, the second vertical connection line DVL2, and the third vertical connection line DVL3. Similarly, each of the second data line DL2, the fourth data line DL4, and the sixth data line DL6 can be electrically connected via the third contact hole CNT3 to a corresponding one of the first additional vertical connection lines DVL1', the second additional vertical connection line DVL2', and the third additional vertical connection line DVL3'. Each of the first horizontal connection line DHL1, the second horizontal connection line DHL2, and the third horizontal connection line DHL3 can be electrically connected via the first connection contact hole DHL-CNT1 to a corresponding one of the first vertical connection lines DVL1, the second vertical connection line DVL2, and the third vertical connection line DVL3. Furthermore, each of the second connection contact holes DHL-CNT2 can be electrically connected to a corresponding one of the first additional vertical connection lines DVL1', the second additional vertical connection line DVL2', and the third additional vertical connection line DVL3'.

[0133] The first vertical connecting line DVL1, the second vertical connecting line DVL2, the third vertical connecting line DVL3, the first additional vertical connecting line DVL1', the second additional vertical connecting line DVL2', and the third additional vertical connecting line DVL3' can be disposed on the same first layer, and the first horizontal connecting line DHL1, the second horizontal connecting line DHL2, and the third horizontal connecting line DHL3 can be disposed on a second layer different from the first layer. For reference, when some components are disposed on the same layer, these components can be formed simultaneously using the same masking process and the same material.

[0134] As mentioned above, Figure 7 The diagram shows a first data transmission line DTL1 comprising a first horizontal connector DHL1, a first vertical connector DVL1, and a first additional vertical connector DVL1'; a second data transmission line DTL2 comprising a second horizontal connector DHL2, a second vertical connector DVL2, and a second additional vertical connector DVL2'; and a third data transmission line DTL3 comprising a third horizontal connector DHL3, a third vertical connector DVL3, and a third additional vertical connector DVL3'. However, this disclosure is not limited thereto.

[0135] For example, as shown in the enlarged schematic diagram of a portion of the display panel 10 according to an embodiment. Figure 8As shown, the first data transmission line DTL1 may include a first horizontal connection line DHL1 and a first vertical connection line DVL1, the second data transmission line DTL2 may include a second horizontal connection line DHL2 and a second vertical connection line DVL2, and the third data transmission line DTL3 may include a third horizontal connection line DHL3 and a third vertical connection line DVL3. For example, each of the first horizontal connection line DHL1, the second horizontal connection line DHL2, and the third horizontal connection line DHL3 can be electrically connected to a corresponding one of the first vertical connection lines DVL1, the second vertical connection line DVL2, and the third vertical connection line DVL3 through the first connection contact hole DHL-CNT1, and can be electrically connected to a corresponding one of the second data line DL2, the fourth data line DL4, and the sixth data line DL6 through the second connection contact hole DHL-CNT2.

[0136] Figure 9 This is a schematic arrangement of the emission areas of a plurality of pixels in the display panel 10 and the electronic device 1 including the display panel 10 according to the embodiment.

[0137] Multiple pixels disposed in the display area DA may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. The first pixel PX1, second pixel PX2, and third pixel PX3 may be arranged repeatedly according to a preset pattern in the x-axis and y-axis directions. Each of the first pixel PX1, second pixel PX2, and third pixel PX3 may include a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The light-emitting element of each pixel may be disposed on the pixel circuit. For example, a light-emitting element including an organic light-emitting diode may be disposed directly above the pixel circuit to overlap with the pixel circuit, or may be configured to partially overlap with the pixel circuit of another pixel disposed in an adjacent row and / or column offset from the pixel circuit.

[0138] Figure 9 The approximate shapes of the pixel electrode PE and emission region of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 are shown. The emission region may be defined by a pixel defining layer having an opening corresponding to the central portion of the pixel electrode PE. Each pixel electrode PE may include a first region PEA1 corresponding to the emission region and a second region PEA2 surrounding the first region PEA1. The first region PEA1 may correspond to the opening of the pixel defining layer, and the second region PEA2 may be a region covered by the pixel defining layer.

[0139] In the first column M1, the first emission region EA1 of the first pixel PX1 and the third emission region EA3 of the third pixel PX3 can be alternately arranged in the second direction (e.g., the y-axis direction). In the second column M2, the second emission region EA2 of the second pixel PX2 can be repeatedly arranged in the second direction (e.g., the y-axis direction). The first column M1 and the second column M2 are alternately arranged in the first direction (e.g., the x-axis direction).

[0140] The arrangement of the first emission region EA1 of the first pixel PX1 and the third emission region EA3 of the third pixel PX3 in the first column M1, which are adjacent to each other in the +x direction of the second column M2, can be the opposite of the arrangement of the first emission region EA1 of the first pixel PX1 and the third emission region EA3 of the third pixel PX3 in the first column M1, which are adjacent to each other in the -x direction of the second column M2. Accordingly, the first emission region EA1 of the first pixel PX1 and the third emission region EA3 of the third pixel PX3 can be arranged alternately in the first sub-row SN1 of each row N in the first direction (e.g., the x-axis direction). The second emission region EA2 of the second pixel PX2 can be arranged repeatedly in the first direction (e.g., the x-axis direction) in the second sub-row SN2 of each row N. For example, in each row N, the first emission region EA1 of the first pixel PX1, the second emission region EA2 of the second pixel PX2, the third emission region EA3 of the third pixel PX3, and the second emission region EA2 of the second pixel PX2 can be arranged repeatedly in a zigzag shape.

[0141] The first emission region EA1 of the first pixel PX1, the second emission region EA2 of the second pixel PX2, and the third emission region EA3 of the third pixel PX3 can each have different areas in the planar image. For example, the third emission region EA3 of the third pixel PX3 can be larger than the first emission region EA1 of the first pixel PX1. The area of ​​the third emission region EA3 of the third pixel PX3 can be larger than the area of ​​the second emission region EA2 of the second pixel PX2. The area of ​​the first emission region EA1 of the first pixel PX1 can be larger than the area of ​​the second emission region EA2 of the second pixel PX2.

[0142] The first emission area EA1, the second emission area EA2, and the third emission area EA3 can have polygonal shapes such as quadrilaterals or octagons, circular shapes, or elliptical shapes. Polygonal shapes can have rounded corners (vertices).

[0143] The first pixel PX1 can be a red pixel R that emits red light, the second pixel PX2 can be a green pixel G that emits green light, and the third pixel PX3 can be a blue pixel B that emits blue light.

[0144] Figure 10 yes Figure 9A schematic diagram of the structure of the light-emitting elements of the display panel 10. For example, Figure 10 Is included Figure 9 A schematic diagram illustrating the structure of a first light-emitting element OLED1 or a second light-emitting element OLED2 in the first pixel PX1 or the second pixel PX2 of the display panel 10. The first light-emitting element OLED1 can emit red light, and the second light-emitting element OLED2 can emit green light.

[0145] like Figure 10 As shown, the first light-emitting element OLED1 can have a structure including a first emission layer disposed between the first pixel electrode PE1 and the common electrode CAT. The first emission layer can be a first color emission layer, and the first pixel electrode PE1 can be a first color pixel electrode. Similarly, the second light-emitting element OLED2 can have a structure including a second emission layer disposed between the second pixel electrode PE2 and the common electrode CAT. The second emission layer can be a second color emission layer, and the second pixel electrode PE2 can be a second color pixel electrode. Because the layer structure of the first light-emitting element OLED1 can be the same as or similar to the layer structure of the second light-emitting element OLED2, for convenience, the layer structure of the first light-emitting element OLED1 is described below.

[0146] Hole injection layer 310 and hole transport layer 320 can be disposed on the first pixel electrode PE1. A first emission layer 331, which is a first color emission layer corresponding to the first pixel electrode PE1, can be disposed on the hole transport layer 320. When needed, an auxiliary hole transport layer can be disposed between the first emission layer 331 (emitting red light) and the hole transport layer 320. Because the auxiliary hole transport layer has a preset thickness determined according to the resonant period of the light emitted from the first emission layer 331, it can improve the color purity of the light emitted from the first emission layer 331, or improve the emission efficiency from the first pixel PX1. Even when the second light-emitting element OLED2 includes a second emission layer 332 corresponding to the second pixel electrode PE2, the auxiliary hole transport layer can still be disposed between the second emission layer 332 and the hole transport layer 320. Because the auxiliary hole transport layer has a preset thickness determined according to the resonant period of the light emitted from the second emission layer 332, the auxiliary hole transport layer can improve the color purity of the light emitted from the second emission layer 332, or improve the emission efficiency from the second pixel PX2.

[0147] An electron transport layer 350 may be disposed on the first emission layer 331 and the second emission layer 332. A buffer layer may be disposed between the first emission layer 331 and the electron transport layer 350 and / or between the second emission layer 332 and the electron transport layer 350. A common electrode CAT, integrally formed as a single unit in the entire light-emitting element, may be disposed on the electron transport layer 350.

[0148] Figure 11 yes Figure 9 A schematic diagram of the structure of another light-emitting element of the display panel 10. For example, Figure 11 Is included Figure 9 A schematic diagram of the structure of the third light-emitting element OLED3 in the third pixel PX3 of the display panel 10. The third light-emitting element OLED3 may be a light-emitting element that emits blue light.

[0149] Hole injection layer 310 and hole transport layer 320 can be disposed on the third pixel electrode PE3, which is the third color pixel electrode. A third emission layer 333, which is the third color emission layer emitting blue light corresponding to the third pixel electrode PE3, can be disposed on the hole transport layer 320. A blue auxiliary layer 333a can be disposed between the hole transport layer 320 and the third emission layer 333. The blue auxiliary layer 333a can improve the light generation efficiency of the third emission layer 333 by adjusting the hole charge balance.

[0150] For reference, the portions of the hole injection layer 310 disposed on the first pixel electrode PE1, the portions of the hole injection layer 310 disposed on the second pixel electrode PE2, and the portions of the hole injection layer 310 disposed on the third pixel electrode PE3 can be electrically connected to each other. This also applies to the hole transport layer 320.

[0151] Electron transport layer 351, electron generation layer 341, hole generation layer 343, and hole transport layer 321 can be sequentially disposed on the third emission layer 333. A second emission layer 333', which emits blue light and corresponds to the third pixel electrode PE3, can be disposed on the hole transport layer 321. A blue auxiliary layer 333b can be disposed between the second emission layer 333' and the hole transport layer 321. The description of the blue auxiliary layer 333a also applies to the blue auxiliary layer 333b. Electron generation layer 341 and hole generation layer 343 can be charge generation layers. When needed, electron generation layer 341 and hole generation layer 343 can be integrally formed as a single unit.

[0152] An electron transport layer 350 may be disposed on the second emitter layer 333'. When needed, a buffer layer may be disposed between the second emitter layer 333' and the electron transport layer 350. A common electrode CAT may be disposed on the electron transport layer 350. In the electron transport layer 350 and / or the common electrode CAT, portions on the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be electrically connected to each other.

[0153] As described above, in the display panel 10 and the electronic device 1 including the display panel 10 according to the embodiment, the third light-emitting element OLED3 emitting blue light of the third pixel PX3 may include multiple emission layers 333 and 333'. Compared with emission layers emitting red light and emission layers emitting green light, emission layers emitting blue light have high power consumption, low brightness, and short lifespan. In contrast, in the display panel 10 and the electronic device 1 including the display panel 10 according to the embodiment, since the third light-emitting element OLED3 emitting blue light of the third pixel PX3 may include multiple emission layers 333 and 333', and electron generation layer 341 and hole generation layer 343 are disposed therebetween, such problems can be solved.

[0154] The first light-emitting element OLED1 of the first pixel PX1 may include a first emitting layer 331, and the second light-emitting element OLED2 of the second pixel PX2 may include a second emitting layer 332. In contrast, the third light-emitting element OLED3 of the third pixel PX3 may include a third emitting layer 333, an electron generating layer 341, a hole generating layer 343, and a second emitting layer 333', etc. Accordingly, the potential between the third pixel electrode PE3 and the common electrode CAT of the third light-emitting element OLED3 needs to be adjusted to a different potential than that between the first pixel electrode PE1 and the common electrode CAT of the first light-emitting element OLED1 and the second pixel electrode PE2 and the common electrode CAT of the second light-emitting element OLED2. This will be described below.

[0155] Figure 12 It can be electrically connected Figure 10 A schematic diagram of the equivalent circuit PC of the first light-emitting element OLED1 or the second light-emitting element OLED2, and Figure 13 It can be electrically connected Figure 11 A schematic diagram of the equivalent circuit PC of the third light-emitting element OLED3. First, the description is shown as follows. Figure 12 The equivalent circuit diagram of the pixel circuit PC is shown in the figure, and it is described as having the same characteristics as... Figure 12 The key points are different from the key points, and are expressed as Figure 13 The equivalent circuit diagram shown is a portion thereof.

[0156] like Figure 12As shown, the pixel circuit PC may include multiple thin-film transistors T1, T2, T3, T4, T5, T6, T7, and T8, and a storage capacitor Cst. The multiple thin-film transistors T1, T2, T3, T4, T5, T6, T7, and T8, and the storage capacitor Cst may be connected to signal lines GWL, GCL, GIL, GBL, EL, and DL, initialization voltage line VIL, first electrode initialization voltage line VL1, first drive voltage line PL1, and bias voltage line VBL. At least one of these lines (e.g., the first drive voltage line PL1) may be shared by pixels arranged adjacent to each other.

[0157] The multiple thin-film transistors T1, T2, T3, T4, T5, T6, T7 and T8 may include a driving transistor T1, a switching transistor T2, a compensation transistor T3, an initialization transistor T4, an operation control transistor T5, an emitter control transistor T6, a bias transistor T7 and an electrode initialization transistor T8.

[0158] The first light-emitting element OLED1 and / or the second light-emitting element OLED2 may include a pixel electrode and a common electrode. The pixel electrode can be connected to the driving transistor T1 via an emission control transistor T6, and the common electrode can receive a common voltage ELVSS. The first light-emitting element OLED1 and / or the second light-emitting element OLED2 can generate light with a brightness corresponding to the driving current.

[0159] Some of the multiple thin-film transistors T1, T2, T3, T4, T5, T6, T7, and T8 may be n-channel metal-oxide-semiconductor (NMOS) field-effect transistors (n-channel MOSFETs), and the remaining thin-film transistors may be p-channel metal-oxide-semiconductor (PMOS) field-effect transistors (p-channel MOSFETs). For example, among the multiple thin-film transistors T1, T2, T3, T4, T5, T6, T7, and T8, the compensation transistor T3 and the initialization transistor T4 may be n-channel MOSFETs (NMOS), and the remaining thin-film transistors may be p-channel MOSFETs (PMOS). In another embodiment, among the multiple thin-film transistors T1, T2, T3, T4, T5, T6, T7, and T8, the compensation transistor T3, the initialization transistor T4, and the electrode initialization transistor T8 may be n-channel MOSFETs (NMOS), and the remaining thin-film transistors may be p-channel MOSFETs (PMOS). In another embodiment, all of the plurality of thin-film transistors T1, T2, T3, T4, T5, T6, T7, and T8 may be NMOS or PMOS. The plurality of thin-film transistors T1, T2, T3, T4, T5, T6, T7, and T8 may each comprise amorphous silicon or polycrystalline silicon. When desired, the NMOS thin-film transistors may comprise oxide semiconductors. In the following description, for ease of description, the case is described where the compensation transistor T3 and the initialization transistor T4 are NMOS comprising oxide semiconductors and the remaining thin-film transistors are PMOS.

[0160] The signal lines may include a first scan line GWL, a second scan line GCL, a third scan line GIL, a fourth scan line GBL, an emit control line EL, and a data line DL. The first scan line GWL can transmit the first scan signal GW, the second scan line GCL can transmit the second scan signal GC, the third scan line GIL can transmit the initialization scan signal GI to the initialization transistor T4, the fourth scan line GBL can transmit the bias scan signal GB to the electrode initialization transistor T7, the emit control line EL can transmit the emit control signal EM to the operation control transistor T5 and the emit control transistor T6, and the data line DL intersects with the first scan line GWL and can transmit the data signal DATA.

[0161] The first driving voltage line PL1 can transmit the first driving voltage ELVDD1 to the driving transistor T1, the initialization voltage line VIL can transmit the initialization voltage Vint to initialize the driving transistor T1, and the first electrode initialization voltage line VL1 can transmit the first electrode initialization voltage Vaint1 to initialize the pixel electrode of the first light-emitting element OLED1 and / or the second light-emitting element OLED2.

[0162] The driving gate electrode of driving transistor T1 can be connected to storage capacitor Cst via second node N2. One of the source and drain regions of driving transistor T1 can be connected to the first driving voltage line PL1 via first node N1 through operation control transistor T5. The other of the source and drain regions of driving transistor T1 can be electrically connected to the pixel electrode of the first light-emitting element OLED1 and / or the second light-emitting element OLED2 via third node N3 through emitter control transistor T6. Driving transistor T1 can receive data signal DATA and supply driving current to the first light-emitting element OLED1 and / or the second light-emitting element OLED2 according to the switching operation of switching transistor T2.

[0163] The gate electrode of the switching transistor T2 can be connected to the first scan line GWL, which transmits the first scan signal GW. One of the source and drain regions of the switching transistor T2 can be connected to the data line DL, and the other of the source and drain regions of the switching transistor T2 can be connected to the driving transistor T1 through the first node N1 and to the first driving voltage line PL1 through the operation control transistor T5. The switching transistor T2 can transmit the data signal DATA from the data line DL to the first node N1 in response to the voltage applied to the first scan line GWL. For example, the switching transistor T2 can perform a switching operation in which it is turned on according to the first scan signal GW transmitted through the first scan line GWL and transmits the data signal DATA to the driving transistor T1 through the first node N1, with the data signal DATA transmitted through the data line DL.

[0164] The compensation gate electrode of compensation transistor T3 can be connected to the second scan line GCL. One of the source and drain regions of compensation transistor T3 can be connected to the pixel electrode of the first light-emitting element OLED1 and / or the second light-emitting element OLED2 via the emitter control transistor T6 through the third node N3. The other of the source and drain regions of compensation transistor T3 can be connected to the first capacitor electrode of the storage capacitor Cst and the drive gate electrode of the driving transistor T1 via the second node N2. The compensation transistor T3 can be turned on according to the second scan signal GC received via the second scan line GCL to connect the diode of the driving transistor T1.

[0165] The initialization gate electrode of the initialization transistor T4 can be connected to the third scan line GIL. One of the source and drain regions of the initialization transistor T4 can be connected to the initialization voltage line VIL. The other of the source and drain regions of the initialization transistor T4 can be connected to the first capacitor electrode of the storage capacitor Cst and the driving gate electrode of the driving transistor T1 via the second node N2. The initialization transistor T4 can apply an initialization voltage Vint from the initialization voltage line VIL to the second node N2 based on the voltage applied to the third scan line GIL. For example, the initialization transistor T4 can be turned on based on the initialization scan signal GI received through the third scan line GIL, and can perform an initialization operation to initialize the voltage of the driving gate electrode of the driving transistor T1 by transmitting the initialization voltage Vint to the driving gate electrode of the driving transistor T1.

[0166] The operation control gate electrode of the operation control transistor T5 can be connected to the emitter control line EL. One of the source and drain regions of the operation control transistor T5 can be connected to the first drive voltage line PL1, and the other of the source and drain regions of the operation control transistor T5 can be connected to the drive transistor T1 and the switch transistor T2 through the first node N1.

[0167] The emission control gate electrode of the emission control transistor T6 can be connected to the emission control line EL. One of the source and drain regions of the emission control transistor T6 can be connected to the driving transistor T1 and the compensation transistor T3 through the third node N3. The other of the source and drain regions of the emission control transistor T6 can be electrically connected to the pixel electrode of the first light-emitting element OLED1 and / or the second light-emitting element OLED2.

[0168] The operation control transistor T5 and the emission control transistor T6 can be simultaneously turned on according to the emission control signal EM transmitted through the emission control line EL, so as to allow the electrical signal from the first drive voltage line PL1 to be transmitted to the first light-emitting element OLED1 and / or the second light-emitting element OLED2, thereby allowing the drive current to flow from the first node N1 to the first light-emitting element OLED1 and / or the second light-emitting element OLED2.

[0169] The bias transistor T7 can be connected between the first node N1 and the bias voltage line VBL. The bias transistor T7 can be turned on according to the bias scan signal GB transmitted via the fourth scan line GBL, and can apply the bias voltage VOBS to the first node N1 to pre-set a voltage suitable for driving the transistor T1 to subsequent operations at the first node N1. From this perspective, the fourth scan line GBL can be considered a bias gate line.

[0170] The first electrode initialization gate electrode of the electrode initialization transistor T8 can be connected to the fourth scan line GBL. One of the source and drain regions of the electrode initialization transistor T8 can be connected to the first light-emitting element OLED1 and / or the second light-emitting element OLED2, and the other of the source and drain regions of the electrode initialization transistor T8 can be connected to the first electrode initialization voltage line VL1 to receive the first electrode initialization voltage Vaint1. The electrode initialization transistor T8 can be turned on according to the bias scan signal GB transmitted through the fourth scan line GBL, and can initialize the pixel electrodes of the first light-emitting element OLED1 and / or the second light-emitting element OLED2.

[0171] The storage capacitor Cst may include a first capacitor electrode and a second capacitor electrode. The first capacitor electrode of the storage capacitor Cst may be connected to the driving gate electrode of the driving transistor T1 through a second node N2, and the second capacitor electrode of the storage capacitor Cst may be connected to the first driving voltage line PL1. The storage capacitor Cst may store a charge corresponding to the difference between the voltage of the driving gate electrode of the driving transistor T1 and the first driving voltage ELVDD1.

[0172] The specific operation of each pixel according to the embodiment is described below.

[0173] When the initialization scan signal GI is supplied via the third scan line GIL during the initialization period, the initialization transistor T4 is turned on according to the initialization scan signal GI, and the driving transistor T1 is initialized by the initialization voltage Vint supplied from the initialization voltage line VIL. When the bias scan signal GB is supplied via the fourth scan line GBL, the electrode initialization transistor T8 can be turned on in response to the bias scan signal GB, and the pixel electrodes of the first light-emitting element OLED1 and / or the second light-emitting element OLED2 can be initialized by the first electrode initialization voltage Vaint1 supplied from the first electrode initialization voltage line VL1. The bias transistor T7 can also be turned on according to the bias scan signal GB, and the bias voltage VOBS can be applied to the first node N1 to preset a voltage suitable for subsequent operation of the driving transistor T1 to the first node N1.

[0174] During the data programming period, when the first scan signal GW and the second scan signal GC are supplied via the first scan line GWL and the second scan line GCL, the switching transistor T2 and the compensation transistor T3 can be turned on according to the first scan signal GW and the second scan signal GC, respectively. For example, the driving transistor T1 can be connected by a diode, and the turned-on compensation transistor T3 is forward biased. Then, a compensation voltage DATA+Vth (Vth has a negative value) can be applied to the driving gate electrode of the driving transistor T1, wherein the compensation voltage DATA+Vth is the voltage from the data signal DATA supplied by the data line DL that reduces the threshold voltage (Vth) of the driving transistor T1. The first driving voltage ELVDD1 and the compensation voltage DATA+Vth can be applied to the two opposite ends of the storage capacitor Cst, respectively, and the charge corresponding to the difference between the voltages at the two opposite ends can be stored in the storage capacitor Cst.

[0175] During the emission period, the operation control transistor T5 and the emission control transistor T6 can be turned on according to the emission control signal EM supplied from the emission control line EL. A drive current corresponding to the voltage difference between the voltage of the drive gate electrode of the drive transistor T1 and the first drive voltage ELVDD1 can be generated, and the drive current can be supplied to the first light-emitting element OLED1 and / or the second light-emitting element OLED2 through the emission control transistor T6.

[0176] As described above, some of the thin-film transistors T1, T2, T3, T4, T5, T6, T7, and T8 may include oxide semiconductors. For example, compensation transistor T3 and initialization transistor T4 may include oxide semiconductors.

[0177] Because polysilicon has high reliability, it is possible to precisely control the flow of the desired current. Accordingly, the driving transistor T1, which directly affects the brightness of the display device, can include a semiconductor layer comprising highly reliable polysilicon, and thus, a high-resolution display device can be realized through this construction. Because oxide semiconductors have high carrier mobility and low leakage current, the voltage drop is small even with long driving times. For example, in oxide semiconductors, the color change of the image based on the voltage drop is small even when driving the display device at low frequencies, so the display device can be driven at low frequencies. Accordingly, by allowing the compensation transistor T3 and the initialization transistor T4 to include oxide semiconductors, a display device in which leakage current is prevented while simultaneously having reduced power consumption can be realized.

[0178] Because oxide semiconductors are photosensitive, changes in current may occur due to external light. Accordingly, external light can be absorbed or reflected by providing a metal layer beneath the oxide semiconductor. For example, each of the compensation transistor T3 and initialization transistor T4, which include an oxide semiconductor, may have gate electrodes on and under the oxide semiconductor layer. For example, in a direction perpendicular to the upper surface of the substrate 100 (z-axis direction) (in a plan view), the metal layer disposed beneath the oxide semiconductor may overlap with the oxide semiconductor.

[0179] Reference above Figure 12 The pixel circuit described is different; except for the first driving voltage line PL1, it can be electrically connected to the third light-emitting element OLED3 included in the third pixel PX3. Figure 13 The pixel circuit PC shown may include a second drive voltage line PL2. When needed, the pixel circuit PC may include a second electrode initialization voltage line VL2 instead of the first electrode initialization voltage line VL1.

[0180] Even when the pixel circuit is electrically connected to the third light-emitting element OLED3, the first capacitor electrode of the storage capacitor Cst can be electrically connected to the driving gate electrode of the driving transistor T1 through the second node N2, and the second capacitor electrode of the storage capacitor Cst can be electrically connected to the first driving voltage line PL1. Accordingly, when the same data signal as the data signal applied to the pixel circuit electrically connected to the first light-emitting element OLED1 is applied to the pixel circuit electrically connected to the third light-emitting element OLED3, a potential identical to the potential between the source electrode and gate electrode of the driving transistor T1 electrically connected to the pixel circuit electrically connected to the first light-emitting element OLED1 can be applied between the source electrode and gate electrode of the driving transistor T1 electrically connected to the pixel circuit electrically connected to the third light-emitting element OLED3. Accordingly, when the same brightness data is applied, the driving transistor T1 electrically connected to the pixel circuit electrically connected to the first light-emitting element OLED1 and the driving transistor T1 electrically connected to the pixel circuit electrically connected to the third light-emitting element OLED3 can operate in the same manner.

[0181] However, in the pixel circuit electrically connected to the third light-emitting element OLED3, the driving transistor T1 can receive the second driving voltage ELVDD2 via the second driving voltage line PL2 instead of the first driving voltage line PL1. For example, the driving gate electrode of the driving transistor T1 can be electrically connected to the storage capacitor Cst via the second node N2, one of the source and drain regions of the driving transistor T1 can be connected to the second driving voltage line PL2 via the first node N1 through the operation control transistor T5, and the other of the source and drain regions of the driving transistor T1 can be electrically connected to the pixel electrode of the third light-emitting element OLED3 via the third node N3 through the emitter control transistor T6. In response to the voltage applied to the second node, the driving transistor T1 can receive the data signal DATA and supply driving current from the first node to the third light-emitting element OLED3 according to the switching operation of the switching transistor T2.

[0182] As described above, unlike the first light-emitting element OLED1 and / or the second light-emitting element OLED2, because the third light-emitting element OLED3 includes an electron-generating layer 341, a hole-generating layer 343, and multiple emitting layers 333 and 333', the potential between the third pixel electrode PE3 and the common electrode CAT of the third light-emitting element OLED3 can be adjusted to be different from the potential between the first pixel electrode PE1 and the common electrode CAT of the first light-emitting element OLED1 or the potential between the second pixel electrode PE2 and the common electrode CAT of the second light-emitting element OLED2. In the display panel 10 and the electronic device 1 including the display panel 10 according to the embodiment, such as... Figure 12 and Figure 13 As shown, the potential between the first pixel electrode PE1 of the first light-emitting element OLED1 and the common electrode CAT, or the potential between the second pixel electrode PE2 of the second light-emitting element OLED2 and the common electrode CAT, can be maintained at approximately the difference between the first driving voltage ELVDD1 and the common voltage ELVSS. Simultaneously, the potential between the third pixel electrode PE3 of the third light-emitting element OLED3 and the common electrode CAT can be maintained at approximately the difference between the second driving voltage ELVDD2 and the common voltage ELVSS. Accordingly, a display panel 10 for displaying high-quality images and an electronic device 1 including the display panel 10 can be realized.

[0183] The potential of the second driving voltage ELVDD2 can be different from the potential of the first driving voltage ELVDD1. For example, the potential of the second driving voltage ELVDD2 can be greater than the potential of the first driving voltage ELVDD1. For example, the common voltage ELVSS can be approximately -6V, the first driving voltage ELVDD1 can be approximately 5V, and the second driving voltage ELVDD2 can be approximately 7V.

[0184] The first pixel electrode PE1 of the first light-emitting element OLED1 and the second pixel electrode PE2 of the second light-emitting element OLED2 can be initialized by the electrode initialization transistor T8 to the first electrode initialization voltage Vaint1 from the first electrode initialization voltage line VL1, and the third pixel electrode PE3 of the third light-emitting element OLED3 can be initialized by the electrode initialization transistor T8 to the second electrode initialization voltage Vaint2 from the second electrode initialization voltage line VL2.

[0185] Because the parasitic capacitances or light-emitting threshold voltages of the pixel electrodes PE1, PE2, and PE3 of the first light-emitting element OLED1, the second light-emitting element OLED2, and the third light-emitting element OLED3 are different from each other, the electrode initialization voltages applied to the pixel electrodes PE1, PE2, and PE3 of the first light-emitting element OLED1, the second light-emitting element OLED2, and the third light-emitting element OLED3 need to be different from each other. For this purpose, the electrode initialization voltage lines for the first light-emitting element OLED1, the second light-emitting element OLED2, and the third light-emitting element OLED3 can be separately provided within the display area DA. However, in a high-resolution display panel 10 and an electronic device 1 including the display panel 10, it may not be easy to separately provide the electrode initialization voltage lines for the first light-emitting element OLED1, the second light-emitting element OLED2, and the third light-emitting element OLED3.

[0186] In the display panel 10 and the electronic device 1 including the display panel 10 according to the embodiment, a second electrode initialization voltage Vaint2, different from the first electrode initialization voltage Vaint1, is applied to at least the third light-emitting element OLED3, and accordingly, the display panel 10 and the electronic device 1 including the display panel 10 can be realized to display high-quality images.

[0187] Figure 14 It is shown that it includes Figure 9 A schematic diagram showing the arrangement of transistors and capacitors in the pixels of the display panel 10. Figures 15 to 22 yes Figure 14 The diagram shows a schematic arrangement of elements such as transistors and capacitors in each layer of the display panel 10. Figure 23 yes Figure 9 A schematic diagram of the pixel electrodes PE1, PE2, and PE3 of the display panel 10, and Figure 24 It is along Figure 14 A schematic cross-sectional view of the display panel 10 taken by lines A-A' and B-B'.

[0188] The display panel 10 and the electronic device 1 including the display panel 10 may have a structure in which a group of third pixel regions PXA3, second pixel regions PXA2, first pixel regions PXA1, and second pixel regions PXA2 arranged sequentially in a first direction (e.g., the x-axis direction) are repeatedly arranged in the first direction (e.g., the x-axis direction). For reference, the region adjacent to each of the +y and -y directions of the third pixel region PXA3 may be the first pixel region PXA1, the region adjacent to each of the +y and -y directions of the first pixel region PXA1 may be the third pixel region PXA3, and the region adjacent to each of the +y and -y directions of the second pixel region PXA2 may be the second pixel region PXA2.

[0189] The pixel circuit of the first pixel PX1 can be located in the first pixel region PXA1, the pixel circuit of the second pixel PX2 can be located in the second pixel region PXA2, and the pixel circuit of the third pixel PX3 can be located in the third pixel region PXA3. The pixel circuit of the first pixel PX1 can be a first-color pixel circuit, the pixel circuit of the second pixel PX2 can be a second-color pixel circuit, and the pixel circuit of the third pixel PX3 can be a third-color pixel circuit. The first color can represent red, the second color can represent green, and the third color can represent blue. However, this is not limited to these. For example, the first color can be green, the second color can be blue, and the third color can be red. Or, for another example, the first color can be blue, the second color can be red, and the third color can be green.

[0190] The third pixel region PXA3 and the second pixel region PXA2, which are set adjacent to each other, can be relative to each other as follows: Figure 14 The imaginary boundary line IBL shown in the figure is symmetrical. This also applies to the case of the first pixel region PXA1 and the second pixel region PXA2. In contrast, pixel regions can have the same structure, rather than a symmetrical structure.

[0191] In the following text, for ease of description, although some conductive patterns are described based on the pixel circuitry set in the third pixel region PXA3, these conductive patterns may also be set symmetrically or similarly in the first pixel region PXA1 and / or the second pixel region PXA2.

[0192] Buffer layer 101 (see) Figure 24A buffer layer 101 may be disposed on the substrate 100, wherein the buffer layer 101 may comprise silicon oxide, silicon nitride, or silicon oxynitride. The buffer layer 101 can prevent metal atoms or impurities from the substrate 100 from diffusing to the first semiconductor layer SACT disposed thereon. The buffer layer 101 can allow the first semiconductor layer SACT to be uniformly crystallized by adjusting the rate of heat supply during the crystallization process for forming the first semiconductor layer SACT.

[0193] Figure 15 The first semiconductor layer SACT shown can be disposed on the buffer layer 101. The first semiconductor layer SACT can include silicon semiconductor. For example, the first semiconductor layer SACT can include amorphous silicon or polycrystalline silicon. For example, the first semiconductor layer SACT can include polycrystalline silicon crystallized at low temperature. When needed, ions can be implanted into at least a portion of the first semiconductor layer SACT. If needed, a lower metal layer corresponding to the shape of the first semiconductor layer SACT can be disposed below the first semiconductor layer SACT to protect the first semiconductor layer SACT. For example, an insulating layer can be disposed between the lower metal layer and the first semiconductor layer SACT.

[0194] The first semiconductor layer SACT may include a first sub-semiconductor layer SACT1 and a second sub-semiconductor layer SACT2 separated from the first sub-semiconductor layer SACT1. The first sub-semiconductor layer SACT1 of the third pixel region PXA3 and the first sub-semiconductor layer SACT1 of the second pixel region PXA2, which is disposed adjacent to the third pixel region PXA3 in the +x direction, may be spaced apart from each other. However, the first sub-semiconductor layer SACT1 of the first pixel region PXA1 and the first sub-semiconductor layer SACT1 of the second pixel region PXA2, which is disposed adjacent to the first pixel region PXA1 in the +x direction, may be integrally formed as a single unit. As described below, the second sub-semiconductor layer SACT2 may be electrically connected to the first sub-semiconductor layer SACT1 via a connection electrode 176 included in the first source / drain layer SD1.

[0195] The first sub-semiconductor layer SACT1 can have a shape that is bent into various forms. Driving transistor T1, switching transistor T2, operation control transistor T5, emitter control transistor T6, and electrode initialization transistor T8 can be disposed in the first sub-semiconductor layer SACT1. For example, the first sub-semiconductor layer SACT1 may include the channel region of each of the driving transistor T1, switching transistor T2, operation control transistor T5, emitter control transistor T6, and electrode initialization transistor T8, as well as source and drain regions on two opposite sides of the channel region. The second sub-semiconductor layer SACT2 may include the channel region, source region, and drain region of the bias transistor T7. Figure 15In the diagram, the positions of the channel regions of transistors T1, T2, T5, T6, T7, and T8 are indicated by the reference numerals on the diagrams for transistors T1, T2, T5, T6, T7, and T8. The source and drain regions are located on one side and the other side of the channel region, respectively.

[0196] First gate insulating layer 102 (see Figure 24 The first gate insulating layer 102 can be disposed on the substrate 100 to cover the first semiconductor layer SACT. The first gate insulating layer 102 may include an insulating material. For example, the first gate insulating layer 102 may include silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0197] like Figure 16 As shown, the first gate layer GTL1 can be disposed on the first gate insulating layer 102. The first gate layer GTL1 may include a first scan line GWL for transmitting the first scan signal GW, a fourth scan line GBL for transmitting the bias scan signal GB to the electrode initialization transistor T8, an emitter control line EL for transmitting the emitter control signal EM to the operation control transistor T5 and the emitter control transistor T6, an initialization voltage line VIL for transmitting the initialization voltage Vint of the initialization driving transistor T1, and a driving gate electrode 131a of the driving transistor T1 with an isolated shape. The driving gate electrode 131a may also serve as the lower electrode of the first electrode of the capacitor Cst.

[0198] The first scan line GWL, the fourth scan line GBL, the emitter control line EL, and the initialization voltage line VIL may have a shape extending in a first direction (e.g., the x-axis direction). The portion of the first semiconductor layer SACT that overlaps with the first scan line GWL, the fourth scan line GBL, and the emitter control line EL may serve as the gate electrode of a transistor. For example, the portion of the first scan line GWL that overlaps with the first semiconductor layer SACT may be the switching gate electrode of a switching transistor T2, the portion of the fourth scan line GBL that overlaps with the first semiconductor layer SACT may be the bias gate electrode of a bias transistor T7, and the portion of the emitter control line EL that overlaps with the first semiconductor layer SACT may be the operation control gate electrode of an operation control transistor T5 and the emitter control gate electrode of an emitter control transistor T6.

[0199] The first gate layer GTL1 may include metals, alloys, conductive metal oxides, or transparent conductive materials. For example, the first gate layer GTL1 may include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The first gate layer GTL1 may have a multilayer structure. For example, the first gate layer GTL1 may have a two-layer structure of Mo / Al or a three-layer structure of Mo / Al / Mo.

[0200] Second gate insulating layer 103 (see Figure 24 The second gate insulating layer 103 may cover the first gate layer GTL1 and be disposed on the first gate insulating layer 102. The second gate insulating layer 103 may include an insulating material that is the same as or similar to the insulating material of the first gate insulating layer 102.

[0201] like Figure 17 As shown, the second gate layer GTL2 can be disposed on the second gate insulating layer 103. The second gate layer GTL2 may include the electrode voltage line HL, the lower gate line GCL1 of the second scan line GCL, and the lower gate line GIL1 of the third scan line GIL. The electrode voltage line HL, the lower gate line GCL1 of the second scan line GCL, and the lower gate line GIL1 of the third scan line GIL may extend in a first direction (e.g., the x-axis direction).

[0202] A portion of the electrode voltage line HL can be the upper electrode of the second electrode of capacitor Cst, and can overlap with the driving gate electrode 131a, which is the lower electrode of capacitor Cst. The upper electrode of capacitor Cst of pixel circuits in the same row can be integrally formed into a single unit extending in a first direction (e.g., the x-axis direction) via the electrode voltage line HL. A first driving voltage ELVDD1 can be applied to the upper electrode of capacitor Cst. An opening SOP can be formed in the upper electrode of storage capacitor Cst, and at least a portion of the driving gate electrode 131a can overlap with the opening.

[0203] The portion of the lower gate line GCL1 of the second scan line GCL that overlaps with the second semiconductor layer OACT described below can be the compensation lower gate electrode of the compensation transistor T3, and the portion of the lower gate line GIL1 of the third scan line GIL that overlaps with the second semiconductor layer OACT can be the first initialization lower gate electrode of the initialization transistor T4.

[0204] The second gate layer GTL2 can include metals, alloys, conductive metal oxides, or transparent conductive materials. For example, the second gate layer GTL2 can include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The second gate layer GTL2 can have a multilayer structure. For example, the second gate layer GTL2 can have a two-layer structure of Mo / Al or a three-layer structure of Mo / Al / Mo.

[0205] First interlayer insulation layer 104 (see...) Figure 24 The first interlayer insulating layer 104 may cover the second gate layer GTL2 and is disposed on the second gate insulating layer 103. The first interlayer insulating layer 104 may include an insulating material. For example, the first interlayer insulating layer 104 may include silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0206] Figure 18 The second semiconductor layer OACT shown can be disposed on the first interlayer insulating layer 104. As described above, the second semiconductor layer OACT can include an oxide semiconductor. The second semiconductor layer OACT can be disposed on a layer different from the first semiconductor layer SACT. When viewed in a direction perpendicular to the substrate 100 (z-axis direction) (or in a plan view), the second semiconductor layer OACT may not overlap with the first semiconductor layer SACT. The second semiconductor layer OACT can form a compensation transistor T3 and an initialization transistor T4. Figure 18 In the diagram, the locations of the channel regions of transistors T3 and T4 are indicated by the reference numerals on transistors T3 and T4. The source region can be located on one side of the channel region, and the drain region can be located on the other side of the channel region.

[0207] The second semiconductor layer OACT may include a first vertical semiconductor layer OACT1 disposed in the third pixel region PXA3 and extending in a second direction (e.g., the y-axis direction), and a semiconductor extension layer OACTE extending from the first vertical semiconductor layer OACT1 in a first direction (e.g., the x-axis direction). Because the second vertical semiconductor layer OACT2 extending in the second direction (e.g., the y-axis direction) may also be disposed in the second pixel region PXA2, one end of the semiconductor extension layer OACTE may be connected to the first vertical semiconductor layer OACT1, and the other end may be connected to the second vertical semiconductor layer OACT2. For example, the first vertical semiconductor layer OACT1, the second vertical semiconductor layer OACT2, and the semiconductor extension layer OACTE disposed in the third pixel region PXA3 may be integrally formed as a single unit. This also applies to the first pixel region PXA1 and the second pixel region PXA2.

[0208] Third gate insulating layer 105 (see Figure 24 The third gate insulating layer 105 can be disposed on the first interlayer insulating layer 104 to cover the second semiconductor layer OACT. The third gate insulating layer 105 may include an insulating material. The third gate insulating layer 105 may include silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0209] like Figure 19 As shown, the third gate layer GTL3 can be disposed on the third gate insulating layer 105. The third gate layer GTL3 may include the upper gate line GCL2 of the second scan line GCL, the upper gate line GIL2 of the third scan line GIL, the second electrode initialization voltage line VL2, and the bias voltage line VBL. The upper gate line GCL2 of the second scan line GCL, the upper gate line GIL2 of the third scan line GIL, the second electrode initialization voltage line VL2, and the bias voltage line VBL may extend in a first direction (e.g., the x-axis direction).

[0210] The portion of the upper gate line GCL2 of the second scan line GCL that overlaps with the second semiconductor layer OACT can be the compensation upper gate electrode of the compensation transistor T3, and the portion of the upper gate line GIL2 of the third scan line GIL that overlaps with the second semiconductor layer OACT can be the first initialization upper gate electrode of the initialization transistor T4. For example, the compensation transistor T3 and the initialization transistor T4 can each have a dual-gate structure, which has gate electrodes on and below the second semiconductor layer OACT.

[0211] The third gate layer GTL3 can include metals, alloys, conductive metal oxides, or transparent conductive materials. For example, the third gate layer GTL3 can include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The third gate layer GTL3 can have a multilayer structure. For example, the third gate layer GTL3 can have a two-layer structure of Mo / Al or a three-layer structure of Mo / Al / Mo.

[0212] For reference, although Figure 24 The diagram shows a third gate insulating layer 105 having a shape corresponding to the entire surface of the substrate 100, and a third gate layer GTL3 disposed on the third gate insulating layer 105; however, this disclosure is not limited thereto. For example, the third gate insulating layer 105 may be formed, a conductive layer for forming the third gate layer GTL3 may be formed on the third gate insulating layer 105, and then the conductive layer may be patterned to form... Figure 19 In the case of the third gate layer GTL3 shown, the third gate insulating layer 105 beneath it can also be patterned. For example, in a plan view, the shape of the third gate insulating layer 105 can be represented to correspond to the shape of the third gate layer GTL3. For example, the third gate insulating layer 105 can be disposed only beneath the third gate layer GTL3.

[0213] Second interlayer insulation layer 106 (see Figure 24 ) can cover Figure 19 At least a portion of the third gate layer GTL3. The second interlayer insulating layer 106 may include an insulating material. For example, the second interlayer insulating layer 106 may include silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0214] Figure 20 The first source / drain layer SD1 shown can be disposed on the second interlayer insulating layer 106. The first source / drain layer SD1 may include a first electrode initialization voltage line VL1, a horizontal connection line BRSH, and connection electrodes 171 to 179. The first electrode initialization voltage line VL1 and the horizontal connection line BRSH may have a shape extending in a first direction (e.g., the x-axis direction). The connection electrodes 171 to 179 may have an isolated shape.

[0215] The first electrode initialization voltage line VL1 can be electrically connected to the first semiconductor layer SACT through a contact hole 67a in the lower part of the insulating layer of each of the second pixel region PXA2 in which the pixel circuit of the second pixel PX2 is disposed and the first pixel region PXA1 in which the pixel circuit of the first pixel PX1 is disposed. Correspondingly, it can be electrically connected to the drain region of the electrode initialization transistor T8 of the second pixel PX2 and the drain region of the electrode initialization transistor T8 of the first pixel PX1. The first electrode initialization voltage line VL1 may be curved and extend in a sawtooth shape in a first direction (e.g., the x-axis direction).

[0216] As described above, since the second electrode initialization voltage line VL2 is disposed on the third gate layer GTL3, one end of the connecting electrode 179 can be electrically connected to the second electrode initialization voltage line VL2 by contacting it via contact hole 67b. For example, one end of the connecting electrode 179 can be electrically connected to the second electrode initialization voltage line VL2 through contact hole 67b passing through the underlying insulating layer. The other end of the connecting electrode 179 can be electrically connected to the drain region of the electrode initialization transistor T8 of the third pixel PX3 through contact hole 67c passing through the underlying insulating layer. Accordingly, the second electrode initialization voltage line VL2 can be electrically connected to the drain region of the electrode initialization transistor T8 of the third pixel PX3. The connecting electrode 179 can be disposed only in the third pixel region PXA3.

[0217] With this configuration, the first electrode initialization voltage Vaint1 can be applied to the electrode initialization transistor T8 of the first pixel PX1 and the electrode initialization transistor T8 of the second pixel PX2 through the first electrode initialization voltage line VL1, and the second electrode initialization voltage Vaint2 can be applied to the electrode initialization transistor T8 of the third pixel PX3 through the second electrode initialization voltage line VL2.

[0218] The horizontal connecting line BRSH extending in the first direction (e.g., the x-axis direction) can be compared with the reference. Figure 7 or Figure 8 A portion of the described data transmission line DTL (e.g., one of the first horizontal connection line DHL1, the second horizontal connection line DHL2, and the third horizontal connection line DHL3) corresponds to this. When needed, the horizontal connection line BRSH can be electrically connected to the dummy electrode 173a located nearby in the -y direction. Where the horizontal connection line BRSH needs to be electrically connected to the vertical connection line BRSV (see...), the connection is further defined. Figure 21 In the case of a dummy electrode 173a, the horizontal connecting line BRSH can be electrically connected to the vertical connecting line BRSV. Thus, the horizontal connecting line BRSH, together with the vertical connecting line BRSV, can be electrically connected to a point not located at... Figure 20The data lines DL of the pixel circuits in another column are shown to transmit data signals to the pixel circuits in that other column. For example... Figure 20 As shown, when the third pixel area PXA3 and the like are not located near the corner of the display area DA but are located at the center of the display area DA, the horizontal connecting line BRSH can be a dummy line that is not subject to an electrical signal or a dummy line that is subject to a preset electrical signal when needed.

[0219] One end of the connection electrode 171 can be electrically connected to the second semiconductor layer OACT via contact hole 51. For example, one end of the connection electrode 171 can be electrically connected to the compensation transistor T3 and the initialization transistor T4 via contact hole 51 passing through the underlying insulating layer. The other end of the connection electrode 171 can be electrically connected to the drive gate electrode 131a of the drive transistor T1, which also acts as the lower electrode of the storage capacitor Cst, via contact hole 52 passing through the underlying insulating layer. Contact hole 52 can pass through the opening SOP of the upper electrode of the storage capacitor Cst.

[0220] The connecting electrode 172 can be electrically connected to the drain region of the driving transistor T1 and the source region of the emitter control transistor T6 through the contact hole 53 passing through the underlying insulating layer. The connecting electrode 172 can be electrically connected to the drain region of the compensation transistor T3 through the contact hole 54 passing through the underlying insulating layer.

[0221] The connecting electrode 173 can be electrically connected to the source region of the switching transistor T2 through the contact hole 55 passing through the insulating layer underneath.

[0222] In the second pixel region PXA2, which is the second region among the third pixel region PXA3, the second pixel region PXA2, the first pixel region PXA1, and the second pixel region PXA2 arranged sequentially in a first direction (e.g., the x-axis direction), the connecting electrode 174a can be electrically connected to the source region of the operation control transistor T5 in the second pixel region PXA2 through the contact hole 56a passing through the insulating layer below it. The connecting electrode 174a in the second pixel region PXA2 can be electrically connected to the electrode voltage line HL, which also acts as the upper electrode of the storage capacitor Cst, through the contact hole 57a passing through the insulating layer below it, and thus electrically connected to the first driving voltage line PL1. As a result, the first driving voltage ELVDD1 of the first driving voltage line PL1 can be transmitted to the operation control transistor T5 in the second pixel PX2, and correspondingly applied to the second pixel electrode PE2 of the second light-emitting element OLED2 through the driving transistor T1, etc. Therefore, this can be understood as the second color pixel circuit of the pixel circuit of the second pixel PX2 being electrically connected to the first driving voltage line PL1.

[0223] The connection electrode 174b of the third pixel region PXA3 can be electrically connected to the source region of the operation control transistor T5 of the third pixel region PXA3 through a contact hole 56b passing through the insulating layer below. As described below, the connection electrode 174b of the third pixel region PXA3 can be electrically connected to the second driving voltage line PL2 thereon. Accordingly, the second driving voltage ELVDD2 of the second driving voltage line PL2 can be transmitted to the operation control transistor T5 in the third pixel PX3, and accordingly applied to the third pixel electrode PE3 of the third light-emitting element OLED3 through the driving transistor T1, etc. This can be understood as the third color pixel circuit of the pixel circuit of the third pixel PX3 being electrically connected to the second driving voltage line PL2.

[0224] In the third pixel region PXA3, the second pixel region PXA2, the first pixel region PXA1, and the second pixel region PXA2, which are the fourth regions arranged sequentially in a first direction (e.g., the x-axis direction), the first pixel PX1 and the second pixel PX2 can share a connection electrode 174d. The connection electrode 174d can be electrically connected to the first sub-semiconductor layer SACT1, which is integrally formed as a single unit in the first pixel region PXA1 and the second pixel region PXA2, through a contact hole 56 passing through the underlying insulating layer, and therefore electrically connected to the source region of the operation control transistor T5 in the first pixel region PXA1 and the source region of the operation control transistor T5 in the second pixel region PXA2. The connection electrode 174d can be electrically connected to the electrode voltage line HL, which also acts as the upper electrode of the storage capacitor Cst, through a contact hole 57 passing through the underlying insulating layer, and therefore electrically connected to the first drive voltage line PL1. Therefore, the first driving voltage ELVDD1 of the first driving voltage line PL1 can be transmitted to the operation control transistor T5 in the first pixel PX1 and the operation control transistor T5 in the second pixel PX2, and correspondingly, transmitted to the first pixel electrode PE1 of the first light-emitting element OLED1 and the second pixel electrode PE2 of the second light-emitting element OLED2 through the driving transistor T1, etc.

[0225] Therefore, this can be understood as the first color pixel circuit of the pixel circuit of the first pixel PX1 being electrically connected to the first driving voltage line PL1. Furthermore, it can be understood that the first color pixel circuit of the pixel circuit in the first pixel PX1 is electrically connected to a corresponding line in the first driving voltage line PL1 via a second color pixel circuit that is located in the same row as the first color pixel circuit and adjacent to the first color pixel circuit in the +x direction. This is because the operation control transistor T5 in the first pixel region PXA1 is electrically connected via contact hole 56 to the connection electrode 174d located adjacent to the second pixel region PXA2 in the +x direction, and the connection electrode 174d is electrically connected via contact hole 82a' to the first driving voltage line PL1 passing through the second pixel region PXA2.

[0226] In the case where the first color pixel circuit in the pixel circuit of the first pixel PX1 is electrically connected to a corresponding line in the first driving voltage line PL1 through a corresponding second color pixel circuit that is arranged in the same row as the first color pixel circuit and is adjacent to the first color pixel circuit in the +x direction, this can mean that the first color pixel circuit is electrically connected to a corresponding line in the first driving voltage line PL1 through a second color pixel circuit that is arranged away from the third color pixel circuit relative to the first color pixel circuit.

[0227] The above description can be understood as follows: the operation control transistor T5 of the first color pixel circuit in the first pixel PX1 is electrically connected to the operation control transistor T5 of the second color pixel circuit, which is located in the same row as the first color pixel circuit and adjacent to the first color pixel circuit in the +x direction, and correspondingly, is electrically connected to the corresponding line in the first driving voltage line PL1. This is because the semiconductor layer of the operation control transistor T5 in the first pixel region PXA1 and the semiconductor layer of the operation control transistor T5 in the second pixel region PXA2 are integrally formed.

[0228] In the case where the operation control transistor T5 of the first color pixel circuit in the pixel circuit of the first pixel PX1 is electrically connected to the operation control transistor T5 of the second color pixel circuit which is located in the same row as the first color pixel circuit and adjacent to the first color pixel circuit in the +x direction, this can mean that the operation control transistor T5 of the first color pixel circuit is electrically connected to the corresponding line in the first drive voltage line PL1 through the operation control transistor T5 of the second color pixel circuit which is set away from the third color pixel circuit relative to the first color pixel circuit.

[0229] Because the driving transistor T1 is electrically connected to the driving voltage line via the operating control transistor T5, it can be understood that the driving transistors T1 of the first color pixel circuit and the second color pixel circuit are electrically connected to the first driving voltage line PL1, and the driving transistor T1 of the third color pixel circuit is electrically connected to the second driving voltage line PL2. However, for example, specifically, depending on the pixel circuit, there may not be an operating control transistor T5, it can be understood that the driving transistors T1 of the first and second color pixel circuits are electrically connected to the first driving voltage line PL1, and the driving transistor T1 of the third color pixel circuit is electrically connected to the second driving voltage line PL2.

[0230] It can be understood that the driving transistor T1 of the first color pixel circuit in the pixel circuit of the first pixel PX1 is electrically connected to the driving transistor T1 of the second color pixel circuit, which is located in the same row as the first color pixel circuit and adjacent to the first color pixel circuit in the +x direction, and correspondingly, is electrically connected to the corresponding line of the first driving voltage line PL1. In the case where the driving transistor T1 of the first color pixel circuit in the pixel circuit of the first pixel PX1 is electrically connected to the driving transistor T1 of the second color pixel circuit, which is located in the same row as the first color pixel circuit and adjacent to the first color pixel circuit in the +x direction, this can mean that the driving transistor T1 of the first color pixel circuit is electrically connected to the corresponding line of the first driving voltage line PL1 through the driving transistor T1 of the second color pixel circuit, which is positioned away from the third color pixel circuit relative to the first color pixel circuit.

[0231] For reference, a connection electrode 174c with an isolated shape may be disposed in the first pixel region PXA1. As described below, the connection electrode 174c may be connected to the second drive voltage line PL2 to allow a similar approximate shape to be present above the pixel region.

[0232] The connection electrode 175 can be electrically connected to the initialization voltage line VIL through contact holes 58 passing through the underlying insulating layer. The connection electrode 175 can also be electrically connected to the initialization transistor T4 through contact holes 59 passing through the underlying insulating layer. Accordingly, a constant initialization voltage can be applied to the semiconductor extension layer OACTE of the second semiconductor layer OACT.

[0233] The connection electrode 176 can electrically connect the first sub-semiconductor layer SACT1 to the second sub-semiconductor layer SACT2. For example, the connection electrode 176 can be electrically connected to the source region of the driving transistor T1, the drain region of the operation control transistor T5, and the drain region of the switching transistor T2 through a contact hole 61a passing through the underlying insulating layer. The connection electrode 176 can be electrically connected to the drain region of the bias transistor T7 through a contact hole 61b passing through the underlying insulating layer.

[0234] The connecting electrode 177 can be electrically connected to the drain region of the emitter control transistor T6 through the contact hole 62 passing through the insulating layer underneath.

[0235] The connecting electrode 178 can be electrically connected to the source region of the bias transistor T7 through a contact hole 65 passing through the underlying insulating layer. The connecting electrode 178 can be electrically connected to the bias voltage line VBL through a contact hole 66 passing through the underlying insulating layer.

[0236] The first source / drain layer SD1 may include metals, alloys, conductive metal oxides, or transparent conductive materials. For example, the first source / drain layer SD1 may include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The first source / drain layer SD1 may have a multilayer structure. For example, the first source / drain layer SD1 may have a two-layer Ti / Al structure or a three-layer Ti / Al / Ti structure.

[0237] First planarization insulation layer 107 (see...) Figure 24 The first planarization insulating layer 107 can be disposed on the second interlayer insulating layer 106 to cover the first source / drain layer SD1. The first planarization insulating layer 107 may include an organic insulating material. For example, the first planarization insulating layer 107 may include benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), polystyrene, polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or mixtures thereof. The first planarization insulating layer 107 may also include an inorganic insulating material, and for example, its upper surface may not be planar.

[0238] like Figure 21As shown, the second source / drain layer SD2 can be disposed on the first planarization insulating layer 107. The second source / drain layer SD2 may include a data line DL, a first driving voltage line PL1, a second driving voltage line PL2, a vertical connection line BRSV, and connection electrodes 181, 182, and 183. The data line DL, the first driving voltage line PL1, the second driving voltage line PL2, and the vertical connection line BRSV may have a shape extending in a second direction (e.g., the y-axis direction). The first driving voltage line PL1 and the second driving voltage line PL2 may be arranged alternately in a first direction (e.g., the x-axis direction).

[0239] The data line DL can be electrically connected to the connection electrode 173 included in the first source-drain layer SD1 through the contact hole 81 passing through the first planarized insulating layer 107. As described above, because the connection electrode 173 is connected to the source region of the switching transistor T2 through the contact hole 55 passing through the insulating layer below it, the data line DL can be electrically connected to the source region of the switching transistor T2.

[0240] In the second pixel region PXA2, which is the second region among the third pixel region PXA3, the second pixel region PXA2, the first pixel region PXA1, and the second pixel region PXA2 arranged sequentially in a first direction (e.g., the x-axis direction), a first driving voltage line PL1 extending in a second direction (e.g., the y-axis direction) can be electrically connected to a connection electrode 174a included in the first source / drain layer SD1 in the second pixel region PXA2 through a contact hole 82a passing through the first planarization insulating layer 107 below it. The first driving voltage line PL1 extending in the second direction (e.g., the y-axis direction) to pass through the second pixel region PXA2, which is the fourth region, can be electrically connected to a connection electrode 174d included in the first source / drain layer SD1 in the second pixel region PXA2 through a contact hole 82a' passing through the first planarization insulating layer 107 below it. As described above, the connecting electrode 174a can be connected to the electrode voltage line HL, which is included in the second gate layer GTL2 and extends in a first direction (e.g., the x-axis direction), through a contact hole 57a passing through the underlying insulating layer, and the connecting electrode 174d can be connected to the electrode voltage line HL, which is included in the second gate layer GTL2 and extends in a first direction (e.g., the x-axis direction), through a contact hole 57a passing through the underlying insulating layer. Accordingly, the first driving voltage line PL1 and the electrode voltage line HL, which are electrically connected to each other, can have (or fully have) a mesh structure. Accordingly, the voltage drop (IR drop) of the first driving voltage ELVDD1 in the display area DA can be prevented or reduced.

[0241] In the third pixel region PXA3, the second driving voltage line PL2 extending in the second direction (e.g., the y-axis direction) can be electrically connected to the connection electrode 174b included in the first source / drain layer SD1 in the third pixel region PXA3 through a contact hole 82b' passing through the first planarization insulating layer 107 below it. The second driving voltage line PL2 extending in the second direction (e.g., the y-axis direction) can even pass through the first pixel region PXA1. However, although the second driving voltage line PL2 can be connected to the connection electrode 174c in the first pixel region PXA1 through a contact hole 82b' passing through the first planarization insulating layer 107 below it, the connection electrode 174c can have an isolated shape and can be not electrically connected to any other element besides the second driving voltage line PL2.

[0242] Vertical connector BRSV can be used with reference Figure 7 or Figure 8 A portion of the described data transmission line DTL (e.g., one of the first vertical connection line DVL1, the second vertical connection line DVL2, the third vertical connection line DVL3, the first additional vertical connection line DVL1', the second additional vertical connection line DVL2', and the third additional vertical connection line DVL3') corresponds to this. Because Figure 21 The diagram shows the vertical connecting line BRSV electrically connected to the component below it via a contact hole, so in Figure 21 When the components shown are positioned near the corner of the display area DA, the vertical connection line BRSV is electrically connected via a contact hole to the horizontal connection line BRSH below it and to the data line DL of the pixel circuit disposed in another column. Accordingly, data signals can be transmitted to the pixel circuit disposed in the other column. In another embodiment, in Figure 21 When the components shown are positioned at the center of the display area DA, the vertical connection line BRSV can be a dummy line that is not subject to an electrical signal or a dummy line that is subject to a preset electrical signal when needed.

[0243] Each of the connection electrode 181 of the first pixel region PXA1, the connection electrode 182 of the second pixel region PXA2, and the connection electrode 183 of the third pixel region PXA3 can be electrically connected to a corresponding connection electrode 177 included in the second source / drain layer SD2 through a contact hole 83 passing through the underlying first planarization insulating layer 107. As described above, the connection electrode 177 can be electrically connected to the drain region of the emitter control transistor T6. Accordingly, each of the connection electrodes 181, 182, and 183 can be electrically connected to the drain region of the corresponding emitter control transistor T6.

[0244] The second source / drain layer SD2 can include metals, alloys, conductive metal oxides, or transparent conductive materials. For example, the second source / drain layer SD2 can include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The second source / drain layer SD2 can have a multilayer structure. For example, the second source / drain layer SD2 can have a two-layer Ti / Al structure or a three-layer Ti / Al / Ti structure.

[0245] Second planarization insulation layer 108 (see...) Figure 24 The second planarization insulating layer 108 can be disposed on the first planarization insulating layer 107 to cover the second source / drain layer SD2. The second planarization insulating layer 108 may include an organic insulating material. For example, the second planarization insulating layer 108 may include benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), polystyrene, polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or mixtures thereof.

[0246] like Figure 22 As shown, a third source / drain layer SD3 can be disposed on the second planarized insulating layer 108. The third source / drain layer SD3 may include a first main portion 190a separated from each other, a bridging portion connecting the first main portion 190a, a second main portion 190b separated from each other, a bridging portion connecting the second main portion 190b, and connecting electrodes 191, 192, and 193. The bridging portion connecting the first main portion 190a to the first main portion 190a may be integrally formed as a single unit, may have a shape extending in a first direction (e.g., the x-axis direction), and may be referred to as a second connecting line. The bridging portion connecting the second main portion 190b to the second main portion 190b may also be integrally formed as a single unit, may have a shape extending in a first direction (e.g., the x-axis direction), and may be referred to as a first connecting line. The second connecting line that connects the first main part 190a to the bridging portion of the first main part 190a and the first connecting line that connects the second main part 190b to the bridging portion of the second main part 190b can be arranged alternately in a second direction (e.g., the y-axis direction).

[0247] The bridging portion connecting the first main portion 190a is electrically connected to the first drive voltage line PL1 through a contact hole 85 passing through the second planarized insulating layer 108 beneath it. Accordingly, the first main portion 190a, the bridging portion connecting the first main portion 190a, the first drive voltage line PL1, and the electrode voltage line HL can all have a complete mesh structure. Accordingly, the voltage drop (IR drop) of the first drive voltage ELVDD1 in the display area DA can be prevented or reduced.

[0248] Similarly, the bridging portion connecting the second main portion 190b can be electrically connected to the second drive voltage line PL2 through contact holes 86 passing through the underlying second planarization insulating layer 108. Accordingly, the second main portion 190b, the bridging portion connecting the second main portion 190b, and the second drive voltage line PL2 can have (or fully have) a mesh structure. Accordingly, voltage drop (IR drop) of the second drive voltage ELVDD2 in the display area DA can be prevented or reduced.

[0249] A first main portion 190a arranged in a first direction (e.g., the x-axis direction) can be considered an extension portion. A first set of extension portions may include extension portions arranged in the first direction (e.g., the x-axis direction) in the order of a third extension portion corresponding to a third pixel electrode PE3, a second extension portion corresponding to a second pixel electrode PE2, a first extension portion corresponding to a first pixel electrode PE1, and a second extension portion corresponding to a second pixel electrode PE2. Such a first set of extension portions can be repeatedly arranged in the first direction (e.g., the x-axis direction) to form the first main portion 190a. Similarly, a second main portion 190b arranged in the first direction (e.g., the x-axis direction) can be considered an extension portion. A second set of extension portions may include extension portions arranged in the first direction (e.g., the x-axis direction) in the order of a first extension portion corresponding to a first pixel electrode PE1, a second extension portion corresponding to a second pixel electrode PE2, a third extension portion corresponding to a third pixel electrode PE3, and a second extension portion corresponding to a second pixel electrode PE2. Such a second set of extension portions can be repeatedly arranged in the first direction (e.g., the x-axis direction) to form the second main portion 190b.

[0250] Connection electrode 191 can be electrically connected to connection electrode 181 in the first pixel region PXA1 through contact hole 87 passing through the second planarization insulating layer 108, and therefore electrically connected to driving transistor T1 in the first pixel region PXA1. As described below, connection electrode 191 can be electrically connected to the first pixel electrode PE1. Connection electrode 192 can be electrically connected to connection electrode 182 in the second pixel region PXA2 through contact hole 88 passing through the second planarization insulating layer 108, and therefore electrically connected to driving transistor T1 in the second pixel region PXA2. As described below, connection electrode 192 can be electrically connected to the second pixel electrode PE2. Connection electrode 193 can be electrically connected to connection electrode 183 in the third pixel region PXA3 through contact hole 89 passing through the second planarization insulating layer 108, and therefore electrically connected to driving transistor T1 in the third pixel region PXA3. As described below, connection electrode 193 can be electrically connected to the third pixel electrode PE3.

[0251] The third source / drain layer SD3 can include metals, alloys, conductive metal oxides, or transparent conductive materials. For example, the third source / drain layer SD3 can include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The third source / drain layer SD3 can have a multilayer structure. For example, the third source / drain layer SD3 can have a two-layer Ti / Al structure or a three-layer Ti / Al / Ti structure.

[0252] Third planarization insulation layer 108' (see...) Figure 24 The third source / drain layer SD3 can be disposed on the second planarization insulating layer 108 to cover the third source / drain layer SD3. The third planarization insulating layer 108' may include an organic insulating material. For example, the third planarization insulating layer 108' may include benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), polystyrene, polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or mixtures thereof.

[0253] like Figure 23 As shown, the pixel electrode layer PXL can be disposed on the third planarization insulating layer 108'. The pixel electrode layer PXL can include multiple pixel electrodes. Figure 23The diagram shows a first pixel electrode PE1 for a first pixel PX1, a second pixel electrode PE2 for a second pixel PX2, and a third pixel electrode PE3 for a third pixel PX3. Each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may include a first region PEA1 (see [link to diagram]). Figure 9 ) and the second region PEA2 surrounding the first region PEA1 (see Figure 9 ).

[0254] The first pixel electrode PE1 can be electrically connected to the connection electrode 191 included in the third source / drain layer SD3 via a contact hole 91 passing through the third planarization insulating layer 108'. Correspondingly, the first pixel electrode PE1 can be electrically connected to the driving transistor T1, which is subject to the first driving voltage ELVDD1, via the emitter control transistor T6 in the first pixel region PXA1. The contact hole 91 can be configured to connect to the second region PEA2 of the first pixel electrode PE1 (see...). Figure 9 Corresponding to ).

[0255] The second pixel electrode PE2 can be electrically connected to the connection electrode 192 included in the third source / drain layer SD3 via a contact hole 92 passing through the third planarization insulating layer 108'. Correspondingly, the second pixel electrode PE2 can be electrically connected to the driving transistor T1, which is subject to the first driving voltage ELVDD1, via the emitter control transistor T6 in the second pixel region PXA2. The contact hole 92 can be configured to connect to the second region PEA2 of the second pixel electrode PE2 (see...). Figure 9 Corresponding to ).

[0256] The third pixel electrode PE3 can be electrically connected to the connection electrode 193 included in the third source / drain layer SD3 via a contact hole 93 passing through the third planarization insulating layer 108'. Correspondingly, the third pixel electrode PE3 can be electrically connected to the driving transistor T1, which is subject to the second driving voltage ELVDD2, via the emitter control transistor T6 in the third pixel region PXA3. The contact hole 93 can be configured to connect to the second region PEA2 of the third pixel electrode PE3 (see...). Figure 9 Corresponding to ).

[0257] The pixel electrode layer PXL can be a (semi-)transparent conductive layer or a reflective conductive layer. For example, the pixel electrode layer PXL may include a reflective layer and a transparent or semi-transparent electrode layer on the reflective layer, wherein the reflective layer includes Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or compounds thereof. The transparent or semi-transparent electrode layer may include indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO). xThe pixel electrode layer PXL can be at least one of ZnO or ZnO2, indium oxide (In2O3), indium gallium oxide (IGO), and zinc aluminum oxide (AZO). For example, the pixel electrode layer PXL can have a three-layer structure of ITO / Ag / ITO.

[0258] For reference, the first pixel electrode PE1 and the third pixel electrode PE3 may be arranged alternately in a second direction (e.g., the y-axis direction). The second pixel electrode PE2 is arranged in the second direction (e.g., the y-axis direction). Accordingly, the first pixel electrode PE1 and the third pixel electrode PE3 are arranged alternately along the second driving voltage line PL2, and the second pixel electrode PE2 is arranged along the first driving voltage line PL1. Therefore, this can be understood as the first color pixel circuit and the third color pixel circuit being arranged alternately along the second driving voltage line PL2, and the second color pixel circuit being arranged along the first driving voltage line PL1.

[0259] A pixel defining layer 109 may be disposed on a third planarization insulating layer 108' to cover the edges of each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. The pixel defining layer 109 may define pixels by including openings corresponding to the emission regions of each pixel. For reference, in Figure 24 In the cross-sectional view, the opening of the pixel defining layer 109 is not shown. An emission layer can be disposed within the opening of the pixel defining layer 109, and a common electrode CAT can be disposed on the emission layer. The first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, the emission layer, and the common electrode CAT can constitute an organic light-emitting diode (OLED). The common electrode CAT can be integrally formed into a single unit, passing through multiple OLEDs, to correspond to multiple pixel electrodes. For reference, the layer structure between the first pixel electrode PE1 or the second pixel electrode PE2 and the common electrode CAT, and the layer structure between the third pixel electrode PE3 and the common electrode CAT, can be consistent with the reference... Figure 10 and Figure 11 The described layer structures are the same. For convenience, Figure 24 The layer between the pixel electrode and the common electrode CAT is not shown.

[0260] The common electrode CAT can be a transparent electrode or a reflective electrode. For example, the common electrode CAT can be a transparent or translucent electrode and can include a thin metal film containing Li, Ca, Al, Ag, Mg or their compounds (e.g., LiF) and having a small work function. The common electrode CAT can further include a transparent conductive oxide (TCO) layer such as ITO, indium zinc oxide (IZO), ZnO, ZnO2, or In2O3 disposed on the thin metal film. The common electrode CAT can be integrally formed as a single unit on the entire surface of the display area DA to cover the display area DA.

[0261] When needed, an encapsulation layer can be disposed on the common electrode CAT. The encapsulation layer may include a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer between the first and second inorganic encapsulation layers.

[0262] Figures 25 to 29 This is a schematic arrangement diagram of elements such as transistors and capacitors in each layer of a display panel 10 and an electronic device 1 including the display panel 10, according to an embodiment. The display panel 10 according to the embodiment may include a buffer layer disposed on a substrate 100 and... Figure 25 The first semiconductor layer SACT shown in the figure is disposed thereon and Figure 16 The first gate layer GTL1 shown in the figure is disposed thereon and Figure 26 The second gate layer GTL2 shown in the figure is disposed thereon and Figure 18 The second semiconductor layer OACT shown in the figure is disposed thereon and Figure 27 The third gate layer GTL3 shown in the figure is disposed thereon and Figure 28 The first source / drain layer SD1 shown in the figure is disposed thereon and Figure 29 The second source / drain layer SD2 shown in the figure, and the layer disposed thereon and Figure 23 The pixel electrode layer PXL is shown in the figure. As described above, an insulating layer or planarization layer, etc., may be disposed therebetween.

[0263] Figure 25 The first semiconductor layer SACT shown can be disposed on the buffer layer 101. The first semiconductor layer SACT can include silicon semiconductor. As described in the embodiments above, the first semiconductor layer SACT can include a first sub-semiconductor layer SACT1 and a second sub-semiconductor layer SACT2 separated from the first sub-semiconductor layer SACT1. In the display panel 10 and the electronic device 1 including the display panel 10 according to the embodiments, the second sub-semiconductor layer SACT2 in the third pixel region PXA3 and the second sub-semiconductor layer SACT2 in the second pixel region PXA2 disposed adjacent to the third pixel region PXA3 in the +x direction can be integrally formed as a single unit. Similarly, the first sub-semiconductor layer SACT1 in the first pixel region PXA1 and the second sub-semiconductor layer SACT2 in the second pixel region PXA2 disposed adjacent to the first pixel region PXA1 in the +x direction can be integrally formed as a single unit. Reference Figure 15 The above description applies directly to Figure 25 The first semiconductor layer SACT is shown in the figure.

[0264] As described above, the first gate insulating layer 102 may cover the first semiconductor layer SACT. (As described above and in...) Figure 16The first gate layer GTL1 shown can be disposed on the first gate insulating layer 102, and the second gate insulating layer 103 can cover the first gate layer GTL1.

[0265] like Figure 26 As shown, the second gate layer GTL2 can be disposed on the second gate insulating layer 103. The second gate layer GTL2 of the display panel 10 and the electronic device 1 including the display panel 10 according to the embodiment are compared with the reference... Figure 17 The difference between the described second gate layers GTL2 is that the second gate layer GTL2 further includes a second electrode initialization voltage line VL2 extending in a first direction (e.g., the x-axis direction) between the lower gate line GIL1 and the electrode voltage line HL, which also serves as the upper electrode of the storage capacitor Cst.

[0266] The first interlayer insulating layer 104 can be disposed on the second gate layer GTL2, and Figure 18 The second semiconductor layer OACT shown can be disposed on the first interlayer insulating layer 104. The third gate insulating layer 105 can be disposed on the second semiconductor layer OACT.

[0267] like Figure 27 As shown, the third gate layer GTL3 can be disposed on the third gate insulating layer 105. The third gate layer GTL3 of the display panel 10 and the electronic device 1 including the display panel 10 according to the embodiment is compared with the reference... Figure 19 The difference between the described third gate layers GTL3 may be that the third gate layer GTL3 includes connection electrodes 161 and 163 but does not include the second electrode initialization voltage line VL2, and some elements included in the third gate layer GTL3 are electrically connected to the elements below it through contact holes 45, 47 and 48.

[0268] A connection electrode 161 can be disposed in the third pixel region PXA3. The connection electrode 161 can be electrically connected to the source region of the electrode initialization transistor T8 in the third pixel region PXA3 via a contact hole 45 formed in the insulating layer thereunder, and simultaneously electrically connected to the second electrode initialization voltage line VL2 via a contact hole 46 formed in the third gate insulating layer 105. Accordingly, a second electrode initialization voltage Vaint2 from the second electrode initialization voltage line VL2 can be applied to the electrode initialization transistor T8 in the third pixel region PXA3.

[0269] The connection electrode 163 can be electrically connected to the drive gate electrode 131a included in the first gate layer GTL1 through a contact hole 48 formed in the insulating layer thereunder. The connection electrode 163 is electrically connected to the connection electrode 171 included in the first source / drain layer SD1. This will be described below.

[0270] At the protruding portion of the bias voltage line VBL extending in the first direction (e.g., the x-axis direction) protruding in the second direction (e.g., the y-axis direction), a contact hole 47 formed in the insulating layer beneath it can be electrically connected to the source region of the bias transistor T7. Accordingly, a bias voltage VOBS from the bias voltage line VBL can be applied to the bias transistor T7. For reference, since the second sub-semiconductor layer SACT2 in the third pixel region PXA3 and the second sub-semiconductor layer SACT2 in the second pixel region PXA2 adjacent to the third pixel region PXA3 in the +x direction are integrally formed into a single unit, the contact hole 47 in the third pixel region PXA3 and the second pixel region PXA2 adjacent to the third pixel region PXA3 in the +x direction can be configured to correspond to the portion between the second sub-semiconductor layer SACT2 in the third pixel region PXA3 and the second sub-semiconductor layer SACT2 in the second pixel region PXA2. Similarly, since the second sub-semiconductor layer SACT2 in the first pixel region PXA1 and the second sub-semiconductor layer SACT2 in the second pixel region PXA2 adjacent to the first pixel region PXA1 in the +x direction are integrally formed into a single unit, the contact hole 47 in the first pixel region PXA1 and the second pixel region PXA2 adjacent to the first pixel region PXA1 in the +x direction can be configured to correspond to the portion between the second sub-semiconductor layer SACT2 in the first pixel region PXA1 and the second sub-semiconductor layer SACT2 in the second pixel region PXA2.

[0271] As referenced above Figure 26 As described, since the second gate layer GTL2 includes the second electrode initialization voltage line VL2, the third gate layer GTL3 may not include the second electrode initialization voltage line VL2.

[0272] As described above, the second interlayer insulating layer 106 can cover the third gate layer GTL3.

[0273] Figure 28 The first source / drain layer SD1 shown can be disposed on the second interlayer insulating layer 106. The first source / drain layer SD1 of the display panel 10 and the electronic device 1 including the display panel 10 according to the embodiment are compared with the reference layer. Figure 20 The difference between the described first source / drain layers SD1 is that the first source / drain layer SD1 does not include the connecting electrodes 174a, 174b, 174c, 174d, 178, and 179, but further includes a first connecting line PCL1 and a second connecting line PCL2, and the shape of some other connecting electrodes is modified. For other matters, see [reference]. Figure 20 The above description can also be applied to Figure 28 The first source / drain layer SD1 is shown in the figure.

[0274] One end of the connection electrode 171 can be electrically connected to the second semiconductor layer OACT via contact hole 51. For example, one end of the connection electrode 171 can be electrically connected to the compensation transistor T3 and the initialization transistor T4 via contact hole 51 through the underlying insulating layer. The other end of the connection electrode 171 can be electrically connected to the connection electrode 163 via contact hole 52 through the underlying second interlayer insulating layer 106. As described above, the connection electrode 163 can be electrically connected to the drive gate electrode 131a included in the first gate layer GTL1 via contact hole 48 formed in the underlying insulating layer. Accordingly, the compensation transistor T3 and the initialization transistor T4 can be electrically connected to the drive gate electrode 131a via the connection electrode 171 and the connection electrode 163.

[0275] The first connection line PCL1 may extend in a first direction (e.g., the x-axis direction). The first connection line PCL1 may be electrically connected to the electrode voltage line HL, which also acts as the upper electrode of the storage capacitor Cst, through a contact hole 57 formed in the insulating layer thereunder.

[0276] In the second pixel region PXA2, which is the second region among the third pixel region PXA3, the second pixel region PXA2, the first pixel region PXA1, and the second pixel region PXA2 arranged sequentially in a first direction (e.g., the x-axis direction), the first connecting line PCL1 may include a protruding portion protruding in a second direction (e.g., the y-axis direction), and at the end of the protruding portion, it is electrically connected to the source region of the operation control transistor T5 in the second pixel region PXA2 through a contact hole 56a passing through the insulating layer underneath. In the first pixel region PXA1, which is the fourth region, and the second pixel region PXA2, which are the third pixel region PXA3, the second pixel region PXA2, the first pixel region PXA1, and the second pixel region PXA2 arranged sequentially in a first direction (e.g., the x-axis direction), the first connecting line PCL1 may have a protruding portion extending in the boundary between the first pixel region PXA1 and the second pixel region PXA2, and at the end of the protruding portion, it is connected to the first sub-semiconductor layer SACT1, which is integrally formed as a single unit in the first pixel region PXA1 and the second pixel region PXA2, through a contact hole 56 formed in the insulating layer thereunder, and thus electrically connected to the source region of the operation control transistor T5 in the first pixel region PXA1 and the source region of the operation control transistor T5 in the second pixel region PXA2.

[0277] As described below, the first connection line PCL1 can be electrically connected to the first drive voltage line PL1 thereon. Accordingly, the first drive voltage ELVDD1 of the first drive voltage line PL1 can be transmitted to the operation control transistor T5 in the first pixel PX1 and the operation control transistor T5 in the second pixel PX2, and the electrode voltage line HL can also serve as the upper electrode of the storage capacitor Cst of all pixels.

[0278] The second connection line PCL2 may also extend in the first direction (e.g., the x-axis direction). The second connection line PCL2 may have a protrusion in the third pixel region PXA3 that protrudes in the second direction (e.g., the y-axis direction), and at this protrusion, it is electrically connected to the source region of the operation control transistor T5 in the third pixel region PXA3 through a contact hole 56b formed in the insulating layer thereunder.

[0279] As described below, the second connection line PCL2 can be electrically connected to the second driving voltage line PL2 thereon. Accordingly, the second driving voltage ELVDD2 of the second driving voltage line PL2 can be transmitted to the operation control transistor T5 in the third pixel PX3, and accordingly, applied to the third pixel electrode PE3 of the third light-emitting element OLED3 by the driving transistor T1, etc.

[0280] As described above, the first planarization insulating layer 107 can cover the first source / drain layer SD1.

[0281] like Figure 29 As shown, the second source / drain layer SD2 can be disposed on the first planarization insulating layer 107. The second source / drain layer SD2 of the display panel 10 and the electronic device 1 including the display panel 10 according to the embodiment are compared with a reference layer. Figure 21 The differences between the second source and drain layers SD2 described may be the positions of contact holes 82a, 82a', 82b, and 82b'.

[0282] In the second pixel region PXA2, which is the second region among the third pixel region PXA3, the second pixel region PXA2, the first pixel region PXA1, and the second pixel region PXA2 arranged sequentially in a first direction (e.g., the x-axis direction), a first driving voltage line PL1 extending in a second direction (e.g., the y-axis direction) can be electrically connected to a first connecting line PCL1 in the second pixel region PXA2 through a contact hole 82a' passing through the first planarization insulating layer 107 beneath it. Similarly, the first driving voltage line PL1 extending in the second direction (e.g., the y-axis direction) to pass through the second pixel region PXA2, which is the fourth region, can be electrically connected to the first connecting line PCL1 in the second pixel region PXA2 through a contact hole 82a' passing through the first planarization insulating layer 107 beneath it.

[0283] As described above, the first connecting line PCL1 can be electrically connected to the electrode voltage line HL, which also acts as the upper electrode of the storage capacitor Cst, via a contact hole 57 formed in the insulating layer beneath it. Accordingly, the electrode voltage line HL and the first connecting line PCL1 extending in the first direction (e.g., the x-axis direction), and the first driving voltage line PL1 extending in the second direction (e.g., the y-axis direction), can be electrically connected to each other to fully form a mesh structure. Accordingly, the voltage drop (IR drop) of the first driving voltage ELVDD1 in the display area DA can be prevented or reduced.

[0284] In the third pixel region PXA3, the second driving voltage line PL2 extending in the second direction (e.g., the y-axis direction) can be electrically connected to the second connecting line PCL2 in the third pixel region PXA3 through a contact hole 82b passing through the first planarization insulating layer 107 below it. In the first pixel region PXA1, the second driving voltage line PL2 extending in the second direction (e.g., the y-axis direction) can be electrically connected to the second connecting line PCL2 in the third pixel region PXA3 through a contact hole 82b' passing through the first planarization insulating layer 107 below it. Accordingly, the second connecting line PCL2 extending in the first direction (e.g., the x-axis direction) and the second driving voltage line PL2 extending in the second direction (e.g., the y-axis direction) can be electrically connected to each other to fully form a mesh structure. Accordingly, the voltage drop (IR drop) of the second driving voltage ELVDD2 in the display area DA can be prevented or reduced.

[0285] The second planarization insulation layer 108 can cover Figure 29 The second source / drain layer SD2 is shown in the figure. Figure 23 The pixel electrode layer PXL shown can be disposed on the second planarization insulating layer 108. For example, the display panel 10 and the electronic device 1 including the display panel 10 according to the embodiment may not include the third source / drain layer SD3. Accordingly, a display panel 10 that displays high-quality images and even an electronic device 1 including the display panel 10 with a simple structure can be realized.

[0286] For reference, with Figure 23 The positions of contact holes 91 and 93 can be changed to correspond to the connection electrode 181 included in the second source / drain layer SD2. Similarly, the positions of contact holes 92 and 93 can be changed to correspond to the connection electrode 182 included in the second source / drain layer SD2.

[0287] The first pixel electrode PE1 can be electrically connected to the connection electrode 181 included in the second source / drain layer SD2 through the contact hole 91 passing through the second planarization insulating layer 108. Accordingly, the first pixel electrode PE1 can be electrically connected to the driving transistor T1, which is subject to the first driving voltage ELVDD1, through the emitter control transistor T6 in the first pixel region PXA1.

[0288] The second pixel electrode PE2 can be electrically connected to the connection electrode 182 included in the second source / drain layer SD2 through the contact hole 92 passing through the second planarization insulating layer 108. Accordingly, the second pixel electrode PE2 can be electrically connected to the driving transistor T1, which is subject to the first driving voltage ELVDD1, through the emitter control transistor T6 in the second pixel region PXA2.

[0289] The third pixel electrode PE3 can be electrically connected to the connection electrode 183 included in the second source / drain layer SD2 through the contact hole 93 passing through the second planarization insulating layer 108. Accordingly, the third pixel electrode PE3 can be electrically connected to the driving transistor T1, which is subject to the second driving voltage ELVDD2, through the emitter control transistor T6 in the third pixel region PXA3.

[0290] The second source / drain layer SD2 can be modified in other ways. For example, as shown in the schematic arrangement diagram of the display panel 10 and the electronic device 1 including the display panel 10, the second source / drain layer SD2 is shown. Figure 30 As shown, in a structure in which a group of third pixel region PXA3, second pixel region PXA2, first pixel region PXA1 and second pixel region PXA2 arranged sequentially in a first direction (e.g., the x-axis direction) is repeatedly placed, a second driving voltage line PL2 may be disposed on the third pixel region PXA3 and the second pixel region PXA2 disposed adjacent to it in the -x direction, and a first driving voltage line PL1 may be disposed on the first pixel region PXA1 and the second pixel region PXA2 disposed adjacent to it in the -x direction.

[0291] For example, the first driving voltage line PL1 can be electrically connected to the first connecting line PCL1 below it through a contact hole 82a in the second pixel region PXA2, which is adjacent to the first pixel region PXA1 in the -x direction, and the second driving voltage line PL2 can be electrically connected to the second connecting line PCL2 below it through a contact hole 82b in the third pixel region PXA3. The first driving voltage line PL1 may include an opening in its middle portion, and the connecting electrode 181 in the first pixel region PXA1 and the connecting electrode 182 in the second pixel region PXA2, which is adjacent to the first pixel region PXA1 in the -x direction, can be disposed in the opening. Similarly, the second driving voltage line PL2 may include an opening in its middle portion, and the connecting electrode 183 in the third pixel region PXA3 and the connecting electrode 182 in the second pixel region PXA2, which is adjacent to the third pixel region PXA3 in the -x direction, can be disposed in the opening.

[0292] So far, although the display panel 10 and the electronic device 1 including the display panel 10 have been described in the case where a second semiconductor layer OACT, which is an oxide semiconductor layer, has been included, this disclosure is not limited thereto. Hereinafter, the case where the display panel 10 and the electronic device 1 including the display panel 10 only include a first semiconductor layer SACT will be described. For example, a first light-emitting element OLED1 capable of emitting red light and a second light-emitting element OLED2 capable of emitting green light may have… Figure 10 The layered structure shown in the diagram, and the third light-emitting element OLED3 that can emit blue light, can have Figure 11 The layered structure shown in the figure.

[0293] Figure 31 This is a schematic diagram of an equivalent circuit PC that can be electrically connected to the first light-emitting element OLED1 or the second light-emitting element OLED2, and Figure 32 This is a schematic diagram of the equivalent circuit PC that can be electrically connected to the third light-emitting element OLED3. First, the description is shown as follows: Figure 31 The equivalent circuit diagram of the pixel circuit PC is shown in the figure, and it is described as having the same characteristics as... Figure 31 The key points are different from the key points, and are expressed as Figure 32 The equivalent circuit diagram shown is a portion thereof.

[0294] like Figure 31As shown, the pixel circuit PC may include multiple thin-film transistors T1, T2, T3, T4, T5, T6, and T7, and a storage capacitor Cst. The multiple thin-film transistors T1, T2, T3, T4, T5, T6, and T7, and the storage capacitor Cst may be connected to signal lines GWL, GIL, EL, and DL, the initialization voltage line VIL, and the first drive voltage line PL1. At least one of these lines (e.g., the first drive voltage line PL1) may be shared by pixels arranged adjacent to each other.

[0295] Multiple thin-film transistors T1, T2, T3, T4, T5, T6, and T7 may include a driving transistor T1, a switching transistor T2, a compensation transistor T3, an initialization transistor T4, an operation control transistor T5, an emitter control transistor T6, and an electrode initialization transistor T7. The compensation transistor T3 may include a first compensation transistor T3-1 and a second compensation transistor T3-2. For example, the first compensation transistor T3-1 and the second compensation transistor T3-2 may be connected in series with each other. The initialization transistor T4 may include a first initialization transistor T4-1 and a second initialization transistor T4-2. For example, the first initialization transistor T4-1 and the second initialization transistor T4-2 may be connected in series with each other.

[0296] The first light-emitting element OLED1 and / or the second light-emitting element OLED2 may include a pixel electrode and a common electrode. The pixel electrode can be connected to the driving transistor T1 via an emission control transistor T6, and the common electrode can receive a common voltage ELVSS. The first light-emitting element OLED1 and / or the second light-emitting element OLED2 can generate light with a brightness corresponding to the driving current.

[0297] The multiple thin-film transistors T1, T2, T3, T4, T5, T6, and T7 can be p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). When needed, the multiple thin-film transistors T1, T2, T3, T4, T5, T6, and T7 can be n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). In the following description, for convenience, the multiple thin-film transistors T1, T2, T3, T4, T5, T6, and T7 are described as p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) including amorphous silicon or polycrystalline silicon.

[0298] The signal lines may include a first scan line GWL, a third scan line GIL, a fifth scan line GIL(n+1), an emit control line EL, and a data line DL. The first scan line GWL transmits the first scan signal GW, the third scan line GIL transmits the initialization scan signal GI to the initialization transistor T4, the fifth scan line GIL(n+1) transmits the electrode initialization scan signal GI(n+1) to the electrode initialization transistor T7, the emit control line EL transmits the emit control signal EM to the operation control transistor T5 and the emit control transistor T6, and the data line DL crosses the first scan line GWL and transmits the data signal DATA.

[0299] The first driving voltage line PL1 can transmit the first driving voltage ELVDD1 to the driving transistor T1, and the initialization voltage line VIL can transmit the initialization voltage Vint to initialize the driving transistor T1. The initialization voltage Vint of the initialization voltage line VIL can be used for the purpose of initializing the pixel electrodes of the first light-emitting element OLED1 and / or the second light-emitting element OLED2.

[0300] The driving gate electrode of driving transistor T1 can be connected to storage capacitor Cst via second node N2. One of the source and drain regions of driving transistor T1 can be connected to the first driving voltage line PL1 via first node N1 through operation control transistor T5. The other of the source and drain regions of driving transistor T1 can be electrically connected to the pixel electrode of the first light-emitting element OLED1 and / or the second light-emitting element OLED2 via third node N3 through emitter control transistor T6. Driving transistor T1 can receive data signal DATA and supply driving current to the first light-emitting element OLED1 and / or the second light-emitting element OLED2 according to the switching operation of switching transistor T2.

[0301] The gate electrode of the switching transistor T2 can be connected to the first scan line GWL, which transmits the first scan signal GW. One of the source and drain regions of the switching transistor T2 can be connected to the data line DL, and the other of the source and drain regions of the switching transistor T2 can be connected to the driving transistor T1 through the first node N1 and to the first driving voltage line PL1 through the operation control transistor T5. The switching transistor T2 can transmit the data signal DATA from the data line DL to the first node N1 in response to the voltage applied to the first scan line GWL. For example, the switching transistor T2 can perform a switching operation in which it is turned on according to the first scan signal GW transmitted through the first scan line GWL and transmits the data signal DATA to the driving transistor T1 through the first node N1, with the data signal DATA transmitted through the data line DL.

[0302] The compensation gate electrode of compensation transistor T3 can also be connected to the first scan line GWL. One of the source and drain regions of compensation transistor T3 can be connected to the pixel electrode of the first light-emitting element OLED1 and / or the second light-emitting element OLED2 via the emitter control transistor T6 through the third node N3. The other of the source and drain regions of compensation transistor T3 can be connected to the first capacitor electrode of storage capacitor Cst and the drive gate electrode of drive transistor T1 via the second node N2. Compensation transistor T3 can connect the diode of drive transistor T1 by being turned on according to the first scan signal GW received via the first scan line GWL.

[0303] The initialization gate electrode of the initialization transistor T4 can be connected to the third scan line GIL. One of the source and drain regions of the initialization transistor T4 can be connected to the initialization voltage line VIL. The other of the source and drain regions of the initialization transistor T4 can be connected to the first capacitor electrode of the storage capacitor Cst and the driving gate electrode of the driving transistor T1 through the second node N2. The initialization transistor T4 can apply an initialization voltage Vint from the initialization voltage line VIL to the second node N2 based on the voltage applied to the third scan line GIL, which is a previous scan line. For example, the initialization transistor T4 can be turned on based on the initialization scan signal GI received through the third scan line GIL, and can perform an initialization operation to initialize the voltage of the driving gate electrode of the driving transistor T1 by transmitting the initialization voltage Vint to the driving gate electrode of the driving transistor T1.

[0304] The operation control gate electrode of the operation control transistor T5 can be connected to the emitter control line EL. One of the source and drain regions of the operation control transistor T5 can be connected to the first drive voltage line PL1, and the other of the source and drain regions of the operation control transistor T5 can be connected to the drive transistor T1 and the switch transistor T2 through the first node N1.

[0305] The emission control gate electrode of the emission control transistor T6 can be connected to the emission control line EL. One of the source and drain regions of the emission control transistor T6 can be connected to the driving transistor T1 and the compensation transistor T3 through the third node N3. The other of the source and drain regions of the emission control transistor T6 can be electrically connected to the pixel electrode of the first light-emitting element OLED1 and / or the second light-emitting element OLED2.

[0306] The operation control transistor T5 and the emission control transistor T6 can be simultaneously turned on according to the emission control signal EM transmitted through the emission control line EL, so as to allow the electrical signal from the first drive voltage line PL1 to be transmitted to the first light-emitting element OLED1 and / or the second light-emitting element OLED2, thereby allowing the drive current to flow through the first light-emitting element OLED1 and / or the second light-emitting element OLED2.

[0307] The electrode initialization gate electrode of the electrode initialization transistor T7 can be connected to the fifth scan line GIL(n+1) which is the next scan line. One of the source and drain regions of the electrode initialization transistor T7 can be connected to the first light-emitting element OLED1 and / or the second light-emitting element OLED2, and the other of the source and drain regions of the electrode initialization transistor T7 can be connected to the initialization voltage line VIL to receive the initialization voltage Vint. The electrode initialization transistor T7 can be turned on according to the electrode initialization scan signal GI(n+1) transmitted through the fifth scan line GIL(n+1), and can initialize the pixel electrodes of the first light-emitting element OLED1 and / or the second light-emitting element OLED2.

[0308] The storage capacitor Cst may include a first capacitor electrode and a second capacitor electrode. The first capacitor electrode of the storage capacitor Cst can be connected to the driving gate electrode of the driving transistor T1 through a second node N2, and the second capacitor electrode of the storage capacitor Cst can be connected to the first driving voltage line PL1. The storage capacitor Cst can store a charge corresponding to the difference between the voltage of the driving gate electrode of the driving transistor T1 and the first driving voltage ELVDD1.

[0309] Because of the specific operation and reference of each pixel according to the embodiment Figure 12 The operations described are similar, so their descriptions are omitted.

[0310] Reference above Figure 31 The pixel circuit described is different; except for the first driving voltage line PL1, it can be electrically connected to the third light-emitting element OLED3 included in the third pixel PX3. Figure 32 The pixel circuit PC shown may also include a second drive voltage line PL2.

[0311] Even when the pixel circuit is electrically connected to the third light-emitting element OLED3, the first capacitor electrode of the storage capacitor Cst is connected to the driving gate electrode of the driving transistor T1 via the second node N2, and the second capacitor electrode of the storage capacitor Cst is connected to the first driving voltage line PL1. Accordingly, when the same data signal as the data signal applied to the pixel circuit electrically connected to the first light-emitting element OLED1 is applied to the pixel circuit electrically connected to the third light-emitting element OLED3, a potential identical to the potential between the source electrode and gate electrode of the driving transistor T1 electrically connected to the pixel circuit of the first light-emitting element OLED1 can be applied between the source electrode and gate electrode of the driving transistor T1 electrically connected to the pixel circuit of the third light-emitting element OLED3. Accordingly, when the same brightness data is applied, the driving transistor T1 of the pixel circuit electrically connected to the first light-emitting element OLED1 and the driving transistor T1 of the pixel circuit electrically connected to the third light-emitting element OLED3 can operate in the same manner.

[0312] However, in the pixel circuit electrically connected to the third light-emitting element OLED3, the driving transistor T1 can receive the second driving voltage ELVDD2 via the second driving voltage line PL2 instead of the first driving voltage line PL1. For example, the driving gate electrode of the driving transistor T1 can be connected to the storage capacitor Cst via the second node N2, one of the source and drain regions of the driving transistor T1 can be connected to the second driving voltage line PL2 via the first node N1 through the operation control transistor T5, and the other of the source and drain regions of the driving transistor T1 can be electrically connected to the pixel electrode of the third light-emitting element OLED3 via the third node N3 through the emitter control transistor T6. The driving transistor T1 can receive the data signal DATA and supply driving current to the third light-emitting element OLED3 according to the switching operation of the switching transistor T2.

[0313] As described above, unlike the first light-emitting element OLED1 and / or the second light-emitting element OLED2, the third light-emitting element OLED3 includes an electron generation layer 341, a hole generation layer 343, and multiple emission layers 333 and 333', etc. Therefore, the potential between the third pixel electrode PE3 and the common electrode CAT of the third light-emitting element OLED3 needs to be adjusted to be different from the potential between the first pixel electrode PE1 and the common electrode CAT of the first light-emitting element OLED1 or the potential between the second pixel electrode PE2 and the common electrode CAT of the second light-emitting element OLED2. In the display panel 10 and the electronic device 1 including the display panel 10 according to the embodiment, such as Figure 31 and 32As shown, the potential between the first pixel electrode PE1 of the first light-emitting element OLED1 and the common electrode CAT, or the potential between the second pixel electrode PE2 of the second light-emitting element OLED2 and the common electrode CAT, can be maintained at approximately the difference between the first driving voltage ELVDD1 and the common voltage ELVSS. Simultaneously, the potential between the third pixel electrode PE3 of the third light-emitting element OLED3 and the common electrode CAT can be maintained at approximately the difference between the second driving voltage ELVDD2 and the common voltage ELVSS. Accordingly, a display panel 10 for displaying high-quality images and an electronic device 1 including the display panel 10 can be realized.

[0314] Figure 33 Is included in Figure 31 and Figure 32 A schematic arrangement of the positions of transistors and capacitors in the pixels of the display panel 10 of the pixel circuit and the electronic device 1 including the display panel 10. Figures 34 to 37 yes Figure 33 The diagram shows a schematic arrangement of elements such as transistors and capacitors in each layer of the display panel 10. Figure 38 It has Figure 33 A schematic diagram of the pixel electrodes of the display panel 10.

[0315] The display panel 10 and the electronic device 1 including the display panel 10 may have a structure in which a group of third pixel regions PXA3, second pixel regions PXA2, first pixel regions PXA1, and second pixel regions PXA2 arranged sequentially in a first direction (e.g., the x-axis direction) are repeatedly arranged in the first direction (e.g., the x-axis direction). For reference, the region adjacent to each of the +y and -y directions of the third pixel region PXA3 may be the first pixel region PXA1, the region adjacent to each of the +y and -y directions of the first pixel region PXA1 may be the third pixel region PXA3, and the region adjacent to each of the +y and -y directions of the second pixel region PXA2 may be the second pixel region PXA2.

[0316] The pixel circuit of the first pixel PX1 can be disposed in the first pixel region PXA1, the pixel circuit of the second pixel PX2 can be disposed in the second pixel region PXA2, and the pixel circuit of the third pixel PX3 can be disposed in the third pixel region PXA3. The third pixel region PXA3 and the second pixel region PXA2, which are disposed adjacent to each other, can be positioned relative to each other as follows: Figure 33 The imaginary boundary lines IBL shown in the figure have the same shape. For example... Figure 33As shown in the figure, the first pixel region PXA1 and the second pixel region PXA2 can have similar shapes relative to the imaginary boundary line IBL. In contrast, pixel regions can have symmetrical shapes. However, various modifications are possible.

[0317] In the following text, for ease of description, although some conductive patterns are described based on the pixel circuitry set in the third pixel region PXA3, these conductive patterns can also be set in the first pixel region PXA1 and / or the second pixel region PXA2 in a similar manner.

[0318] A buffer layer may be disposed on the substrate 100, wherein the buffer layer 110 may comprise silicon oxide, silicon nitride, or silicon oxynitride. The buffer layer can prevent metal atoms or impurities from the substrate 100 from diffusing to the first semiconductor layer SACT disposed thereon. The buffer layer can allow the first semiconductor layer SACT to be uniformly crystallized by adjusting the rate of heat application during the crystallization process for forming the first semiconductor layer SACT.

[0319] Figure 34 The first semiconductor layer SACT shown can be disposed on a buffer layer. The first semiconductor layer SACT can include silicon semiconductor. For example, the first semiconductor layer SACT can include amorphous silicon or polycrystalline silicon. For example, the first semiconductor layer SACT can include polycrystalline silicon crystallized at low temperature. When needed, ions can be implanted into at least a portion of the first semiconductor layer SACT. When needed, a lower metal layer corresponding to the shape of the first semiconductor layer SACT can be disposed below the first semiconductor layer SACT to protect the first semiconductor layer SACT. For example, an insulating layer can be disposed between the lower metal layer and the first semiconductor layer SACT.

[0320] The first semiconductor layer SACT can have a shape that is bent into various forms. Driving transistor T1, switching transistor T2, compensation transistor T3, initialization transistor T4, operation control transistor T5, emitter control transistor T6, and electrode initialization transistor T7 can be disposed in the first semiconductor layer SACT. For example, the first semiconductor layer SACT may include a channel region of each of the driving transistor T1, switching transistor T2, compensation transistor T3, initialization transistor T4, operation control transistor T5, emitter control transistor T6, and electrode initialization transistor T7, and source and drain regions on two opposite sides of the channel region.

[0321] A first gate insulating layer may cover the first semiconductor layer SACT and be disposed on the substrate 100. The first gate insulating layer may include an insulating material. For example, the first gate insulating layer may include silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0322] like Figure 35As shown, the first gate layer GTL1 can be disposed on the first gate insulating layer. The first gate layer GTL1 may include a first scan line GWL for transmitting the first scan signal GW, a third scan line GIL for transmitting the initialization scan signal GI to the initialization transistor T4, an emitter control line EL for transmitting the emitter control signal EM to the operation control transistor T5 and the emitter control transistor T6, and a drive gate electrode 131a with an isolated shape for driving the transistor T1. The drive gate electrode 131a may also serve as the lower electrode of the first electrode of the capacitor Cst. The material and layering structure of the first gate layer GTL1 are the same as those described above.

[0323] The first scan line GWL, the third scan line GIL, and the emission control line EL can have a shape extending in a first direction (e.g., the x-axis direction). The portion of the first semiconductor layer SACT that overlaps with the first scan line GWL, the third scan line GIL, and the emission control line EL can serve as the gate electrode of a transistor. For example, the portion of the first scan line GWL that overlaps with the first semiconductor layer SACT can be the switching gate electrode of the switching transistor T2 and the compensation gate electrode of the compensation transistor T3; the portion of the third scan line GIL that overlaps with the first semiconductor layer SACT can be the initialization gate electrode of the initialization transistor T4 and the electrode initialization gate electrode of the electrode initialization transistor T7; and the portion of the emission control line EL that overlaps with the first semiconductor layer SACT can be the operation control gate electrode of the operation control transistor T5 and the emission control gate electrode of the emission control transistor T6.

[0324] For reference, the first scan line GWL extending in the first direction (e.g., the x-axis direction) has a protruding portion protruding in the second direction (e.g., the y-axis direction) and overlaps twice with the first semiconductor layer SACT at the portion corresponding to the compensation transistor T3. Accordingly, the compensation transistor T3 may be a dual-gate transistor with two channel regions. Because the first semiconductor layer SACT has a curved shape, the third scan line GIL extending in the first direction (e.g., the x-axis direction) overlaps twice with the first semiconductor layer SACT at the portion corresponding to the initialization transistor T4. Accordingly, the initialization transistor T4 may also be a dual-gate transistor with two channel regions.

[0325] A second gate insulating layer GTL2 may be disposed on the first gate insulating layer to cover the first gate layer GTL1. The second gate insulating layer may include an insulating material that is the same as or similar to the insulating material of the first gate insulating layer GTL1.

[0326] like Figure 36As shown, a second gate layer GTL2 can be disposed on a first gate insulating layer GTL1. The second gate layer GTL2 may include an electrode voltage line HL (which may be a first connection line PCL1), a second connection line PCL2, and an initialization voltage line VIL. The electrode voltage line HL, the second connection line PCL2, and the initialization voltage line VIL may extend in a first direction (e.g., the x-axis direction). The material and layering structure of the second gate layer GTL2 are the same as those described above.

[0327] A portion of the electrode voltage line HL can be the upper electrode of the second electrode of capacitor Cst, and can overlap with the driving gate electrode 131a, which is the lower electrode of capacitor Cst. The upper electrode of capacitor Cst of pixel circuits in the same row can be integrally formed into a single unit extending in a first direction (e.g., the x-axis direction) via the electrode voltage line HL. Accordingly, the electrode voltage line HL can be the second connection line PCL2. As described below, a first driving voltage ELVDD1 can be applied to the electrode voltage line HL. For example, the first driving voltage ELVDD1 can be applied to the upper electrode of capacitor Cst. An opening SOP can be formed in the upper electrode of capacitor Cst, and at least a portion of the driving gate electrode 131a can overlap with the opening.

[0328] As described below, the second drive voltage ELVDD2 can be applied to the second connection line PCL2. The initialization voltage line VIL can transmit the initialization voltage Vint.

[0329] The first interlayer insulating layer may cover the second gate layer GTL2 and be disposed on the second gate insulating layer. The first interlayer insulating layer may include an insulating material. For example, the first interlayer insulating layer may include silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0330] Figure 37 The first source / drain layer SD1 shown can be disposed on the first interlayer insulating layer. The first source / drain layer SD1 may include a data line DL, a first drive voltage line PL1, a second drive voltage line PL2, and connecting electrodes 171, 175, 181, and 183. The data line DL, the first drive voltage line PL1, and the second drive voltage line PL2 may have a shape extending in a second direction (e.g., the y-axis direction). The connecting electrodes 171, 175, 181, 182, 183, and 184 may have an isolated shape. The material and layering structure of the first source / drain layer SD1 may be the same as those described above.

[0331] The data line DL can be electrically connected to the source region of the switching transistor T2 through the contact hole 81 that passes through the underlying insulating layer.

[0332] In the second pixel region PXA2 of the second region among the third pixel region PXA3, the second pixel region PXA2, the first pixel region PXA1, and the second pixel region PXA2 arranged sequentially in the first direction (e.g., the x-axis direction), a first driving voltage line PL1 extending in the second direction (e.g., the y-axis direction) can be electrically connected via a contact hole 82a passing through the underlying first interlayer insulating layer to an electrode voltage line HL, which is the first connecting line PCL1 and extends in the first direction (e.g., the x-axis direction), and is included in the second gate layer GTL2 in the second pixel region PXA2. Accordingly, the first driving voltage line PL1 and the electrode voltage line HL electrically connected to each other can have (or fully have) a mesh structure. Accordingly, the voltage drop (IR drop) of the first driving voltage ELVDD1 in the display area DA can be prevented or reduced.

[0333] In the third pixel region PXA3 and the first pixel region PXA1, a second driving voltage line PL2 extending in a second direction (e.g., the y-axis direction) can be electrically connected via a contact hole 82b passing through the underlying first interlayer insulating layer to a second connecting line PCL2 included in the second gate layer GTL2 and extending in the third pixel region PXA3 in the first direction (e.g., the x-axis direction). Accordingly, the second driving voltage line PL2 and the second connecting line PCL2 electrically connected to each other can have (or fully have) a mesh structure. Accordingly, the voltage drop (IR drop) of the second driving voltage ELVDD2 in the display region DA can be prevented or reduced.

[0334] In the second pixel region PXA2, the first driving voltage line PL1 can be electrically connected to the emitter control transistor T6 in the second pixel region PXA2 through a contact hole 82c formed in the insulating layer beneath it. Correspondingly, the first driving voltage ELVDD1 can be applied to the emitter control transistor T6 in the second pixel region PXA2. Because the second driving voltage line PL2, instead of the first driving voltage line PL1, passes through the first pixel region PXA1, the emitter control transistor T6 in the first pixel region PXA1 may not be connected to the second driving voltage line PL2. Instead, the connection electrode 184 in the first pixel region PXA1 can electrically connect the first driving voltage line PL1 to the emitter control transistor T6 in the first pixel region PXA1. For example, one end of the connection electrode 184 in the first pixel region PXA1 can be electrically connected to the electrode voltage line HL, which is the first connection line PCL1, through a contact hole 84a passing through the first interlayer insulating layer beneath it, and the other end can be electrically connected to the emitter control transistor T6 in the first pixel region PXA1 through a contact hole 84b formed in the insulating layer beneath it. Accordingly, a first driving voltage ELVDD1 can be applied to the emitter control transistor T6 in the first pixel region PXA1. For this purpose, as Figure 34 As shown, the portion of the first semiconductor layer SACT corresponding to the emitter control transistor T6 in the first pixel region PXA1 can protrude much more in the +x direction than the portion of the first semiconductor layer SACT corresponding to the emitter control transistor T6 in another pixel region.

[0335] In the third pixel region PXA3, the second driving voltage line PL2 can be electrically connected to the emitter control transistor T6 in the third pixel region PXA3 through a contact hole 82c formed in the insulating layer thereunder. Accordingly, the second driving voltage ELVDD2 can be applied to the emitter control transistor T6 in the third pixel region PXA3.

[0336] One end of the connection electrode 171 can be electrically connected to the first semiconductor layer SACT via contact hole 51. For example, one end of the connection electrode 171 can be electrically connected to the compensation transistor T3 and the initialization transistor T4 via contact hole 51 passing through the underlying insulating layer. The other end of the connection electrode 171 can be electrically connected to the drive gate electrode 131a of the drive transistor T1, which also acts as the lower electrode of the capacitor Cst, via contact hole 52 passing through the underlying insulating layer. Contact hole 52 can pass through the opening SOP of the upper electrode of the capacitor Cst.

[0337] The connection electrode 175 can be electrically connected to the initialization voltage line VIL through a contact hole 58 passing through the underlying first interlayer insulating layer. The connection electrode 175 can also be electrically connected to the first semiconductor layer SACT through a contact hole 59 passing through the underlying insulating layer. For example, the connection electrode 175 can be electrically connected to the initialization transistor T4 and the electrode initialization transistor T7 through the contact hole 59 passing through the underlying insulating layer.

[0338] Each of the connection electrode 181 in the first pixel region PXA1, the connection electrode 182 in the second pixel region PXA2, and the connection electrode 183 in the third pixel region PXA3 can be electrically connected to the drain region of the emitter control transistor T6 through a contact hole 83 passing through the underlying insulating layer.

[0339] A first planarization insulating layer may be disposed on the first interlayer insulating layer to cover the first source / drain layer SD1. The first planarization insulating layer may include the same material as described above.

[0340] like Figure 38 As shown, the pixel electrode layer PXL can be disposed on the first planarization insulating layer. The pixel electrode layer PXL may include multiple pixel electrodes. Figure 38 The diagram shows a first pixel electrode PE1 for a first pixel PX1, a second pixel electrode PE2 for a second pixel PX2, and a third pixel electrode PE3 for a third pixel PX3. Each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may include a first region PEA1 (see [link to diagram]). Figure 9 ) and the second region PEA2 surrounding the first region PEA1 (see Figure 9 The pixel electrode layer PXL may include the same materials and layered structures as described above.

[0341] The first pixel electrode PE1 can be electrically connected to the connection electrode 181 included in the first source / drain layer SD1 through a contact hole 91 passing through the first planarization insulating layer. Correspondingly, the first pixel electrode PE1 can be electrically connected to the driving transistor T1, which is subject to the first driving voltage ELVDD1, through the emitter control transistor T6 in the first pixel region PXA1. The contact hole 91 can be configured to connect to the second region PEA2 of the first pixel electrode PE1 (see...). Figure 9 Corresponding to ).

[0342] The second pixel electrode PE2 can be electrically connected to the connection electrode 182 included in the first source / drain layer SD1 through a contact hole 92 passing through the first planarization insulating layer. Correspondingly, the second pixel electrode PE2 can be electrically connected to the driving transistor T1, which is subject to the first driving voltage ELVDD1, through the emitter control transistor T6 in the second pixel region PXA2. The contact hole 92 can be configured to connect to the second region PEA2 of the second pixel electrode PE2 (see...). Figure 9 Corresponding to ).

[0343] The third pixel electrode PE3 can be electrically connected to the connection electrode 183 included in the first source / drain layer SD1 through a contact hole 93 passing through the first planarization insulating layer. Correspondingly, the third pixel electrode PE3 can be electrically connected to the driving transistor T1, which is subject to the second driving voltage ELVDD2, through the emitter control transistor T6 in the third pixel region PXA3. The contact hole 93 can be configured to connect to the second region PEA2 of the third pixel electrode PE3 (see...). Figure 9 Corresponding to ).

[0344] The descriptions of the pixel confinement layer, emitter layer, and common electrode CAT, etc., are the same as those described above.

[0345] In addition to the pixel circuits described so far, this disclosure applies to a variety of pixel circuits.

[0346] For example, as illustrated, the pixel circuit can be electrically connected to the display panel 10 according to the embodiment and the light-emitting element included in the electronic device 1 including the display panel 10. Figure 39 and Figure 40 As shown, the pixel circuits in the third pixel PX3, the first pixel PX1, and the second pixel PX2 can be electrically connected to the second driving voltage line PL2. For example, with Figure 31 Unlike the pixel circuits in the first pixel PX1 and the second pixel PX2, the second driving voltage line PL2 can partially overlap with the two gate electrodes of the compensation transistor T3 with a dual-gate structure to form a transistor.

[0347] For example, as referenced above Figure 31 As described, in the pixel circuit of the first pixel PX1 and the pixel circuit of the second pixel PX2, the operation control transistor T5 can be electrically connected to the first drive voltage line PL1. This differs from, as... Figure 40As shown, in the pixel circuit of the third pixel PX3, the second driving voltage line PL2 can partially overlap with the area between the two gate electrodes of the compensation transistor T3 with a dual-gate structure to form a transistor, and simultaneously, an operation control transistor T5 is electrically connected to the pixel circuit in the third pixel PX3. Thus, the potential between the third pixel electrode PE3 and the common electrode CAT of the third light-emitting element OLED3 can be adjusted to be different from the potential between the first pixel electrode PE1 and the common electrode CAT of the first light-emitting element OLED1 and the second pixel electrode PE2 and the common electrode CAT of the second light-emitting element OLED2.

[0348] Figure 41 and Figure 42 It is a pixel circuit PC that can be electrically connected to the light-emitting elements included in the display panel 10 and the electronic device 1 including the display panel 10 according to the embodiment. Figure 41 and Figure 42 The pixel circuit PC shown includes a drive transistor T1, a switch transistor T2, an initialization transistor T3, an initialization transistor T4, an operation control transistor T5, an emission control transistor T6, a storage capacitor Cst, and a holding capacitor Chold. Figure 41 and Figure 42 The diagram shows that the operation control transistor T5 is a p-channel metal-oxide-semiconductor field-effect transistor (MOSFET), and the remaining transistors are n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0349] The initialization transistor T3 can be electrically connected between the reference voltage line VRL and the second node N2 corresponding to the driving gate electrode of the driving transistor T1. The initialization transistor T3 can be turned on according to the reference signal GR transmitted through the reference gate line GRL, and can transmit the reference voltage VREF from the reference voltage line VRL to the second node N2, thereby initializing the potential of the driving gate electrode of the driving transistor T1.

[0350] Initialize transistor T4 can be with Figure 12 Corresponding to the electrode initialization transistor T8, one of the source and drain regions of the initialization transistor T4 can be electrically connected to the electrode initialization voltage line VL that provides the electrode initialization voltage Vaint, and the other can be electrically connected to the pixel electrode of the first light-emitting element OLED1 and / or the second light-emitting element OLED2.

[0351] The storage capacitor Cst can be electrically connected between the second node N2 corresponding to the driving gate electrode of the driving transistor T1 and the third node N3 corresponding to one of the source and drain regions of the driving transistor T1 connected to the emitter control transistor T6. For example, Figure 41The pixel circuit PC shown can be a source follower type circuit. The storage capacitor Cst can store the threshold voltage of the driving transistor T1 and the voltage corresponding to the data signal DATA.

[0352] A holding capacitor Chold can be connected between the first drive voltage line PL1 and the third node N3. The holding capacitor Chold ensures that the voltage at the third node N3 of the drive transistor T1 does not fluctuate and has a constant voltage in the event of ambient signal fluctuations.

[0353] The driving transistor T1, switching transistor T2, and operation control transistor T5 are the same as those described above. However, the emitter control transistor T6 can be an n-channel MOSFET (NMOS). The emitter control transistor T6 can be turned on according to the inverted emitter control signal EMB supplied from the inverted emitter control line EBL.

[0354] For example, in the pixel circuit of the first pixel PX1 and the pixel circuit of the second pixel PX2, the operation control transistor T5 can be electrically connected to the first driving voltage line PL1. In contrast, in the pixel circuit of the third pixel PX3, the operation control transistor T5 can be electrically connected to the second driving voltage line PL2. Therefore, the potential between the third pixel electrode PE3 and the common electrode CAT of the third light-emitting element OLED3 can be adjusted to a different potential than the potential between the first pixel electrode PE1 and the common electrode CAT of the first light-emitting element OLED1 and the second pixel electrode PE2 and the common electrode CAT of the second light-emitting element OLED2.

[0355] According to embodiments, a display panel capable of displaying high-quality images and an electronic device including the display panel can be realized. However, the scope of this disclosure is not limited by this effect.

[0356] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects in each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the figures, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the claims.

Claims

1. A display panel, comprising: The first driving voltage line and the second driving voltage line are arranged alternately in the display area in a first direction and extend in a second direction that intersects the first direction; The first color pixel circuit and the third color pixel circuit are alternately arranged along the second driving voltage line; and The second color pixel circuit is arranged along the first driving voltage line. The first color pixel circuit and the second color pixel circuit are electrically connected to the first driving voltage line, and the third color pixel circuit is electrically connected to the second driving voltage line. The potential of the second driving voltage supplied through the second driving voltage line is different from the potential of the first driving voltage supplied through the first driving voltage line.

2. The display panel according to claim 1, wherein, The potential of the second driving voltage supplied through the second driving voltage line is greater than the potential of the first driving voltage supplied through the first driving voltage line.

3. The display panel according to claim 1, wherein, Each of the first color pixel circuits in the first color pixel circuit is electrically connected to a corresponding first driving voltage line in the first driving voltage line through an adjacent second color pixel circuit in the second color pixel circuits arranged in the same row.

4. The display panel according to claim 1, wherein, A group of pixel circuits, including those arranged in the first direction in the order of third color pixel circuit, second color pixel circuit, first color pixel circuit, and second color pixel circuit, is repeatedly arranged in the first direction, and The first color pixel circuit in the group is electrically connected to a corresponding first drive voltage line in the first drive voltage line via a second color pixel circuit that is configured to be remote from the third color pixel circuit relative to the first color pixel circuit in the group.

5. The display panel according to claim 1, wherein, The operation control transistors of the first color pixel circuit and the second color pixel circuit are electrically connected to the first driving voltage line, and the operation control transistor of the third color pixel circuit is electrically connected to the second driving voltage line.

6. The display panel according to claim 1, wherein, The operation control transistor of each of the first color pixel circuits is electrically connected to the operation control transistor of an adjacent second color pixel circuit in the same row, and correspondingly, is electrically connected to a corresponding first driving voltage line in the first driving voltage line.

7. The display panel according to claim 1, wherein, A group of pixel circuits, including those arranged in the first direction in the order of third color pixel circuit, second color pixel circuit, first color pixel circuit, and second color pixel circuit, is repeatedly arranged in the first direction, and The operation control transistor of the first color pixel circuit in the group is electrically connected to the operation control transistor of the second color pixel circuit that is configured to be far away from the third color pixel circuit relative to the first color pixel circuit in the group, and correspondingly, is electrically connected to a corresponding first drive voltage line in the first drive voltage line.

8. The display panel according to claim 1, wherein, The driving transistors of the first color pixel circuit and the second color pixel circuit are electrically connected to the first driving voltage line, and the driving transistor of the third color pixel circuit is electrically connected to the second driving voltage line.

9. The display panel according to claim 1, wherein, The driving transistor of each first color pixel circuit in the first color pixel circuit is electrically connected to the driving transistor of an adjacent second color pixel circuit in the second color pixel circuit arranged in the same row, and correspondingly, is electrically connected to a corresponding first driving voltage line in the first driving voltage line.

10. The display panel according to claim 1, wherein, A group of pixel circuits, including those arranged in the first direction in the order of third color pixel circuit, second color pixel circuit, first color pixel circuit, and second color pixel circuit, is repeatedly arranged in the first direction, and The driving transistor of the first color pixel circuit in the group is electrically connected to the driving transistor of the second color pixel circuit that is configured to be remote from the third color pixel circuit relative to the first color pixel circuit in the group, and correspondingly, is electrically connected to a corresponding first driving voltage line in the first driving voltage line.

11. The display panel according to claim 1, further comprising: The first connecting line and the second connecting line are arranged alternately in the second direction and extend in the first direction. Each of the first connecting lines is electrically connected to the first driving voltage line, and each of the second connecting lines is electrically connected to the second driving voltage line.

12. The display panel according to claim 11, wherein, The first connecting line and the second connecting line are disposed on the first driving voltage line and the second driving voltage line, and Each of the first connecting lines is repeatedly arranged in the first direction, wherein each of the groups includes an extension portion arranged in the first direction in the order of a first extension portion corresponding to a first color pixel electrode, a second extension portion corresponding to a second color pixel electrode, a third extension portion corresponding to a third color pixel electrode, and a second extension portion corresponding to a second color pixel electrode. Each of the second connecting lines has a group of lines that are repeatedly arranged in the first direction, wherein each of the groups includes an extension portion arranged in the first direction in the order of a third extension portion corresponding to a third color pixel electrode, a second extension portion corresponding to a second color pixel electrode, a first extension portion corresponding to a first color pixel electrode, and a second extension portion corresponding to a second color pixel electrode.

13. The display panel according to claim 11, wherein, The first connecting line and the second connecting line are disposed below the first driving voltage line and the second driving voltage line, respectively.

14. The display panel according to claim 13, wherein, Each of the third color pixel circuits in the third color pixel circuit includes: An initialization transistor having one end electrically connected to a pixel electrode; and Connect the electrodes, electrically connect the other end of the initialization transistor to the initialization voltage line, and position it below the first connection line and the second connection line.

15. The display panel according to claim 13, wherein, Each of the first color pixel circuits in the first color pixel circuit is electrically connected to a corresponding first connection line in the first connection line.

16. The display panel according to claim 13, wherein, Each of the first color pixel circuits includes an emission control transistor and a connection electrode that electrically connects the emission control transistor to a corresponding first connection line in the first connection line. The connecting electrode, the first driving voltage line, and the second driving voltage line are disposed on the same layer.

17. The display panel according to any one of claims 1 to 10, further comprising: The first color pixel electrode is electrically connected to each of the first color pixel circuits in the first color pixel circuit. The second color pixel electrode is electrically connected to each of the second color pixel circuits in the second color pixel circuit. The third color pixel electrode is electrically connected to each of the third color pixel circuits in the third color pixel circuit. as well as A common electrode is disposed above the first color pixel electrode, the second color pixel electrode, and the third color pixel electrode, and the common electrode is integrally formed into a single unit. The first color emitting layer is disposed between the first color pixel electrode and the common electrode, the second color emitting layer is disposed between the second color pixel electrode and the common electrode, and a plurality of third color emitting layers and a charge generation layer disposed between the plurality of third color emitting layers are disposed between the third color pixel electrode and the common electrode.

18. A display panel, comprising: Light-emitting diode; The first driving voltage line transmits the first driving voltage; The second driving voltage line transmits a second driving voltage that is different from the first driving voltage. A storage capacitor includes a first capacitor electrode and a second capacitor electrode, wherein the second capacitor electrode is electrically connected to the first driving voltage line; as well as The driving transistor, in response to a voltage applied to a second node electrically connected to the electrode of the first capacitor, controls the amount of driving current flowing from a first node electrically connected to the second driving voltage line to the light-emitting diode.

19. An electronic device comprising: Display panel; as well as The lower cover forms the exterior of the electronic device and has an opening that exposes a portion of the display panel. The display panel includes: The first driving voltage line and the second driving voltage line are arranged alternately in the display area in a first direction and extend in a second direction that intersects the first direction; The first color pixel circuit and the third color pixel circuit are alternately arranged along the second driving voltage line; and The second color pixel circuit is arranged along the first driving voltage line, and The first color pixel circuit and the second color pixel circuit are electrically connected to the first driving voltage line, and the third color pixel circuit is electrically connected to the second driving voltage line.

20. The electronic device according to claim 19, wherein, The potential of the second driving voltage supplied through the second driving voltage line is different from the potential of the first driving voltage supplied through the first driving voltage line.

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