Preparation method of high-temperature superconducting quantum voltage chip and quantum voltage chip

Abstract

The invention relates to the technical field of superconducting electronics devices, and provides a preparation method of a high-temperature superconducting quantum voltage chip and a quantum voltage chip, and the preparation method comprises the steps: providing a single-crystal substrate, and etching a step structure on the surface of the single-crystal substrate to obtain the single-crystal substrate with the step structure; an yttrium barium copper oxide thin film is epitaxially grown on the surface of a single crystal substrate with a step structure, the yttrium barium copper oxide thin film forms step grain boundaries at the border of the edge of the step structure, and each step grain boundary forms a Josephson junction; a buffer layer and an electrode layer are arranged on the surface of the yttrium barium copper oxide thin film, the yttrium barium copper oxide thin film is patterned to form a winding line structure, the quantum voltage chip is obtained, and the winding line structure crosses the step grain boundary and connects the Josephson junctions in series. According to the technical scheme, the technical problem that the quantum voltage chip Josephson junction array in the prior art is low in preparation freedom degree is solved.

Description

Technical Field

[0001] This invention belongs to the field of superconducting electronic device technology, and more specifically, relates to a method for preparing a high-temperature superconducting quantum voltage chip and the quantum voltage chip itself. Background Technology

[0002] Quantum voltage is a quantum phenomenon based on the Josephson effect in superconductivity, and its uncertainty is unaffected by environmental factors such as external temperature drift. Low-temperature superconducting quantum voltage standards need to operate in the liquid helium temperature range, requiring a liquid helium Dewar or a high-powered refrigerator to maintain this temperature. This results in high energy consumption and bulky size for current quantum voltage standards. High-temperature superconducting quantum voltage standards can operate in the liquid nitrogen temperature range, around 77K. Since maintaining this temperature only requires liquid nitrogen and a low-power refrigerator, the energy consumption and size of the quantum voltage system are significantly reduced, improving its portability.

[0003] The physical structure that generates quantum voltage is the superconducting Josephson junction, which consists of superconductors on both sides and a barrier layer in the middle. By cascading a large number of Josephson junctions, i.e., forming an array, a large number of quantum voltages can be generated. Traditional high-temperature superconducting quantum voltage chips are arrayed based on bicrystalline grain boundaries. Since bicrystalline grain boundary arrays are epitaxially grown on a bicrystalline substrate matched with the high-temperature superconducting material, superconducting wire structures need to traverse the substrate grain boundaries. However, bicrystalline substrates are typically sintered using a top-seeded flux method and then cut into substrates of specific sizes through a pre-set slicing program. The grain boundary positions and angles are fixed, so the array depends on the fixed distribution of grain boundaries on the substrate, resulting in poor flexibility in the design and fabrication of the array circuit. Furthermore, the quality of the bicrystalline substrate depends on the precision of the grain splicing and the sintering process during production, thus affecting the quality of the arrayed chip. In addition, its production method is relatively complex and the price is relatively high. Summary of the Invention

[0004] The purpose of this invention is to provide a method for preparing a high-temperature superconducting quantum voltage chip and a quantum voltage chip, thereby solving or at least alleviating one or more of the above-mentioned problems and other problems existing in the prior art.

[0005] The technical solution of the present invention is as follows:

[0006] This invention proposes a method for fabricating a high-temperature superconducting quantum voltage chip, comprising:

[0007] A single-crystal substrate is provided, and a stepped structure is etched on the surface of the single-crystal substrate to obtain a single-crystal substrate with a stepped structure;

[0008] A yttrium barium copper oxide thin film is epitaxially grown on the surface of the single crystal substrate with the stepped structure. The yttrium barium copper oxide thin film forms step grain boundaries at the edge junctions of the stepped structure, and each step grain boundary constitutes a Josephson junction.

[0009] A buffer layer and an electrode layer are disposed on the surface of the yttrium barium copper oxide thin film, and the yttrium barium copper oxide thin film is patterned to form a meandering line structure to obtain a quantum voltage chip. The meandering line structure crosses the step grain boundary and connects multiple Josephson junctions in series.

[0010] As a further technical solution, the single-crystal substrate includes a single-crystal strontium titanate substrate or a single-crystal lanthanum aluminate substrate.

[0011] As a further technical solution, the stepped grain boundary includes one or both of linear stepped grain boundaries and annular stepped grain boundaries.

[0012] As a further technical solution, the etching is performed using reactive ion beam etching, wherein the ion source screen voltage is 530–535 eV, the accelerating voltage is 200–210 V, the oxygen flow rate is 1–8 sccm, the angle between the ion bombardment direction and the single crystal substrate is 60°–90°, and the etching time is 80–90 min.

[0013] As a further technical solution, the epitaxial growth is performed using pulsed laser deposition, wherein the laser energy of the pulsed laser deposition method is 200-300 mJ, the laser pulse frequency is 1-5 Hz, the heating stage temperature is 700-900 °C, and the oxygen atmosphere is 20-100 Pa.

[0014] As a further technical solution, the yttrium barium copper oxide thin film is epitaxially grown to a thickness of 150-200 nm.

[0015] As a further technical solution, the buffer layer is a titanium layer; and / or

[0016] The electrode layer is a gold layer.

[0017] As a further technical solution, the thickness of the buffer layer is 10–15 nm; and / or

[0018] The thickness of the electrode layer is 50–55 nm.

[0019] As a further technical solution, the meandering line structure and the stepped grain boundary intersect each other perpendicularly.

[0020] This invention also proposes a quantum voltage chip, prepared by the aforementioned method, comprising:

[0021] A single-crystal substrate with a stepped surface structure;

[0022] A yttrium barium copper oxide thin film is epitaxially grown on the surface of the single crystal substrate, and step grain boundaries are formed at the edges of the step structure, with each step grain boundary constituting a Josephson junction;

[0023] The meandering line structure is formed by patterning the yttrium barium copper oxide film, the meandering line structure spans the stepped grain boundaries and connects multiple Josephson junctions in series.

[0024] The beneficial effects of this invention are as follows:

[0025] Unlike the fabrication method of bicrystalline grain boundary arrays, this invention utilizes stepped grain boundaries to achieve the series connection of a large number of Josephson junctions. Furthermore, the number and positional distribution of the substrate stepped structures can be freely defined, thereby increasing the degree of freedom in the fabrication and series connection of Josephson junction arrays. This, in turn, increases the degree of freedom in the microwave drive design of quantum voltage chips, ultimately resulting in a highly integrated quantum voltage chip with improved microwave coupling efficiency and uniformity. Specifically, a stepped structure is first freely defined and fabricated on a single-crystal substrate. Then, a yttrium barium copper oxide (YTO) thin film is epitaxially grown. Due to the different epitaxial directions of the YTO at the edges of the stepped structures, grain boundaries, i.e., superconducting weak connections, are formed at the edges of the stepped structures, serving as barrier layers for the Josephson junctions. Finally, by processing the YTO near the stepped structures into a meandering line structure as a superconducting wire, a Josephson junction array whose number and position can be freely defined is formed. Attached Figure Description

[0026] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. Obviously, the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0027] Figure 1 A flowchart illustrating a method for fabricating a high-temperature superconducting quantum voltage chip according to an embodiment of the present invention;

[0028] Figure 2 This is a schematic diagram of a pulsed laser deposition method provided in an embodiment of the present invention;

[0029] Figure 3 This is a schematic diagram of the quantum voltage chip in Example 1;

[0030] Figure 4 This is a schematic diagram of the quantum voltage chip in Example 2;

[0031] Figure 5 This is a schematic diagram of the quantum voltage chip in Example 3;

[0032] Figure 6 This is a schematic diagram of the quantum voltage chip in Example 4. Detailed Implementation

[0033] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0034] It should be understood that, unless the context clearly indicates otherwise, the terms "comprising," "including," or "having" as used herein refer to the presence of a particular element, but do not exclude the presence or addition of one or more other elements. Furthermore, as used herein, "comprising" and / or "including" specify the presence of shapes, numbers, steps, operations, members, elements, and / or combinations thereof, and do not exclude the presence or addition of one or more other shapes, numbers, operations, elements, and / or combinations thereof.

[0035] In this invention, the numerical range indicated by "~" refers to the range of values ​​specified as the lower limit and upper limit, respectively, before or after the term. When multiple values ​​for the upper or lower limit of any numerical range are mentioned, the range disclosed herein can be understood as a range with any one of the mentioned upper limit values ​​as its upper limit and any one of the mentioned lower limit values ​​as its lower limit.

[0036] The following will describe in detail a method for preparing a high-temperature superconducting quantum voltage chip according to an embodiment of the present invention, and the quantum voltage chip itself.

[0037] According to one aspect of the present invention, a method for fabricating a high-temperature superconducting quantum voltage chip is proposed.

[0038] Please refer to Figure 1 , Figure 1 This is a flowchart of a method for fabricating a high-temperature superconducting quantum voltage chip according to an embodiment of the present invention. The method may include steps S1 to S3:

[0039] Step S1: Provide a single crystal substrate and etch a stepped structure on the surface of the single crystal substrate to obtain a single crystal substrate with a stepped structure.

[0040] In this invention, the single-crystal substrate can be a single-crystal strontium titanate substrate or a single-crystal lanthanum aluminate substrate. When etching the stepped structure, the stepped structure pattern can be defined first using ultraviolet lithography, and then etched using an argon-ion reactive ion beam. Specifically, photoresist is spin-coated onto the surface of a single-crystal strontium titanate substrate or a single-crystal lanthanum aluminate substrate. After baking and cooling, ultraviolet lithography is performed using a transparent mask for ultraviolet exposure. After exposure, the substrate is developed using a developer to remove the exposed photoresist. The area where the photoresist was removed is then etched using an argon-ion reactive ion beam. After etching, the photoresist is removed by rinsing with acetone, resulting in a single-crystal substrate with a stepped structure. The position, number, and shape type of the stepped structure in this invention can be customized by combining microwave spatial electromagnetic field distribution simulation, greatly improving the freedom of Josephson array fabrication.

[0041] Step S2: A yttrium barium copper oxide thin film is epitaxially grown on the surface of a single crystal substrate with a stepped structure. Step boundaries are formed at the edges of the yttrium barium copper oxide thin film, and each step boundary constitutes a Josephson junction.

[0042] In this invention, Josephson junctions are fabricated using weak connections formed by step grain boundaries in yttrium barium copper oxide thin films. The shape of the step grain boundaries can be at least one of linear or annular step grain boundaries. Pulsed laser deposition can be used for the epitaxial growth of the yttrium barium copper oxide thin film; a schematic diagram of pulsed laser deposition is shown below. Figure 2 As shown, a pulsed laser bombards a target, sputtering high-energy target particles. These particles are deposited on a single-crystal substrate parallel to the target on a heating stage below, and epitaxially grown into a thin film. Furthermore, the single-crystal substrate is fixed to the heating stage with silver paste to ensure temperature uniformity and good contact. The growth thickness of the yttrium barium copper oxide (YBO) film is monitored in real time using a high-energy reflection electron diffraction (HEAD) device. Although the thickness of the YBO film has some influence on the superconducting critical current of the fabricated Josephson junction, the superconducting critical current of the Josephson junction is related not only to the thickness of the YBO film but also to the width of the Josephson junction. The effect of thickness variation can be adjusted by synchronously correcting the width of the Josephson junction. Therefore, this invention does not have a precise requirement for the thickness of the YBO film; a range of 150–200 nm is acceptable.

[0043] In this invention, the specific parameters of the pulsed laser deposition method may include: laser wavelength of 248 nm, laser energy of 200-300 mJ, laser pulse frequency of 1-5 Hz, heating stage temperature of 700-900 °C, oxygen atmosphere of 20-100 Pa, and distance between the target and the heating stage of 15-28 cm.

[0044] Step S3: A buffer layer and an electrode layer are formed on the surface of the yttrium barium copper oxide thin film, and the yttrium barium copper oxide thin film is patterned to form a meandering line structure to obtain a quantum voltage chip. The meandering line structure crosses the step grain boundary and connects multiple Josephson junctions in series.

[0045] In this invention, an electron beam evaporation or magnetron sputtering method can be used to sequentially grow a buffer layer and an electrode layer on the surface of a yttrium barium copper oxide (YBO) thin film through a perforated metal mask. The buffer layer can be a titanium layer with a thickness of 10–15 nm; the electrode layer can be a gold layer with a thickness of 50–55 nm. This invention can pattern the YBO thin film using photolithography and etching to form a meandering line structure. By controlling the width of the meandering line structure and the number of times it crosses the step structure, the critical current and the number of series junctions of the Josephson junction can be controlled. During the patterning of the YBO thin film, ultraviolet photoresist is spin-coated onto the surface of the YBO thin film. After baking and cooling, ultraviolet photolithography is used to expose the film using a transparent mask. After exposure, a developer is used to remove the photoresist from the exposed portion of the YBO thin film surface. Argon ions are used to etch the area where the photoresist was removed. After etching, acetone is used to rinse away the unexposed photoresist, resulting in a quantum voltage chip.

[0046] In this invention, the sample is rotated at a constant speed during etching, and the critical current is controlled in the milliampere range by controlling the Josephson junction width and the thickness of the barium copper oxide film.

[0047] In one embodiment of the present invention, when etching the stepped structure on the surface of a single crystal substrate, reactive ion beam etching is used. The reactive ion beam etching has an ion source screen voltage of 530-535 eV, an accelerating voltage of 200-210 V, an oxygen flow rate of 1-8 sccm, an angle of 60°-90° between the ion bombardment direction and the single crystal substrate, and an etching time of 80-90 min.

[0048] In this invention, the performance of the quantum voltage chip is further improved through a specific step structure etching process. The main technical challenge in fabricating the quantum voltage chip lies in the etching process of the substrate material. High-performance quantum voltage chips require a maximum number of Josephson junctions connected in series within the Josephson junction array, while also demanding good consistency among each series-connected Josephson junction, ensuring that all step structures distributed within the Josephson junction array are as microscopically consistent as possible. The inventors have creatively discovered that the fabrication method for the quantum voltage chip of this invention, when using the aforementioned etching process parameters, can ensure the consistency of the step structure at the microscale. This lays the foundation for fabricating high-performance Josephson junction arrays, ultimately improving the overall performance of the quantum voltage chip.

[0049] In one embodiment of the invention, the meandering line structure and the stepped grain boundary intersect each other perpendicularly.

[0050] In this invention, when the meandering line structure and the stepped grain boundary intersect each other perpendicularly, the critical current of the Josephson junction can be better controlled, thereby further improving the overall performance of the quantum voltage chip.

[0051] According to another aspect of the present invention, a quantum voltage chip is also provided, prepared by the above-described preparation method, comprising:

[0052] A single-crystal substrate with a stepped surface structure;

[0053] Yttrium barium copper oxide thin films are epitaxially grown on the surface of a single-crystal substrate, and step grain boundaries are formed at the edges of the step structure. Each step grain boundary constitutes a Josephson junction.

[0054] The meandering line structure, formed by patterning a yttrium barium copper oxide thin film, crosses step grain boundaries and connects multiple Josephson junctions in series.

[0055] The following will describe in detail, with reference to examples, a method for fabricating a high-temperature superconducting quantum voltage chip according to the present invention. The embodiments of the present invention described below can be modified in various ways, therefore the scope of the present invention should not be construed as limited to the embodiments described in detail below. The embodiments are provided to help those skilled in the art to more readily understand the present invention.

[0056] The raw materials used in the following examples are all commercially available conventional raw materials.

[0057] Example 1

[0058] A method for fabricating a high-temperature superconducting quantum voltage chip includes the following steps:

[0059] S1. Spin-coat UV photoresist on the surface of a single-crystal strontium titanate substrate at 5000 r / min for 30 s. After coating, place it on an 80℃ heating stage for 10 min. After heating, place it on a copper metal plate to cool for 2 min. Use UV lithography to expose the substrate with a transparent mask containing a stepped grain boundary pattern. After exposure, develop the substrate with developer to remove the photoresist from the exposed area. Use an argon ion reactive ion beam to etch the area where the photoresist was removed. After etching, rinse with acetone to remove the photoresist and obtain a single-crystal strontium titanate substrate with a stepped structure and a step angle of 60°.

[0060] The reactive ion beam etching setup had an ion source screen voltage of 530 eV, an acceleration voltage of 200 V, an oxygen flow rate of 3 sccm, an ion bombardment direction angle of 30° with the single crystal substrate, and an etching time of 80 min.

[0061] S2. Using silver paste, the above-mentioned single-crystal strontium titanate substrate with a stepped structure is uniformly attached to the heating stage of the pulsed laser deposition chamber. The substrate surface is parallel to the target material. A yttrium barium copper oxide thin film is epitaxially grown on the substrate surface using pulsed laser deposition. The specific parameters of pulsed laser deposition are: laser wavelength 248nm, laser energy 200mJ, laser pulse frequency 1Hz, heating stage temperature 700℃, oxygen atmosphere 20Pa, and distance between the target material and the heating stage 15cm. The growth thickness of the yttrium barium copper oxide thin film is monitored using a high-energy electron diffraction device until the thickness of the yttrium barium copper oxide thin film reaches 200nm.

[0062] S3. Using electron beam evaporation, a 10nm thick titanium layer as a buffer layer and a 50nm thick gold layer as an electrode layer are sequentially grown on the surface of a yttrium barium copper oxide thin film through a perforated metal mask. The yttrium barium copper oxide thin film with gold electrodes is removed from the chamber. UV photoresist is spin-coated on the surface of the yttrium barium copper oxide thin film at a speed of 5000r / min for 30s. After the photoresist coating is completed, it is placed on an 80℃ heating stage for 10min. After heating, it is placed on a copper metal plate for 2min to cool down. UV lithography is used with a transparent mask containing a meandering line structure pattern. After the meandering line structure and the step grain boundaries are perpendicularly aligned, UV exposure is performed. After exposure, development is performed using a developer to remove the photoresist from the exposed part. Argon ion reactive ion beam is used to etch the part where the photoresist has been removed. After etching, acetone is used to rinse and remove the photoresist to obtain a quantum voltage chip.

[0063] A schematic diagram of the quantum voltage chip is shown below. Figure 3 As shown in the figure, the winding line structure path has mutually perpendicular intersecting substrate steps (microscopically step grain boundaries) and electrodes on both sides. This quantum voltage chip has a longer effective current path, which can accumulate higher quantum voltage output, thus improving the integration and practicality of the quantum chip.

[0064] Example 2

[0065] A method for fabricating a high-temperature superconducting quantum voltage chip includes the following steps:

[0066] S1. Spin-coat UV photoresist on the surface of a single-crystal strontium titanate substrate at 5000 r / min for 30 s. After coating, place it on an 80℃ heating stage for 10 min. After heating, place it on a copper metal plate to cool for 2 min. Use UV lithography and a transparent mask with a stepped grain boundary pattern for UV exposure. After exposure, develop with developer to remove the photoresist from the exposed area. Use an argon ion reactive ion beam to etch the photoresist-removed area. After etching, rinse with acetone to remove the photoresist. Repeat the above steps once to obtain a single-crystal strontium titanate substrate with a double-step structure, one step angle is 60° and the other step angle is 80°.

[0067] When etching a stepped structure with a step angle of 60°, the reactive ion beam etching parameters are: ion source screen voltage of 535 eV, acceleration voltage of 210 V, oxygen flow rate of 3 sccm, ion bombardment direction angle with single crystal substrate of 30°, and etching time of 90 min.

[0068] When etching a stepped structure with a step angle of 80°, the reactive ion beam etching parameters are: ion source screen voltage of 535 eV, acceleration voltage of 210 V, oxygen flow rate of 6 sccm, ion bombardment direction angle with single crystal substrate of 30°, and etching time of 90 min.

[0069] S2. Using silver paste, the above-mentioned single-crystal strontium titanate substrate with a stepped structure is uniformly attached to the heating stage of the pulsed laser deposition chamber. The substrate surface is parallel to the target material. A yttrium barium copper oxide thin film is epitaxially grown on the substrate surface using pulsed laser deposition. The specific parameters of pulsed laser deposition are: laser wavelength 248nm, laser energy 300mJ, laser pulse frequency 5Hz, heating stage temperature 900℃, oxygen atmosphere 100Pa, and distance between the target material and the heating stage 28cm. The growth thickness of the yttrium barium copper oxide thin film is monitored using a high-energy electron diffraction device until the thickness of the yttrium barium copper oxide thin film reaches 200nm.

[0070] S3. Using electron beam evaporation, a 15nm thick titanium layer as a buffer layer and a 55nm thick gold layer as an electrode layer are sequentially grown on the surface of a yttrium barium copper oxide thin film through a perforated metal mask. The yttrium barium copper oxide thin film with gold electrodes is removed from the chamber. UV photoresist is spin-coated on the surface of the yttrium barium copper oxide thin film at a speed of 5000r / min for 30s. After the photoresist coating is completed, it is placed on an 80℃ heating stage for 10min. After heating, it is placed on a copper metal plate for 2min to cool down. UV lithography is used with a transparent mask containing a meandering line structure pattern. After the meandering line structure and the step grain boundaries are perpendicularly aligned, UV exposure is performed. After exposure, development is performed using a developer to remove the photoresist from the exposed part. Argon ion reactive ion beam is used to etch the part where the photoresist has been removed. After etching, acetone is used to rinse and remove the photoresist to obtain a quantum voltage chip.

[0071] A schematic diagram of the quantum voltage chip is shown below. Figure 4 As shown in the figure, the meandering line structure connects two linear substrate steps (microscopically step grain boundaries) with different step angles in series. This can broaden the range of operating parameters and optimize the voltage stability and noise margin of the quantum voltage chip by complementing the characteristics of the two Josephson arrays.

[0072] Example 3

[0073] A method for fabricating a high-temperature superconducting quantum voltage chip includes the following steps:

[0074] S1. A UV photoresist was spin-coated on the surface of a single-crystal lanthanum aluminate substrate at a speed of 5000 r / min for 30 s. After coating, the substrate was placed on an 80℃ heating stage for 10 min. After heating, the substrate was placed on a copper metal plate for 2 min to cool down. UV lithography was used, and a transparent mask with a stepped grain boundary pattern was used for UV exposure. After exposure, the substrate was developed with a developer to remove the photoresist from the exposed area. The area where the photoresist was removed was etched with an argon ion reactive ion beam. After etching, the photoresist was removed by rinsing with acetone to obtain a single-crystal lanthanum aluminate substrate with a stepped structure and a step angle of 60°.

[0075] The reactive ion beam etching setup had an ion source screen voltage of 530 eV, an acceleration voltage of 200 V, an oxygen flow rate of 8 sccm, an ion bombardment direction at an angle of 90° to the single crystal substrate, and an etching time of 80 min.

[0076] S2. Using silver paste, the above-mentioned single-crystal lanthanum aluminate substrate with a stepped structure is uniformly attached to the heating stage of the pulsed laser deposition chamber. The substrate surface is parallel to the target material. A yttrium barium copper oxide thin film is epitaxially grown on the substrate surface using pulsed laser deposition. The specific parameters of pulsed laser deposition are: laser wavelength 248nm, laser energy 200mJ, laser pulse frequency 1Hz, heating stage temperature 700℃, oxygen atmosphere 20Pa, and distance between the target material and the heating stage 15cm. The growth thickness of the yttrium barium copper oxide thin film is monitored using a high-energy electron diffraction device until the thickness of the yttrium barium copper oxide thin film reaches 150nm.

[0077] S3. Using magnetron sputtering, a 10nm thick titanium layer as a buffer layer and a 50nm thick gold layer as an electrode layer are sequentially grown on the surface of a yttrium barium copper oxide thin film through a perforated metal mask. The yttrium barium copper oxide thin film with gold electrodes is removed from the chamber, and ultraviolet photoresist is spin-coated on the surface of the yttrium barium copper oxide thin film at a speed of 5000r / min for 30s. After the photoresist coating is completed, it is placed on an 80℃ heating stage for 10min. After heating, it is placed on a copper metal plate for 2min to cool down. Ultraviolet lithography is used, with a transparent mask containing a meandering line structure pattern. After the meandering line structure and the step grain boundaries are perpendicularly aligned, ultraviolet exposure is performed. After exposure, development is performed using a developer to remove the photoresist from the exposed part. Argon ion reactive ion beam is used to etch the part where the photoresist has been removed. After etching, acetone is used to rinse and remove the photoresist to obtain a quantum voltage chip.

[0078] A schematic diagram of the quantum voltage chip is shown below. Figure 5 As shown in the figure, the meandering line structure crosses the ring substrate steps (microscopically, step grain boundaries) vertically. This allows for the connection of a large number of Josephson junctions within a limited area, which helps to improve the cumulative output of quantum voltage and increase integration density.

[0079] Example 4

[0080] A method for fabricating a high-temperature superconducting quantum voltage chip includes the following steps:

[0081] S1. A UV photoresist was spin-coated on the surface of a single-crystal lanthanum aluminate substrate at a speed of 5000 r / min for 30 s. After coating, the substrate was placed on an 80℃ heating stage for 10 min. After heating, the substrate was placed on a copper metal plate for 2 min to cool down. UV lithography was used, and a transparent mask with a stepped grain boundary pattern was used for UV exposure. After exposure, the substrate was developed with a developer to remove the photoresist from the exposed area. The area where the photoresist was removed was etched with an argon ion reactive ion beam. After etching, the photoresist was removed by rinsing with acetone to obtain a single-crystal lanthanum aluminate substrate with a stepped structure and a step angle of 60°.

[0082] The reactive ion beam etching setup had an ion source screen voltage of 535 eV, an acceleration voltage of 210 V, an oxygen flow rate of 8 sccm, an ion bombardment direction at an angle of 90° to the single-crystal substrate, and an etching time of 90 min.

[0083] S2. Using silver paste, the above-mentioned single-crystal lanthanum aluminate substrate with a stepped structure is uniformly attached to the heating stage of the pulsed laser deposition chamber. The substrate surface is parallel to the target material. A yttrium barium copper oxide thin film is epitaxially grown on the substrate surface using pulsed laser deposition. The specific parameters of pulsed laser deposition are: laser wavelength 248nm, laser energy 300mJ, laser pulse frequency 5Hz, heating stage temperature 900℃, oxygen atmosphere 100Pa, and distance between the target material and the heating stage 28cm. The growth thickness of the yttrium barium copper oxide thin film is monitored using a high-energy electron diffraction device until the thickness of the yttrium barium copper oxide thin film reaches 150nm.

[0084] S3. Using magnetron sputtering, a 15nm thick titanium layer as a buffer layer and a 55nm thick gold layer as an electrode layer are sequentially grown on the surface of a yttrium barium copper oxide thin film through a perforated metal mask. The yttrium barium copper oxide thin film with gold electrodes is removed from the chamber, and ultraviolet photoresist is spin-coated on the surface of the yttrium barium copper oxide thin film at a speed of 5000r / min for 30s. After the photoresist coating is completed, it is placed on an 80℃ heating stage for 10min. After heating, it is placed on a copper metal plate for 2min to cool down. Ultraviolet lithography is used, with a transparent mask containing a meandering line structure pattern. After the meandering line structure and the step grain boundaries are perpendicularly aligned, ultraviolet exposure is performed. After exposure, development is performed using a developer to remove the photoresist from the exposed part. Argon ion reactive ion beam is used to etch the part where the photoresist has been removed. After etching, acetone is used to rinse and remove the photoresist to obtain a quantum voltage chip.

[0085] A schematic diagram of the quantum voltage chip is shown below. Figure 6As shown in the figure, the substrate steps (microscopically step grain boundaries) have a linear morphology that extends radially from the central region to the periphery. The meandering line structure vertically intersects multiple radial linear substrate steps, which ensures that the current density carried by each Josephson array is basically consistent, which is beneficial to the stability of the output voltage of the quantum voltage chip.

[0086] As can be seen from Examples 1 to 4, the fabrication method of the high-temperature superconducting quantum voltage chip provided by the present invention is more flexible, has a higher degree of array integration, and is lower in cost.

[0087] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a high-temperature superconducting quantum voltage chip, characterized in that, include: A single-crystal substrate is provided, and a stepped structure is etched on the surface of the single-crystal substrate to obtain a single-crystal substrate with a stepped structure; A yttrium barium copper oxide thin film is epitaxially grown on the surface of the single crystal substrate with the stepped structure. The yttrium barium copper oxide thin film forms step grain boundaries at the edge junctions of the stepped structure, and each step grain boundary constitutes a Josephson junction. A buffer layer and an electrode layer are disposed on the surface of the yttrium barium copper oxide thin film, and the yttrium barium copper oxide thin film is patterned to form a meandering line structure to obtain a quantum voltage chip. The meandering line structure crosses the step grain boundary and connects multiple Josephson junctions in series.

2. The method for fabricating a high-temperature superconducting quantum voltage chip according to claim 1, characterized in that, The single-crystal substrate includes a single-crystal strontium titanate substrate or a single-crystal lanthanum aluminate substrate.

3. The method for fabricating a high-temperature superconducting quantum voltage chip according to claim 1, characterized in that, The stepped grain boundaries include one or both of linear stepped grain boundaries and annular stepped grain boundaries.

4. The method for fabricating a high-temperature superconducting quantum voltage chip according to claim 1, characterized in that, The etching is performed using reactive ion beam etching, wherein the ion source screen voltage is 530–535 eV, the accelerating voltage is 200–210 V, the oxygen flow rate is 1–8 sccm, the angle between the ion bombardment direction and the single crystal substrate is 60°–90°, and the etching time is 80–90 min.

5. The method for fabricating a high-temperature superconducting quantum voltage chip according to claim 1, characterized in that, The epitaxial growth is performed using pulsed laser deposition, wherein the laser energy is 200–300 mJ, the laser pulse frequency is 1–5 Hz, the heating stage temperature is 700–900 °C, and the oxygen atmosphere is 20–100 Pa.

6. The method for fabricating a high-temperature superconducting quantum voltage chip according to claim 1, characterized in that, The yttrium barium copper oxide thin film is epitaxially grown to a thickness of 150–200 nm.

7. The method for fabricating a high-temperature superconducting quantum voltage chip according to claim 1, characterized in that, The buffer layer is a titanium layer; and / or The electrode layer is a gold layer.

8. The method for fabricating a high-temperature superconducting quantum voltage chip according to claim 1, characterized in that, The thickness of the buffer layer is 10–15 nm; and / or The thickness of the electrode layer is 50–55 nm.

9. The method for fabricating a high-temperature superconducting quantum voltage chip according to claim 1, characterized in that, The meandering line structure and the stepped grain boundary intersect each other perpendicularly.

10. A quantum voltage chip, characterized in that, Prepared by the preparation method according to any one of claims 1 to 9, comprising: A single-crystal substrate with a stepped surface structure; A yttrium barium copper oxide thin film is epitaxially grown on the surface of the single crystal substrate, and step grain boundaries are formed at the edges of the step structure, with each step grain boundary constituting a Josephson junction; The meandering line structure is formed by patterning the yttrium barium copper oxide thin film, the meandering line structure spans the stepped grain boundaries and connects multiple Josephson junctions in series.

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