Self-cooling liquid cooling type 2.5 D chip co-packaging method

Abstract

The invention discloses a self-cooling liquid cooling type 2.5 D chip co-packaging method, and belongs to the technical field of semiconductor packaging. According to the method, a chip packaging structure containing a high-aspect-ratio microchannel structure and a first bonding piece is prepared by adopting a CoWoS-TIV manufacturing process, then a chip packaging cover plate structure containing a manifold structure and a second bonding piece is prepared, and the chip packaging cover plate structure and the second bonding piece are packaged. The two parts are bonded to form a sealed cavity containing a micro-channel system; then, a TIM layer is arranged on the end face of the cover plate, an MEMS liquid cooling chip is attached to the end face of the cover plate, electric interconnection is achieved through a fan-out type conductive structure, and a total packaging body is formed through debonding, buckling and overall molding packaging. The CoWoS-TIV manufacturing process is used for replacing TSV, the cost and complexity are reduced, the MEMS liquid cooling chip and the micro-channel system are integrated, self-cooling is achieved through direct contact between cooling liquid and a chip heat source, and 3000-watt high-power-consumption stable operation is supported.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology and relates to a self-cooling liquid-cooled 2.5D chip co-packaging method. Specifically, this invention achieves self-cooling function by integrating a microfluidic heat dissipation system, and is suitable for high heat density scenarios such as artificial intelligence (AI) computing chips, optical communication modules, and high-performance computing (HPC) chips. Background Technology

[0002] Currently, 2.5D packaging technologies such as TSMC's CoWoS (Chip-on-Wafer-on-Substrate) achieve heterogeneous integration of multiple chips through silicon interposers, but rely on TSV (Through Silicon Vias) processes, which suffer from high equipment costs and declining yields as the interposer area increases. Meanwhile, in scenarios such as high-performance chips and mobile devices, traditional heat dissipation solutions, such as air cooling, passive cooling, or basic microfluidic liquid cooling, typically have a heat flux density handling capacity of less than 200W / cm², making it difficult to meet the heat dissipation requirements of next-generation AI chips exceeding 500W / cm². Local hotspot temperatures on the chip can reach above 85°C, leading to performance throttling and decreased reliability, failing to meet the heat dissipation requirements of high-density packaged chips. Furthermore, traditional heat dissipation solutions require independent installation space, have low integration with chip packaging, and external heat dissipation modules occupy large spaces and generate noise, contradicting the thinner and lighter requirements of mobile devices and edge computing devices.

[0003] In existing technologies, such as the "IMEC-Si" cooling mechanism developed by TSMC, direct liquid contact cooling is used, but it still has limitations such as low integration and high cost. Although MEMS liquid cooling technology has potential, it has not yet been deeply integrated with 2.5D packaging. Summary of the Invention

[0004] The purpose of this invention is to provide a self-cooling liquid-cooled 2.5D chip co-packaging method, which integrates MEMS liquid-cooled chip and microfluidic system into the packaging structure to prepare a 2.5D co-package with integrated electrical interconnection and liquid cooling functions, thereby solving the above-mentioned technical problems.

[0005] The objective of this invention is achieved through the following technical solution: A self-cooled liquid-cooled 2.5D chip co-packaging method includes the following steps: S1. A chip package structure comprising SoC, HBM and ASIC is fabricated using the CoWoS-TIV ​​process. A high aspect ratio microchannel structure is formed on the upper surface of the chip package structure. The microchannel structure is precisely positioned to correspond to the heat-generating core areas of the SoC and HBM. A ring-shaped first bonding member is provided on the upper surface of the package structure surrounding the microchannel structure. S2. Prepare a chip packaging cover structure, wherein the chip packaging cover structure is formed by processing a silicon wafer adapted to the packaging structure to form a manifold structure, and a second bonding member is provided on the periphery of the manifold structure corresponding to the position of the first bonding member, wherein the second bonding member is materially compatible with the first bonding member and structurally adapted. S3. Align the chip packaging cover structure with the chip packaging structure. First, use an adhesive to bond the second bonding component to the first bonding component. Then, use a eutectic bonding process to seal and fix the second bonding component to the first bonding component, forming a sealed cavity. Make I / O holes at preset positions on the chip packaging cover structure. The I / O holes are connected to the manifold structure and serve as the coolant inlet and outlet. The microchannel structure, manifold structure, and I / O holes form a complete microfluidic system. S4. A thermal interface material is coated on the end face of the chip packaging cover structure around the I / O hole to form a TIM layer. The MEMS liquid cooling chip is then mounted on the TIM layer so that the inlet and outlet of the MEMS liquid cooling chip are precisely aligned with the I / O hole and sealed and connected. S5. A fan-out conductive structure is fabricated using the RDL process. BGA balls are implanted at the preset pads at the bottom of the fan-out conductive structure, and a conductive package structure is fabricated at the preset pads at the top of the fan-out conductive structure. S6. Remove the temporary bonding adhesive layer and glass substrate of the chip packaging structure, align and fix the chip packaging structure and the conductive packaging structure, and use the molding packaging process to encapsulate the entire structure as a whole to form a 2.5D co-package with integrated electrical interconnection and liquid cooling functions.

[0006] As a further improvement of the present invention, the aspect ratio of the microchannel structure in S1 is 10:1 to 20:1, the channel width is 10-100μm, the depth is 100-500μm, and the cross-section is a rectangular, trapezoidal or arc-shaped structure.

[0007] As a further improvement of the present invention, the first bonding member in S1 is a glass wall panel.

[0008] As a further improvement of the present invention, the preparation of the chip packaging structure in S1 further includes the following steps: S101. Select a glass substrate and coat its surface with a temporary bonding adhesive layer. S102. Using TIV technology, the copper pillars are inserted into the temporary bonding adhesive layer according to the preset positions of the copper pillars. S103. Use epoxy resin encapsulation material to mold and encapsulate the copper pillar to form the first encapsulation layer. After curing, grind the upper surface until the upper end of the copper pillar is exposed. S104. A chip mounting layer is fabricated on the exposed copper pillar end face using microbound technology. The SoC, HBM and ASIC are then mounted and fixed on the chip mounting layer. S105. Use epoxy resin encapsulation material to mold and encapsulate to form a second encapsulation layer covering SoC, HBM and ASIC. After curing, polish the upper surface until it is flat. S106. Deposit a first etch mask layer on the surface of the second encapsulation layer. The first etch mask layer is made of silicon dioxide or silicon nitride and has a thickness of 1-3 μm. S107. Photoresist is coated on the surface of the first etch mask layer to form a first photoresist layer, and the microchannel pattern is transferred by photolithography. The first etch mask layer is etched with plasma according to the microchannel pattern to etch the microchannel pattern on the first etch mask layer, and then the photoresist is removed. S108. Based on the microchannel pattern on the first etch mask layer, a microchannel structure is formed by a Bosch deep reactive ion etching process. After etching, residual photoresist and etching byproducts are removed. S109. A first passivation layer is formed on the surface of the first etch mask layer and the microchannel structure, and a first bonding element is disposed on the first passivation layer around the microchannel structure.

[0009] As a further improvement of the present invention, the manifold structure in S2 is processed by dry etching or wet etching processes, and the cross-section is a rectangular, circular or arc structure with a depth-to-width ratio of 10:1 to 20:1.

[0010] As a further improvement of the present invention, the preparation of the chip packaging cover structure in S2 further includes the following steps: S201. Deposit a second etch mask layer on the surface of a silicon wafer. The second etch mask layer is made of silicon dioxide, silicon nitride, or titanium oxide and has a thickness of 1-2 μm. S202: Photoresist is coated on the surface of the second etch mask layer to form a second photoresist layer. The manifold structure pattern is transferred by photolithography, and the exposure accuracy is controlled within ±1μm. S203. Using the second photoresist layer as a mask, the pattern is transferred to the second etching mask layer by plasma dry etching. S204. Remove the second photoresist layer and vacuum dry; S205. Using the second etch mask layer as a shield, the silicon wafer is vertically etched using the Bosch process of DRIE to form a manifold structure. After etching, residual impurities are removed. S206. A second passivation layer is formed on the surface of the second etch mask layer and the manifold structure, and a second bonding element is disposed on the second passivation layer around the manifold structure.

[0011] As a further improvement of the present invention, the eutectic bonding temperature of S3 is 200-300℃, and the I / O holes are fabricated by laser drilling process.

[0012] As a further improvement of the present invention, the TIM material mentioned in S4 is a silicone grease with a thermal conductivity of 5 W / m·K, and the MEMS liquid cooling chip is based on a piezoelectric micropump driving the coolant, including a piezoelectric micropump, a liquid cooling film integrating microchannels and coolant, and a liquid cooling drive chip.

[0013] The above technical solution has the following beneficial effects: 1. By adopting the CoWoS-TIV ​​process to replace the traditional TSV technology, high-density integration and efficient electrical interconnection of SoC, HBM and ASIC are achieved, ensuring the stability and timeliness of signal transmission between chips, while reducing packaging costs and process complexity.

[0014] 2. Innovatively integrates MEMS liquid-cooled chip and microfluidic system. The microchannel structure precisely corresponds to the core heat-generating area of ​​the chip. Self-cooling is achieved by the coolant directly contacting the heat source of the chip. The thermal resistance is reduced to 4°C / W, with no local overheating. It can support the chip to operate stably under high power consumption of 3000W. The theoretical heat dissipation efficiency reaches 3000W / cm², far exceeding traditional air cooling (50-200W / cm²) and traditional liquid cooling (500-1000W / cm²).

[0015] 3. MEMS liquid-cooled chips consume only 1W / cm², are millimeter-sized, have no moving parts and are noiseless. Compared with traditional air cooling (5-50W fan power consumption, 20-50dB noise) and traditional liquid cooling (10-100W pump power consumption, 10-30dB noise), they are more suitable for high-performance chips, mobile devices, biometric detection chips, optical communication modules and other scenarios that require low power consumption, small size and low noise.

[0016] 4. The precise matching of the first and second bonding components and the eutectic bonding sealing process ensure the sealing performance of the microfluidic system and prevent coolant leakage from affecting chip operation; the passivation layer design on the surface of the microchannel and manifold structure improves surface smoothness and corrosion resistance and reduces coolant flow resistance.

[0017] 5. A fan-out conductive structure is adopted to realize the fan-out and interconnection of electrical signals. Combined with integrated molding packaging process, the stability of the overall packaging structure is ensured, and the synergistic effect of electrical performance and heat dissipation performance is achieved, taking into account integration, reliability and heat dissipation efficiency. Attached Figure Description

[0018] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are merely exemplary, and those skilled in the art can derive other embodiments based on the provided drawings without creative effort.

[0019] The structures, proportions, sizes, etc. shown in this specification are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0020] Figure 1 This is a schematic diagram of the overall process of the present invention.

[0021] Figure 2 This is a schematic diagram of the fabrication process of the chip packaging structure provided by the present invention.

[0022] Figure 3 This is a schematic diagram of the fabrication process of the chip packaging cover structure provided by the present invention.

[0023] Figure 4 This is a schematic diagram of the chip packaging cover structure and the chip packaging structure assembly structure provided by the present invention.

[0024] Figure 5 The diagram shows the chip packaging cover structure, chip packaging structure, and MEMS liquid-cooled chip assembly structure provided by the present invention.

[0025] Figure 6 This is a schematic diagram of the fan-out conductive structure, BGA ball, and conductive package structure provided by the present invention.

[0026] Figure 7 This is a schematic diagram of the overall structure of the present invention.

[0027] In the picture: 101. Glass substrate; 102. Temporary bonding adhesive layer; 103. Copper pillar; 104. First encapsulation layer; 105. Chip mounting layer; 106. SoC; 107. HBM; 108. ASIC; 109. Second encapsulation layer; 110. First etch mask layer; 111. Photoresist layer; 112. Microchannel structure; 113. First passivation layer; 114. First bonding element; 201. Silicon wafer; 202. Second etch mask layer; 203. Second photoresist layer; 204. Manifold structure; 205. Second passivation layer; 206. Second bonding element; 207. I / O hole; 208. TIM layer; 3. MEMS liquid-cooled chips; 401. Fan-out conductive structure; 402. BGA ball; 403. Conductive packaging structure; 5. Overall packaging structure. Detailed Implementation

[0028] In this invention, unless otherwise stated, directional terms such as "upper," "lower," "top," and "bottom" are generally used in relation to the direction shown in the accompanying drawings, or in relation to the vertical, perpendicular, or gravitational direction of the component itself; similarly, for ease of understanding and description, "inner" and "outer" refer to the inner and outer contours of each component itself, but the above directional terms are not intended to limit this invention.

[0029] First embodiment, such as Figure 1 As shown, a self-cooled liquid-cooled 2.5D chip co-packaging method includes the following steps: S1. The target chip package structure is fabricated using the CoWoS-TIV ​​(Wafer-Level System Integration - Through-Silicon Via) process. This process enables high-density integration and efficient electrical interconnection of SoC, HBM, and ASIC, ensuring the stability and timeliness of signal transmission between chips. After the package structure is formed, a high aspect ratio microchannel structure is formed on its upper surface through photolithography and deep etching processes. The aspect ratio is preferably 10:1 to 20:1, the channel width is 10-100μm, and the depth is 100-500μm. Mass production is achieved through wafer-level processes to balance heat dissipation area and structural strength.

[0030] The microchannel structure is precisely positioned to correspond to the heat-generating core areas of the SoC and HBM. It can be positioned near or directly in contact with the top surface, ensuring that heat dissipated during operation is rapidly conducted through the packaging substrate to the microchannel structure, laying the foundation for subsequent liquid cooling. The microchannel cross-section can be rectangular, trapezoidal, or arc-shaped, all achieving the same heat dissipation performance.

[0031] On the upper surface of the packaging structure surrounding the microchannel structure, an annular first bonding component is set by sputtering. The first bonding component is a glass wall plate with a raised design. Its core function is to provide reliable bonding sites for the subsequent microchannel sealing structure, ensuring the sealing performance of the coolant when it flows in the microchannel and preventing leakage from affecting the chip's operation.

[0032] Specifically, such as Figure 2 As shown, the fabrication method of the chip packaging structure in S1 is as follows: S101. Select a glass substrate 101 with satisfactory flatness and high temperature resistance, and uniformly coat a temporary bonding adhesive layer 102 on its surface. The adhesive layer material can be a pyrolytic or UV-debonding adhesive, which is used to temporarily fix the subsequent structure. The subsequent debonding can be achieved by heating or UV irradiation.

[0033] S102. Using TIV (Through-InFO-Via) technology, copper pillars 103 are inserted into the temporary bonding adhesive layer 102 according to the preset positions of the copper pillars. Using TIV technology as a vertical interconnect can provide a lower insertion loss path than traditional through-silicon vias (TSVs).

[0034] S103. Using epoxy resin encapsulation material, the copper pillar 103 is completely encapsulated through molding encapsulation process to form the first encapsulation layer 104. After the encapsulation material is cured, the upper surface of the first encapsulation layer 104 is polished by mechanical grinding combined with chemical polishing process until the upper end of the copper pillar 103 is completely exposed to ensure the reliability of subsequent electrical connection.

[0035] S104. On the exposed copper pillar end face of the first packaging layer 104, a chip mounting layer 105 is prepared that is precisely aligned with and electrically connected to the copper pillar 103. The chip mounting layer 105 is prepared using the microbound process. Subsequently, the SoC 106, HBM 107 and ASIC 108 are mounted on the chip mounting layer 105 in an orderly manner according to the preset circuit layout and fixed by reflow soldering or thermal bonding process to ensure the electrical signal conduction and mechanical stability between each chip and the copper pillar.

[0036] S105. On the chip mounting layer 105 and the surface of each chip, epoxy resin encapsulation material is used to mold and encapsulate to form a second encapsulation layer 109. During encapsulation, pressure and temperature are controlled to ensure complete coverage of SoC106, HBM107 and ASIC108, while avoiding chip damage due to pressure. After curing, the upper surface is polished to a smooth surface, laying the foundation for subsequent mask layer preparation.

[0037] S106. Silicon dioxide (SiO2) is deposited on the surface of the second packaging layer 109 as the first etching mask layer 110 by PECVD or thermal oxidation process, with the thickness controlled at 1-3μm. Silicon nitride can also be used as an equivalent mask material to improve the corrosion resistance during the etching process.

[0038] S107. A first photoresist layer 111 is formed by uniformly coating photoresist on the surface of the first etch mask layer 110. The coating, exposure, and development processes are completed sequentially using a photolithography process to accurately transfer the preset microchannel pattern onto the first photoresist layer 111. The exposure accuracy is controlled at the micrometer level to ensure that the pattern accurately corresponds to the SoC and HBM heat dissipation areas. Then, the first etch mask layer 110 is etched with plasma according to the microchannel pattern to etch the microchannel pattern onto the first etch mask layer 110. After that, the photoresist is removed.

[0039] S108. Based on the microchannel pattern on the first etch mask layer 110, vertical etching is performed using the Bosch process of deep reactive ion etching (DRIE), with the aspect ratio controlled between 10:1 and 20:1, to form a microchannel structure 112. After etching, a plasma cleaning process is used to remove residual photoresist and etching byproducts to avoid residual impurities affecting the subsequent passivation effect.

[0040] S109. A first passivation layer 113 is formed on the surface of the first etch mask layer 110 and the microchannel structure 112 by plasma-enhanced chemical vapor deposition process, which improves the surface smoothness and corrosion resistance and reduces the flow resistance of coolant. A first bonding member 114 is then set on the first passivation layer 113 on the periphery of the microchannel structure 112 to provide sealing sites for subsequent cover plate bonding.

[0041] S2. Fabrication of the chip packaging cover structure. The chip packaging cover structure uses a silicon wafer adapted to the packaging structure. A manifold structure is fabricated using dry etching and wet etching processes. This manifold structure consists of several manifolds used for the distribution and convergence of coolant. Its channel dimensions match the microchannel structure, and the cross-section can be rectangular, circular, or other isomorphic to meet the fluid flow requirements. A second bonding member is disposed around the manifold structure at the position corresponding to the first bonding member. The second bonding member also uses a glass wall panel.

[0042] Specifically, such as Figure 3 As shown, the fabrication method of the chip packaging cover structure in S2 is as follows: S201. A second etching mask layer 202 is formed by depositing silicon dioxide (SiO2) on the surface of silicon wafer 201 through PECVD or thermal oxidation process. The thickness is controlled at 1-2μm, which can effectively prevent damage to the silicon wafer body by subsequent etching processes. Alternatively, silicon nitride or titanium oxide can be used as equivalent mask materials to improve the etching selectivity and stability of the mask layer.

[0043] S202. Photoresist is uniformly coated on the surface of the second etch mask layer 202 to form a second photoresist layer 203 with uniform thickness. The coating thickness is controlled at 3-5 μm according to the exposure requirements. The coating, exposure, and development processes are completed sequentially using photolithography to accurately transfer the preset manifold structure pattern onto the second photoresist layer 203. The exposure accuracy is controlled at ±1 μm to ensure that the manifold pattern is precisely aligned with the microchannel structure 112 on the chip packaging structure.

[0044] S203. Using plasma dry etching process, the manifold structure pattern is accurately transferred to the second etching mask layer 202 using the formed second photoresist layer 203 as a mask. During the etching process, the etching rate and time are controlled to avoid over-etching and damage to the mask layer.

[0045] S204. After etching, the second photoresist layer 203 is removed by oxygen plasma cleaning process, and residual photoresist debris and organic impurities on the surface are removed at the same time. After cleaning, vacuum drying is performed to ensure that the surface of the second etch mask layer 202 is clean and dry.

[0046] S205. Using the formed second etch mask layer 202 as a shield, the silicon wafer 201 is vertically etched using the DRIE Bosch process, with the aspect ratio strictly controlled between 10:1 and 20:1, forming a manifold structure 204 adapted to the microchannel structure 112. Its cross-section can be rectangular, trapezoidal, or other isomorphic configurations to meet the requirements for coolant distribution and convergence. After etching, a mixed-gas plasma cleaning process is used to thoroughly remove residual photoresist and byproducts such as silicon slag generated during etching, preventing impurities from affecting subsequent passivation and bonding quality.

[0047] S206. A second passivation layer 205 is formed on the surface of the second etch mask layer 202 and the manifold structure 204 using plasma-enhanced chemical vapor deposition (PECVD). The thickness is controlled between 0.5-1 μm, effectively improving surface smoothness and resistance to coolant corrosion, and reducing fluid flow resistance. On the second passivation layer 205 surrounding the manifold structure 204, a ring-shaped second bonding member 206 is provided at the position corresponding to the first bonding member 114. The structure can adopt a raised design to provide reliable sites for subsequent sealing bonding of the cover plate and the packaging structure.

[0048] S3, such as Figure 4 As shown, the chip packaging cover structure is aligned with the chip packaging structure, and the second bonding member 206 is glued to the first bonding member 114 using adhesive. Then, a eutectic bonding process is used to seal and fix the second bonding member 206 and the first bonding member 114, so that the manifold structure 204 and the microchannel structure 112 are precisely connected and form a sealed cavity. Subsequently, I / O holes 207 are made at preset positions on the chip packaging cover structure using laser drilling. The I / O holes 207 are connected to the manifold structure 204 and serve as the coolant inlet and outlet. The microchannel structure 112, the manifold structure 204, and the I / O holes 207 together form a complete microfluidic system, providing a pathway for coolant circulation and heat dissipation.

[0049] S4, such as Figure 5As shown, a thermal interface material (TIM) is uniformly coated on the end face of the chip packaging cover structure surrounding the I / O hole 207 to form a TIM layer 208. The TIM material used is a silicone grease with a thermal conductivity of 5 W / m·K. The MEMS liquid-cooled chip 3 is then mounted on the TIM layer 208 and fixed using a thermally conductive adhesive or precision pressing process, ensuring that the inlet and outlet of the MEMS liquid-cooled chip 3 precisely correspond to and are sealed to the I / O hole 207. In this solution, the MEMS liquid-cooled chip 3 is based on a piezoelectric micropump driving the coolant, utilizing the inverse piezoelectric effect to generate unidirectional liquid flow, forming ultra-low power consumption and ultra-quiet active heat dissipation. Its structure includes a piezoelectric micropump, a liquid-cooled film integrating microchannels and coolant, and a liquid-cooled driving chip. Cooling is achieved through phase change, with a theoretical heat dissipation efficiency of 3000 W / cm² and a power consumption of only 1 W / cm². The overall size is in the millimeter range, suitable for high-density packaging requirements.

[0050] S5, such as Figure 6 As shown, a fan-out conductive structure 401 is fabricated using RDL (Rewiring Layer) technology. Electroplated copper, aluminum, or alloy materials can be selected. Wiring patterns are formed through photolithography, etching, and deposition processes to achieve fan-out and interconnection of electrical signals. Alternatively, sputtering can be used to form the RDL structure as an equivalent implementation. BGA balls 402 are implanted into the pre-set pads at the bottom of the fan-out conductive structure 401 using a ball-mounting machine. A conductive package structure 403 is fabricated at the pre-set pads at the top of the fan-out conductive structure 401. Its size and spacing are precisely matched to the pads at the bottom of the chip package structure, providing a foundation for subsequent electrical connections.

[0051] S6, such as Figure 7 As shown, the temporary bonding adhesive layer is debonded by heating or ultraviolet irradiation, removing the glass substrate 101 and the temporary bonding adhesive layer 102. Then, the chip packaging structure is aligned with the conductive packaging structure 403 and fastened together. Precision pressing and reflow soldering processes are used to achieve electrical conductivity and mechanical fixation between the two. Subsequently, a molding packaging process is employed, using high-temperature resistant, low-stress epoxy resin as the packaging material, to encapsulate the conductive packaging structure at the top of the fan-out conductive structure 401, the chip packaging structure, the cover plate, and the MEMS liquid-cooled chip 3, forming the overall packaging structure 5. During the packaging process, molding pressure and temperature are controlled to prevent damage to the internal structure or sealing failure, ultimately forming a 2.5D co-package integrating electrical interconnection and liquid cooling functions, ensuring overall structural stability and achieving synergistic performance of electrical and heat dissipation capabilities.

[0052] The performance parameters of the MEMS liquid-cooled chip 3 used in this invention are compared with those of traditional air-cooled and traditional liquid-cooled chips as follows:

[0053] This demonstrates that MEMS liquid-cooled chips have low power consumption and small size, making them more suitable for applications such as biosensor chips and optical communication modules, significantly improving overall heat dissipation performance.

[0054] This invention innovatively integrates a MEMS liquid-cooled chip and a microfluidic system based on traditional 2.5D packaging. By using the CoWoS-TIV ​​process instead of TSV, cost and complexity are reduced. The overall package structure includes SoC (System-on-a-Chip), HBM (High-bandwidth Memory), ASIC (Application-Specific Integrated Circuit), thermal interface material (TIM), etc., and direct heat dissipation is achieved through microfluidics, reducing thermal resistance to 4°C / W, eliminating localized overheating, and supporting stable chip operation at high power consumption of 3000 watts.

[0055] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, functions, devices, components, and / or combinations thereof.

[0056] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0057] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for co-packaging a self-cooled liquid-cooled 2.5D chip, characterized in that, Includes the following steps: S1. A chip package structure including SoC, HBM and ASIC is fabricated using the CoWoS-TIV ​​process. A high aspect ratio microchannel structure is formed on the upper surface of the chip package structure. The microchannel structure is precisely positioned to correspond to the heat-generating core areas of the SoC and HBM. A ring-shaped first bonding member is provided on the upper surface of the package structure surrounding the microchannel structure. S2. Prepare a chip packaging cover structure, wherein the chip packaging cover structure is formed by processing a silicon wafer adapted to the packaging structure to form a manifold structure, and a second bonding member is provided on the periphery of the manifold structure corresponding to the position of the first bonding member, wherein the second bonding member is materially compatible with the first bonding member and structurally adapted. S3. Align the chip packaging cover structure with the chip packaging structure. First, use an adhesive to bond the second bonding component to the first bonding component. Then, use a eutectic bonding process to seal and fix the second bonding component to the first bonding component, forming a sealed cavity. Make I / O holes at preset positions on the chip packaging cover structure. The I / O holes are connected to the manifold structure and serve as the coolant inlet and outlet. The microchannel structure, manifold structure, and I / O holes form a complete microfluidic system. S4. A thermal interface material is coated on the end face of the chip packaging cover structure around the I / O hole to form a TIM layer. The MEMS liquid cooling chip is then mounted on the TIM layer so that the inlet and outlet of the MEMS liquid cooling chip are precisely aligned with the I / O hole and sealed and connected. S5. A fan-out conductive structure is fabricated using the RDL process. BGA balls are implanted at the preset pads at the bottom of the fan-out conductive structure, and a conductive package structure is fabricated at the preset pads at the top of the fan-out conductive structure. S6. Remove the temporary bonding adhesive layer and glass substrate of the chip packaging structure, align and fix the chip packaging structure and the conductive packaging structure, and use the molding packaging process to encapsulate the entire structure as a whole to form a 2.5D co-package with integrated electrical interconnection and liquid cooling functions.

2. The self-cooled liquid-cooled 2.5D chip co-packaging method according to claim 1, characterized in that, The microchannel structure described in S1 has a depth-to-width ratio of 10:1 to 20:1, a channel width of 10-100μm, a depth of 100-500μm, and a rectangular, trapezoidal, or arc-shaped cross-section.

3. The self-cooled liquid-cooled 2.5D chip co-packaging method according to claim 1, characterized in that, In S1, the first bonding component is a glass wall panel.

4. The self-cooled liquid-cooled 2.5D chip co-packaging method according to claim 1, characterized in that, The fabrication of the chip packaging structure in S1 also includes the following steps: S101. Select a glass substrate and coat its surface with a temporary bonding adhesive layer. S102. Using TIV technology, the copper pillars are inserted into the temporary bonding adhesive layer according to the preset positions of the copper pillars. S103. Use epoxy resin encapsulation material to mold and encapsulate the copper pillar to form the first encapsulation layer. After curing, grind the upper surface until the upper end of the copper pillar is exposed. S104. A chip mounting layer is fabricated on the exposed copper pillar end face using microbound technology. The SoC, HBM and ASIC are then mounted and fixed onto the chip mounting layer. S105. Use epoxy resin encapsulation material to mold and encapsulate to form a second encapsulation layer covering SoC, HBM and ASIC. After curing, polish the upper surface until it is flat. S106. Deposit a first etch mask layer on the surface of the second encapsulation layer. The first etch mask layer is made of silicon dioxide or silicon nitride and has a thickness of 1-3 μm. S107. Photoresist is coated on the surface of the first etch mask layer to form a first photoresist layer, and the microchannel pattern is transferred by photolithography. The first etch mask layer is etched with plasma according to the microchannel pattern to etch the microchannel pattern on the first etch mask layer, and then the photoresist is removed. S108. Based on the microchannel pattern on the first etch mask layer, a microchannel structure is formed by a Bosch deep reactive ion etching process. After etching, residual photoresist and etching byproducts are removed. S109. A first passivation layer is formed on the surface of the first etch mask layer and the microchannel structure, and a first bonding element is disposed on the first passivation layer around the microchannel structure.

5. The self-cooled liquid-cooled 2.5D chip co-packaging method according to claim 1, characterized in that, The manifold structure described in S2 is processed by dry etching or wet etching processes, and has a rectangular, circular or arc-shaped cross-section with a depth-to-width ratio of 10:1 to 20:

1.

6. The self-cooled liquid-cooled 2.5D chip co-packaging method according to claim 1, characterized in that, The fabrication of the chip packaging cover structure in S2 also includes the following steps: S201. Deposit a second etch mask layer on the surface of a silicon wafer. The second etch mask layer is made of silicon dioxide, silicon nitride, or titanium oxide and has a thickness of 1-2 μm. S202: Photoresist is coated on the surface of the second etch mask layer to form a second photoresist layer. The manifold structure pattern is transferred by photolithography, and the exposure accuracy is controlled within ±1μm. S203. Using the second photoresist layer as a mask, the pattern is transferred to the second etching mask layer by plasma dry etching. S204. Remove the second photoresist layer and vacuum dry; S205. Using the second etch mask layer as a shield, the silicon wafer is vertically etched using the Bosch process of DRIE to form a manifold structure. After etching, residual impurities are removed. S206. A second passivation layer is formed on the surface of the second etch mask layer and the manifold structure, and a second bonding element is disposed on the second passivation layer around the manifold structure.

7. The self-cooled liquid-cooled 2.5D chip co-packaging method according to claim 1, characterized in that, The eutectic bonding temperature of S3 is 200-300℃, and the I / O holes are fabricated using laser drilling technology.

8. The self-cooled liquid-cooled 2.5D chip co-packaging method according to claim 1, characterized in that, The TIM material mentioned in S4 is a silicone grease with a thermal conductivity of 5 W / m·K. The MEMS liquid cooling chip is based on a piezoelectric micropump driving the coolant and includes a piezoelectric micropump, a liquid cooling film integrating microchannels and coolant, and a liquid cooling drive chip.

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