Network processing using fixed function logic components closely coupled with programmable logic and software

Abstract

Implementations of an architecture for network processing per operational component using fixed function logic closely coupled to programmable logic and software are provided. One aspect provides an integrated circuit device for network processing, the device including a combinable processing pipeline including a programmable on-operation component and a fixed function logic on-operation component closely coupled with programmable logic and software. The apparatus further includes a compute complex component including processing circuitry implementing software for controlling the programmable per-operation component and the fixed function logic per-operation component, where for the first processing pipeline, the processing circuitry is configured to perform the first function using the programmable per-operation component; and for a second processing pipeline, the processing circuitry is configured to perform a second function per operational component using fixed function logic.

Description

Background Technology

[0001] Many different solutions have been proposed to offload the host networking process to hardware. For example, intelligent network interface cards (NICs) based on field-programmable gate arrays (FPGAs) have been considered. The advantages offered by this solution include programmability comparable to software and performance and efficiency comparable to hardware. Other solutions include application-specific integrated circuit (ASIC) based NICs, which offer cost-effective performance but have limited flexibility compared to FPGA-based NICs. Summary of the Invention

[0002] This summary is provided to introduce, in a simplified form, some concepts that will be further described in the detailed embodiments described below. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Furthermore, the claimed subject matter is not limited to embodiments that address any or all the shortcomings mentioned in any part of this disclosure.

[0003] Implementations of an architecture for network processing using fixed-function logic per-op components tightly coupled to programmable logic and software are provided. One aspect provides an integrated circuit device for network processing, the device including a composable processing pipeline comprising programmable per-op components and fixed-function logic per-op components tightly coupled to programmable logic and software. The device also includes a computational complex assembly including processing circuitry implementing software for controlling the programmable per-op components and the fixed-function logic per-op components, wherein for a first processing pipeline, the processing circuitry is configured to perform a first function using the programmable per-op components; and for a second processing pipeline, the processing circuitry is configured to perform a second function using the fixed-function logic per-op components. Attached Figure Description

[0004] Figure 1 An example integrated circuit device architecture for offloading network processes is shown.

[0005] Figure 2 This demonstrates an example of processing a pipelined data flow using FPGA per-operation components and ASIC per-byte components, which can be used... Figure 1 This is achieved through integrated circuit devices.

[0006] Figure 3 An example integrated circuit device architecture with FPGA-based per-operation components and ASIC-based per-operation components is shown.

[0007] Figure 4An example of a pipelined data flow that can be composably processed using an ASIC tightly coupled to programmable logic and software per operating component is shown, which can be used... Figure 3 This is achieved through integrated circuit devices.

[0008] Figure 5 An example of a composable processing pipeline that bypasses the ASIC per-operation component is shown, which can use... Figure 3 This is achieved through integrated circuit devices.

[0009] Figure 6 An example of a composable processing pipeline that bypasses the FPGA by operating components is shown, which can use... Figure 3 This is achieved through integrated circuit devices.

[0010] Figure 7 An example of a data flow pipeline that can be combined to process data using an ASIC per-operation component for front-end processing and an FPGA per-operation component for back-end processing is shown, which can be used... Figure 3 This is achieved through integrated circuit devices.

[0011] Figure 8 An example of a composable processing pipeline is shown, in which software initiates both operation-based and byte-based processing supported by ASIC byte-based components, ASIC operation-based components, and FPGA operation-based components, which can be used... Figure 3 This is achieved through integrated circuit devices.

[0012] Figure 9 It shows that it can be used Figure 3 A flowchart of an example method for network processing implemented on an integrated circuit device.

[0013] Figure 10 It shows that it can be achieved Figure 3 A schematic diagram of an example computing system for integrated circuit devices. Detailed Implementation

[0014] Network processing devices, such as smart NICs, can be implemented in various ways. Common implementations of such devices include using FPGAs and / or ASICs. Different implementations and architectures can be designed for specific purposes, thus providing a variety of functions for different applications. FPGAs are programmable / reprogrammable integrated circuits that offer high flexibility. For example, their programmability / reprogrammability allows for more standardized manufacturing and interfaces, while still enabling them to be implemented in different applications. On the other hand, ASIC architectures are typically manufactured for specific functions / purposes. Thus, they generally operate at higher speeds and perform their intended functions more efficiently compared to other logic devices. Additionally, because they are designed for specific purposes, their space requirements are relatively lower than other logic devices. However, these advantages come at the cost of higher initial development and testing costs.

[0015] Some smart NIC architectures employ a combination of FPGA and ASIC designs. Many of these devices are typically implemented using three main components: an operation component, a byte component, and a control component. Figure 1 An example integrated circuit device architecture for offloading network processes is illustrated. Example integrated circuit device 100 includes an operation module 102, a byte module 104, and a computing complex module / component 106. Each module 102 to 106 communicates with a set of memory devices. In the illustrated example, the component communicates with a dynamic random access memory (DRAM) array 108. For connectivity, example integrated circuit device 100 includes a peripheral component interconnect fast (PCI-e) connection 110 for connecting to a host device and an Ethernet connection 112 for connecting to other hardware, such as a networking switch. Other types and standard networking protocols can also be implemented, as should be readily understood.

[0016] Modules 102 through 106 can be implemented using various components and hardware architectures. The press-operation module 102 may include one or more press-operation components, which are programmable components that can provide various functionalities. For example, a press-operation component may provide functionality for processing network packets and / or storing transaction headers and metadata. The press-operation component may be implemented to support programmability at full press-operation rates. In some implementations, hard paths are used to reduce power consumption in common scenarios while providing full programmability support for each operation. Power consumption can be determined by processing each operation in a programmable manner. In the example integrated circuit device 100, the press-operation component is implemented using FPGA programmable logic. Other types of programmable logic devices can also be implemented. In some implementations, the press-operation component is implemented using one or more microcontrollers.

[0017] Byte module 104 may include one or more byte components, which are components that can provide computationally intensive functionality. Byte components are typically implemented with hard logic and are not programmable. In some implementations, byte module 104 includes configurable components. A byte component can be viewed as a data path processor controlled by an operation component. Byte module 104 provides interfaces such as PCI-e physical layer (PHY) and controller, Ethernet PHY and controller, data movement, transformation (e.g., encryption), and computation (e.g., cyclic redundancy check (CRC)) capabilities. For example, a byte component may provide functionality to process data bytes for each network packet and / or storage transaction, as well as input / output (I / O) interfaces. A byte component may accept commands with operands from an operation component. For example, such a command may include "read host data specified by the provided collection list into a buffer while performing CRC calculation, encryption, decryption, checksum calculation, and CRC calculation." In example integrated circuit device 100, the byte component is implemented using an ASIC. Computational complex module 106 may be implemented using a processor-based computing subsystem. For example, the computing complex module 106 can be implemented using various central processing unit (CPU) architectures. In some implementations, the computing complex module 106 includes multiple CPU cores configured to run control plane software agents.

[0018] Figure 2 An example processing pipeline 200 is shown using FPGA per-operation components 202A and 202B and ASIC per-byte components 204A to 204C to process the data flow, which can be used Figure 1 This is implemented using integrated circuit devices. Different device architectures can be implemented to perform the various functions described herein. For example, instead of FPGAs as per-operation components, any other type of programmable logic device can be implemented as an per-operation component. In some implementations, one or more microcontrollers are implemented.

[0019] For example, example processing pipeline 200 depicts a data stream of incoming packets received from a network connection, such as an Ethernet connection. The incoming packet arrives at a first ASIC byte component 204A, which performs an external partial checksum operation. The packet header and metadata are then sent to a first FPGA byte component 202A for packet processing. The data, along with command data for invoking a second ASIC byte component 204B to perform its intended function, is then sent to the second ASIC byte component 204B. In example pipeline 200, the second ASIC byte component 204B performs decryption and Internet checksum functions. The packet header and metadata are then sent to the second FPGA byte component 202B for packet processing. The data, along with command data for invoking a third ASIC byte component 204C to perform its intended function, is then sent to the third ASIC byte component 204C. In example pipeline 200, the third ASIC byte component 204C performs packet editing and direct memory access (DMA) to the host system.

[0020] Figure 2 A concrete example of a processing pipeline is depicted and provided for illustrative purposes only. Figure 1 The processing pipeline implemented by the integrated circuit device may include additional functions, including those not shown, performed using FPGA per-operation components and ASIC per-byte components in various configurations. The functions performed may vary depending on the processing pipeline. Although the components are depicted as separate entities, they may or may not be implemented as a single physical device, as their representation may be a logical representation used to depict the data flow. In some implementations, functions performed by two FPGA per-operation components 202A, 202B are performed by the same physical FPGA per-operation component device. Similarly, a single ASIC per-byte component may be utilized multiple times at different points within the processing pipeline.

[0021] Figure 1 and Figure 2 The implementation described utilizes programmable logic to implement the per-operation components, while the per-byte components are implemented in the ASIC and invoked by the programmable logic. For various use cases, this implementation can lead to unoptimized data flow and performance. For example, implementing all per-operation components in an FPGA allows for programmability and flexibility, but this implementation challenges the availability of FPGA resources to support all functions at the desired performance level. For scenarios where the software running in the computing complex module / component 106 needs to handle packet / store transactions, no hardware offloading functionality is available.

[0022] Based on the above observations, a network processing device architecture including a composable processing pipeline is provided. This composable processing pipeline includes configurable, programmable, on-operation components tightly coupled to programmable logic and software. In some implementations, these programmable on-operation components are ASIC-based. ASIC on-operation components can be implemented to perform well-known or commonly used functions, leveraging the speed and efficiency of the ASIC architecture to improve the performance of the network processing device. This architecture can be implemented for a variety of applications. For example, a smart NIC architecture can be implemented using configurable ASIC on-operation components tightly coupled to programmable logic and software, providing flexibility in supporting a variety of use case scenarios. A unified set of application programming interfaces (APIs) can be defined for the configurable hardwired logic, software, and programmable logic to invoke on-operation and on-byte offloading / acceleration functions implemented in the ASIC. In contrast, traditional architectures utilize different sets of APIs used separately by hardware and software. In some implementations, the configurable ASIC on-operation components are implemented so that they can be invoked by the programmable logic and software in the compute complex components via a unified set of APIs. For example, ASICs can be implemented such that each functional block and sub-functional block can be directly invoked by hardware, by an FPGA, or by software running in a computing complex to perform the set functions.

[0023] Implementing an architecture for configurable ASIC-operated components tightly coupled with programmable logic and software enables access to processing pipelines that provide optimized data flow for many different use cases. For example, use cases involving lower programmability and associated processing pipelines can implement such configurable ASIC-operated components to reduce latency and cross-sectional bandwidth between the ASIC and FPGA. In some implementations, the ASIC-operated component includes network packet and memory I / O processing function blocks. Each block can be individually invoked by the FPGA programmable logic or software within the compute complex component to execute one or more of its configured functions. In some processing pipelines, such functions can also be invoked by arrival events of network packet and memory transactions.

[0024] Figure 3 An example integrated circuit device architecture with FPGA-based per-operation components and ASIC-based per-operation components is shown. Figure 1 The examples shown in the figure are similar. Figure 3Example integrated circuit device 300 includes a computing complex module 106 and a byte module 104 implemented using ASIC byte components. Example integrated circuit device 300 also includes a per-operation module, which includes an FPGA per-operation component 302 and an ASIC per-operation component 304. As should be readily understood, device 300 may include multiple FPGA per-operation components 302 and / or multiple ASIC per-operation components 304. Furthermore, per-operation components 302 and 304 can be implemented in various ways. FPGA per-operation component 302 can also be implemented using any programmable logic device, including non-FPGA architectures. In some implementations, one or more microcontrollers are implemented. ASIC per-operation component 304 can also be implemented using any fixed-function logic device, including non-FPGA architectures. ASIC per-operation component 304 can be implemented to include different functional blocks and / or sub-functional blocks, including but not limited to network packet processing functional blocks and storage input / output processing functional blocks. Figure 1 The examples shown in the figure are similar. Figure 3 The example integrated circuit device 300 includes a DRAM 108, a PCI-e 110, and an Ethernet 112 interface. As should be readily understood, other types and standard network protocols can also be implemented.

[0025] The ASIC operator component 304 can be implemented as a configurable component tightly coupled to the programmable logic and software within the computational complex component 106. In some implementations, the ASIC operator component 304 includes function blocks that can be individually invoked using a unified set of APIs, such as those defined for the FPGA operator component 302. This implementation provides a high degree of flexibility by combining software and hardware function blocks to implement processing pipelines for various use cases and allowing customization in various deployment scenarios. For example, a first processing pipeline can be executed by utilizing the FPGA operator component 302 to perform one or more of its configured functions while bypassing the ASIC operator component 304. A second processing pipeline can be executed by utilizing the ASIC operator component 304 to perform one or more of its configured functions while bypassing the FPGA operator component 302.

[0026] Figure 4A sample composable processing pipeline 400 is illustrated using p-operation components 402A, 402B of fixed-function logic tightly coupled with programmable logic and software to execute data flows. In addition to the configurable fixed-function logic p-operation components 402A, 402B, the sample composable processing pipeline 400 also includes programmable p-operation components 404A, 404B and byte-by-byte components 406A through 406C of fixed-function logic. For illustrative purposes, the fixed-function logic components are illustrated as ASIC-based components, but can be implemented using any type of fixed-function logic architecture. Similarly, the programmable p-operation components are illustrated as FPGA-based components, but can be implemented using any type of programmable logic device architecture. Software 408 implemented in the computational complex component can invoke the ASIC p-operation components 402A, 402B and the intermediate ASIC byte-by-byte component 406B to execute its configured functions. For example, the sample processing pipeline 400 provides a high-level diagram illustrating the logical data flow of incoming packets received from a network connection, such as an Ethernet connection.

[0027] and Figure 2 Compared to the assembly line described in [the text], Figure 4 The example composable processing pipeline 400 also includes ASIC p-operation components 402A and 402B, which are tightly coupled to the programmable logic and software 408 in the computing complex component and can be invoked via a unified set of APIs. ASIC p-operation components 402A and 402B can be implemented in various ways. In some implementations, ASIC p-operation components 402A and 402B are implemented as including network packetization and storage I / O processing function blocks, each of which can be individually invoked by the programmable logic or software 408 implemented in the computing complex component. Depending on the processing pipeline to be executed, ASIC p-operation components 402A and 402B can be bypassed, or, using defined APIs, ASIC p-operation components 402A and 402B can be invoked to perform offloading / acceleration functions provided in the function blocks implemented in the ASIC. For example, FPGA p-operation components 404A and 404B can be used to execute a first processing pipeline to perform its set functions while bypassing ASIC p-operation components 402A and 402B. The ASIC per-byte component 402A, 402B can be used to execute a second processing pipeline to perform its set functions, while bypassing the FPGA per-byte component 404A, 404B. The semantics of invoking the accelerated functions can include parsing packets, performing specific types of lookups, performing cryptographic offloading of payloads, etc. To further support different use cases and scenarios, the intermediate ASIC per-byte component 406B can be invoked by software 408 implemented in the computational complex component, the preceding ASIC per-byte component 402A, or the preceding FPGA per-byte component 404A.

[0028] Figure 4 The architecture described provides a configurable and flexible system that can implement composable processing pipelines, supporting a variety of processing pipelines and use cases. For example, processing pipeline 400 can be configured to support... Figure 2 The processing pipeline described herein is a combined processing pipeline with similar functionality, wherein the FPGA press operation components 404A, 404B control the acceleration functions to be invoked for each network packet and / or storage I / O transaction. In this implementation, the ASIC press operation components 402A, 402B can be bypassed in this processing pipeline.

[0029] Figure 5 A data flow of an example composable processing pipeline 500 bypassing ASIC press components 402A, 402B is illustrated. In the example composable processing pipeline 500, ASIC press components 402A, 402B are depicted as being bypassed 502, while FPGA press components 404A, 404B perform processing. An intermediate ASIC press component 406B can be invoked by software 408 implemented in a computational complex component or by the preceding FPGA press component 404A (bypassing the first ASIC press component 402A). Packet headers and metadata are then forwarded from the intermediate ASIC press component 406B to the second FPGA press component 404B, thereby bypassing the second ASIC press component 402B.

[0030] By bypassing the ASIC button operation components 402A and 402B, Figure 5 The composable processing pipeline 500 described in the document and Figure 2 The processing pipeline functionality described herein is executed similarly. Other processing pipelines can be implemented for different scenarios and use cases using configurable ASIC button-operated components. For example, different processing pipelines can be implemented where the ASIC button-operated components are invoked to execute the configured functions, while bypassing the FPGA button-operated components.

[0031] Figure 6A data flow of an example composable processing pipeline 600 bypassing FPGA press-operation components 404A, 404B is illustrated. In the example composable processing pipeline 600, FPGA press-operation components 404A, 404B are depicted as being bypassed 602, and press-operation functions are executed in an ASIC pipeline via ASIC press-operation components 402A, 402B. The ASIC press-operation components are tightly coupled to programmable logic and can receive inputs that will otherwise be fed to the FPGA press-operation components. For example, the depicted model includes an ASIC byte-by-byte component 406A that feeds command data to the FPGA press-operation component 404A; and when the FPGA press-operation component 404A is bypassed, it is fed to the ASIC press-operation component 402A. In this scenario, byte-by-byte functions executed by ASIC byte-by-byte components 406B, 406C can be directly invoked by ASIC press-operation components 402A, 402B using a unified set of APIs similarly defined for FPGA press-operation components 404A, 404B.

[0032] Figure 5 and Figure 6 Two distinct processing pipelines are depicted, one based on operational function and the other on an FPGA based on operational components. Figure 5 ) or ASIC according to operating components ( Figure 6 ) Execution. Unused button-operation components are bypassed. By implementing configurable ASIC button-operation components that are tightly coupled with programming logic and software, Figure 4 The model illustrated in the diagram enables the execution of two processing pipelines. In this implementation, the functional processing pipeline can still operate even though components are bypassed, because the remaining components can be manipulated using a unified API in this scenario. For example, different components can be configured to be invoked through the same unified API set. Besides... Figure 5 and Figure 6 In addition to the two processing pipelines illustrated, other use cases involving different combinations of bypass components can also be implemented.

[0033] Figure 7 A sample composable processing pipeline 700 is illustrated using an ASIC press-operation component 402A for front-end processing and an FPGA press-operation component 404B for back-end processing. In the sample composable processing pipeline 700, the entire press-operation functionality is broken down into a "front-end" and a "back-end". This implementation can be advantageous for a variety of use cases. For example, when a new function cannot be fully supported by the ASIC press-operation component 402A but can be supplemented by the FPGA press-operation component 404B, it can be implemented that: the ASIC press-operation component 402A performs the front-end processing, and the FPGA press-operation component 404B performs the back-end processing. Figure 7As shown, the first FPGA button operation component 404A is bypassed by 702, and front-end processing is performed by the ASIC button operation component 402A. The second FPGA button operation component 406B can be used to provide supplementary functionality to the ASIC button operation component 402A for back-end processing. Although the FPGA button operation components 406A and 406B are discussed as separate components, they can be implemented as a single physical component because their depiction in the figures is a logical representation for the purpose of representing data flow.

[0034] In addition to utilizing and implementing different processing pipelines and data flows for different ASICs and FPGAs based on their operating components, the architecture described in this paper also enables the software implemented within the computing complex components to provide the main control of the processing pipeline. Figure 8 An example of a composable processing pipeline 800 is illustrated, wherein software 408 initiates per-operation and per-byte processing supported by ASIC per-byte components, ASIC per-operation components, and FPGA per-operation components. As shown, software 408 running within the computational complex component provides the main control for orchestrating the processing pipeline 800. Figure 8 As illustrated by the arrows, software 408 running within a computing complex component can invoke ASIC / FPGA per-operation and ASIC per-byte functions from its respective component to utilize acceleration features implemented in hardware function blocks. Data flow is primarily handled by software 408, and this functionality can be invoked accordingly via a unified set of APIs defined for the respective component. For example, software 408 running within a computing complex component can uniformly apply APIs for invoking a given component.

[0035] Figures 4 to 8 This describes an example of the features of a processing pipeline that utilizes the functionality of various components and their settings. Figure 3 The processing pipeline implemented by the integrated circuit device can include implementations of various FPGA and ASIC components, which have different function blocks and sub-function blocks for performing different functions, including those not illustrated or discussed herein. As should be readily understood, the types of components and functions implemented can vary depending on the process to be performed. For example, Figures 4 to 8 Fixed-function logic components are illustrated as ASIC-based components, but such components can be implemented using any type of fixed-function logic architecture. Similarly, programmable, per-operation components are illustrated as FPGA-based components, but can be implemented using any type of programmable logic device architecture. Additionally, Figures 4 to 8The diagram illustrates a logical representation of data flow in various processing pipelines. Thus, the illustrated and described components can represent a single physical device or multiple devices. For example, the depicted processing pipeline may include multiple FPGA-operated components. In a physical implementation, the FPGA component may be implemented as a single FPGA device, and the data flow is illustrated as passing through said device multiple times (e.g., for grouped processing).

[0036] Figure 9 A flowchart of an example method 900 for network processing is shown. Method 900 can be executed using an integrated circuit device including a composable processing pipeline capable of implementing different composable processing pipelines. The composable processing pipeline includes programmable per-operation components and fixed-function logic per-operation components. For example, method 900 can use... Figure 3 The integrated circuit devices depicted and described herein are used to perform this action. In some implementations, programmable operands include FPGA operands. However, other programmable devices, such as microcontrollers and other programmable processors, can be implemented as programmable operands. Fixed-function logic operands can be implemented using any fixed-function logic architecture. In some implementations, fixed-function logic operands include ASIC operands.

[0037] At step 902, method 900 includes executing a first combined processing pipeline. Executing the first combined processing pipeline includes: at sub-step 902A, using a computational complex component to select a programmable button-operated component for executing a first function of the first combined processing pipeline. At sub-step 902B, the computational complex component controls the programmable button-operated component to execute the first function. In some implementations, executing the first combined processing pipeline includes bypassing a fixed-function logic button-operated component. Figure 5 The text describes an example of such a pipeline that bypasses fixed functional logic by operating components.

[0038] At step 904, method 900 includes executing a second combined processing pipeline. Executing the second combined processing pipeline includes: at sub-step 904A, using a compute complex component to select a fixed-function logic button operation component for executing a second function of the second combined processing pipeline. At sub-step 904B, the compute complex component controls the fixed-function logic button operation component to execute the second function. The fixed-function logic button operation component may be configured to be invoked via a unified API set using programmable logic and software within the compute complex component. In some implementations, the fixed-function logic button operation component includes function blocks and / or sub-function blocks, including but not limited to network packetization and storage I / O processing function blocks. Function blocks and sub-function blocks may be implemented to be individually invoked using programmable logic or software within the compute complex component to execute one or more of their configured functions.

[0039] In some implementations, performing the second combined processing pipeline includes bypassing programmable button components. Figure 6 The document describes an example of such a pipeline that bypasses programmable per-operation components. In some implementations, performing a second combined processing pipeline involves using a fixed-function logic per-byte component of an integrated circuit device (e.g., an ASIC per-byte component) to perform a third function. This fixed-function logic per-byte component can be implemented to be invoked via a unified set of APIs. In some implementations, this fixed-function logic per-byte component can be invoked by both programmable per-operation components and fixed-function logic per-operation components. In other implementations, this fixed-function logic per-byte component can be invoked by software running within a computational complex component.

[0040] In addition to the combined processing pipeline described above with respect to steps 902 and 904, other variations and scenarios can be implemented using similar integrated circuit device designs. At step 906, method 900 optionally includes performing a third combined processing pipeline. The third combined processing pipeline includes performing a third function using a fixed-function logic button actuation component and performing a fourth function using a programmable button actuation component. This programmable button actuation component may be the same as or different from the programmable button actuation component described above with respect to performing the first function in the first combined processing pipeline. For example, an integrated circuit device can perform functions complementary to the fixed-function logic button actuation component by using a programmable button actuation component, thereby performing functions that cannot be fully supported by the fixed-function logic button actuation component. In some implementations, the fixed-function logic button actuation component performs "front-end processing" functions, while the programmable button actuation component performs "back-end processing" functions complementary to the front-end processing. Figure 7 The text describes an example of such a pipeline that uses different components to perform separate front-end and back-end processing.

[0041] In some embodiments, the methods and processes described herein can be attached to a computing system of one or more computing devices. In particular, these methods and processes can be implemented as computer applications or services, application programming interfaces (APIs), libraries, and / or other computer program products.

[0042] Figure 10 A non-limiting embodiment of computing system 1000 that can perform one or more of the methods and processes described above is illustrated schematically. For example, computing system 1000 can implement the methods and processes described above and Figure 3The integrated circuit device 300 is illustrated in the figure. The computing system 1000 is shown in a simplified form. The components of the computing system 1000 may be included in one or more personal computers, server computers, tablet computers, home entertainment computers, network computing devices, video game devices, mobile computing devices, mobile communication devices (e.g., smartphones) and / or other computing devices, as well as wearable computing devices (such as smartwatches and head-mounted augmented reality devices).

[0043] The computing system 1000 includes processing circuitry 1002, volatile memory 1004, and non-volatile storage device 1006. The computing system 1000 may optionally include a display subsystem 1008, an input subsystem 1010, a communication subsystem 1012, and / or... Figure 10 Other components not shown.

[0044] Processing circuitry typically includes one or more logic processors, which are physical devices configured to execute instructions. For example, a logic processor can be configured to execute instructions that are part of one or more applications, programs, routines, libraries, objects, components, data structures, or other logical constructs. Such instructions can be implemented to perform tasks, implement data types, change the state of one or more components, achieve technical effects, or otherwise achieve desired results.

[0045] The logical processor may include one or more physical processors configured to execute software instructions. Additionally or alternatively, the logical processor may include one or more hardware logic circuits or firmware devices configured to execute hardware-implemented logic or firmware instructions. The processor of the processing circuit 1002 may be single-core or multi-core, and the instructions executed thereon may be configured for sequential, parallel, and / or distributed processing. The various components of the processing circuit may optionally be distributed across two or more separate devices, which may be remotely deployed and / or configured for collaborative processing. For example, aspects of the computing system disclosed herein may be virtualized and executed by remotely accessible networked computing devices configured in a cloud computing environment. In this case, it will be understood that these virtualized aspects operate on different physical logical processors on various different machines. These different physical logical processors on various machines will be understood to be collectively included by the processing circuit 1002.

[0046] The non-volatile storage device 1006 includes one or more physical devices configured to store instructions executable by processing circuitry to implement the methods and processes described herein. When such methods and processes are implemented, the state of the non-volatile storage device 1006 may be transformed—for example, to store different data.

[0047] The non-volatile storage device 1006 may include removable and / or built-in physical devices. The non-volatile storage device 1006 may include optical storage, semiconductor memory, and / or magnetic storage, or other mass storage technologies. The non-volatile storage device 1006 may include non-volatile, dynamic, static, read / write, read-only, sequential access, location-addressable, file-addressable, and / or content-addressable devices. It should be understood that the non-volatile storage device 1006 is configured to retain instructions even when power is lost from the non-volatile storage device 1006.

[0048] Volatile memory 1004 may include a physical device including random access memory. Volatile memory 1004 is typically used by processing circuitry 1002 to temporarily store information during processing of software instructions. It should be understood that volatile memory 1004 typically does not continue storing instructions when power is turned off.

[0049] The processing circuitry 1002, the volatile memory 1004, and the non-volatile storage device 1006 can be integrated together into one or more hardware logic components. Such hardware logic components may include, for example, field-programmable gate arrays (FPGAs), programmable application-specific integrated circuits (PASICs / ASICs), programmable application-specific standard products (PSSPs / ASSPs), system-on-a-chip (SoCs), and complex programmable logic devices (CPLDs).

[0050] The terms "module," "program," and "engine" can be used to describe aspects of computing system 1000, typically implemented in software by a processor, to perform specific functions using portions of volatile memory. These functions involve transformation processes specifically configured to perform those functions. Therefore, a module, program, or engine can be instantiated using portions of volatile memory 1004 via processing circuitry 1002 executing instructions stored in non-volatile storage device 1006. It should be understood that different modules, programs, and / or engines can be instantiated from the same application, service, code block, object, library, routine, API, function, etc. Similarly, the same module, program, and / or engine can be instantiated from different applications, services, code blocks, objects, routines, APIs, functions, etc. The terms "module," "program," and "engine" can encompass individuals or groups of executable files, data files, libraries, drivers, scripts, database records, etc.

[0051] When included, the display subsystem 1008 can be used to present a visual representation of the data stored by the non-volatile storage device 1006. This visual representation can take the form of a GUI. Since the methods and processes described herein change the data stored by the non-volatile storage device, and thus transform the state of the non-volatile storage device, the state of the display subsystem 1008 may also be transformed to visually represent the changes in the underlying data. The display subsystem 1008 may include one or more display devices that utilize virtually any type of technology. Such display devices may be combined with the processing circuitry 1002, the volatile memory 1004, and / or the non-volatile storage device 1006 in a shared housing, or such display devices may be peripheral display devices.

[0052] When included, the input subsystem 1010 may include one or more user input devices, such as a keyboard, mouse, touchscreen, camera, or microphone, or interface with such user input devices.

[0053] The communication subsystem 1012 can be configured to communicatively couple the various computing devices described herein to each other and to other devices. The communication subsystem 1012 may include wired and / or wireless communication devices compatible with one or more different communication protocols. As a non-limiting example, the communication subsystem can be configured to communicate via wired or wireless local area networks or wide area networks, broadband cellular networks, etc. In some embodiments, the communication subsystem may allow the computing system 1000 to send and / or receive messages from other devices via a network (such as the Internet).

[0054] The following paragraphs provide additional description of the subject matter of this disclosure. One aspect provides an integrated circuit device for network processing, the device comprising: a composable processing pipeline including: a programmable bit-operated component; and a fixed-function logic bit-operated component tightly coupled to programmable logic and software; and a computing complex assembly including processing circuitry implementing software for controlling the programmable bit-operated component and the fixed-function logic bit-operated component, wherein: for a first combined processing pipeline, the processing circuitry is configured to perform a first function using the programmable bit-operated component; and for a second combined processing pipeline, the processing circuitry is configured to perform a second function using the fixed-function logic bit-operated component. In this aspect, additionally or alternatively, the processing circuitry is configured to bypass the fixed-function logic bit-operated component for the first combined processing pipeline; and for the second combined processing pipeline, the processing circuitry is configured to bypass the programmable bit-operated component. In this aspect, additionally or alternatively, the fixed-function logic bit-operated component includes function blocks that can be individually invoked using a unified application programming interface (API) set. In this aspect, additionally or alternatively, the function block can be individually invoked by a computational complex component. In this aspect, additionally or alternatively, the function block includes one or more of a network packet processing function block or a storage input / output processing function block. In this aspect, additionally or alternatively, the programmable per-operation component includes a field-programmable gate array (FPGA) per-operation component. In this aspect, additionally or alternatively, the fixed-function logic per-operation component includes an application-specific integrated circuit (ASIC). In this aspect, additionally or alternatively, the integrated circuit device further includes an ASIC per-byte component, wherein for a second combined processing pipeline, the processing circuitry is configured to use the ASIC per-byte component to perform a third function. In this aspect, additionally or alternatively, the ASIC per-byte component can be invoked by a fixed-function logic per-operation component or a programmable per-operation component using a unified application programming interface (API) set. In this respect, additionally or alternatively, the integrated circuit device further includes a second programmable button operation component, wherein for the third combined processing pipeline, the processing circuitry is configured to perform a third function using a fixed-function logic button operation component and to perform a fourth function using the second programmable button operation component.

[0055] On the other hand, a network processing method is provided for implementation on an integrated circuit device including a composable processing pipeline. The method includes: executing a first composable processing pipeline, including: using a computing complex component to select a programmable p-operation component for executing a first function of the first composable processing pipeline; and using the computing complex component to control the programmable p-operation component to execute the first function; and executing a second composable processing pipeline, including: using the computing complex component to select a fixed-function logic p-operation component for executing a second function of the second composable processing pipeline, wherein the fixed-function logic p-operation component is tightly coupled to programmable logic and software running on the computing complex component; and using the computing complex component to control the fixed-function logic p-operation component to execute the second function. In this aspect, additionally or alternatively, executing the first composable processing pipeline includes bypassing the fixed-function logic p-operation component; and executing the second composable processing pipeline includes bypassing the programmable p-operation component. In this aspect, additionally or alternatively, the fixed-function logic p-operation component includes a function block that can be individually invoked by the computing complex component of the integrated circuit device using a unified application programming interface (API) set. In this aspect, additionally or alternatively, the programmable per-operation component includes a field-programmable gate array (FPGA) per-operation component; and the fixed-function logic per-operation component includes an application-specific integrated circuit (ASIC) per-operation component. In this aspect, additionally or alternatively, performing the second combined processing pipeline includes using an ASIC per-byte component to perform a third function, wherein the ASIC per-byte component can be invoked by the fixed-function logic per-operation component, the programmable per-operation component, or the computational complex component using a unified application programming interface (API) set.

[0056] On the other hand, an integrated circuit device for network processing is provided, the device comprising: a composable processing pipeline including: a field-programmable gate array (FPGA) per-operation component; and an application-specific integrated circuit (ASIC) per-operation component; and a computing complex component including processing circuitry implementing software for controlling the FPGA per-operation component and the ASIC per-operation component, wherein: for a first combined processing pipeline, the processing circuitry is configured to bypass the ASIC per-operation component; and for a second combined processing pipeline, the processing circuitry is configured to bypass the FPGA per-operation component. In this aspect, additionally or alternatively, the ASIC per-operation component includes function blocks that can be individually invoked using a unified application programming interface (API) set. In this aspect, additionally or alternatively, the function blocks can be individually invoked by the computing complex component. In this aspect, additionally or alternatively, the integrated circuit device further includes an ASIC per-byte component, wherein for the second combined processing pipeline, the processing circuitry is configured to use the ASIC per-byte component to perform functions. In this respect, additionally or alternatively, ASIC byte-based components can be invoked by ASIC byte-based components, FPGA byte-based components, or compute complex components using a unified set of application programming interfaces (APIs).

[0057] As used herein, “and / or” means any one or all of the plurality of possibilities described. For example, the phrase “element A and / or element B” covers embodiments having a single element A, having a single element B, or having elements A and B used together.

[0058] It should be understood that the configurations and / or methods described herein are exemplary in nature, and these specific embodiments or examples should not be considered limiting, as many variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. Thus, the various actions illustrated and / or described may be performed in the illustrated and / or described order, or in other orders, may be performed in parallel, or may be omitted. Similarly, the order of the processes described above may be changed.

[0059] The subject matter of this disclosure includes all novel and non-obvious combinations and sub-combinations of various processes, systems and configurations, and other features, functions, actions and / or properties disclosed herein, and any and all equivalents thereof.

Claims

1. An integrated circuit device (300) for network processing, the device (300) comprising: A composable processing pipeline (400) comprising: Programmable button operation component (404A); and Fixed-function logic tightly coupled to programmable logic and software, operating component (402A); and A computing complex component (408) includes processing circuitry that implements software for controlling the programmable key-operated component (404A) and the fixed-function logic key-operated component (402A), wherein: For the first combined processing pipeline, the processing circuitry is configured to perform a first function using the programmable button-operated component (404A); and For the second combined processing pipeline, the processing circuitry is configured to perform the second function using the fixed-function logic button operation component (402A).

2. The integrated circuit device according to claim 1, wherein: For the first combined processing pipeline, the processing circuitry is configured to bypass the fixed-function logic button operation component; and For the second combined processing pipeline, the processing circuitry is configured to bypass the programmable button operation component.

3. The integrated circuit device of claim 1, wherein the fixed-function logic as an operating component includes function blocks that can be individually invoked using a unified application programming interface (API) set.

4. The integrated circuit device of claim 3, wherein the functional block can be individually invoked by the computing complex component.

5. The integrated circuit device according to claim 3, wherein the functional block includes one or more of the following: a network packet processing functional block or a storage input / output processing functional block.

6. The integrated circuit device of claim 1, wherein the programmable button operation component includes a field-programmable gate array (FPGA) button operation component.

7. The integrated circuit device of claim 1, wherein the fixed-function logic per-operation component includes an application-specific integrated circuit (ASIC).

8. The integrated circuit device of claim 1, further comprising an application-specific integrated circuit (ASIC) byte component, wherein, for the second combined processing pipeline, the processing circuitry is configured to use the ASIC byte component to perform a third function.

9. The integrated circuit device of claim 8, wherein the ASIC byte-by-byte component is callable by the fixed-function logic byte-by-operation component or the programmable byte-by-operation component using a unified application programming interface (API) set.

10. The integrated circuit device of claim 1, further comprising a second programmable button operation component, wherein, for a third combined processing pipeline, the processing circuitry is configured to perform a third function using the fixed-function logic button operation component and a fourth function using the second programmable button operation component.

11. A method (900) for network processing, performed on an integrated circuit device (300) including a composable processing pipeline (400), the method (900) comprising: The first combined processing pipeline (902) includes: Using a computational complex component to select a programmable button component (902A) for performing a first function of the first combined processing pipeline; and Using the computing complex component to control the programmable button component to perform the first function (902B); and The second combined processing pipeline (904) includes: The computing complex component is used to select a fixed-function logic button operation component (904A) for performing a second function of the second combined processing pipeline, wherein the fixed-function logic button operation component is tightly coupled to programmable logic and software running on the computing complex component; and The computational complex component is used to control the fixed-function logic button component to perform the second function (904B).

12. The method of claim 11, wherein: Executing the first combined processing pipeline includes bypassing the fixed-function logic by operating the component; and Performing the second combined processing pipeline includes bypassing the programmable button operation component.

13. The method of claim 11, wherein the fixed-function logic comprises function blocks as operating components, the function blocks being individually invoked by the computing complex components of the integrated circuit device using a unified set of application programming interfaces (APIs).

14. The method of claim 11, wherein the programmable button operation component includes a field-programmable gate array (FPGA) button operation component; and wherein the fixed function logic button operation component includes an application-specific integrated circuit (ASIC) button operation component.

15. The method of claim 11, wherein performing the second combined processing pipeline includes using an application-specific integrated circuit (ASIC) byte-by-byte component to perform the third function, wherein the ASIC byte-by-byte component is callable by the fixed-function logic byte-by-operation component, the programmable byte-by-operation component, or the computing complex component using a unified application programming interface (API) set.

16. An integrated circuit device (300) for network processing, the device (300) comprising: A composable processing pipeline (400) comprising: Field-Programmable Gate Array (FPGA) operated by component (404A); and Application-Specific Integrated Circuits (ASICs) by operating component (402A); and A computing complex component (408) includes processing circuitry that implements software for controlling the FPGA pressing operation component (404A) and the ASIC pressing operation component (402A), wherein: For the first combined processing pipeline, the processing circuitry is configured to bypass the ASIC button operation component (402A); and For the second combined processing pipeline, the processing circuitry is configured to bypass the FPGA press operation component (404A).

17. The integrated circuit device of claim 16, wherein the ASIC as an operating component includes function blocks that can be individually invoked using a unified set of application programming interfaces (APIs).

18. The integrated circuit device of claim 17, wherein the functional block can be individually invoked by the computing complex component.

19. The integrated circuit device of claim 16, further comprising an ASIC byte component, wherein, for the second combined processing pipeline, the processing circuitry is configured to perform a function using the ASIC byte component.

20. The integrated circuit device of claim 16, wherein the ASIC byte-based component is callable by the ASIC operation-based component, the FPGA operation-based component, or the computing complex component using a unified application programming interface (API) set.

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