Buffer transistor and inverter transistor embedded in interconnect metal layer

Abstract

Integrated circuit devices having a buffer transistor or inverter transistor formed between top side BEOL (back-end-of-line) metal layers are described. The buffer transistor or the inverter transistor includes an active region and a source / drain that may be formed in a space between the top-side metal layers. In some examples, the transistors are formed between metal layers farthest from the substrate. The transistor is connected to the wiring above or below the transistor to buffer and / or invert a signal through the wiring. For example, a transistor may include an active region positioned between a power wiring and a ground wiring, and connected to a signal wiring between the power wiring and the ground wiring to enhance and / or invert a signal propagating along the signal wiring. In various cases, the active region of the transistor is formed of a thin channel material.

Description

Technical Field

[0001] The embodiments described herein relate to signal routing in semiconductor devices. More specifically, the embodiments described herein relate to implementing buffer transistors or inverter transistors in interconnect layers for signal buffering. Background Technology

[0002] Massive integration of integrated circuits (such as very large-scale integration (VLSI)) can involve signals that travel globally across many circuits or blocks of circuitry. In some instances, these signals can travel long distances across many circuits or blocks of circuitry. In such instances, the signal may need to be amplified (e.g., boosted or buffered) at one or more points along its path to maintain signal strength and an acceptable signal-to-noise ratio. In current specific implementations, buffering or inversion is typically implemented by placing the buffer circuitry or inverter circuitry within the transistor region of the device (e.g., at the silicon / CMOS level of the device). However, placing the buffer circuitry or inverter circuitry within the transistor region requires the signal to travel along vias between the transistor region and the global signal path layer, which is typically located in the top-side metal layer of the device.

[0003] Placing buffer or inverter circuits within the transistor region occupies valuable silicon area within the transistor region, and still results in long travel paths for signals as they travel up / down between the transistor region and the top metal layer. Additionally, the buffer or inverter circuits and their associated vias leading to the top metal layer create path congestion, which needs to be considered in the device design. For example, complex or undesirable pathways may be needed to route signals around path congestion caused by the buffer or inverter circuits and their associated vias. Therefore, there are both electrical (e.g., high resistance on long travel paths) and mechanical (e.g., area occupation and path congestion) problems associated with buffer or inverter circuits located within the transistor region. Attached Figure Description

[0004] The features and advantages of the methods and apparatus of the embodiments described in this disclosure will be more fully understood when taken in conjunction with the accompanying drawings, by referring to the following detailed description of the currently preferred, but only exemplary, embodiments according to which the present disclosure is described: Figure 1 A top view illustration depicts a conceptual device having buffer transistors between top-side metal layers according to some embodiments.

[0005] Figure 2 This is a cross-sectional side view illustration of a device according to some embodiments, showing along... Figure 1 The buffer transistor in line 2-2.

[0006] Figure 3 This is a cross-sectional side view illustration of a device according to some embodiments, showing along... Figure 1 The buffer transistor in line 3-3.

[0007] Figure 4 A three-dimensional perspective view of a buffer transistor according to some embodiments is depicted.

[0008] Figure 5 A schematic diagram of a buffer transistor according to some implementation schemes is depicted.

[0009] Figure 6 A three-dimensional perspective illustration of another buffer transistor according to some embodiments is depicted.

[0010] Figure 7 A schematic diagram of another buffer transistor according to some implementation schemes is depicted.

[0011] Figure 8 A top-side plan view illustration of a contemplated device according to some embodiments is depicted, illustrating various layouts of the buffer transistor.

[0012] Figure 9 This is a block diagram of one implementation of the example system.

[0013] While the embodiments disclosed herein are susceptible to various modifications and alternatives, specific embodiments of the invention are illustrated by way of example in the accompanying drawings and described in detail herein. However, it should be understood that the drawings and their detailed description are not intended to limit the scope of the claims to the specific forms disclosed. Rather, this application is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure of this application as defined by the appended claims. Detailed Implementation

[0014] This disclosure relates to implementing transistors (such as buffer transistors) between metal layers (e.g., top-side metal layers) above the transistor regions of an integrated circuit device. In various embodiments, these top-side metal layers may be referred to as BEOL (“back-end process”) metal layers. The top-side metal layers may provide wiring (e.g., paths) for control signals and / or power signals. Many current designs of the cell provide power or signal connections and wiring for transistors or other structures above the transistor regions. For example, power or signal connections and wiring may be located in the top-side layers of the device. As used herein, the term “top-side” refers to a region in the device that is vertically located above the active layers of the device (e.g., above the transistor regions of the device when viewed in a typical cross-sectional view). For example, top-side may refer to components (such as contacts or layers) located above the transistor regions in a vertical dimension, as depicted in figures and described herein. In some instances, the term “front-side” may be used interchangeably with the term “top-side.”

[0015] As used herein, the term "wiring" refers to any combination of metal vias, metal wires, metal traces, etc., that provide a path / route between two structures. Additional embodiments are conceivable in which the metal in the "wiring" is replaced with an alternative conductive material. For example, the metal in the "wiring" could be replaced with a superconducting material, a semiconductor material, or a non-metallic conductor.

[0016] As described above, in large-scale integration, placing buffer transistors or inverter transistors within the transistor regions of an integrated circuit device can lead to electrical (e.g., high resistance) and mechanical (e.g., area occupation / area utilization and path congestion) problems. This disclosure recognizes that these problems can be mitigated by placing buffer transistors or inverter transistors in locations between top-side wiring layers (e.g., top-side metal wiring layers) rather than within the transistor regions of the integrated circuit device. Placing buffer transistors or inverter transistors in these locations allows for connections between the buffer transistor or inverter transistor and its associated signal path to be implemented over short distances. For example, a buffer transistor or inverter transistor can be coupled to a signal path located in a top-side metal layer directly above or below the buffer transistor or inverter transistor. These shorter connection distances reduce the resistance in the connection between the buffer transistor or inverter transistor and the signal path, which improves the electrical properties of signal transmission. In some instances, by implementing these shorter connection paths, fewer buffer transistors or inverter transistors are required for global signal transmission across the device. Reducing the number of buffer transistors or inverter transistors increases the flexibility in the design or fabrication of these devices.

[0017] By placing the transistors between the top-side metal layers, buffer transistors or inverter transistors are moved out of the transistor region of the device, freeing up occupied area within the transistor region. This freed-up area can be used, for example, to increase the number of other types of transistors or circuit elements, thereby enabling more complex or powerful devices. Additionally, moving buffer transistors or inverter transistors out of the device's transistor region eliminates potential blockage caused by transistors. Freeing up occupied area and removing blockages allows for greater flexibility in the design or fabrication of integrated circuit devices. For example, by freeing up occupied area and removing blockages, the design of integrated circuits can include more optimized routing strategies for signals within the device. In some instances, fabrication can also be more efficient through optimized design strategies.

[0018] Some embodiments disclosed herein have three main elements: 1) a transistor region; 2) a first metal layer and a second metal layer located in a top-side metal layer above the transistor region, wherein one or more of these metal layers include signal wiring, power wiring, and ground power wiring; and 3) a transistor circuit located between the first and second metal layers. In various embodiments, the transistor circuit is a buffer transistor or an inverter transistor, comprising: an active region; a gate; a signal input coupled to the gate and a portion of the signal wiring; a voltage supply input coupled to the power wiring; a ground power input coupled to the ground power wiring; and a signal output coupled to another portion of the signal wiring. In some embodiments, the signal wiring, power wiring, and ground power wiring are located in the same top-side metal layer (e.g., the first or second metal layer). In some envisioned embodiments, the transistor circuit is a two-stage or single-stage inverter circuit, wherein the active region includes a p-type active region and an n-type active region.

[0019] Various examples of embodiments having these main components are now described in this disclosure. It should be noted that the embodiments illustrated in this disclosure depict a design template for a device having a buffer transistor positioned between top-side metal layers. Those skilled in the art will recognize that the embodiments illustrated in this disclosure can also be design templates for inverter transistors positioned between top-side metal layers, or combinations of buffer transistors and inverter transistors. Therefore, the design templates depicted in this disclosure provide basic building blocks upon which many different types of wiring schemes and logic functions (such as NAND and NOR) of the device can be constructed based on the interconnection schemes of the transistors in the design template. Additional embodiments incorporating variations in the size and / or width of the active region, using more metal tracks in the first or second metal layer, are conceivable.

[0020] Figure 1 A top view illustration depicts a contemplated device having buffer transistors between top-side metal layers according to some embodiments. In the illustrated embodiment, two top-side metal layers 110 and 120 of device 100 are shown. Top-side metal layers 110 and 120 may be, for example, BEOL metal layers located vertically above the transistor region of device 100. In some embodiments, metal layer 110 is a metal layer that is vertically closer to the transistor region of device 100 (e.g., metal layer 110 is a lower metal layer, and metal layer 120 is a top metal layer, such as...). Figure 2 and Figure 3 (As shown).

[0021] In various embodiments, metal layer 110 includes wirings 112A to 112F, and metal layer 120 includes wirings 122A to 122F. Since metal layers 110 and 120 are adjacent metal layers in the top-side metal layers, wirings 112A to 112F and wirings 122A to 122F can extend perpendicularly to each other, such as... Figure 3 As shown. Routes 112A to 112F and 122A to 122F may include signal wiring, power wiring, or ground power wiring. In some embodiments, one or more of routes 112 and 122 are global wirings. A global wiring may be, for example, a route that carries a signal over a long distance and attempts to avoid detours in the path of the route when passing over transistor regions not connected to the route.

[0022] In some embodiments, device 100 includes one or more buffer transistors positioned in a vertical space between metal layers 110 and 120. In the illustrated embodiment, device 100 includes buffer transistors 130 and 140. Dashed lines represent the horizontal area occupied by buffer transistors 130 and 140. Buffer transistor 130 includes an active region 132 positioned parallel to wiring 112 and perpendicular to wiring 122. Buffer transistor 140 includes an active region 142 positioned parallel to wiring 122 and perpendicular to wiring 112. Active region 132 may intersect wiring 122 below, while active region 142 may intersect wiring 112 above. In various embodiments, active regions 132A and 132B are complementary active regions (e.g., one is a PMOS active region and the other is an NMOS active region). Active regions 142A and 142B may similarly be complementary active regions.

[0023] Figure 2 This is a cross-sectional side view illustration of device 100 according to some embodiments, which shows along... Figure 1The buffer transistor 130 is located at line 2-2. Note that... Figure 2 Only a portion of device 100, including buffer transistor 130 along line 2-2, is shown. Additionally, for illustrative purposes, representative elements in device 100 (such as, but not limited to, substrate 200, transistor region 210, and dielectric 220) and their dimensions and spacing relative to each other are shown. In the illustrated embodiment, device 100 includes substrate 200, with transistor region 210 situated above the substrate.

[0024] In various embodiments, metal layers 110 and 120 (e.g., top-side / BEOL metal layers) are positioned above transistor region 210. In some embodiments, metal layers 110 and 120 are higher metal layers. For example, metal layers 110 and 120 may be metal layers that are vertically further away from transistor region 210 than other metal layers (e.g., there is an additional metal layer between transistor region 210 and metal layer 110). However, metal layers 110 and 120 may be any pair of adjacent (e.g., vertically adjacent) metal layers positioned above transistor region 210. For example, embodiments in which metal layers 110 and 120 are the two metal layers vertically closest to transistor region 210 are contemplated.

[0025] In some embodiments, a dielectric layer 220 is positioned between metal layers 110 and 120. The dielectric 220 may comprise any suitable dielectric material for providing electrical insulation and mechanical support between metal layers 110 and 120. For example, the dielectric 220 may comprise silicon oxide. A buffer transistor 130 including active regions 132A / 132B may be formed between metal layers 110 and 120 and is at least partially surrounded by the dielectric 220. In various embodiments, such as Figure 2 As shown, active areas 132A, 132B and wirings 112C to 112E are parallel and extend into and out of the page, while wiring 122B extends horizontally along the page.

[0026] Figure 3 This is a cross-sectional side view illustration of device 100 according to some embodiments, which shows along... Figure 1 The buffer transistor 140 is located at line 3-3. Note that... Figure 3 Only a portion of device 100, including the buffer transistor 140 along line 3-3, is shown. Additionally, with... Figure 2 Similarly, for illustrative purposes, the elements in device 100 (such as, but not limited to, substrate 200, transistor region 210 and dielectric 220) and their dimensions and spacing relative to each other are shown representatively.

[0027] In various embodiments, the buffer transistor 140, including active regions 142A / 142B, is formed between metal layers 110 and 120 and is at least partially surrounded by dielectric 220. In some embodiments, such as Figure 3 As shown, active areas 142A and 142B and wirings 122D to 122F are parallel and extend into and out of the page, while wiring 112B extends horizontally along the page. Figure 2 and Figure 3 As shown, a buffer transistor (e.g., buffer transistor 130 or buffer transistor 140) may be formed in the vertical space between two adjacent metal layers (e.g., metal layer 110 and metal layer 120) above the transistor region 210 of device 100 (e.g., on the top side of the transistor region).

[0028] In some embodiments, the active regions 132 of buffer transistor 130 and 142 of buffer transistor 140 are active regions made of thin channel material. For example, the channel material can be approximately several tens or fewer atomic layers. Thin channel materials can include, but are not limited to, 2D (two-dimensional) materials, CNTs (carbon nanotubes), and oxide semiconductors (e.g., indium gallium zinc oxide and tungsten-doped indium oxide). Examples of 2D materials include, but are not limited to, graphene, silicene, BNNS (boron nitride nanosheets), TMDC (transition metal dichalcogenide), phosphorene, and metal oxide nanosheets. Utilizing these types of materials allows for the realization of silicon-like active region characteristics in several layers that can be positioned between existing top-side metal layers in a device layout. As described herein, buffer transistors having these types of active regions and positioned between top-side metal layers can be implemented in various device designs, where buffer transistors are placed at various locations within a device (such as device 100) to provide buffering for signals propagating across the device.

[0029] Figures 4 to 7 A schematic diagram depicts a hypothetical implementation of a buffer transistor design that can be implemented in the space between top-side metal layers, as described herein. Figure 4 A three-dimensional perspective view of a buffer transistor 130 according to some embodiments is depicted. In the illustrated embodiments, the buffer transistor 130 is a two-stage inverter circuit, wherein active regions 132A and 132B are complementary active regions. In some embodiments, active region 132A is a p-type active region, and active region 132B is an n-type active region.

[0030] In various embodiments, the buffer transistor 130 utilizes connections to wirings 112C through 112E in the metal layer 110 to increase the strength of the signal input to the buffer transistor. In the illustrated embodiment, wiring 112D is a signal wiring, wiring 112C is a power wiring, and wiring 112E is a ground power wiring. A voltage supply input 430 for the buffer transistor 130 is provided by connecting wiring 112C (e.g., a power wiring) to source line 432 (above the metal layer 110) using via 434. Source line 432 then extends over and connects to the source region of active region 132A to provide a voltage supply input for the buffer transistor 130. A ground power input 440 for the buffer transistor 130 is provided by connecting wiring 112E (e.g., a ground power wiring) to source line 442 (above the metal layer 110) using via 444. Then, source line 442 extends over and connects to the source region of active region 132B to provide a ground power input for buffer transistor 130. Power supply wiring (e.g., wiring 112C) and ground power supply wiring (e.g., wiring 112E) also provide electrical shielding for buffer transistor 130 because the wiring (e.g., rail) is positioned along the outer periphery of the buffer transistor.

[0031] In some embodiments, wiring 112D includes input wiring 112D' connected to signal input 410 of buffer transistor 130 and output wiring 112D'' connected to signal output 420 of buffer transistor 130. Input wiring 112D' and output wiring 112D'' may be physically separated (e.g., cut-off) portions of wiring 112D within a region of buffer transistor 130. Embodiments in which input wiring 112D' and output wiring 112D'' are created by inserting electrical isolation within wiring 112D are contemplated.

[0032] In some embodiments, a signal input 410 to a buffer transistor 130 is formed by connecting an input wiring 112D' to a gate line 412 (above the metal layer 110) using a via 414. The gate line 412 then extends over both active regions 132A and 132B to form the gate for a first stage of the buffer transistor 130 (e.g., the first stage of a two-stage inverter circuit). The gate line 412 may extend, for example, over a channel region in both active regions 132A and 132B. The gate line 412 may be connected to the channel region in both active regions 132A and 132B to provide input to the first stage.

[0033] The output of the first stage is provided via stage output line 416, which extends over and connects to the drain regions of both active regions 132A and 132B. To route the output of the first stage to the input of the second stage of the buffer transistor 130 on stage output line 416, a local interconnect 418 can be connected to stage output line 416. In various embodiments, local interconnect 418 may be a C-shaped line connected to the end of stage output line 416, then routed over and connected to the channel regions of both active regions 132A and 132B to provide an input to the second stage of the buffer transistor 130. Therefore, local interconnect 418 provides a same-layer connection for routing signals from the output of the first stage of the buffer transistor 130 to the input of the second stage.

[0034] In various embodiments, routing of the local interconnect 418 is permitted if there is sufficient space between metal layer 110 and metal layer 120. For example, in a higher metal layer (e.g., a metal layer further away from the transistor region), the metal layer and the dielectric between them can be larger, and therefore have more space to accommodate the local interconnect 418. Accommodating the local interconnect 418 may include allowing routing of the local interconnect without causing it to electrically interfere with other wiring or components, or without causing it to violate any design rules or guidelines. In a lower metal layer (e.g., a metal layer closer to the transistor region), the height of the local interconnect 418 may have to be limited. In some embodiments, the local interconnect 418 may be formed using a portion of the metal layer above the buffer transistor 130 (e.g., a portion of metal layer 120). For example, vias may be added to connect the stage output line 416 to the local interconnect 418 positioned in the metal layer 120 above the buffer transistor 130.

[0035] After local interconnect 418 routes the signal to the input of the second stage of buffer circuit 130, the output of the second stage (e.g., the final signal output stage) is provided by stage output line 422. Stage output line 422 can be positioned above and connected to the drain regions of both active regions 132A and 132B. Then, via 424 is used to connect stage output line 422 (above metal layer 110) to wiring 112D'' to provide signal output 420 for buffer transistor 130. After passing through the two-stage inverter circuit of buffer transistor 130 described above, the output signal on signal output 420 has an increased strength relative to the input signal on signal input 410.

[0036] Figure 5A schematic diagram of a buffer transistor 130 according to some embodiments is depicted. In the illustrated embodiments, the buffer transistor 130 includes a first-stage inverter 510 and a second-stage inverter 520. In various embodiments, wiring 112C carries VDD 506 (e.g., a voltage supply input). Wiring 112C is connected via source line 432 to the source of the p-type region (e.g., active region 132A) in the first-stage inverter 510 and the second-stage inverter 520. Wiring 112E carries VSS 508 (e.g., a ground power supply input) and is connected via source line 442 to the source of the n-type region (e.g., active region 132B) in the first-stage inverter 510 and the second-stage inverter 520. These connections to VDD 506 and VSS 508 provide operating power to the first-stage inverter 510 and the second-stage inverter 520.

[0037] In some implementations, the first-stage inverter 510 receives the input signal 502 provided on wiring 112D'. The output of the first-stage inverter 510 is then connected to the input of the second-stage inverter 520 via a combination of stage output line 416 and local interconnect line 418. The output signal 504 is then output from the second-stage inverter 520 on wiring 112D''.

[0038] Figure 6 A three-dimensional perspective view of a buffer transistor 140 according to some embodiments is depicted. In the illustrated embodiment, the buffer transistor 140 is a two-stage inverter circuit, wherein active regions 132A and 132B are complementary active regions. In some embodiments, active region 142A is a p-type active region, and active region 142B is an n-type active region.

[0039] In various embodiments, buffer transistor 140 is structurally similar to buffer transistor 130, but connected to metal layer 120 instead of metal layer 110. For example, buffer transistor 140 may utilize connections to wirings 122D to 122F in metal layer 120 to increase the strength of the signal input to the buffer transistor. In the illustrated embodiment, wiring 122D is a power supply wiring, and wiring 122F is a ground power supply wiring. A voltage supply input 630 for buffer transistor 140 is provided by connecting wiring 122D (e.g., a power supply wiring) to source line 632 (below metal layer 120) using via 634. Source line 632 then extends over and connects to the source region of active region 142A to provide a voltage supply input for buffer transistor 140. A ground power supply input 640 for buffer transistor 140 is provided by connecting wiring 122F (e.g., a ground power supply wiring) to source line 642 (below metal layer 120) using via 644. Then, source line 642 extends over and connects to the source region of active region 142B to provide a ground power input for buffer transistor 140. Power supply wiring (e.g., wiring 122D) and ground power supply wiring (e.g., wiring 122F) also provide electrical shielding for buffer transistor 140 because the wiring (e.g., rail) is positioned along the outer periphery of the buffer transistor.

[0040] In some embodiments, wiring 122E is a signal wiring. Wiring 122E may include an input wiring 122E' connected to a signal input 610 of a buffer transistor 140 and an output wiring 122E'' connected to a signal output 620 of a buffer transistor. The input wiring 122E' and the output wiring 122E'' may be portions of wiring 122E that are physically separated (e.g., cut) in a region of the buffer transistor 140. Embodiments in which the input wiring 122E' and the output wiring 122E'' are created by inserting electrical isolation within the wiring 122E are contemplated.

[0041] In some embodiments, a signal input 610 to a buffer transistor 140 is formed by connecting an input wiring 122E' to a gate line 612 (below the metal layer 120) using a via 614. The gate line 612 extends over both the channel regions of active regions 142A and 142B to form the gate of a first stage of the buffer transistor 140 (e.g., the first stage of a two-stage inverter circuit). The gate line 612 may be connected to the channel region in both active regions 142A and 142B to provide an input to the first stage of the buffer transistor 140.

[0042] The output of the first stage is provided via stage output line 616, which extends over and connects to the drain regions of both active regions 142A and 142B. The output of the first stage is routed to the input of the second stage of the buffer transistor 140 via a local interconnect 618 connected to the stage output line 616. In various embodiments, the local interconnect 618 may be a C-shaped wire connected to the end of the stage output line 616, then routed over and connected to the channel regions of both active regions 142A and 142B to provide an input to the second stage of the buffer transistor 140. Therefore, the local interconnect 618 provides a same-layer connection for routing signals from the output of the first stage of the buffer transistor 140 to the input of the second stage.

[0043] In various embodiments, if sufficient space exists between metal layer 110 and metal layer 120, routing of a local interconnect 618, similar to local interconnect 418, is permitted. Furthermore, accommodating local interconnect 618 may include allowing routing of the local interconnect without causing it to electrically interfere with other wiring or components, or without violating any design rules or guidelines. In lower metal layers (e.g., metal layers closer to the transistor region), the height of local interconnect 618 may have to be limited. In some embodiments, under constraints, local interconnect 618 may be formed using a portion of the metal layer below buffer transistor 140 (e.g., a portion of metal layer 110). For example, vias may be added to connect stage output line 616 to local interconnect 618 located in metal layer 110 below buffer transistor 140.

[0044] After local interconnect 618 routes the signal to the input of the second stage of buffer circuit 140, the output of the second stage (e.g., the final signal output stage) is provided by stage output line 622. Stage output line 622 may be positioned above and connected to the drain regions of both active regions 142A and 142B. Via via 624 connects stage output line 622 (below metal layer 120) to wiring 122E'' to provide signal output 620 for buffer transistor 140. After passing through the two-stage inverter circuit of buffer transistor 140 described herein, the output signal at signal output 620 has an increased strength relative to the input signal at signal input 610.

[0045] Figure 7A schematic diagram of a buffer transistor 140 according to some embodiments is depicted. In the illustrated embodiments, the buffer transistor 140 includes a first-stage inverter 710 and a second-stage inverter 720. In various embodiments, wiring 122D carries VDD 706 (e.g., a voltage supply input). Wiring 122D is connected via source line 632 to the source of the p-type region (e.g., active region 142A) in the first-stage inverter 710 and the second-stage inverter 720. Wiring 122F carries VSS 708 (e.g., a ground power supply input) and is connected via source line 642 to the source of the n-type region (e.g., active region 142B) in the first-stage inverter 710 and the second-stage inverter 720. These connections to VDD 706 and VSS 708 provide operating power to the first-stage inverter 710 and the second-stage inverter 720.

[0046] In some implementations, the first-stage inverter 710 receives the input signal 702 provided on wiring 122E'. The output of the first-stage inverter 710 is then connected to the input of the second-stage inverter 720 via a combination of stage output line 616 and local interconnect line 618. The output signal 704 is then output from the second-stage inverter 720 on wiring 122E''. As described above, both buffer transistors 130 and 140 are two-stage inverter circuits capable of providing output signals (e.g., output signals 504 and 704) with a strength greater than the input signals (e.g., input signals 502 and 702). The buffer transistors are positioned on two metal layers (e.g., metal layer 110 and metal layer 120, as shown in the image). Figure 2 and Figure 3 In the case shown, the buffer transistor can provide such buffering (e.g., amplification) of the signal propagating through device 100 without any increase in the device's occupied area or area, because the buffer transistor is located in the space already present in the device.

[0047] The number and layout (e.g., placement) of the buffer transistors (e.g., buffer transistor 130 or buffer transistor 140) described herein may vary based on the design or operational needs of the device implementing the buffer transistors. For example, embodiments in which multiple buffer transistors are stacked together across multiple columns or rows of wiring in the device (e.g., across multiple wirings in metal layer 110 or metal layer 120) are conceivable. In some embodiments, the stacked buffer transistors may share a common ground power supply wiring between them. In such embodiments, the stacked buffer transistors may be stacked aligned (e.g., if the width of the active region is constrained) or stacked in an interleaved pattern to allow for a larger active region width.

[0048] Figure 8A top-side plan view of a contemplated device according to several embodiments is depicted, illustrating various layouts of a buffer transistor. In the illustrated embodiment, device 800 includes a metal layer 110 with wirings 112A to 112J and a metal layer 120 with wirings 122A to 122K. Wirings 112B and 112F may be power supply wirings (e.g., VDD), while wiring 112D is a ground power supply wiring. Wirings 112C and 112E may be signal wirings.

[0049] The pairing of buffer transistors 130A (with active regions 132A and 132B) and 130B (with active regions 132A' and 132B') represents a pair of buffer transistors stacked in alignment. Note that the complementary pair of active regions is flipped between buffer transistors 130A and 130B to allow the buffer transistors to share a ground power supply trace (trace 112D). Therefore, the active region 132B of buffer transistor 130A is adjacent to the active region 132B' of buffer transistor 130B. Although buffer transistors 130A and 130B share a common ground power supply trace, the buffer transistors have separate power supply traces (e.g., traces 112B and 112F, respectively) and also operate to buffer (e.g., amplify) different signals on different signal traces (e.g., traces 112C and 112E, respectively).

[0050] Because buffer transistors 130A and 130B are aligned (e.g., the left and right edges of the buffer transistors are aligned in the diagram), the width of the active region 132 is constrained and cannot be increased (note that the width of the active region is vertical in the diagram). Figure 8 As shown in the examples of buffer transistors 130C and 130D, interleaving the buffer transistors allows for an increase in the width of the active region 132. In the illustrated embodiment, buffer transistor 130C includes active regions 132A'' and 132B'', while buffer transistor 130D includes active regions 132A''' and 132B'''.

[0051] Similar to the pairing of buffer transistors 130A and 130B, complementary pairs of active regions are flipped between buffer transistors 130C and 130D to allow the ground power supply wiring (wiring 112D) to be shared by the buffer transistors. However, by interleaving buffer transistors 130C and 130D, the widths of active regions 132A'', 132B'', 132A''', and 132B''' can be increased because their sizes are not constrained by adjacent buffer transistors. For example, the sizes of active regions 132A'' and 132B'' in buffer transistor 130C are not constrained by the placement of buffer transistor 130D, and vice versa. Therefore, interleaving buffer transistors 130C and 130D allows for the implementation of wider active regions in device 800. These wider active regions can be used to increase the amplification strength of the buffer transistors. For example, the signal strength increase provided by buffer transistors 130C / 130D can be greater than the signal strength increase provided by buffer transistors 130A / 130B. With the active region rotated 90 degrees in a horizontal dimension parallel to the substrate, the stacked buffer transistors can be stacked in alignment (e.g., if the width of the active region is constrained), or metal layers 120 can be used as wiring (e.g., 122A to 122K) to stack in an interlaced pattern.

[0052] Although a buffer transistor has been described above, it is logical and easy for those skilled in the art to construct other logic functions and logic gates using the described concepts and constructions. For example, an inverter can be constructed simply by employing the second stage in the buffer. And for another example, other logic gates (such as NAND and NOR) can be constructed by using more wiring metal tracks in metal layer 110 or metal layer 120, and the size and width of the active region can be freely adjusted.

[0053] Example computer system Next, turn to Figure 9 This diagram illustrates a block diagram of one embodiment of system 900, which may incorporate and / or otherwise utilize the methods and mechanisms described herein. In the illustrated embodiment, system 900 includes at least one instance of a system-on-a-chip (SoC) 906, which may include various types of processing units (such as a central processing unit (CPU), graphics processing unit (GPU), or other processing units), communication architectures, and interfaces to memory and input / output devices. In some embodiments, one or more processors in SoC 906 include multiple execution lanes and instruction dispatch queues. In various embodiments, SoC 906 is coupled to external memory 902, peripheral devices 904, and power supply 908.

[0054] A power supply 908 is also provided, which supplies power voltage to the SoC 906 and one or more power voltages to the memory 902 and / or peripheral devices 904. In various embodiments, the power supply 908 represents a battery (e.g., a rechargeable battery in a smartphone, laptop, tablet, or other device). In some embodiments, more than one instance of the SoC 906 is included (and more than one external memory 902 is also included).

[0055] Memory 902 is any type of memory, such as Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Dual Data Rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, and / or low-power versions of SDRAM, such as LPDDR2), RAMBUS DRAM (RDRAM), Static RAM (SRAM), etc. One or more memory devices are coupled onto a circuit board to form a memory module, such as a Single In-line Memory Module (SIMM), a Dual In-line Memory Module (DIMM), etc. Alternatively, the devices may be mounted with a SoC or integrated circuit in a chip stack configuration, package stack configuration, or multi-chip module configuration.

[0056] Depending on the type of system 900, peripheral device 904 may include any desired circuitry. For example, in one embodiment, peripheral device 904 may include devices for various types of wireless communication, such as Wi-Fi, Bluetooth, cellular, GPS, etc. In some embodiments, peripheral device 904 may also include additional storage devices, including RAM storage devices, solid-state storage devices, or disk storage devices. Peripheral device 904 may include user interface devices such as displays, including touch displays or multi-touch displays, keyboards or other input devices, microphones, speakers, etc.

[0057] As illustrated, system 900 is shown to have applications in a wide range of fields. For example, system 900 can be used as part of a chip, circuit, component, etc., in a desktop computer 910, laptop computer 920, tablet computer 930, cellular or mobile phone 940, or television 950 (or a set-top box coupled to a television). Smartwatches and health monitoring devices 960 are also illustrated. In some embodiments, a smartwatch may include various general computing-related functions. For example, a smartwatch may provide access to email, mobile phone services, user calendars, etc. In various embodiments, a health monitoring device may be a dedicated medical device or otherwise include dedicated health-related functionality. For example, a health monitoring device may monitor a user's vital signs, track the user's proximity to other users for epidemiological social distancing purposes, contact tracing, provide communication to emergency services in the event of a health crisis, etc. In various embodiments, the aforementioned smartwatch may or may not include some or any health monitoring-related functions. Other wearable devices are also envisioned, such as devices worn around the neck, implantable devices, glasses designed to provide augmented and / or virtual reality experiences, etc.

[0058] System 900 can be further used as part of cloud-based service 970. For example, the previously mentioned devices and / or other devices can access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Furthermore, system 900 can be used in one or more devices in home 980, in addition to those previously mentioned. For example, home appliances can monitor and detect noteworthy situations. For example, various devices in the home (e.g., refrigerators, cooling systems, etc.) can monitor the status of the devices and should provide an alert to the homeowner (or, for example, a repair service) upon detecting a specific event. Alternatively, a thermostat can monitor the temperature in the home and can automatically adjust the heating / cooling system based on the homeowner's history of responses to various situations. Figure 9 The document also exemplifies the application of System 900 to various modes of transportation 990. For example, System 900 can be used for control and / or entertainment systems in airplanes, trains, buses, taxis, private cars, watercraft ranging from private boats to cruise ships, and (for rental or private use) scooters. In various cases, System 900 can be used to provide automated guidance (e.g., autonomous vehicles) and general system control. Many other implementations are possible and contemplated. It should be noted that... Figure 9 The devices and applications illustrated are merely illustrative and not intended to be limiting. Other devices are possible and envisioned.

[0059] This disclosure includes references to “implementation” or groups of “implementation” (e.g., “some implementations” or “various implementations”). An implementation is a different specific implementation or instance of the disclosed concepts. References to “implementation,” “an implementation,” “a particular implementation,” etc., do not necessarily refer to the same implementation. A large number of possible implementations are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the substance or scope of this disclosure.

[0060] This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all specific implementations of all these embodiments will necessarily exhibit any or all of the potential advantages. Whether a particular embodiment achieves an advantage depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an embodiment falling within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular embodiment may include other circuitry outside the scope of this disclosure, in conjunction with one embodiment of the disclosed embodiments, which negates or diminishes one or more of the disclosed advantages. Furthermore, suboptimal design execution of a particular embodiment (e.g., the implementing technique or tool) may also negate or diminish the disclosed advantages. Even assuming an implementation of the technique, the realization of advantages may still depend on other factors, such as the environmental circumstances in which the implementation is deployed. For example, the inputs provided to a particular embodiment may prevent one or more problems addressed in this disclosure from occurring in a particular context, and as a result, the benefits of its solution may not be realized. In view of the existence of possible factors outside this disclosure, it is hereby expressed that any potential advantages described herein should not be construed as a limitation of the claims that must be satisfied in order to prove infringement. Rather, the identification of such potential advantages is intended to illustrate the types of improvements available to the designer who benefits from this disclosure. Describing such advantages permanently (e.g., stating that a particular advantage "may occur") is not intended to convey a question about whether such advantages can actually be realized, but rather to recognize that the realization of such advantages often depends on the technological reality of additional factors.

[0061] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on this disclosure, even where only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative and not restrictive, without any statement to the contrary in this disclosure. Therefore, this application is intended to allow for claims covering the disclosed embodiments, as well as such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art to the advantage of this disclosure.

[0062] For example, the features in the present application can be combined in any suitable manner. Thus, during the filing of the present application (or an application claiming priority therefrom), new claims can be made for any such combination of features. Specifically, referring to the appended claims, the features of the dependent claims can, where appropriate, be combined with the features of other dependent claims, including claims that depend on other independent claims. Similarly, the features from the respective independent claims can be combined where appropriate.

[0063] Thus, although the appended dependent claims can be drafted such that each dependent claim depends on a single other claim, additional dependencies are also contemplated. Any combination of dependent features consistent with the present disclosure is contemplated, and these combinations can be claimed in the present application or another application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0064] Where appropriate, it is also contemplated that claims drafted in one format or statutory type (e.g., apparatus) are intended to support corresponding claims in another format or statutory type (e.g., method).

[0065] Since the present disclosure is a legal document, various terms and phrases are subject to regulatory and judicial interpretation. It is hereby announced that the following paragraphs and the definitions provided throughout the present disclosure will be used to determine how to interpret claims drafted based on the present disclosure.

[0066] References to items in the singular form (i.e., a noun or noun phrase preceded by "a," "an," or "the") are intended to mean "one or more" unless the context clearly dictates otherwise. Thus, without accompanying context, a reference to an "item" in a claim does not exclude additional instances of that item. "Multiple" items refers to a collection of two or more items.

[0067] The word "may" is used herein in an enabling sense (i.e., having the potential to, being able to), rather than in a mandatory sense (i.e., must).

[0068] The terms "comprising" and "including" and their forms are open-ended and mean "including but not limited to."

[0069] When the term “or” is used in this disclosure in relation to a list of options, it will generally be understood to be used in an inclusive sense unless the context otherwise provides. Thus, the expression “x or y” is equivalent to “x or y, or both”, and therefore covers 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as “either x or y, but not both” make it clear that “or” is used in an exclusive sense.

[0070] The expressions “w, x, y, or z, or any combination thereof” or “...at least one of w, x, y, and z” are intended to cover all possibilities involving a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase “...at least one of w, x, y, and z” therefore refers to at least one element in the set [w, x, y, z], thus covering all possible combinations of that list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0071] In this disclosure, various “labels” may precede nouns or noun phrases. Unless the context otherwise provides, different labels used for features (e.g., “first circuit,” “second circuit,” “specific circuit,” “given circuit,” etc.) refer to different instances of the feature. Additionally, unless otherwise stated, the labels “first,” “second,” and “third” do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0072] The phrase "based on" is used to describe one or more factors that influence the determination. This term does not exclude the possibility that additional factors might influence the determination. That is, the determination may be based solely on the specified factors or on the specified factors along with other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover implementations where A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on."

[0073] The phrases “responding to” and “responding” describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, whether these factors are used in conjunction with or independently of the specified factor. That is, the effect may respond solely to these factors, or it may respond to the specified factor as well as other unspecified factors. Consider the phrase “responding to B and executing A.” This phrase specifies that B is a factor that triggers the execution of A or triggers a specific result of A. This phrase does not exclude that the execution of A may also respond to certain other factors, such as C. This phrase also does not exclude that the execution of A may be jointly executed in response to B and C. This phrase is also intended to cover implementation schemes where A is executed solely in response to B. As used herein, the phrase “responding” is synonymous with the phrase “at least partially responding to.” Similarly, the phrase “responding to” is synonymous with the phrase “at least partially responding to.”

[0074] Within this disclosure, different entities (which may be referred to differently as “units,” “circuits,” other components, etc.) may be described or protected by the claims as being “configured” to perform one or more tasks or operations. This expression—[entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a tangible thing). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be considered “configured” to perform a task even if the structure is not currently being operated. Thus, an entity described or stated as being “configured” to perform a task refers to tangible things such as devices, circuits, systems with processor units, and memory storing program instructions executable to perform the task. This phrase is not used herein to refer to intangible things.

[0075] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured" to perform those tasks / operations, even if not specifically stated.

[0076] The term "configured as" is not intended to mean "able to be configured as." For example, an unprogrammed FPGA is not considered "configured as" to perform a specific function. However, the unprogrammed FPGA can be "configurable as" to perform that function. After proper programming, the FPGA can then be considered "configured as" to perform a specific function.

[0077] For the purposes of this U.S. patent application, the statement in the claims that the structure is “configured” to perform one or more tasks is expressly intended for the claim element. NoReferencing 35 USC § 112(f). If an applicant wishes to invoke part 112(f) during the filing of a U.S. patent application based on this disclosure, it will use the structure “component for [performing function]” to describe the elements of the claims.

[0078] Different “circuits” may be described in this disclosure. These circuits, or “circuits”, constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom-designed or taken from standard libraries. In various specific implementations, circuits may include digital components, analog components, or a combination of both, depending on the circumstances. Certain types of circuits may be commonly referred to as “cells” (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such cells also refer to circuits or circuitry.

[0079] Therefore, the circuits / units / components and other elements illustrated in the accompanying drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the function of that circuit. For example, a particular “decoding unit” can be described as having the function of executing “the opcode of a processing instruction and routing that instruction to one or more of a plurality of functional units,” meaning that the decoding unit is “configured” to perform that function. To those skilled in the art of computers, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0080] In various implementations, as discussed in the preceding paragraphs, the arrangement of circuits, cells, and other elements defined by the functions or operations they are configured to perform, their relationship to each other, and the manner in which such circuits / cells / components interact form a microarchitecture definition of hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, a microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations are derived, all of which fall within the broader structure described by the microarchitecture definition. That is, those skilled in the art, with the microarchitecture definition provided according to this disclosure, can implement this structure without excessive experimentation and using the application of a person of ordinary skill in the art, by encoding the description of the circuits / cells / components in a hardware description language (HDL) such as Verilog or VHDL. The HDL description is often expressed in a way that can be revealed as functional. However, for those skilled in the art, the HDL description is a way of translating the structure of a circuit, cell, or component into the details of the next level of implementation. Such HDL descriptions can take the following forms: behavioral code (which is typically non-synthesizable), Register Transfer Language (RTL) code (which is typically synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). HDL descriptions can be sequentially synthesized against a library of cells designed for a given integrated circuit manufacturing technology and can be modified for timing, power, and other reasons to obtain a final design database that is sent to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuitry or portions thereof can also be custom-designed in a schematic editor and captured into the integrated circuit design along with the synthesized circuitry. The integrated circuit can include transistors and other circuit elements (e.g., passive components such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some implementations may implement multiple integrated circuits coupled together to implement the hardware circuitry, and / or discrete components may be used in some implementations. Alternatively, the HDL design can be synthesized into a programmable logic array such as a Field Programmable Gate Array (FPGA) and implemented within the FPGA. This decoupling between the design of a set of circuits and their subsequent low-level implementations often results in a situation where the circuit or logic designer never specifies a particular set of structures for the low-level implementation that goes beyond a description of what the circuit is configured to do, because that process is performed at different stages of the circuit implementation process.

[0081] The fact that a circuit can be implemented to the same specifications using many different low-level combinations of circuit elements results in a large number of equivalent circuit structures. As noted, these low-level circuit implementations can vary depending on the manufacturing technology, the foundry chosen to manufacture the integrated circuit, the cell library provided for a particular project, and so on. In many cases, the choice of different design tools or methods to produce these different implementations can be arbitrary.

[0082] Furthermore, for a given implementation, a single concrete implementation of the circuit's specific functional specifications typically involves a large number of devices (e.g., millions of transistors). Therefore, the shearing volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single implementation, let alone a large number of equivalent possible implementations. To this end, this disclosure describes the structure of a circuit using functional abbreviations commonly used in industry.

Claims

1. An apparatus, the apparatus comprising: A transistor region of an integrated circuit, the transistor region being located above the substrate in a vertical dimension perpendicular to the substrate; A first metal layer, which is located above the transistor region in the vertical dimension; A second metal layer, which is located above the first metal layer in the vertical dimension; At least one of the first metal layer and the second metal layer includes power wiring, ground power wiring and signal wiring; and A transistor circuit, positioned in the vertical dimension between the first metal layer and the second metal layer, wherein the transistor circuit comprises: Active region; Gate; A signal input, the signal input being coupled to the gate and a portion of the signal wiring; The voltage supply input of the active region is coupled to the power supply wiring; The grounding power input of the active area is coupled to the grounding power wiring; and A signal output coupled to an additional portion of the signal wiring.

2. The apparatus of claim 1, wherein the transistor circuit is a buffer transistor circuit configured to increase the strength of the signal received at the signal input.

3. The apparatus according to claim 1, wherein the transistor circuit is an inverter transistor circuit, and the active region includes a p-type active region and an n-type active region.

4. The apparatus of claim 3, wherein the transistor circuit further comprises a partial via between one or more of the gate, the voltage supply input, the ground power input, and the signal output and one or both of the first metal layer and the second metal layer.

5. The apparatus of claim 3, wherein the transistor circuit further includes a local interconnect between the drain region and the gate region of the active region.

6. The apparatus of claim 1, wherein the power supply wiring, the ground power supply wiring, and the signal wiring are oriented parallel to each other in a horizontal dimension parallel to the substrate, and wherein the active region is positioned between the power wiring and the ground wiring in the horizontal dimension.

7. The apparatus according to claim 1, further comprising: An additional transistor circuit is positioned in the vertical dimension between the first metal layer and the second metal layer, wherein the additional transistor circuit includes an additional active region.

8. The apparatus of claim 7, wherein the additional active region is orthogonal to the active region in a horizontal dimension parallel to the substrate.

9. The apparatus of claim 1, wherein the transistor circuit is located in a dielectric layer between the first metal layer and the second metal layer.

10. The apparatus of claim 1, wherein the active region is formed of a thin channel material positioned between the first metal layer and the second metal layer.

11. An apparatus comprising: A transistor circuit, wherein the transistor circuit is located within the transistor region of an integrated circuit, and the transistor is located above the substrate in a vertical dimension perpendicular to the substrate; A first metal layer, which is located above the transistor region in the vertical dimension; A second metal layer is located above the transistor region in the vertical dimension; At least one of the first metal layer and the second metal layer includes power supply wiring, ground power supply wiring and signal wiring, wherein a portion of the signal wiring is coupled to the transistor circuit. and A transistor circuit, positioned in the vertical dimension between the first metal layer and the second metal layer, wherein the transistor circuit comprises: p-type active region; n-type active region; A gate input, the gate input being coupled to the portion of the signal wiring coupled to the transistor circuit; A voltage supply input, which is coupled to the source region in the p-type active region and the power supply wiring; A grounding power input, said grounding power input being coupled to the source region in the n-type active region and the grounding power wiring; and A gate output, which is coupled to an additional portion of the signal wiring.

12. The apparatus of claim 11, wherein the power supply wiring, the ground power supply wiring, and the signal wiring are oriented parallel to each other along a first direction in a horizontal dimension parallel to the substrate.

13. The apparatus of claim 12, wherein the p-type active region and the n-type active region are oriented parallel to each other along the first direction in the horizontal dimension.

14. The apparatus of claim 12, wherein the transistor circuit includes a gate line oriented along a second direction in the horizontal dimension, the second direction being perpendicular to the first direction, and wherein the gate line extends in the vertical dimension over both the p-type active region and the n-type active region.

15. The apparatus of claim 11, wherein the voltage supply input comprises: A metal line, the metal line being positioned at least partially above the source region in the p-type active region; and A via, which is coupled between the metal wire and the power wiring.

16. The apparatus of claim 11, wherein the grounding power input comprises: A metal line, the metal line being positioned at least partially above the source region in the n-type active region; and A via, which is coupled between the metal wire and the ground power supply wiring.

17. The apparatus of claim 11, wherein the transistor circuit comprises: A first gate line, the first gate line being oriented along a direction in the horizontal dimension, wherein the gate line is at least partially positioned above the channel regions of both the p-type active region and the n-type active region in the vertical dimension; First-stage output line, the first-stage output line being oriented along the direction, wherein the first-stage output line is at least partially positioned above the drain regions of both the p-type active region and the n-type active region in the vertical dimension; and A local interconnect line is connected to both ends of the first-stage output line, wherein at least a portion of the local interconnect line is positioned in the vertical dimension above the channel region of both the p-type active region and the n-type active region.

18. The apparatus of claim 17, wherein the gate output includes a second-stage output line oriented along a second direction, wherein the second-stage output line is at least partially positioned above the drain region of both the p-type active region and the n-type active region in the vertical dimension.

19. The apparatus of claim 11, wherein the transistor circuit is located in a dielectric layer between the first metal layer and the second metal layer.

20. An apparatus comprising: A transistor region of an integrated circuit, the transistor region being located above the substrate in a vertical dimension perpendicular to the substrate; A first metal layer, located above the transistor region in the vertical dimension, wherein the first metal layer includes a first power supply wiring, a first ground power supply wiring, and a first signal wiring; A second metal layer is located above the first metal layer in the vertical dimension, wherein the second metal layer includes a second power supply wiring, a second ground power supply wiring, and a second signal wiring. and A first buffer transistor circuit, positioned in the vertical dimension between the first metal layer and the second metal layer, wherein the first buffer transistor circuit includes: First p-type active region; The first type n active region; A first gate input, the first gate input being coupled to a portion of the first signal wiring; A first voltage supply input, the first voltage supply input being coupled to a first source region in the first p-type active region and the first power supply wiring; A first ground power input, the first ground power input being coupled to a first source region in the first n-type active region and the first ground power wiring; and A first gate output, the first gate output being coupled to an additional portion of the first signal wiring; and A second buffer transistor circuit, positioned in the vertical dimension between the first metal layer and the second metal layer, wherein the second buffer transistor circuit includes: Second p-type active region; The second type n active region; A second gate input, the second gate input being coupled to a portion of the second signal wiring; The second voltage supply input is coupled to the second source region in the second p-type active region and the second power supply wiring. A second grounding power input, coupled to the second source region in the second n-type active region and the second grounding power wiring; and A second gate output is coupled to an additional portion of the second signal wiring.

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