Component on-orbit verification system and component on-orbit verification method

Abstract

The invention provides a component on-orbit verification system and a component on-orbit verification method. The system comprises a power panel, a plurality of tested daughter boards and a main control board, the power supply board is connected with the main control board and each tested sub-board to form a power supply channel; each tested daughter board is internally provided with a POL power supply, a buffer circuit and a plurality of tested components, the POL power supply is connected with the buffer circuit and the tested components, and the buffer circuit is connected with the tested components; a power supply module, a master control FPGA and a satellite communication interface are arranged in the master control board, and the power supply module is connected with the master control FPGA and used for supplying power to the master control FPGA; the master control FPGA is connected with the buffer circuit to form an I / O channel, is connected with the satellite communication interface, and is used for generating a test instruction according to the key start bit stream and the component test program, analyzing and counting the function state data of all types of tested components to obtain batch test results, and sending the batch test results to the satellite communication interface. And sending the batch test result to a satellite platform through a satellite communication interface.

Description

Technical Field

[0001] This application mainly relates to the field of satellite testing technology, and in particular to an on-orbit verification system and method for components. Background Technology

[0002] With the booming development of commercial spaceflight, a large number of unverified components without radiation resistance are being used on commercial satellites, leading to frequent on-orbit failures. Therefore, it is necessary to design an on-orbit verification system suitable for large-scale, multi-type components to lay a data foundation for the widespread application of these components. Summary of the Invention

[0003] The purpose of this invention is to provide an on-orbit verification system and method for electronic components, which can realize on-orbit verification of large batches and various types of electronic components.

[0004] In a first aspect, this application provides an on-orbit verification system for electronic components, comprising: a power board, several sub-boards under test, and a main control board; The power board is connected to the main control board and each of the tested sub-boards to form a power channel, which is used to convert the primary power provided by the satellite platform to power the main control board and each of the tested sub-boards. Each of the test sub-boards is provided with a POL power supply, a buffer circuit and several test components, wherein the POL power supply is connected to the buffer circuit and the test components to generate a voltage rail that matches the operating power requirements of each of the several test components. The buffer circuit is connected to the device under test and is used to receive test commands from the main control board and send the functional status data of the device under test to the main control board according to the test commands. The main control board is equipped with a power supply module, a main control FPGA and a satellite communication interface, wherein the power supply module is connected to the main control FPGA and is used to supply power to the main control FPGA. The main control FPGA is connected to the buffer circuit to form an I / O channel and is also connected to the satellite communication interface. It is used to generate test instructions based on the key start bit stream and component test program, analyze and statistically analyze the functional status data of all types of components under test, obtain batch test results, and send the batch test results to the satellite platform through the satellite communication interface.

[0005] In some embodiments, the test instructions include instructions for verifying single-event effects of the device under test, wherein the single-event effects include single-event lockout, single-event flip, single-event interruption, and single-event burnout.

[0006] In some embodiments, the power board is provided with a short-circuit protection module, a soft-start module, a filtering module and a power module; The short-circuit protection module is connected to the primary power supply and is used to realize graded protection and surge suppression functions; The soft-start module is connected to the filter module and is used to realize the soft-start function inside the power board; The filtering module is connected to the power supply module and is used to filter out high-frequency interference inside the power supply board and suppress low-frequency interference. The power module is connected to the main control board and each tested sub-board to prevent interference and create an isolated environment for the power supply.

[0007] In some embodiments, the main control board is further provided with a program storage module, a watchdog circuit, a data storage module, and a transceiver module; The program storage module is used to store the key startup bit stream and component test program in a triple redundancy manner; The watchdog circuit is used to implement the automatic restart function of the main control FPGA; The data storage module is used to store the test results and functional bit streams of each of the tested components; The transceiver module is used to establish communication between the main control board and each of the tested sub-boards.

[0008] In some embodiments, the main control FPGA includes a main control power control module, multiple test result statistics modules for different component types, an interface communication module, and a test result feedback control module; wherein the different component types include: AD conversion type, power supply type, memory type, and logic gate circuit type; The main power control module is connected to the multiple test result statistics modules and the components under test on all the test sub-boards. It is used to realize the EN control and PG status monitoring of the components under test on all the test sub-boards, and to send the monitored PG status to the test result statistics module with the same component type. Each of the multiple test result statistics modules is connected to a component under test of the same type, and is used to realize the functional control of the component under test of the same type, and to count the test results of the component under test of the same type. The test result feedback control module and the multiple test result statistics modules are used to summarize the test results of all components under test. The interface communication module is connected to the test result feedback control module to realize bidirectional transmission of the summarized test results.

[0009] In some embodiments, the plurality of test sub-boards, the main control board and the power board are stacked together in a layered structure, wherein an aluminum alloy frame is used for contact positioning between each two layers.

[0010] In some embodiments, the satellite communication interface includes an LVDS signal interface, a CAN interface, and an RS-422 interface.

[0011] In some embodiments, the buffer circuit includes a power supply control module under test, a load switch, and a level conversion chip; The power supply under test control module is connected to the main control FPGA and is used to realize the EN control and PG status monitoring of the load switch; The load switch is connected to the POL power supply and is used to monitor the current status of the plurality of tested components and to control the power on and off of the plurality of tested components. The level conversion chip is connected to the main control FPGA and the plurality of devices under test, and is used to select the transmission direction of the communication and to realize the signal level conversion between the main control FPGA and the plurality of devices under test.

[0012] In a second aspect, this application provides an on-orbit verification method for components, applied to an on-orbit verification system for components as described in some embodiments of the first aspect, comprising: The main control FPGA obtains the current status of the several memory-type components through the load switch in the target board under test, which is equipped with several memory-type components, and determines whether the current status is abnormal. If the current status is abnormal, the main control FPGA restarts the load switch through the power supply control module under test in the target board under test. When the load switch is restarted, restoring the functionality of the plurality of storage components, the main control FPGA records a single-event lock-up event occurring in the plurality of storage components; and, If the load switch is restarted more than twice and the functions of the storage components cannot be restored, the main control FPGA records the failure of the storage components and will no longer participate in subsequent tests.

[0013] In some embodiments, the on-orbit verification method for components further includes: The main control FPGA writes initial data to the plurality of storage components through the level conversion chip in the target test board; The main control FPGA reads data from the plurality of storage components in one reading cycle and compares it with the initial data; If more than one bit of incorrect judgment occurs within a bit width during a read cycle, the main control FPGA records a single-event flip for the plurality of storage components.

[0014] The beneficial effects of this application are as follows: 1. Implement an on-orbit verification system and method applicable to a large number of diverse components. The number of test sub-boards can be set according to different power consumption constraints, thereby improving energy utilization and verification efficiency.

[0015] 2. Based on modular and standardized interface design, a reconfigurable verification platform is established to improve adaptability and scalability to different satellite platforms; 3. It realizes multiple coverage detections of existing single-event effects and is compatible with any type of component, with a wide range of applications; 4. This solution adopts a multi-channel parallel verification architecture, which has a simple circuit hardware design and facilitates subsequent expansion. Attached Figure Description

[0016] The above and other objects, features, and advantages of this disclosure will become more apparent from the more detailed description of some embodiments thereof in the accompanying drawings, in which: Figure 1 This invention provides an assembly schematic diagram of an on-orbit verification system for components. Figure 2 An exploded view of an on-orbit verification system for components provided in this application is shown; Figure 3 The system block diagram of the on-orbit verification system for components is shown; Figure 4 A schematic diagram of the power tree of the on-orbit verification system for components is shown. Figure 5 The functional block diagram of the main control FPGA is shown; Figure 6 A flowchart of the on-orbit verification method for components provided in this application is shown. Detailed Implementation

[0017] The principles of this disclosure will now be described with reference to some embodiments. It should be understood that these embodiments are described for illustrative purposes only and to assist those skilled in the art in understanding and implementing this disclosure, and do not impose any limitation on the scope of this disclosure. The disclosure described herein may be implemented in ways other than those described below.

[0018] In the following description and claims, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains.

[0019] References to "an embodiment," "embodiment," "exemplary embodiment," etc., in this disclosure indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment needs to include specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an exemplary embodiment, whether explicitly described or not, those skilled in the art will recognize that such a feature, structure, or characteristic affects its connection to other embodiments.

[0020] It should be understood that while the terms “first” and “second”, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The term “and / or” as used herein includes any and all combinations of one or more of the listed terms.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. The singular forms “a,” “an,” and “the” used herein also include the plural forms unless the context clearly indicates otherwise. The terms “a group of elements” or “a collection of elements” as used herein are intended to include one or more elements. It should also be understood that the terms “comprising,” “including,” “having,” “possessing,” “including,” and / or “comprising,” when used herein, specify the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof.

[0022] Figure 1 This paper shows an assembly schematic diagram of an on-orbit verification system for components provided in this application. Figure 2 An exploded view of an on-orbit verification system for components provided in this application is shown. See also... Figure 1 , Figure 2 The on-orbit verification system for components includes: a power board, and several (e.g., ...) Figure 1 The n items in the test board and the main control board, where n is an integer greater than 1.

[0023] Several test sub-boards, main control boards and power supply boards are stacked together in a layered structure, with aluminum alloy frames used for contact positioning between each two layers, thereby ensuring excellent protection and structural strength of the circuit board.

[0024] Figure 3 The system block diagram of the on-orbit verification system for components is shown.

[0025] Specifically, the power supply board is connected to the main control board and each test board to form a power channel, which is used to convert the primary power provided by the satellite platform to power the main control board and each test board. Each test board is equipped with a POL power supply, a buffer circuit, and several test components. The POL power supply is connected to the buffer circuit and the test components to generate a voltage rail that matches the operating power requirements of each test component. The buffer circuit is connected to the test components to receive test commands from the main control board and send the functional status data of the test components to the main control board according to the test commands. The main control board is equipped with a power supply module, a main control FPGA, and a satellite communication interface. The power supply module is connected to the main control FPGA to power the main control FPGA. The main control FPGA is connected to the buffer circuit to form an I / O channel and is connected to the satellite communication interface. It is used to generate test commands based on the key start bit stream and the component test program, analyze and statistically analyze the functional status data of all types of test components to obtain batch test results, and send the batch test results to the satellite platform through the satellite communication interface.

[0026] Satellite communication interfaces include LVDS signal interface, CAN interface and RS-422 interface.

[0027] Specifically, the components under test (DUTs) within each DUT can be of the same or different types, without restriction. The number of DUTs can be flexibly adjusted based on the satellite platform's weight, power consumption, size envelope allocation requirements, and component verification needs, thereby improving resource utilization efficiency.

[0028] exist Figure 3 In the example shown, the power board, the main control board, and each daughter board under test have connectors, so that a power channel is formed between the power board and the main control board and each daughter board under test, and an I / O channel is formed between the main control board and each daughter board under test.

[0029] In this example, the type and quantity of the components under test on each sub-board under test can be configured according to the maximum power consumption of each sub-board under test. For example, based on the average power consumption distribution of the satellite platform and the power consumption of the main control board and power supply board, the maximum power consumption of the specified sub-board under test is calculated with a 50% margin principle, thereby determining the maximum power consumption of the sub-board under test.

[0030] The test instructions generated by the main control FPGA include instructions for verifying the single-event effects of the device under test. The single-event effects include single-event lockout, single-event flip, single-event interrupt, and single-event burnout. The specific configuration can be configured according to the type and quantity of the device under test.

[0031] like Figure 3 As shown, in this embodiment, the buffer circuit includes a power supply control module under test, a load switch, and a level conversion chip.

[0032] The power supply under test (UTP) control module is connected to the main control FPGA to implement EN control of the load switch and PG status monitoring; the load switch is connected to the POL power supply to monitor the current status of several UTP components and to implement power-on / off control of several UTP components; the level conversion chip is connected to the main control FPGA and several UTP components to select the transmission direction of communication and to implement signal level conversion between the main control FPGA and several UTP components.

[0033] Figure 4 A power tree diagram of an on-orbit verification system for components is shown. (For example...) Figure 1 , Figure 4 As shown, the power board contains a short-circuit protection module, a soft-start module, a filtering module, and a power supply module.

[0034] The short-circuit protection module is connected to the primary power supply to implement graded protection and surge suppression functions; the soft-start module is connected to the filter module to implement the soft-start function inside the power board; the filter module is connected to the power supply module to filter out high-frequency interference inside the power board and suppress low-frequency interference; the power supply module is connected to the main control board and each tested sub-board to prevent interference and form an isolated power supply environment.

[0035] Specifically, taking a power board with an input voltage of 28V and an output voltage rail of 12V as an example, the power tree of the on-orbit verification system for components includes two branches. One branch undergoes voltage conversion through a POL power supply to generate various voltage rails such as 5V / 3.3V / 1.8V for supplying power to several components under test individually or in combination. The other branch undergoes voltage conversion through a power supply module to generate various voltage rails such as 5V / 3.3V / 1.8V for supplying power to the main control board.

[0036] Figure 5 The functional block diagram of the main control FPGA is shown. Figure 5 The main control FPGA includes a main control power control module, multiple test result statistics modules for different component types, an interface communication module, and a test result feedback control module. The different component types include: AD conversion type, power type, memory type, and logic gate circuit type.

[0037] The main power control module is connected to multiple test result statistics modules and all devices under test (DUTs) on the DUTs, enabling EN control and PG status monitoring of all DUTs on the DUTs, and sending the monitored PG status to the test result statistics module with the same component type. Each of the multiple test result statistics modules is connected to a DUT of the same type, enabling functional control of each DUT of the same type and statistical analysis of the test results. The test result feedback control module is connected to multiple test result statistics modules to summarize the test results of all DUTs. The interface communication module is connected to the test result feedback control module to enable bidirectional transmission of the summarized test results.

[0038] exist Figure 3 In the example shown, the main control FPGA is JFM7K325T-C; multiple test result statistics modules include a single-event effect test result statistics module for connecting AD conversion devices, a feedback signal level monitoring test result statistics module for connecting power supply devices, a storage read / write / erase control test result statistics module for connecting storage devices, and an IO / RAM toggle function interrupt test result statistics module for connecting logic gate circuit devices.

[0039] Specifically, the test result statistics module in the main control FPGA is not limited to the above examples. The above examples are only for reference and can be flexibly adjusted according to the total number of types of components under test.

[0040] like Figure 3 As shown, the main control board also includes a program storage module, a watchdog circuit, a data storage module, and a transceiver module.

[0041] The program storage module is used to store key startup bit streams and component test programs in a triple-modular redundancy manner; the watchdog circuit is used to realize the automatic restart function of the main control FPGA; the data storage module is used to store the test results and functional bit streams of each component under test; the transceiver module is used to establish communication between the main control board and each daughter board under test.

[0042] The beneficial effects of the above-mentioned on-orbit verification system for components are: 1. Implement an on-orbit verification system and method applicable to a large number of diverse components. The number of test sub-boards can be set according to different power consumption constraints, thereby improving energy utilization and verification efficiency.

[0043] 2. Based on modular and standardized interface design, a reconfigurable verification platform is established to improve adaptability and scalability to different satellite platforms; 3. It realizes multiple coverage detections of existing single-event effects and is compatible with any type of component, with a wide range of applications; 4. This solution adopts a multi-channel parallel verification architecture, which has a simple circuit hardware design and facilitates subsequent expansion.

[0044] Another aspect of this application provides an on-orbit verification method for electronic components, implemented using the on-orbit verification system for electronic components described in the above embodiments, for detecting single-event effects in storage-type electronic components.

[0045] Single-event effects in storage devices include two types: single-event lock-in and single-event flip.

[0046] Figure 6 A flowchart of the on-orbit verification method for components provided in this application is shown. This method is applied to, for example... Figure 3 The component on-orbit verification system shown.

[0047] like Figure 6 As shown, the process for detecting single-event lock (SOL) in storage devices includes the following steps: The main control FPGA obtains the current status of several memory-type components by setting load switches in the target board under test, which contains several memory-type components.

[0048] The system determines whether the current status is abnormal. If the current status is abnormal, the main control FPGA restarts the load switch through the power supply control module in the target board under test. If the current status is abnormal, no action is taken. When the load switch is restarted and the functions of several storage components are restored, the main control FPGA records that a single-event lock occurs in several storage components. If the load switch is restarted more than twice and the functions of several storage components cannot be restored, the main control FPGA records the failure of several storage components and they will no longer be included in subsequent tests.

[0049] like Figure 6 As shown, the process for detecting single-event upsets in storage devices includes the following steps: The main control FPGA writes initial data to several storage components through the level conversion chip in the target board under test; The main control FPGA reads data from several storage components within one read cycle and compares it with the initial data; If more than one bit of incorrect judgment occurs within a bit width in a read cycle, the main control FPGA records a single-event flip for several storage components.

[0050] Specifically, any single-event effects that could lead to functional failure in other types of components can also be implemented in the above-mentioned on-orbit verification system for components, which will not be elaborated here.

[0051] The basic concepts have been described above. Obviously, for those skilled in the art, the above disclosure is merely illustrative and does not constitute a limitation of this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this application, and therefore remain within the spirit and scope of the exemplary embodiments of this application.

[0052] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic related to at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0053] Some aspects of this application can be executed entirely by hardware, entirely by software (including firmware, resident software, microcode, etc.), or by a combination of hardware and software. The aforementioned hardware or software may be referred to as a "data block," "module," "engine," "unit," "component," or "system." The processor may be one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DAPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, or combinations thereof. Furthermore, aspects of this application may manifest as computer products residing in one or more computer-readable media, including computer-readable program code. For example, computer-readable media may include, but are not limited to, magnetic storage devices (e.g., hard disks, floppy disks, magnetic tapes, etc.), optical discs (e.g., compressed CDs, digital multifunction DVDs, etc.), smart cards, and flash memory devices (e.g., cards, sticks, key drives, etc.).

[0054] A computer-readable medium may contain a propagated data signal containing computer program code, for example, on baseband or as part of a carrier wave. This propagated signal may take various forms, including electromagnetic, optical, and so on, or suitable combinations thereof. A computer-readable medium can be any computer-readable medium other than a computer-readable storage medium, which can be connected to an instruction execution system, apparatus, or device to enable communication, propagation, or transmission of a program for use. The program code located on the computer-readable medium can be propagated through any suitable medium, including radio, cable, fiber optic cable, radio frequency signals, or similar media, or any combination of the above media.

[0055] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0056] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used in the description of embodiments are modified in some examples with the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may be changed depending on the characteristics required by individual embodiments. In some embodiments, numerical parameters should take into account specified significant digits and employ a general method of digit reservation. Although the numerical ranges and parameters used to confirm their breadth of scope in some embodiments of this application are approximate values, in specific embodiments, such values ​​are set as precisely as feasible.

Claims

1. An on-orbit verification system for electronic components, characterized in that, include: The power supply board, several test sub-boards, and the main control board; The power board is connected to the main control board and each of the tested sub-boards to form a power channel, which is used to convert the primary power provided by the satellite platform to power the main control board and each of the tested sub-boards. Each of the test sub-boards is provided with a POL power supply, a buffer circuit and several test components, wherein the POL power supply is connected to the buffer circuit and the test components to generate a voltage rail that matches the operating power requirements of each of the several test components. The buffer circuit is connected to the device under test and is used to receive test commands from the main control board and send the functional status data of the device under test to the main control board according to the test commands. The main control board is equipped with a power supply module, a main control FPGA and a satellite communication interface, wherein the power supply module is connected to the main control FPGA and is used to supply power to the main control FPGA. The main control FPGA is connected to the buffer circuit to form an I / O channel and is also connected to the satellite communication interface. It is used to generate test instructions based on the key start bit stream and component test program, analyze and statistically analyze the functional status data of all types of components under test, obtain batch test results, and send the batch test results to the satellite platform through the satellite communication interface.

2. The on-orbit verification system for components as described in claim 1, characterized in that, The test instructions include instructions for verifying the single-event effect of the device under test, wherein the single-event effect includes single-event lockout, single-event flip, single-event interruption, and single-event burnout.

3. The on-orbit verification system for components as described in claim 1, characterized in that, The power board is equipped with a short-circuit protection module, a soft-start module, a filtering module and a power module; The short-circuit protection module is connected to the primary power supply and is used to realize graded protection and surge suppression functions; The soft-start module is connected to the filter module and is used to realize the soft-start function inside the power board; The filtering module is connected to the power supply module and is used to filter out high-frequency interference inside the power supply board and suppress low-frequency interference. The power module is connected to the main control board and each tested sub-board to prevent interference and create an isolated environment for the power supply.

4. The on-orbit verification system for components as described in claim 1, characterized in that, The main control board is also equipped with a program storage module, a watchdog circuit, a data storage module, and a transceiver module; The program storage module is used to store the key startup bit stream and component test program in a triple redundancy manner; The watchdog circuit is used to implement the automatic restart function of the main control FPGA; The data storage module is used to store the test results and functional bit streams of each of the tested components; The transceiver module is used to establish communication between the main control board and each of the tested sub-boards.

5. The on-orbit verification system for components as described in claim 1, characterized in that, The main control FPGA includes a main control power control module, multiple test result statistics modules for different component types, an interface communication module, and a test result feedback control module; wherein the different component types include: AD conversion type, power supply type, memory type, and logic gate type; The main power control module is connected to the multiple test result statistics modules and the components under test on all the test sub-boards. It is used to realize the EN control and PG status monitoring of the components under test on all the test sub-boards, and to send the monitored PG status to the test result statistics module with the same component type. Each of the multiple test result statistics modules is connected to a component under test of the same type, and is used to realize the functional control of the component under test of the same type, and to count the test results of the component under test of the same type. The test result feedback control module and the multiple test result statistics modules are used to summarize the test results of all components under test. The interface communication module is connected to the test result feedback control module to realize bidirectional transmission of the summarized test results.

6. The on-orbit verification system for components as described in claim 1, characterized in that, The plurality of test sub-boards, the main control board and the power board are stacked together in a layered structure, with an aluminum alloy frame used for contact positioning between each two layers.

7. The on-orbit verification system for components as described in claim 1, characterized in that, The satellite communication interface includes an LVDS signal interface, a CAN interface, and an RS-422 interface.

8. The on-orbit verification system for components as described in claim 1, characterized in that, The buffer circuit includes a power supply control module under test, a load switch, and a level conversion chip. The power supply under test control module is connected to the main control FPGA and is used to realize the EN control and PG status monitoring of the load switch; The load switch is connected to the POL power supply and is used to monitor the current status of the plurality of tested components and to control the power on and off of the plurality of tested components. The level conversion chip is connected to the main control FPGA and the plurality of devices under test, and is used to select the transmission direction of the communication and to realize the signal level conversion between the main control FPGA and the plurality of devices under test.

9. A method for on-orbit verification of electronic components, characterized in that, The system is applied to the on-orbit verification system for components as described in claim 8, comprising: The main control FPGA obtains the current status of the several memory-type components through the load switch in the target board under test, which is equipped with several memory-type components, and determines whether the current status is abnormal. If the current status is abnormal, the main control FPGA restarts the load switch through the power supply control module under test in the target board under test. When the load switch is restarted, restoring the functionality of the plurality of storage components, the main control FPGA records a single-event lock-up event occurring in the plurality of storage components; and, When the load switch is restarted more than twice and the functions of the storage components cannot be restored, the main control FPGA records the failure of the storage components so that the storage components will no longer participate in subsequent tests.

10. The on-orbit verification method for components as described in claim 9, characterized in that, Also includes: The main control FPGA writes initial data to the plurality of storage components through the level conversion chip in the target test board; The main control FPGA reads data from the plurality of storage components in one reading cycle and compares it with the initial data; If more than one bit of incorrect judgment occurs within a bit width during a read cycle, the main control FPGA records a single-event flip for the plurality of storage components.

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