ATE clock signal adjusting system and adjusting method

Abstract

The invention provides an ATE clock signal adjusting system and method, and the system comprises a data clock signal transmitting module which is used for transmitting a data clock signal to a signal adjusting module; the signal adjusting module is used for configuring and sending a first control level, a second control level or a third control level corresponding to a current state level to the chip to be tested based on the current state level of the data clock signal; the first control level is configured to be higher than a nominal high level value of the chip to be tested, and the second control level is configured to be lower than a nominal low level value of the chip to be tested; the third control level is configured to be equal to a nominal low level value of the chip to be tested. By adopting the scheme, signal attenuation caused by long-line transmission and a one-drive multi-topological structure can be effectively compensated, so that the amplitude of the data clock signal at the chip end to be tested meets the requirement and has allowance. Moreover, the leakage current of the chip is prevented from being increased, and the service life of the to-be-tested chip is prolonged.

Description

Technical Field

[0001] This invention relates to the field of digital circuit design technology, and in particular to an ATE clock signal adjustment system and adjustment method. Background Technology

[0002] Automated test equipment typically consists of multiple resource boards, each of which integrates multi-pin electronic chips. These pin electronic chips integrate core functions such as drivers and comparators.

[0003] During actual testing, the control commands and data signals output by the ASIC chip are connected to the differential input data bus of the pin electronics chip. When the chip under test (DUT) requires a clock input, the ASIC chip outputs a corresponding signal, and the pin electronics chip activates its drive function, sending the data clock signal to the DUT. The high and low levels output by the pin electronics chip can be configured via a digital-to-analog converter (DAC).

[0004] To save testing resources and improve testing efficiency, a one-to-many topology is usually adopted on the pin card, which branches the drive signal of one pin electronic chip into multiple paths, such as eight paths, and sends them to eight chips under test respectively.

[0005] However, after the data clock signal is output from the pin electronics chip, it needs to travel a relatively long transmission path to reach the chip under test (DUT). Specifically, the signal is first transmitted to the pin header via a cable approximately 50 centimeters long, then through a trace approximately 10 to 20 inches long on the pin header, and finally through a probe to contact the clock pin of the DUT. Due to the long transmission path, signal loss and reflection occur during transmission, resulting in a degraded signal quality.

[0006] like Figure 1 and Figure 2 As shown, taking a serial flash memory chip powered by a 50 MHz data clock signal and a 3V power supply as an example, the high level of the pin electronic chip is configured as 3V, and the low level as 0V, with a peak-to-peak voltage of 3V. Due to the excessively long signal path and the heavy line load caused by the one-drive-multiple topology, the signal is severely attenuated. The peak-to-peak voltage reaching the chip under test is approximately 2.5V - 0.6V = 1.9V, a voltage compression of about 1.1V. At this point, the high level of the chip under test is approximately 2.5V, and the low level is approximately 0.6V. Although this meets the requirements, there is absolutely no margin. Fifty MHz is already the rate limit under this signal topology. Summary of the Invention

[0007] This invention provides an ATE clock signal adjustment system and method that, while ensuring the normal operation of the chip under test, ensures that the amplitude of the data clock signal at the chip under test meets the requirements and has a margin.

[0008] This invention discloses a multi-point linkage protection system for ATE equipment, the system comprising: Chip under test; The data clock signal transmitting module is configured to send a data clock signal to the signal conditioning module; The signal adjustment module configures and sends a first control level, a second control level, or a third control level corresponding to the current state level to the chip under test based on the current state level of the data clock signal. Wherein, the first control level is configured to be higher than the nominal high level value of the chip under test, the second control level is configured to be lower than the nominal low level value of the chip under test, and the third control level is configured to be equal to the nominal low level value of the chip under test.

[0009] Furthermore, the system also includes: a state division module; The state division module is configured to divide state levels into one-to-one correspondences with the first control level, the second control level, and the third control level based on the flip state and time interval of the data clock signal.

[0010] Furthermore, the signal adjustment module includes a digital-to-analog converter; The digital-to-analog converter is used to configure the level value of the first control level, the second control level, or the third control level issued by the signal adjustment module.

[0011] Furthermore, the signal adjustment module also includes a signal control unit and a signal output unit; Based on the current state level, the signal control unit sends a control command to the signal output unit to output the first control level, the second control level, or the third control level. The signal output unit outputs the first control level, the second control level, or the third control level to the chip under test based on the control command.

[0012] Furthermore, it also includes: resource boards, cable assemblies, and pin connectors; The output terminal of the signal output unit is connected to the resource board, the resource board is connected to the pin card through the cable assembly, and the pin card is connected to the chip under test.

[0013] Furthermore, it also includes a feedback module; The chip under test receives and responds to the data clock signal, and sends the response signal to the feedback module. The feedback module is configured to receive the response signal and transmit the response signal back to the signal control unit.

[0014] Another aspect of the present invention provides an ATE clock signal adjustment method, the method comprising: Send data clock signal; Based on the current state level of the data clock signal, configure and send a first control level, a second control level, or a third control level corresponding to the current state level to the chip under test; Wherein, the first control level is configured to be higher than the nominal high level value of the chip under test, the second control level is configured to be lower than the nominal low level value of the chip under test, and the third control level is configured to be equal to the nominal low level value of the chip under test.

[0015] Furthermore, before identifying the current state level of the data clock signal, the method further includes: Based on the flip state and time interval of the data clock signal, state levels are divided to correspond one-to-one with the first control level, the second control level, and the third control level.

[0016] Furthermore, the state level includes a valid high level state, a valid low level state, and an invalid level state; Wherein, the data clock signal being in a valid high-level state refers to the period from the rising edge to the falling edge of the data clock signal; the data clock signal being in a valid low-level state refers to the period from the falling edge to the rising edge of the data clock signal; and the data clock signal being in an invalid level state refers to the period during which the data clock signal stops toggling.

[0017] Furthermore, based on the current state level of the data clock signal, configuring and sending a first control level, a second control level, or a third control level corresponding to the current state level to the chip under test includes: When the data clock signal is in the effective high level state, the signal adjustment module sends the first control level to the chip under test; When the data clock signal is in the effective low level state, the signal adjustment module sends the second control level to the chip under test; When the data clock signal is in the invalid level state, the signal adjustment module sends the third control level to the chip under test.

[0018] Another aspect of the present invention provides an ATE one-drive multi-testing device that employs the aforementioned ATE clock signal adjustment system.

[0019] Compared with the prior art, the present invention has at least the following technical effects: During valid clock transitions, this invention employs a first control level higher than the nominal high level and a second control level lower than the nominal low level to perform overdrive compensation. This effectively compensates for signal attenuation caused by long-line transmission and multi-topology single-drive systems, ensuring that the signal amplitude reaching the chip under test meets requirements and has sufficient margin. During the inactive clock period, a third control level equal to the nominal low level is used to prevent increased chip leakage current and improve the lifespan of the chip under test. Attached Figure Description

[0020] Figure 1 This is a simplified diagram illustrating the signal waveform of a clock signal in the background technology. Figure 2 This is a simplified schematic diagram of the ATE clock signal adjustment system in Embodiment 1 of the present invention; Figure 3 This is a simplified schematic diagram of the clock signal waveform obtained by the ATE clock signal adjustment system in Embodiment 1 of the present invention. Figure 4 This is a simplified structural diagram of the ATE clock signal adjustment system in Embodiment 1 of the present invention; Figure 5 This is a diagram of the ATE clock signal transmission link in Embodiment 1 of the present invention; Figure 6 This is a simplified schematic diagram of the structure of the pin card PCB trace with one drive for eight pins in Embodiment 1 of the present invention. Detailed Implementation

[0021] The following description, with reference to schematic diagrams, illustrates a preferred embodiment of the present invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0022] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0023] Example 1 Please refer to Figure 2 This embodiment discloses an ATE clock signal adjustment system, the system comprising: The chip under test (DUT) includes a data clock signal transmitting module configured to send a data clock signal TX_D to the signal adjustment module. The signal adjustment module, based on the current state level of the data clock signal TX_D, configures and sends a first control level Vih, a second control level Vil, or a third control level VTT corresponding to the current state level to the DUT to adjust the amplitude of the data clock signal TX_D. Specifically, the first control level Vih is configured to be higher than the nominal high level value of the DUT, the second control level Vil is configured to be lower than the nominal low level value of the DUT, and the third control level VTT is configured to be equal to the nominal low level value of the DUT.

[0024] In this embodiment, during the valid clock transition period, overdrive compensation is performed using a first control level Vih (higher than the nominal high level) and a second control level Vil (lower than the nominal low level). This effectively compensates for signal attenuation caused by long-line transmission and the multi-topology single-drive configuration, ensuring that the signal amplitude reaching the chip under test meets the requirements and has sufficient margin. During the idle period when the clock is invalid, a third control level VTT (equal to the nominal low level) is used to prevent increased chip leakage current and improve the lifespan of the chip under test.

[0025] The inventors discovered that because the data clock signal TX_D needs to be transmitted over a long line and uses a one-drive-multiple topology, the signal suffers severe attenuation, resulting in insufficient signal margin at the chip under test (DUT). While overdrive methods can compensate for signal attenuation by boosting the high level and lowering the low level, improving the signal margin during effective clock transitions, the idle period when the clock is ineffective allows sufficient time for the voltage to stabilize to the set level. This leads to increased leakage current in the DUT, causing test failures.

[0026] Therefore, this embodiment also includes the following: during the idle period when the clock is invalid, the chip is driven by a third control level VTT equal to the nominal low level value to avoid voltage causing an increase in chip leakage current, thereby ensuring the normal operation of the chip under test while maintaining signal integrity.

[0027] In this embodiment, the nominal high-level value is the standard high-level voltage value required for the chip under test to operate normally, that is, the standard voltage that the chip can correctly identify as logic "1". The nominal low-level value is the standard low-level voltage value required for the chip under test to operate normally, that is, the standard voltage that the chip can correctly identify as logic "0".

[0028] Furthermore, the system also includes a state division module.

[0029] The state division module is configured to divide the state levels into one-to-one correspondences with the first control level Vih, the second control level Vil, and the third control level VTT based on the toggle state and time interval of the data clock signal TX_D.

[0030] In this embodiment, the state division module is integrated into the control chip ASIC. The data clock signal transmission module is integrated into the pin electronics chip.

[0031] In this embodiment, the state level includes a valid high level state, a valid low level state, and an invalid level state; wherein, the data clock signal TX_D being in a valid high level state means that the data clock signal TX_D is between the rising edge and the falling edge; the data clock signal TX_D being in a valid low level state means that the data clock signal TX_D is between the falling edge and the rising edge; and the data clock signal TX_D being in an invalid level state means that the data clock signal TX_D stops toggling.

[0032] The following is a specific example of signal compensation based on an ATE clock signal adjustment system: In traditional two-level driving schemes, the pin electronics chip configures the high level as 3V and the low level as 0V. Due to signal attenuation, the high level reaches only 2.5V and the low level is only 0.6V when it reaches the chip under test, which is just at the critical state.

[0033] Please refer to Figure 3 Using the ATE clock signal adjustment system disclosed in this embodiment, the first control level Vih is configured to 3.4V, the second control level Vil to -0.3V, and the third control level VTT to 0V. Then, during the transmission of four clock pulses—that is, when the data clock signal TX_D is between its rising and falling edges (effective high level)—the signal adjustment module outputs the first control level Vih at 3.4V; when the data clock signal TX_D is between its falling and rising edges (effective low level)—the signal adjustment module outputs the second control level Vil at -0.3V. After line attenuation, the high level reaching the chip under test is approximately 2.6V, and the low level is approximately 0.4V, meeting the level requirements and providing a margin. Finally, when the four clock pulses have been transmitted and the clock enters a static state (ineffective level state), the signal adjustment module switches to outputting the third control level VTT at 0V, ensuring that no leakage voltage appears at the chip under test and preventing an increase in leakage current.

[0034] In one specific example, the signal conditioning module includes a digital-to-analog converter.

[0035] The digital-to-analog converter is used to configure the level values ​​of the first control level Vih, the second control level Vil, or the third control level VTT issued by the signal adjustment module.

[0036] Furthermore, the signal adjustment module also includes a signal control unit and a signal output unit.

[0037] The signal control unit sends a control command to the signal output unit based on the current state level, which outputs the first control level Vih, the second control level Vil, or the third control level VTT. The signal output unit outputs the first control level Vih, the second control level Vil, or the third control level VTT to the chip under test based on the control command.

[0038] In a specific example, the signal control unit is a logic control circuit (not shown) integrated within a control chip ASIC. This logic control circuit generates corresponding control instructions CTRL and the data clock signal TX_D, sending them to the pin-level electronic chip, based on the current state of the data clock signal TX_D. When the data clock signal TX_D is at a valid high level, the logic control circuit outputs a control instruction corresponding to the first control level Vih; when the data clock signal TX_D is at a valid low level, it outputs a control instruction corresponding to the second control level Vil; and when the data clock signal TX_D is at an invalid level, it outputs a control instruction corresponding to the third control level VTT.

[0039] Please refer to Figure 4 In another specific example, the signal output unit is a multiplexer driver circuit 1 integrated within a pin-based electronic chip. The input terminals of this multiplexer driver circuit 1 are respectively connected to a first control level Vih, a second control level Vil, and a third control level VTT configured by the digital-to-analog converter. The control signal input terminal is connected to the control command CTRL, and the data signal input terminal is connected to the data clock signal TX_D. The output terminal is connected to the DATA pin of the pin-based electronic chip, from which the data clock signal is output to the chip under test (DUT). The multiplexer driver circuit 1 selects and outputs the corresponding control level to the DUT based on the combination of the control command sent by the ASIC and the data clock signal TX_D. The multiplexer driver circuit 1 can be configured via the serial peripheral interface bus of the ASIC to enable the three-level output function.

[0040] Please refer to Figure 5 The ATE clock signal adjustment system also includes a resource board, cable assemblies, and pin cards; The output terminal of the signal output unit is connected to the resource board, the resource board is connected to the pin card through the cable assembly, and the pin card is connected to the chip under test.

[0041] Furthermore, the ATE clock signal adjustment system also includes a feedback module.

[0042] The chip under test receives and responds to the data clock signal, and the response signal is sent to the feedback module; the feedback module is configured to receive the response signal of the chip under test and send the response signal back to the signal control unit.

[0043] Please continue to refer to this. Figure 4 In a specific example, the feedback module is comparator 2. The input of comparator 2 is connected to the data pin DATA of the pinned electronic chip to receive the response signal from the chip under test. The output of comparator 2 is connected to the signal control unit of the control chip via the receive data channel RX_D. Comparator 2 is configured to convert the analog response signal returned by the chip under test into a digital signal and transmit it back to the signal control unit for analysis and processing via the receive data channel RX_D, thereby achieving closed-loop control of signal transmission.

[0044] In this embodiment, the pin electronic chip also includes an enable signal VTT_EN, which is the third control level VTT function enable bit, configured by the control chip ASIC via the Serial Peripheral Interface (SPI) bus. When the enable signal VTT_EN is enabled and the control signal CTRL is high, the pin electronic chip outputs the third control level VTT regardless of the state of the data clock signal TX_D, corresponding to the invalid level state of the clock signal. When the control signal CTRL is low, the pin electronic chip outputs either the first control level Vih or the second control level Vil according to the state of the data clock signal TX_D, corresponding to the valid high level state and valid low level state of the clock signal, respectively.

[0045] In this embodiment, the ATE clock signal adjustment system is suitable for batch testing of memory chips such as serial flash memory chips, NOR Flash, NAND Flash, and EEPROM. In the field of microcontroller testing, the device is suitable for testing MCU chips using serial interfaces such as SPI and I2C. Furthermore, the device can also be applied to parallel testing of various types of integrated circuits such as sensor chips, power management chips, and RF chips. Those skilled in the art can select different one-drive multi-test devices according to actual needs; no specific limitations are imposed here.

[0046] In terms of topology, the ATE clock signal adjustment system supports multiple parallel test chips such as one-to-four, one-to-eight, one-to-sixteen, or even one-to-thirty-two. Those skilled in the art can select the number of parallel test chips according to the actual situation, and no specific restrictions are made here.

[0047] Please refer to Figure 6 Taking a pin-type PCB trace with one-to-eight capability as an example, the black lines in the diagram represent the copper foil traces on the pin-type PCB that transmit clock signals, and the circular nodes represent signal branching points. After a single clock signal is output from the pin-type electronic chip PE, it branches step by step through the pin-type PCB traces: first, it splits into two paths at the first-level branch node, and each path then splits into four paths at the second-level branch node, ultimately forming a parallel test topology with one-to-eight capability, simultaneously driving eight chips under test.

[0048] Example 2 Based on the same inventive concept, this embodiment discloses an ATE clock signal adjustment method, which is implemented using the ATE clock signal adjustment system disclosed in Embodiment 1. The method includes: S1. Send data clock signal TX_D; S2. Based on the current state level of the data clock signal TX_D, configure and send a first control level Vih, a second control level Vil, or a third control level VTT corresponding to the current state level to the chip under test; Wherein, the first control level Vih is configured to be higher than the nominal high level value of the chip under test, the second control level Vil is configured to be lower than the nominal low level value of the chip under test, and the third control level VTT is configured to be equal to the nominal low level value of the chip under test.

[0049] In this embodiment, the state level includes a valid high level state, a valid low level state, and an invalid level state.

[0050] Wherein, the data clock signal TX_D being in a valid high-level state means that the data clock signal TX_D is in the period from rising edge to falling edge; the data clock signal TX_D being in a valid low-level state means that the data clock signal TX_D is in the period from falling edge to rising edge; and the data clock signal TX_D being in an invalid level state means that the data clock signal TX_D stops toggling.

[0051] Specifically, in step S2, configuring and sending a first control level Vih, a second control level Vil, or a third control level VTT corresponding to the current state level to the chip under test based on the current state level of the data clock signal TX_D includes: S31. When the data clock signal TX_D is in the effective high level state, the signal adjustment module sends the first control level Vih to the chip under test; S32. When the data clock signal TX_D is in the effective low level state, the signal adjustment module sends the second control level Vil to the chip under test; S33. When the data clock signal TX_D is in the invalid level state, the signal adjustment module sends the third control level VTT to the chip under test.

[0052] In a specific example, the first control level Vih of the pinned electronic chip is set to 3.4V, and the second control level Vil is set to -0.3V, with a peak-to-peak voltage of 3.7V. After line attenuation, the peak-to-peak voltage reaching the chip under test is approximately 2.6V - 0.4V = 2.2V, with a high level of approximately 2.6V and a low level of approximately 0.4V. This meets the voltage level requirements of the chip under test and provides a certain margin. During the idle period when the clock is invalid, the signal conditioning module outputs a third control level VTT of 0V, ensuring that no negative voltage appears at the chip under test and preventing test failure due to increased leakage current caused by negative voltage.

[0053] It is understood that the above-mentioned ATE clock signal adjustment method and the ATE clock signal adjustment system disclosed in Embodiment 1 are based on the same technical design principle, and both can achieve the same technical purpose. The effect that the ATE clock signal adjustment system can achieve has been described in detail in Embodiment 1, so it will not be repeated here.

[0054] Various modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the invention. Thus, if these modifications and variations of the invention fall within the scope of the claims of the invention and their equivalents, the invention is also intended to include these modifications and variations.

Claims

1. An ATE clock signal adjustment system, characterized in that, The system includes: Chip under test; The data clock signal transmitting module is configured to send a data clock signal to the signal conditioning module; The signal adjustment module configures and sends a first control level, a second control level, or a third control level corresponding to the current state level to the chip under test based on the current state level of the data clock signal. Wherein, the first control level is configured to be higher than the nominal high level value of the chip under test, the second control level is configured to be lower than the nominal low level value of the chip under test, and the third control level is configured to be equal to the nominal low level value of the chip under test.

2. The ATE clock signal adjustment system as described in claim 1, characterized in that, The system also includes: a state division module; The state division module is configured to divide state levels into one-to-one correspondences with the first control level, the second control level, and the third control level based on the flip state and time interval of the data clock signal.

3. The ATE clock signal adjustment system as described in claim 1, characterized in that, The signal adjustment module includes a digital-to-analog converter; The digital-to-analog converter is used to configure the level value of the first control level, the second control level, or the third control level.

4. The ATE clock signal adjustment system as described in claim 3, characterized in that, The signal adjustment module also includes a signal control unit and a signal output unit; Based on the current state level, the signal control unit sends a control command to the signal output unit to output the first control level, the second control level, or the third control level. The signal output unit outputs the first control level, the second control level, or the third control level to the chip under test based on the control command.

5. The ATE clock signal adjustment system as described in claim 4, characterized in that, Also includes: Resource boards, cable assemblies, and pin headers; The output terminal of the signal output unit is connected to the resource board, the resource board is connected to the pin card through the cable assembly, and the pin card is connected to the chip under test.

6. The ATE clock signal adjustment system as described in claim 5, characterized in that, It also includes a feedback module; The chip under test receives and responds to the data clock signal, and sends the response signal to the feedback module. The feedback module is configured to receive the response signal and transmit the response signal back to the signal control unit.

7. A method for adjusting an ATE clock signal, characterized in that, The method includes: Send data clock signal; Based on the current state level of the data clock signal, configure and send a first control level, a second control level, or a third control level corresponding to the current state level to the chip under test; Wherein, the first control level is configured to be higher than the nominal high level value of the chip under test, the second control level is configured to be lower than the nominal low level value of the chip under test, and the third control level is configured to be equal to the nominal low level value of the chip under test.

8. The ATE clock signal adjustment method as described in claim 7, characterized in that, Before sending a data clock signal to the chip under test, the method further includes: Based on the flip state and time interval of the data clock signal, state levels are divided to correspond one-to-one with the first control level, the second control level, and the third control level.

9. The ATE clock signal adjustment method as described in claim 8, characterized in that, The state levels include a valid high level state, a valid low level state, and an invalid level state; Wherein, the data clock signal being in a valid high-level state refers to the period from the rising edge to the falling edge of the data clock signal; the data clock signal being in a valid low-level state refers to the period from the falling edge to the rising edge of the data clock signal; and the data clock signal being in an invalid level state refers to the period during which the data clock signal stops toggling.

10. The ATE clock signal adjustment method as described in claim 9, characterized in that, Based on the current state level of the data clock signal, configuring and sending a first control level, a second control level, or a third control level corresponding to the current state level to the chip under test includes: When the data clock signal is in the effective high level state, the signal adjustment module sends the first control level to the chip under test; When the data clock signal is in the effective low level state, the signal adjustment module sends the second control level to the chip under test; When the data clock signal is in the invalid level state, the signal adjustment module sends the third control level to the chip under test.

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