Advanced extensible interface bus control module and random access data memory

Abstract

The invention belongs to the technical field of communication and data processing, and particularly relates to an advanced extensible interface bus control module and a random access data memory. Comprising a write channel interface module which establishes a write address channel, a write data channel and a write response channel between the write channel interface module and an advanced extensible interface, writes data into a random storage array and receives write control and address signals from the random storage array; an address reading channel and a data reading channel are established between the reading channel interface module and the advanced extensible interface, reading control and address signals are input to the random storage array, and data stored in the random storage array are read; the single-channel read-write arbitration module is used for arbitrating read-write requests of the write channel interface module and the read channel interface module; according to the invention, the data storage and processing requirements of high data depth and high data width can be met, and meanwhile, the method has relatively low resource occupation and relatively low data read-write delay.

Description

Technical Field

[0001] This invention belongs to the field of communication and data processing technology, and specifically relates to an advanced expandable interface bus control module and a random access data memory. Background Technology

[0002] With the development of communication and data processing technologies, the bandwidth of parallel processing data is becoming increasingly abundant. This has led to higher demands on the data bandwidth, multi-port scalability, and low latency of traditional programmable gate array (PLA) random access data memories. Therefore, an advanced scalable interface bus control module for random access data memories has emerged.

[0003] Given the use of various types of random access data storage (RAM), with varying interface bandwidth and storage depth, significant latency exists between different RAMs during data read and write operations. Furthermore, data read / write operations, system time, and error correction / verification across different RAM cells are all critical factors in the data storage and processing process. Summary of the Invention

[0004] The purpose of this invention is to provide an advanced scalable interface bus control module and a random access data storage device. This invention can be used in high-speed, low-latency data storage and processing, and can meet the data storage and processing requirements of high data depth and high data width, while having low resource consumption and low data read and write latency.

[0005] To address the aforementioned technical problems, this invention provides an advanced scalable interface bus control module, comprising:

[0006] The write channel interface module establishes write address channels, write data channels, and write response channels with the advanced extensible interface, writes data to the random access memory array, and receives write control and address signals from the random access memory array.

[0007] The read channel interface module establishes read address channels and read data channels with the advanced expandable interface, and inputs read control and address signals to the random access memory array, as well as reads data stored in the random access memory array;

[0008] A single-channel read / write arbitration module is used to arbitrate read / write requests from the write channel interface module and the read channel interface module.

[0009] The verification register module is connected to the optional verification module within the write channel interface module and the read channel interface module. The optional verification module is used to generate a check bit when writing to the random access memory array and to perform data integrity verification when reading out of the random access memory array. The verification register module is used to issue an interrupt signal when a write transaction is completed, a read transaction is completed, or a verification error occurs.

[0010] Preferably, the write channel interface module includes:

[0011] The write address pipeline has its input connected to the bus write address signal [14:0] and its output connected to the logic "1" terminal of the unaligned narrowband burst control module 1, WRAP address generation module 1, address increment module 1 and the second selector.

[0012] The non-aligned narrowband burst control module one includes input burst size signals [7:0] at its input end and access address of module one at its output end;

[0013] The WRAP address generation module has its output address connected to module one.

[0014] Address increment module one, whose output terminal is connected to the logic "0" terminal of the second selector, and the output terminal of the second selector outputs random storage address signals [14:0];

[0015] ECC verification module one and ECC verification module two, the input terminal of ECC verification module one receives read data signals [39:0], the output terminal one of ECC verification module one outputs error-correctable signals and non-error-correctable signals, and the output terminal two of ECC verification module one is connected to data correction module one, the output terminal of data correction module one is connected to the logic "0" terminal of the third selector; the input terminal of ECC verification module two receives bus write data signals [31:0], the output terminal one of ECC verification module two outputs random read and write data signals [39:0], the output terminal two of ECC verification module two is connected to the logic "1" terminal of the third selector, and the output terminal of the third selector outputs random read and write data signals [39:0];

[0016] The ID caching module takes the write address ID signal as input and outputs the write response ID signal as output.

[0017] Preferably, the read channel interface module includes:

[0018] The read address pipeline has its input connected to the bus read address signal [14:0] and its output connected to the logic "1" terminal of the unaligned narrowband burst control module II, WRAP address generation module II, address increment module II and the fifth selector.

[0019] The second unaligned narrowband burst control module also includes an input burst size signal [7:0] at its input end, and the output end is connected to the address of the second module.

[0020] WRAP address generation module two, whose output end is connected to module two;

[0021] Address addition module two, whose output terminal is connected to the logic "0" terminal of the fifth selector, and the output terminal of the fifth selector outputs random storage address signal [14:0];

[0022] The buffer pipeline receives read data signals [39:0] at its input end and connects to the logic "1" terminal of the ECC verification module's three and six selectors at its output end;

[0023] ECC verification module three and data correction module two, the output terminal one of the ECC verification module three outputs an error-correctable signal and an error-uncorrectable signal, and the output terminal two of the ECC verification module three outputs a read error correction signal to the logic "0" terminal of the sixth selector, the output terminal three of the ECC verification module three is connected to the data correction module two, the output terminal of the data correction module two outputs a read data signal to the logic "0" terminal of the sixth selector; the output terminal of the sixth selector outputs a bus read data signal [39:0].

[0024] Preferably, the write address pipeline, the read address pipeline, and the buffer pipeline each consist of a cache and a selector.

[0025] Preferably, the address increment module one and the address increment module two are loopback burst address generation modules; the data correction module one and the data correction module two include a Hamming code error correction generation module, a Hamming code single-bit error correction module, and a single error correction and double error detection generation module; the ECC verification module one, the ECC verification module two, and the ECC verification module three include a Hamming code module and a single error correction and double error detection module; the WRAP address generation module one and the WRAP address generation module two are address generators for the WRAP burst controller.

[0026] Preferably, the Hamming code error correction generation module includes a parity check module and an 18-bit wide data input XOR module; the ID cache module is a BID synchronization module, which implements a FIFO buffer based on SRL16E for synchronizing the BID signal.

[0027] The present invention also provides a random access data storage device, comprising:

[0028] The random access memory array consists of a normal data storage array, a redundant storage array, and a built-in self-test controller. The normal data storage array is used to store data in normal mode. The redundant storage array is used to replace faulty partitioning units in the normal data storage array during self-testing in replacement mode. The built-in self-test controller is used to control the self-testing behavior of the memory and has priority control.

[0029] As described above, an advanced scalable interface bus control module has one end connected to the random access memory array and the other end connected to the advanced scalable interface bus, and the advanced scalable interface bus is connected to two master devices and one slave device.

[0030] Preferably, both the normal storage array and the redundant storage array are composed of multiple array-distributed static storage cells, sharing word lines in the horizontal direction and bit lines in the vertical direction; data can be read and written to any storage cell of the array through the joint operation of row decoding circuit and column decoding circuit; the storage cell is opened by raising the word line, and then read or write operations are performed through the bit line pairs.

[0031] Preferably, the built-in self-test controller includes:

[0032] A built-in self-test address generator is used to generate memory addresses in the self-test state, which is implemented by an address counter;

[0033] A built-in self-test data generator is used to generate data in the self-test state, which is implemented by a state machine;

[0034] The built-in self-test verification module is used to test the storage units of normal data storage arrays and redundant storage arrays to determine whether the corresponding storage units are abnormal, and to pass the test results to the built-in self-test response module.

[0035] A built-in self-test response module is used to respond to the self-test results provided by the built-in self-test verification module in order to avoid invalid redundant replacements.

[0036] Preferably, the following data reading process is also included:

[0037] Initialize the register state and keep it idle;

[0038] Read data acquisition address; enable via advanced expandable interface bus, control module's main reset input signal for system reset and acquisition address start; output signal to drive random access memory array reset interface, and acquire address at the same system time;

[0039] Read the secure address of the data; after the second clock cycle following data acquisition, transmit the data address to the address interface of the random access memory array and use it as the secure address;

[0040] Read data full flag; Read address data from random access memory array, random access address to memory array, add read address and near empty offset and compare with write address to generate near empty flag; add write address and near full offset and compare with read address to generate near full flag; compare read address and write address, and generate empty full flag according to the status of near empty and near full flags.

[0041] Complete data reading; obtain valid and secure data from the random state memory through the data storage register, and synchronize and align the data according to the clock and reset signals for easy data retrieval at any time;

[0042] Read the last address of the data; the address obtained after the clock edge is mapped to the address control port and configuration word line of the random state memory;

[0043] The last data is read completely; through read control logic and adjustment of delay, read enable is generated sequentially within one cycle to obtain the corresponding stored data from a storage unit;

[0044] Read the last data on the bus; adjust the read data according to address and timing and send it to the advanced expandable bus, and read it according to the control operation of the master and slave devices;

[0045] Read the data and wait for new instructions; after completing the read and storage operation, allow new instructions to intervene. If read and write requests occur simultaneously, read takes priority.

[0046] Compared with the prior art, the present invention has the following beneficial effects:

[0047] This invention discloses an advanced scalable interface for random access data storage. It includes an advanced scalable bus write channel interface module, a read channel interface module, an optional single-channel read / write arbitration module, and an error checking operation status module. The read / write channel supports a maximum parallel data width of 1024 bits and a maximum address width of 64 bits for data access depth. The entire module supports a maximum clock frequency of 300 MHz, and the minimum clock latency for the data read channel is 3 clock cycles. It allows for flexible configuration of interface data bandwidth and storage depth, enabling synchronous processing latency across different random access data storage devices during data read and write operations. The method described in this application can be used in high-speed, low-latency data storage and processing, meeting the needs of data storage and processing with high data depth and high data width, while also exhibiting low resource consumption and low data read / write latency. Attached Figure Description

[0048] Figure 1 This is a system architecture diagram of an advanced scalable interface bus control module in one embodiment.

[0049] Figure 2 This is a logic block diagram of the write channel interface module in one embodiment.

[0050] Figure 3 This is a logic block diagram of the phase increment calculation module of the read channel interface module in one embodiment.

[0051] Figure 4 This is a schematic diagram of the data reading process in one embodiment.

[0052] Figure 5 This is a schematic diagram of a random access data storage device in one embodiment. Detailed Implementation

[0053] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0054] like Figures 1-5 As shown, this embodiment of the invention specifically provides an advanced expandable interface bus control module, including:

[0055] The write channel interface module establishes write address channels, write data channels, and write response channels with the advanced extensible interface, writes data to the random access memory array, and receives write control and address signals from the random access memory array.

[0056] The read channel interface module establishes read address channels and read data channels with the advanced expandable interface, and inputs read control and address signals to the random access memory array, as well as reads data stored in the random access memory array;

[0057] A single-channel read / write arbitration module is used to arbitrate read / write requests from the write channel interface module and the read channel interface module.

[0058] The verification register module is connected to the optional verification module within the write channel interface module and the read channel interface module. The optional verification module is used to generate a check bit when writing to the random access memory array and to perform data integrity verification when reading out of the random access memory array. The verification register module is used to issue an interrupt signal when a write transaction is completed, a read transaction is completed, or a verification error occurs.

[0059] Preferably, the write channel interface module includes:

[0060] The write address pipeline has its input connected to the bus write address signal [14:0] and its output connected to the logic "1" terminal of the unaligned narrowband burst control module 1, WRAP address generation module 1, address increment module 1 and the second selector.

[0061] The non-aligned narrowband burst control module one includes input burst size signals [7:0] at its input end and access address of module one at its output end;

[0062] The WRAP address generation module has its output address connected to module one.

[0063] Address increment module one, whose output terminal is connected to the logic "0" terminal of the second selector, and the output terminal of the second selector outputs random storage address signals [14:0];

[0064] ECC verification module one and ECC verification module two, the input terminal of ECC verification module one receives read data signals [39:0], the output terminal one of ECC verification module one outputs error-correctable signals and non-error-correctable signals, and the output terminal two of ECC verification module one is connected to data correction module one, the output terminal of data correction module one is connected to the logic "0" terminal of the third selector; the input terminal of ECC verification module two receives bus write data signals [31:0], the output terminal one of ECC verification module two outputs random read and write data signals [39:0], the output terminal two of ECC verification module two is connected to the logic "1" terminal of the third selector, and the output terminal of the third selector outputs random read and write data signals [39:0];

[0065] The ID caching module takes the write address ID signal as input and outputs the write response ID signal as output.

[0066] Preferably, the read channel interface module includes:

[0067] The read address pipeline has its input connected to the bus read address signal [14:0] and its output connected to the logic "1" terminal of the unaligned narrowband burst control module II, WRAP address generation module II, address increment module II and the fifth selector.

[0068] The second unaligned narrowband burst control module also includes an input burst size signal [7:0] at its input end, and the output end is connected to the address of the second module.

[0069] WRAP address generation module two, whose output end is connected to module two;

[0070] Address addition module two, whose output terminal is connected to the logic "0" terminal of the fifth selector, and the output terminal of the fifth selector outputs random storage address signal [14:0];

[0071] The buffer pipeline receives read data signals [39:0] at its input end and connects to the logic "1" terminal of the ECC verification module's three and six selectors at its output end;

[0072] ECC verification module three and data correction module two, the output terminal one of the ECC verification module three outputs an error-correctable signal and an error-uncorrectable signal, and the output terminal two of the ECC verification module three outputs a read error correction signal to the logic "0" terminal of the sixth selector, the output terminal three of the ECC verification module three is connected to the data correction module two, the output terminal of the data correction module two outputs a read data signal to the logic "0" terminal of the sixth selector; the output terminal of the sixth selector outputs a bus read data signal [39:0].

[0073] Preferably, the write address pipeline, the read address pipeline, and the buffer pipeline each consist of a cache and a selector.

[0074] Preferably, the address increment module one and the address increment module two are loopback burst address generation modules; the data correction module one and the data correction module two include a Hamming code error correction generation module, a Hamming code single-bit error correction module, and a single error correction and double error detection generation module; the ECC verification module one, the ECC verification module two, and the ECC verification module three include a Hamming code module and a single error correction and double error detection module; the WRAP address generation module one and the WRAP address generation module two are address generators for the WRAP burst controller.

[0075] Preferably, the Hamming code error correction generation module includes a parity check module and an 18-bit wide data input XOR module; the ID cache module is a BID synchronization module, which implements a FIFO buffer based on SRL16E for synchronizing the BID signal.

[0076] The Advanced Scalable Interface (AMI) for accessing random access memory (RAM) meets the performance requirements of AMI-based systems and provides minimal latency for RAM access. The latency from active to ready response for each channel is one clock cycle, depending on current kernel activity. AMI RAM separates write and read channel activities, allowing the control module to handle read and write operations from the AMI simultaneously, while the checksum register module obtains injection and checksum status via an additional, independent optional interface. The timing relationships between all write addresses and write data channels (as well as read addresses and read data channels) are designed to conform to the AMI standard, thus avoiding any deadlocks.

[0077] The Advanced Expansion Interface (ALEI) random access memory does not perform address decoding; all received operations are accepted. ALEI provides address decoding through read / write modules.

[0078] All random access memories (RAMs) compatible with the Advanced Scalable Interface (ASPI) data can be interconnected with the ASPI bus control module. The slave input port of the RAM control module on the ASPI bus interconnect is equal to the width of the RAM (equal to the size of the ASPI RAM control module). The ASPI RAM does not need to know the data width or burst size of the requesting master because the interconnector translates all operations to accommodate the data width and burst size of the data bus connected to the ASPI RAM (and block memory). The ASPI bus control, through the addition of read / write data and error correction design, simultaneously controls the random access memory array for read / write and redundant operations. The read / write channel supports a maximum parallel data width of 1024 bits and a maximum data access depth of 64 bits for the address width. The maximum supported clock frequency for the entire module is 300 MHz, and the minimum clock delay for the data read channel is 3 clock cycles. The error correction code generates an 8-bit error correction bit by operating on 64 bits of data. It can correct single-bit errors and detect double-bit errors.

[0079] In this embodiment, all write operations are initiated on the write address channel (AW) of the advanced scalable bus, which specifies the type of write transaction and the corresponding address information. The address bus can be latency-controlled via a register or directly input. The handshake protocol follows a valid and ready mechanism. All address and control information is only valid upon confirmation of a valid signal. When a slave station issues a ready signal, it will capture the signal and accept the operation. The write data channel (W) transmits all write data for a single or burst write operation. The write response channel (B) is used for handshaking or responding to write operations.

[0080] This embodiment is used to generate WRAP addresses for read / write channels. When the address exceeds the boundary, it restarts from the starting position; the maximum WRAP value is controlled by generating a corresponding control signal based on whether the current access has reached the maximum limit.

[0081] Design strategy for this embodiment:

[0082] (1) Calculate the total access size required based on the current advanced scalable bus request and the random state memory address to ensure that the effective address range is not exceeded during WRAP burst transfers.

[0083] (2) Cyclic adjustment: When the address exceeds the boundary, start again from the starting position.

[0084] (3) Control the maximum WRAP value: Generate the corresponding control signal based on whether the current access has reached the maximum limit. Check the current burst type to generate a narrow burst count load value for unaligned narrow burst transmissions of operation type WRAP / INCR.

[0085] Design strategy: Calculate the number of bytes per address and the narrow burst address offset based on the current burst length and burst transmission size, and adjust the load value of the narrow burst transmission.

[0086] Buffered line operations are implemented on the advanced scalable bus as WRAP burst types when submitted to random state memory. The address bus can be latency-controlled via registers or directly input. The WRAP burst type allows burst sizes of 2, 4, 8, and 16 data transfers.

[0087] WRAP bursts are processed in the controller's address generator logic and submitted to the random state memory. The address seen by the random state memory must increment to the boundary and then wrap around to the beginning of the cache line address. For example, the processor sends a first cache line read request for the target word to address 0x04h. The 32-bit random state memory will see the following address request sequence: 0x04h, 0x08h, 0x0Ch, 0x00h.

[0088] Figure 4 The diagram shown illustrates a data reading process in one embodiment. In one embodiment, the data reading state machine includes the following steps:

[0089] Step 401: Initialize the register state and keep it idle.

[0090] by Figure 3 Taking the logic block diagram of the read channel phase increment calculation module shown as an example, the data state is initialized, the previous state value is cleared, and the array unit is initialized in a certain order. The 7-bit wide address from the FPGA control module changes from high to low and remains in an idle state.

[0091] Step 402: Read the data acquisition address.

[0092] The advanced expandable bus interface is re-enabled, and the controller's main reset input signal is used for system reset and address acquisition start. The output signal drives the random access memory array reset interface and acquires the same system time for address acquisition.

[0093] Step 403: Read the data security address.

[0094] After the second clock cycle following data acquisition, the data address is transmitted to the address interface of the random access memory array and used as a secure address.

[0095] Step 404: Read the full data flag.

[0096] The first step is to write the address data from the random access memory (RAM) onto the bus. The second step is to read the address data from the RAM. The third step is to write the random access address back to the RAM, add the read address and the near-empty offset, compare it with the write address to generate a near-empty flag; add the write address and the near-full offset, compare it with the read address to generate a near-full flag; compare the read address and write address, and generate an empty / full flag based on the near-empty and near-full flags. Since the read and write addresses are generated by different clocks, the generation of status flags is cross-clock domain. To avoid metastability caused by asynchronous transmission and to correctly generate status flags, a binary-to-Gray code converter is needed to ensure that only one bit of the address changes at any given time.

[0097] Step 405: Read the complete data.

[0098] The system obtains valid and secure data from the random state storage device through the data storage register, and synchronizes and aligns the data according to the clock and reset signals, facilitating data retrieval at any time.

[0099] Step 406: Read the last address of the data.

[0100] The address obtained by the clock edge is mapped to the address control port and configuration word line of the random state storage device.

[0101] Step 407: Read the final data completely.

[0102] Through fully customized read control logic, the latency can be adjusted to sequentially generate read enable / disable reads within a single cycle, thus completing the aforementioned functions. Specifically, for a given storage unit, the corresponding stored data is retrieved.

[0103] Step 408: Read the last data on the bus.

[0104] After completing step 407, the read data is sent to the advanced expandable bus according to the address and timing adjustment, and read according to the control operation of the master and slave devices.

[0105] Step 409: Read the data and wait for new instructions.

[0106] After a read-to-store operation is completed, new commands can be allowed to intervene. If read and write requests occur simultaneously, read takes priority.

[0107] Figure 5 The diagram shown illustrates a random access data memory in one embodiment. In one embodiment, the storage unit is as follows:

[0108] The array is composed of static storage cells that share word lines horizontally and bit lines vertically. Data can be read from and written to any storage cell in the array through the combined operation of row and column decoding circuits. The storage cell is opened by raising the word line, and then read or write operations are performed using the bit line pairs.

[0109] The random access memory (RAM) array's storage cells are dual-port read / write capable. Based on a standard 6T complementary CMOS memory cell, two word lines are introduced to modify it into an 8T cell. This results in a stable structure, eliminates static DC power consumption, and achieves high-level operation through P-channel transistor conduction, eliminating threshold loss and increasing anti-interference capability. It includes a pair of cross-coupled inverters. If the data is subjected to slight interference, the positive feedback loop can recover the data.

[0110] During a read operation, BL and BLN are precharged to a high level, then WL is raised to turn on the transmission transistor, and then discharged through the transmission transistor to pull a bit line down. During a write operation, BL or BLN is pulled low, and the internal node is written with new data by discharging through the transmission transistor.

[0111] The sensitive amplifier is a differential latch-type sensitive amplifier, which is faster and consumes less power than traditional op-amp type amplifiers.

[0112] and Figure 5 A redundant architecture design for a random access data storage device is a storage system with a redundant architecture and built-in self-detection and self-repair functions, including:

[0113] Normal data storage array, used to store data in normal mode;

[0114] Redundant storage columns are used in replacement mode to replace faulty partitions in the normal data storage array during self-testing;

[0115] The system includes a built-in self-test controller to control the self-testing behavior of the memory, and this built-in self-test controller has priority control; a built-in self-test address generator to generate memory addresses in the self-testing state, implemented by an address counter; a built-in self-test data generator to generate data in the self-testing state, implemented by a state machine; a built-in self-test verification module to test the memory cells of normal and redundant memory arrays, determine whether the corresponding memory cells are abnormal, and pass the test results to the built-in response module; and a built-in self-test response module to respond to the self-test results provided by the built-in self-test verification module, avoiding invalid redundant replacements.

[0116] During the chip power-on phase, test data is written and read from the normal and redundant memory arrays and compared with the original test data to generate self-test results. When only one partition cell of the memory array fails, the response module changes the internal address mapping relationship through self-testing to ensure that the memory can still work normally, which can significantly improve the chip yield.

[0117] In one embodiment, a data access interface is provided, which can be a high-level scalable interface that can access random access memory. At the same time, for low-latency, high-bandwidth memory, this module can also be used for the storage and processing of real data.

[0118] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. An advanced expandable interface bus control module, characterized in that, include: The write channel interface module establishes write address channels, write data channels, and write response channels with the advanced extensible interface, writes data to the random access memory array, and receives write control and address signals from the random access memory array. The read channel interface module establishes read address channels and read data channels with the advanced expandable interface, and inputs read control and address signals to the random access memory array, as well as reads data stored in the random access memory array; A single-channel read / write arbitration module is used to arbitrate read / write requests from the write channel interface module and the read channel interface module. The verification register module is connected to the optional verification module within the write channel interface module and the read channel interface module. The optional verification module is used to generate a check bit when writing to the random access memory array and to perform data integrity verification when reading out of the random access memory array. The verification register module is used to issue an interrupt signal when a write transaction is completed, a read transaction is completed, or a verification error occurs.

2. The advanced expandable interface bus control module as described in claim 1, characterized in that, The write channel interface module includes: The write address pipeline has its input connected to the bus write address signal [14:0] and its output connected to the logic "1" terminal of the unaligned narrowband burst control module 1, WRAP address generation module 1, address increment module 1 and the second selector. The non-aligned narrowband burst control module one includes input burst size signals [7:0] at its input end and access address of module one at its output end; The WRAP address generation module has its output address connected to module one. Address increment module one, whose output is connected to the logic "0" terminal of the second selector, and the output of the second selector outputs random storage address signals [14:0]; ECC verification module one and ECC verification module two, wherein the input terminal of ECC verification module one receives read data signals [39:0], the output terminal one of ECC verification module one outputs error-correctable signals and non-error-correctable signals, and the output terminal two of ECC verification module one is connected to data correction module one, the output terminal of data correction module one is connected to the logic "0" terminal of a third selector; the input terminal of ECC verification module two receives bus write data signals [31:0], the output terminal one of ECC verification module two outputs random read / write data signals [39:0], the output terminal two of ECC verification module two is connected to the logic "1" terminal of a third selector, and the output terminal of the third selector outputs random read / write data signals [39:0]; The ID caching module takes the write address ID signal as input and outputs the write response ID signal as output.

3. The advanced expandable interface bus control module as described in claim 2, characterized in that, The read channel interface module includes: The read address pipeline has its input connected to the bus read address signal [14:0] and its output connected to the logic "1" terminal of the unaligned narrowband burst control module II, WRAP address generation module II, address increment module II and the fifth selector. The second unaligned narrowband burst control module also includes an input burst size signal [7:0] at its input end, and the output end is connected to the address of the second module. WRAP address generation module two, whose output end is connected to module two; Address addition module two, whose output terminal is connected to the logic "0" terminal of the fifth selector, and the output terminal of the fifth selector outputs random storage address signal [14:0]; The buffer pipeline receives read data signals [39:0] at its input end and connects to the logic "1" terminal of the ECC verification module's three and six selectors at its output end; ECC verification module three and data correction module two, the output terminal one of the ECC verification module three outputs an error-correctable signal and an error-uncorrectable signal, and the output terminal two of the ECC verification module three outputs a read error correction signal to the logic "0" terminal of the sixth selector, the output terminal three of the ECC verification module three is connected to the data correction module two, the output terminal of the data correction module two outputs a read data signal to the logic "0" terminal of the sixth selector; the output terminal of the sixth selector outputs a bus read data signal [39:0].

4. The advanced expandable interface bus control module as described in claim 3, characterized in that, The write address pipeline, the read address pipeline, and the buffer pipeline each consist of a cache and a selector.

5. The advanced expandable interface bus control module as described in claim 3, characterized in that, The address increment module one and the address increment module two are loopback burst address generation modules; the data correction module one and the data correction module two include a Hamming code error correction generation module, a Hamming code single-bit error correction module, and a single error correction double error detection generation module; the ECC verification module one, the ECC verification module two, and the ECC verification module three include a Hamming code module and a single error correction double error detection module; the WRAP address generation module one and the WRAP address generation module two are address generators for the WRAP burst controller.

6. The advanced expandable interface bus control module as described in claim 5, characterized in that, The Hamming code error correction generation module includes a parity check module and an 18-bit wide data input XOR module; the ID cache module is a BID synchronization module, which implements a FIFO buffer based on SRL16E for the synchronization of BID signals.

7. A random access data storage device, characterized in that, include: The random access memory array consists of a normal data storage array, a redundant storage array, and a built-in self-test controller. The normal data storage array is used to store data in normal mode. The redundant storage array is used to replace faulty partitioning units in the normal data storage array during self-testing in replacement mode. The built-in self-test controller is used to control the self-testing behavior of the memory and has priority control. An advanced scalable interface bus control module as described in any one of claims 1 to 6, wherein one end is connected to the random access memory array and the other end is connected to the advanced scalable interface bus, and the advanced scalable interface bus is connected to two master devices and one slave device.

8. A random access data storage device as described in claim 7, characterized in that, Both the normal storage array and the redundant storage array are composed of multiple array-distributed static storage cells, sharing word lines in the horizontal direction and bit lines in the vertical direction; through the joint operation of row decoding circuits and column decoding circuits, data can be read and written to any storage cell of the array. The memory cell is accessed by raising the word line, and then read or write operations are performed by using bit line pairs.

9. A random access data storage device as described in claim 7, characterized in that, The built-in self-test controller includes: A built-in self-test address generator is used to generate memory addresses in the self-test state, which is implemented by an address counter; A built-in self-test data generator is used to generate data in the self-test state, which is implemented by a state machine; The built-in self-test verification module is used to test the storage units of normal data storage arrays and redundant storage arrays to determine whether the corresponding storage units are abnormal, and to pass the test results to the built-in self-test response module. A built-in self-test response module is used to respond to the self-test results provided by the built-in self-test verification module in order to avoid invalid redundant replacements.

10. A random access data storage device as described in claim 7, characterized in that, It also includes the following data reading process: Initialize the register state and keep it idle; Read data acquisition address; enable via advanced expandable interface bus, control module's main reset input signal for system reset and acquisition address start; output signal to drive random access memory array reset interface, and acquire address at the same system time; Read the secure address of the data; after the second clock cycle following data acquisition, transmit the data address to the address interface of the random access memory array and use it as the secure address; Read data full flag; Read address data from random access memory array, random access address to memory array, add read address and near-empty offset to write address to generate near-empty flag; The write address and the near-full offset are added together and compared with the read address to generate the near-full flag; Compare the read address with the write address, and then generate an empty / full flag based on the status of the almost empty and almost full flags; Read all data; The system obtains valid security data from the random state memory through the data storage register, and performs data synchronization and alignment according to the clock and reset signals, facilitating data retrieval at any time. Read the last address of the data; the address obtained after the clock edge is mapped to the address control port and configuration word line of the random state memory; The last data is read completely; through read control logic and adjustment of delay, read enable is generated sequentially within one cycle to obtain the corresponding stored data from a storage unit; Read the last data on the bus; adjust the read data according to address and timing and send it to the advanced expandable bus, and read it according to the control operation of the master and slave devices; Read the data and wait for new instructions; after completing the read and storage operation, allow new instructions to intervene. If read and write requests occur simultaneously, read takes priority.

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