Failure mechanism analysis and life evaluation method suitable for SiC MOSFETs with different gate structures
By performing junction temperature calibration and power cycling tests on SiC MOSFETs with different gate structures, combined with dynamic and static parameter monitoring and multiphysics simulation, the problem of the influence of gate structure differences in SiC MOSFET failure mechanism analysis was solved, achieving accuracy and reliability in lifetime assessment and supporting the reliability design of traction converters.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SOUTHWEST JIAOTONG UNIV
- Filing Date
- 2026-01-12
- Publication Date
- 2026-04-24
AI Technical Summary
Existing failure mechanism analyses of SiC MOSFETs do not fully consider differences in gate structure, resulting in insufficient accuracy in lifetime prediction and making it difficult to meet the reliability requirements of traction converters.
By selecting SiC MOSFETs with different gate structures, junction temperature calibration experiments and power cycling tests were conducted. Combined with dynamic and static parameter monitoring and multiphysics simulation, the competitive failure mechanism of the devices was analyzed, and the lifetime was evaluated using Weibull distribution fitting.
It improves the accuracy of junction temperature monitoring, clarifies the failure mechanism of devices under different gate structures, achieves accuracy and reliability in lifetime assessment, and supports the reliable operation of traction converters.
Smart Images
Figure CN121920146A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of power device reliability monitoring and lifetime assessment technology, and particularly relates to a failure mechanism analysis and lifetime assessment method applicable to SiC MOSFETs with different gate structures. Background Technology
[0002] Replacing silicon (Si)-based devices with silicon carbide-based metal-oxide-semiconductor field-effect transistors (SiC MOSFEETs) can effectively promote the high efficiency and lightweight design of traction converters, and has become an important development trend in urban rail train traction drive systems. However, traction converters operate under non-steady conditions such as sudden starts and stops and variable loads, causing power devices to be frequently subjected to thermal shocks, leading to fatigue failure and ultimately traction converter failure and train power loss. Therefore, it is crucial to explore the failure mechanism of SiC MOSFETs and accurately assess their lifespan.
[0003] Existing methods for analyzing the failure mechanisms of SiC MOSFET devices can be broadly categorized into characterization modeling, simulation analysis, and experimental testing. Characterization modeling can quantitatively reveal microscopic failure mechanisms, but it suffers from complex models and excessive computational costs when analyzing long-term failure mechanisms. Simulation analysis can avoid destructive testing and save on testing costs, but it tends to overlook factors such as material parameter uncertainties and packaging process randomness, thus its accuracy needs improvement. Among experimental testing methods, the power cycling test (PCT) is a key means of evaluating the reliability of power devices. Existing PCT studies mostly focus on packaging reliability and do not fully consider the impact of differences in the gate structure of SiC MOSFETs on reliability, resulting in low accuracy in device lifetime prediction and difficulty in meeting the reliability requirements of traction converters.
[0004] Meanwhile, in the crucial power cycling experiment of junction temperature monitoring, while the temperature-sensitive electrical parameter (TSEP)-based method offers low intrusion and high flexibility, the impact of process consistency for different gate structures on the accuracy of junction temperature monitoring is still insufficiently studied, further affecting the reliability of failure mechanism analysis. Therefore, there is an urgent need for a failure mechanism analysis and lifetime assessment method for SiC MOSFETs that fully considers differences in gate structure, in order to improve assessment accuracy and ensure the reliable operation of traction converters. Summary of the Invention
[0005] To address the issues of insufficient consideration of gate structure differences and inadequate lifetime prediction accuracy in existing SiC MOSFET failure mechanism studies, this invention provides a failure mechanism analysis and lifetime assessment method applicable to SiC MOSFETs with different gate structures.
[0006] The present invention provides a method for failure mechanism analysis and lifetime assessment of SiC MOSFETs with different gate structures, comprising the following steps:
[0007] Step 1: Select the device under test.
[0008] Two commercially available SiC MOSFETs with similar rated voltage and rated current were selected as the device under test (DUT), specifically a trench gate MOSFET and a planar gate MOSFET.
[0009] Step 2: Junction temperature calibration experiment.
[0010] Select the forward voltage V of the body diode sd Junction temperature is monitored as a temperature-sensitive electrical parameter. One device under test is randomly selected from both planar gate and trench gate devices, and a gate turn-off negative voltage V is systematically set. gs Measure V at different junction temperatures sd value.
[0011] Step 3: Power Cyclic Experiment Platform Setup and Parameter Settings.
[0012] A power cycling test platform was built, which included the device under test (DUT), gate driver board, power supply, host computer, mold temperature controller, and water cooler.
[0013] Experimental conditions were set up as follows: three DUTs were used as a group, and two parallel experiments were conducted with the same type of devices, each using 6 devices, labeled DUT1 to DUT6; the single power cycle period was 6s, including 2s of heating time and 4s of cooling time. The maximum junction temperature and junction temperature fluctuation of the two types of devices were controlled to be consistent. During the heating stage, heating was carried out by DC load current, and during the cooling stage, the optimal turn-off negative voltage determined by the gate driver board was output and combined with water cooling machine for heat dissipation.
[0014] Step 4: Monitoring dynamic and static parameters.
[0015] Online monitoring of junction temperature T j , saturation conduction voltage V ds and thermal resistance R th Used to assess package failure; offline monitoring of threshold voltage V th It is used to assess the failure status of the gate oxide layer or chip.
[0016] Dynamic parameters, including the activation delay time t, are tested using the double-pulse test method. d.on Rise time t rShutdown delay time t d.off descent time t off Activate Energy E on and shut-off energy E off .
[0017] Step 5: Analysis of competition failure mechanism.
[0018] Package failures in power cycling tests include two competing failure modes: bond wire failure and solder layer failure; according to V ds and R th The changing trend of V is used to determine the V of the two devices. ds and R th Has the failure criterion been met: ΔV ds >5%, ΔR th >20%, further determine the dominant failure mode in the package failure, and clarify the dominant failure mechanism under different gate structures.
[0019] Step 6: Life assessment.
[0020] Based on device failure time data obtained from power cycling experiments, the Weibull distribution fitting method was used to quantitatively evaluate the service life differences of two SiC MOSFETs with different gate structures through probability density function and cumulative distribution function.
[0021] The probability density function of the Weibull distribution is:
[0022]
[0023] In the formula, β is the shape parameter, η is the scale parameter, and t is the lifetime time; β>1 indicates that the failure rate increases with time, which is applicable to aging failure; η is the characteristic lifetime, that is, the time when 50% of the device is expected to fail.
[0024] The cumulative distribution function is used to estimate the cumulative probability of a device failing before a certain cycle. The calculation formula is as follows:
[0025]
[0026] Based on the failure cycle data of the two devices in the power cycling experiment, probability density function curves and cumulative distribution function curves were plotted, and the failure types of the devices were observed through the two curves. If the cumulative failure probability is specified, the lifetime difference of the two gate structures of SiC MOSFETs can be further determined.
[0027] Furthermore, in step 1, the planar gate adopts a two-dimensional planar structure, with the source, drain, and gate coplanar, and the MOS channel laterally connecting the source and drain; the trench gate is based on a three-dimensional trench design, with the gate embedded in the vertical trench formed by etching, and the oxide layer covering the sidewalls and bottom to achieve dual-channel conduction.
[0028] Furthermore, in step 2, based on the computer-aided design (TCAD) technology, a cell simulation model of a planar gate and a trench gate SiCMOSFET is constructed to analyze the total current density distribution under different gate turn-off negative voltages. When the gate turn-off negative voltage is insufficient, the measured current mainly flows through the channel rather than the body diode, causing the calibration curve to shift. When the gate negative voltage is sufficient, the measured current flows entirely through the body diode, and the calibration curves highly overlap.
[0029] Junction temperature dynamic monitoring employs a low-current excitation method: a sufficiently selected turn-off negative voltage is applied to the device gate, and a 10mA-level measurement current is applied to the drain to reduce self-heating effects. The forward voltage V of the body diode is acquired in real time. sd The junction temperature T is inverted by combining the pre-established junction temperature-voltage drop calibration curve. j .
[0030] Furthermore, in step 4:
[0031] The failure criterion for the package is: saturation voltage drop V ds The rise is 105% of the initial value or the thermal resistance R from the chip pn junction to the external package. th_JC It rose to 120% of the initial value.
[0032] Threshold voltage V th The measurement employed a gate-drain short-circuit circuit. During measurement, a 6V voltage was applied to the drain, and the current was limited to 4mA through a 1.5kΩ resistor. Two additional power cycling experiments were set up: inf01~inf03 and Cree01~Cree03, with an offline V test performed every 4000 cycles. th Measurement.
[0033] Thermal resistance R th-JC The calculation formula is:
[0034]
[0035] In the formula: T j(t) T c(t) These represent the junction temperature and external package temperature at time t, respectively; P is the device's heat dissipation power; R th-JC(t) The transient junction-shell thermal resistance is calculated; a thermal transient measurement is performed every 6000 power cycles to calculate the thermal impedance response curves under different aging conditions.
[0036] Furthermore, in step 5:
[0037] The electro-thermal-structural multiphysics simulation of a TO-247 packaged SiC MSOFET device was performed using COMSOL finite element simulation software. By applying a constant current load to simulate the heating stage, the current density distribution was obtained, and the main heat sources during the conduction stage of the device were analyzed. Furthermore, the location of the highest temperature was determined based on the temperature distribution. Finally, the location of the maximum thermomechanical stress was obtained by combining thermal-structural coupling analysis. By combining the finite element simulation results with the changes in electrical parameters presented by experiments, the mechanism analysis of multiple failure modes of the package was realized.
[0038] Further analysis of the competition mechanism between chip degradation and package failure: The planar gate device exhibits a uniform electric field distribution, suppressing gate oxide degradation, V th Only slow negative drift, lifetime is mainly dominated by package failure; high electric field concentration at trench corners of trench gate devices, gate oxide degradation is triggered first in the later stage of power cycling, forming uneven current distribution and hot spots, aggravating thermal fatigue of bonding wires, chip degradation actively accelerates package failure, forming a synergistic degradation.
[0039] The beneficial technical effects of this invention compared to the prior art are as follows:
[0040] 1. This invention fully considers the process differences of SiC MOSFETs with different gate structures, and determines the optimal turn-off negative voltage through a systematic junction temperature calibration experiment, which improves the accuracy of junction temperature monitoring and lays the foundation for subsequent failure mechanism analysis and lifetime assessment.
[0041] 2. This invention simultaneously monitors dynamic and static parameters and, combined with multiphysics simulation, reveals the competitive failure mechanism of chips and packages under different gate structures. It clarifies the difference between the failure of planar gate devices dominated by package failure and the chip-package co-degradation of trench gate devices, filling the research gap in the failure mechanism of gate structure influence.
[0042] 3. This invention uses Weibull distribution fitting to achieve quantitative evaluation of the service life of SiC MOSFETs with different gate structures, providing direct data support for the selection and reliability design of SiC MOSFET devices in traction converters.
[0043] 4. The experimental method of this invention can be adapted to the actual operating conditions of traction converters. The measurement process is low-invasive, the monitoring parameters are easy to obtain, and the robustness is strong. It can be widely applied to the reliability assessment of various converter systems containing SiC MOSFETs. Attached Figure Description
[0044] Figure 1 This is a flowchart of the failure mechanism analysis and lifetime assessment method for SiC MOSFETs with different gate structures according to the present invention.
[0045] Figure 2This is the cell structure of a planar gate MOSFET device.
[0046] Figure 3 This is the cell structure of a trench gate MOSFET device.
[0047] Figure 4 This is a power cycling experimental platform.
[0048] Figure 5 This is a control strategy for power cycling experiments.
[0049] Figure 6 This is a threshold voltage measurement circuit.
[0050] Figure 7 This is a schematic diagram of a dual-pulse test circuit.
[0051] Figure 8 This is a schematic diagram of the gate drive pulse train.
[0052] Figure 9 This is the geometric model of a SiC MOSFET.
[0053] Figure 10 This is the positive feedback competition mechanism for planar gate MOSFET devices.
[0054] Figure 11 This is the positive feedback competition mechanism for trench gate MOSFET devices. Detailed Implementation
[0055] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.
[0056] This invention provides a method for failure mechanism analysis and lifetime assessment of SiC MOSFETs with different gate structures. Through power cycling experiments combined with temperature-sensitive parameter calibration, dynamic and static parameter monitoring, and statistical distribution fitting, it achieves failure mechanism analysis and quantitative lifetime assessment of SiC MOSFETs with different gate structures. The process is as follows: Figure 1 As shown, the specific steps include:
[0057] Step 1: Select the device under test.
[0058] Two commercial SiC MOSFETs with similar rated voltage and rated current were selected as devices under test (DUTs), specifically a trench gate MOSFET (IMW120R140M1H) and a planar gate MOSFET (C2M0160120D).
[0059] Planar gate MOSFET device cell structure as follows Figure 2As shown, a two-dimensional planar structure is adopted, with the source, drain, and gate coplanar, and the MOS channel laterally connecting the source and drain. The cell structure of the trench gate MOSFET device is shown below. Figure 3 As shown, based on a three-dimensional trench design, the gate is embedded in a vertical trench formed by etching, and an oxide layer covers the sidewalls and bottom to achieve dual-channel conduction.
[0060] Step 2: Junction temperature calibration experiment.
[0061] Select the forward voltage V of the body diode sd Junction temperature is monitored as a temperature-sensitive electrical parameter (TSEP). One device under test is randomly selected from both planar gate and trench gate devices, and a gate turn-off negative voltage V is systematically set. gs Measure V at different junction temperatures sd value.
[0062] To investigate the influence mechanism of gate turn-off negative voltage on junction temperature calibration curves, a cell simulation model of planar gate and trench gate SiC MOSFETs was constructed based on technology computer-aided design (TCAD). The total current density distribution under different gate turn-off negative voltages was analyzed. When the gate turn-off negative voltage is insufficient, the measurement current mainly flows through the channel rather than the body diode, resulting in a deviation of the calibration curve. When the gate negative voltage is sufficient, the measurement current flows entirely through the body diode, and the calibration curves highly overlap.
[0063] Junction temperature dynamic monitoring employs a low-current excitation method: a sufficiently selected turn-off negative voltage is applied to the device gate, and a 10mA-level measurement current is applied to the drain to reduce self-heating effects. The forward voltage V of the body diode is acquired in real time. sd The junction temperature T is inverted by combining the pre-established junction temperature-voltage drop calibration curve. j .
[0064] Step 3: Power Cyclic Experiment Platform Setup and Parameter Settings.
[0065] Building a power cycling experimental platform, such as Figure 4 As shown, the platform includes the device under test (DUT), gate driver board, power supply, host computer, mold temperature controller, and water cooler.
[0066] Experimental conditions: Three DUTs are used as a group, and two parallel experiments are conducted with the same type of devices, each using 6 devices, labeled DUT1~DUT6.
[0067] The timing diagram of the power cycle control strategy is as follows: Figure 5As shown, the single power cycle period is 6s, including 2s heating time and 4s cooling time. The maximum junction temperature and junction temperature fluctuation of the two devices are controlled to be consistent. During the heating stage, heating is achieved by DC load current, and during the cooling stage, the optimal turn-off negative voltage is output by the gate driver board and combined with water cooling machine for heat dissipation.
[0068] The detailed experimental conditions are shown in Table 1. The maximum junction temperature of both devices is 130℃, the junction temperature fluctuation is 80℃, and the load current is 15A.
[0069] Table 1 Power Cycling Experiment Conditions
[0070]
[0071] Step 4: Monitoring dynamic and static parameters.
[0072] Online monitoring of junction temperature T j , saturation conduction voltage V ds and thermal resistance R th Used to assess package failure; offline monitoring of threshold voltage V th It is used to assess the failure status of the gate oxide layer or chip.
[0073] The failure criterion for the package is: saturation voltage drop V ds The rise is 105% of the initial value or the thermal resistance R from the chip pn junction to the external package. th_JC It rose to 120% of the initial value.
[0074] Threshold voltage V th The measurement uses a grid-drain short-circuit measurement circuit (such as...) Figure 6 As shown), a 6V voltage was applied to the drain during measurement, and the current was limited to 4mA through a 1.5kΩ resistor; two additional power cycling experiments were set up: inf01~inf03 group and Cree01~Cree03 group, with an offline V test performed every 4000 cycles. th Measurement.
[0075] Thermal resistance R th-JC The calculation formula is:
[0076]
[0077] In the formula: T j(t) T c(t) These represent the junction temperature and external package temperature at time t, respectively; P is the device's heat dissipation power; R th-JC(t) The transient junction-shell thermal resistance is calculated; a thermal transient measurement is performed every 6000 power cycles to calculate the thermal impedance response curves under different aging conditions.
[0078] The mechanism of dynamic parameter degradation was investigated using the double-pulse test method. The schematic diagram of the double-pulse test circuit is shown below. Figure 7 As shown, it mainly includes the load inductor L and the high-voltage DC source V. Bus Bus capacitor C bus The transistor under test (DUT) and the diode under test (D) H The test parameters for the drive circuit are shown in Table 2.
[0079] Table 2. Double Pulse Test Parameters
[0080]
[0081] During the test, a dual-pulse drive signal (such as...) is sent. Figure 8 As shown), energy is stored in the load inductor during the first pulse's on-time, and the off-time and off-time energy are measured at the off-time; an "L-D" pattern is formed during the interval between two pulses. H "Circuit; the activation time and activation energy are measured at the moment the second pulse is activated."
[0082] The calculated dynamic parameters include the activation delay time t. d.on Rise time t r Shutdown delay time t d.off descent time t off Activate Energy E on and shut-off energy E off .
[0083] Step 5: Analysis of competition failure mechanism.
[0084] Package failures in power cycling tests include two competing failure modes: bond wire failure and solder layer failure; according to V ds and R th The changing trend of V is used to determine the V of the two devices. ds and R th Has the failure criterion been met: ΔV ds >5%, ΔR th >20%, further determine the dominant failure mode in the package failure, and clarify the dominant failure mechanism under different gate structures.
[0085] Furthermore, the electro-thermal-structural multiphysics simulation of the TO-247 packaged SiC MSOFET device was performed using COMSOL finite element simulation software. The geometric model is as follows: Figure 9 As shown, by applying a constant current load to simulate the heating stage, the current density distribution is obtained, and the main heat sources of the device during the conduction stage are analyzed; further, the location of the highest temperature is obtained based on the temperature distribution; finally, the location of the maximum thermomechanical stress is obtained by combining thermal-structural coupling analysis; by combining the finite element simulation results with the changes in electrical parameters presented by the experiment, the mechanism analysis of multiple failure modes of the package is realized.
[0086] Further analysis of the competition mechanism between chip degradation and package failure: The planar gate device exhibits a uniform electric field distribution, suppressing gate oxide degradation, V th With only slow negative drift, lifetime is mainly dominated by package failure; in trench gate devices, high electric fields concentrate at the trench corners, triggering gate oxide degradation first in the later stages of power cycling, forming uneven current distribution and hot spots, exacerbating bond wire thermal fatigue, and actively accelerating chip degradation and package failure, forming a synergistic degradation. The positive feedback competition mechanisms of planar gate MOSFET devices and trench gate MOSFET devices are as follows: Figure 10 , Figure 11 As shown.
[0087] Step 6: Life assessment.
[0088] Based on device failure time data obtained from power cycling experiments, the Weibull distribution fitting method was used to quantitatively evaluate the service life differences of two SiC MOSFETs with different gate structures through probability density function and cumulative distribution function.
[0089] The probability density function (PDF) of the Weibull distribution is:
[0090]
[0091] In the formula, β is the shape parameter, η is the scale parameter, and t is the lifetime time; β>1 indicates that the failure rate increases with time, which is applicable to aging failure; η is the characteristic lifetime, that is, the time when 50% of the device is expected to fail.
[0092] The cumulative distribution function (CDF) is used to estimate the cumulative probability of a device failing before a certain cycle. The calculation formula is as follows:
[0093]
[0094] Based on the failure cycle data of the two devices in the power cycling experiment, probability density function curves and cumulative distribution function curves were plotted. The failure type of the device (e.g., early failure, stable failure, or aging failure) was observed through the two curves. If the cumulative failure probability is specified, the lifetime difference of the two gate structures of SiC MOSFETs can be further determined.
Claims
1. A method for failure mechanism analysis and lifetime assessment of SiC MOSFETs with different gate structures, characterized in that, Includes the following steps: Step 1: Select the device under test; Two commercial SiC MOSFETs with similar rated voltage and rated current were selected as the device under test (DUT), specifically a trench gate MOSFET and a planar gate MOSFET. Step 2: Junction temperature calibration experiment; Select the forward voltage V of the body diode sd Junction temperature is monitored as a temperature-sensitive electrical parameter. One device under test is randomly selected from both planar gate and trench gate devices, and a gate turn-off negative voltage V is systematically set. gs Measure V at different junction temperatures sd value; Step 3: Power Cyclic Experiment Platform Setup and Parameter Setting; A power cycling test platform was built, which included the device under test (DUT), gate driver board, power supply, host computer, mold temperature controller, and water cooler. Experimental conditions were set as follows: three DUTs were used as a group, and two parallel experiments were conducted with the same type of devices, each group using six devices, labeled DUT1 to DUT6; the single power cycle period was 6s, including 2s of heating time and 4s of cooling time. The maximum junction temperature and junction temperature fluctuation of the two types of devices were controlled to be consistent. During the heating stage, heating was carried out by DC load current, and during the cooling stage, the optimal turn-off negative voltage was output by the gate driver board and combined with water cooling. Step 4: Monitoring dynamic and static parameters; Online monitoring of junction temperature T j , saturation conduction voltage V ds and thermal resistance R th Used to assess package failure; offline monitoring of threshold voltage V th It is used to assess the failure status of the gate oxide layer or chip. Dynamic parameters, including the activation delay time t, are tested using the double-pulse test method. d.on Rise time t r Shutdown delay time t d.off descent time t off Activate Energy E on and shut-off energy E off ; Step 5: Analysis of the competition failure mechanism; Package failures in power cycling tests include two competing failure modes: bond wire failure and solder layer failure; according to V ds and R th The changing trend of V is used to determine the V of the two devices. ds and R th Has the failure criterion been met: ΔV ds >5%, ΔR th >20%, further determine the dominant failure mode in the package failure, and clarify the dominant failure mechanism under different gate structures; Step 6: Lifetime assessment; Based on the device failure time data obtained from power cycling experiments, the Weibull distribution fitting method was used to quantitatively evaluate the difference in service life between two SiC MOSFETs with different gate structures through probability density function and cumulative distribution function. The probability density function of the Weibull distribution is: ； In the formula, β is the shape parameter, η is the scale parameter, and t is the lifetime time; β>1 indicates that the failure rate increases with time, which is applicable to aging failure. η is the characteristic lifetime, which is the time when 50% of the device is expected to fail; The cumulative distribution function is used to estimate the cumulative probability of a device failing before a certain cycle. The calculation formula is as follows: ； Based on the failure cycle data of the two devices in the power cycling experiment, probability density function curves and cumulative distribution function curves were plotted, and the failure types of the devices were observed through the two curves. If the cumulative failure probability is specified, the lifetime difference of the two gate structures of SiC MOSFETs can be further determined.
2. The method for failure mechanism analysis and lifetime assessment of SiC MOSFETs with different gate structures according to claim 1, characterized in that, In step 1, the planar gate adopts a two-dimensional planar structure, with the source, drain, and gate coplanar, and the MOS channel is laterally connected to the source and drain; the trench gate is based on a three-dimensional trench design, with the gate embedded in the vertical trench formed by etching, and the oxide layer covering the sidewalls and bottom to achieve dual-channel conduction.
3. The method for failure mechanism analysis and lifetime assessment of SiC MOSFETs with different gate structures according to claim 1, characterized in that, In step 2, a cell simulation model of a planar gate and a trench gate SiCMOSFET is constructed based on the computer-aided design (TCAD) system. The total current density distribution under different gate turn-off negative voltages is analyzed. When the gate turn-off negative voltage is insufficient, the measured current mainly flows through the channel rather than the body diode, causing the calibration curve to shift. When the gate negative voltage is sufficient, the measured current flows completely through the body diode, and the calibration curves highly overlap. Junction temperature dynamic monitoring employs a low-current excitation method: a sufficiently low turn-off negative voltage is applied to the device gate, and a 10mA-level measurement current is applied to the drain to reduce self-heating effects. The forward voltage V of the body diode is acquired in real time. sd The junction temperature T is inverted by combining the pre-established junction temperature-voltage drop calibration curve. j .
4. The method for failure mechanism analysis and lifetime assessment of SiC MOSFETs with different gate structures according to claim 1, characterized in that, In step 4: The failure criterion for the package is: saturation voltage drop V ds The rise is 105% of the initial value or the thermal resistance R from the chip pn junction to the external package. th_JC It rose to 120% of the initial value; Threshold voltage V th The measurement employed a gate-drain short-circuit circuit. During measurement, a 6V voltage was applied to the drain, and the current was limited to 4mA through a 1.5kΩ resistor. Two additional power cycling experiments were set up: inf01~inf03 and Cree01~Cree03, with an offline V test performed every 4000 cycles. th Measurement; Thermal resistance R th-JC The calculation formula is: ； In the formula: T j(t) T c(t) These represent the junction temperature and external package temperature at time t, respectively; P is the device's heat dissipation power; R th-JC(t) The transient junction-shell thermal resistance is calculated; a thermal transient measurement is performed every 6000 power cycles to calculate the thermal impedance response curves under different aging conditions.
5. The method for failure mechanism analysis and lifetime assessment of SiC MOSFETs with different gate structures according to claim 1, characterized in that, In step 5: The electro-thermal-structural multiphysics simulation of a TO-247 packaged SiC MSOFET device was performed using COMSOL finite element simulation software. A constant current load was applied to simulate the heating stage, obtaining the current density distribution and analyzing the main heat sources during the conduction phase. Furthermore, the location of the highest temperature was determined based on the temperature distribution. Finally, the location of the maximum thermomechanical stress was determined by combining thermal-structural coupling analysis. The finite element simulation results were combined with experimental findings on electrical parameter changes to achieve mechanism analysis of multiple failure modes in the package. Further analysis of the competition mechanism between chip degradation and package failure: The planar gate device exhibits a uniform electric field distribution, suppressing gate oxide degradation, V th Only slow negative drift, lifetime is mainly dominated by package failure; high electric field concentration at trench corners of trench gate devices, gate oxide degradation is triggered first in the later stage of power cycling, forming uneven current distribution and hot spots, aggravating thermal fatigue of bonding wires, chip degradation actively accelerates package failure, forming a synergistic degradation.