Adaptive power supply wiring method and system of processor and related equipment

Abstract

The invention is suitable for the technical field of processors, and particularly relates to a self-adaptive power supply wiring method and system of a processor and related equipment. According to the invention, multiple power supply network schemes are established according to the unit density of different areas of the processor chip; selecting one of a plurality of power supply network schemes as a reference scheme, and preliminarily placing units of the processor chip based on the reference scheme; performing regional division on the initial power supply network based on the size of the reference scheme; counting the number of standard units or the equivalent unit area in each physical area unit and calculating the corresponding unit density to obtain the area unit density corresponding to the plurality of physical area units; and adjusting the layout and wiring of the physical region units into a corresponding power supply network scheme based on the density of the region units, so as to realize the self-adaptive power supply wiring of the processor chip. Compared with the prior art, winding resources of areas with different densities can be saved, and the occupation of a power supply network on wiring tracks and metal resources is remarkably reduced.

Description

Technical Field

[0001] This invention relates to the field of processor technology, and in particular to an adaptive power routing method, system and related equipment for processors. Background Technology

[0002] This invention belongs to the field of back-end physical design and design automation (EDA) technology of integrated circuits. Specifically, it involves power grid (PG) routing technology in the custom design process of RISC-V processors. Its core application is in the back-end implementation stage of complex designs such as large-scale digital chips, SoCs and high-performance processors.

[0003] In the physical implementation of integrated circuits, the power network is a core infrastructure that ensures the normal operation of the chip. Its core function is to provide stable and uniform power supply to standard cells, ensuring power integrity. In existing technologies, the construction of power networks generally adopts a unified power network scheme: that is, within the scope of the chip or functional module, fixed parameters such as metal layer selection, line width, line spacing, and grid spacing are predefined to generate a globally consistent power network structure. This structure is fixed in the early stages of placement and routing, serving as a constraint for subsequent cell placement and signal routing.

[0004] The existing solutions are advantageous due to their simple process and ease of automation, and are therefore widely used in early process nodes (such as 90nm and above) or smaller-scale chip designs. However, with the increase in chip size, the complexity of functional modules, and the prevalence of advanced process nodes (such as 32nm and below), the cell density in different regions of the design layout exhibits a significant non-uniform distribution. The existing unified solutions reveal the following key shortcomings:

[0005] 1. Mismatch between power supply capacity and actual demand: In low cell density areas, the uniform high-density PG pattern provides power redundancy far exceeding actual demand, resulting in a waste of power network resources; while in critical areas with high cell density and high current demand (such as computing cores and memory controllers), the uniform structure makes it difficult to provide targeted enhanced power supply, and there is a risk of insufficient local power supply capacity.

[0006] 2. Poor power supply balance: It cannot adapt to the transient current differences in different areas. In designs with large fluctuations in cell density, problems such as excessive IR voltage drop in local areas and unstable power supply are likely to occur, affecting the reliability of chip operation.

[0007] 3. Over-occupancy of signal cabling resources: In low-density areas, the dense power network occupies a large amount of metal resources and signal cabling tracks, resulting in a decrease in the routing ability of long lines and cross-regional signals, which limits the optimization space of signal cabling.

[0008] 4. Timing convergence efficiency is affected: An unreasonable power network distribution will increase the parasitic coupling capacitance between signal lines and power lines, interfere with the signal transmission of the critical path, prolong the timing optimization cycle, and even lead to timing convergence difficulties.

[0009] Therefore, there is an urgent need for a new adaptive power routing method, system, and related equipment for processors to solve the above-mentioned technical problems. Summary of the Invention

[0010] This invention provides an adaptive power routing method, system, and related equipment for processors, aiming to provide a technical solution that can dynamically adapt the power network density according to the differences in cell density, optimize the utilization of routing resources, and improve timing convergence efficiency while ensuring power supply integrity.

[0011] In a first aspect, the present invention provides an adaptive power routing method for a processor, the adaptive power routing method comprising the following steps: S1. Establish multiple power network schemes based on the cell density of different regions of the processor chip; S2. Select one of the various power network schemes as a reference scheme, and perform preliminary placement of the processor chip units based on the reference scheme to obtain an initial power network; S3. Based on the dimensions of the reference scheme, the initial power network is divided into regions to obtain multiple physical region units; the number of standard units or equivalent unit areas in each physical region unit are counted and the corresponding unit density is calculated to obtain the region unit density corresponding to the multiple physical region units. S4. Based on the density of the physical area units, adjust the layout and wiring of the physical area units to the corresponding power network scheme to realize the adaptive power wiring of the processor chip.

[0012] Preferably, the power network scheme includes a first power network scheme, a second power network scheme, and a third power network scheme. The first power network scheme is defined as A when it is suitable for the cell density of the processor chip, the second power network scheme is defined as B when it is suitable for the cell density of the processor chip, and the third power network scheme is defined as C when it is suitable for the cell density of the processor chip, satisfying the condition: A < B < C.

[0013] In step S2, the second power network scheme is selected as the baseline scheme.

[0014] Preferably, the power network scheme includes metal layer selection parameters, line width parameters, line spacing parameters, and grid spacing parameters.

[0015] Preferably, the metal layer selection parameters, line width parameters, line spacing parameters, and grid spacing parameters differ between different power network schemes.

[0016] In a second aspect, the present invention also provides an adaptive power routing system for a processor, the adaptive power routing system comprising: The scheme establishment module is used to establish multiple power network schemes based on the cell density of different regions of the processor chip. An initial power network generation module is used to select one of the various power network schemes as a reference scheme, and to initially place the units of the processor chip based on the reference scheme to obtain an initial power network. The region division module is used to divide the initial power network into regions based on the size of the reference scheme to obtain multiple physical region units; count the number of standard units or equivalent unit area in each physical region unit and calculate the corresponding unit density to obtain the region unit density corresponding to the multiple physical region units. The adjustment module is used to adjust the layout and wiring of the physical region units according to the region unit density to the corresponding power network scheme, thereby realizing the adaptive power wiring of the processor chip.

[0017] Preferably, the power network scheme includes a first power network scheme, a second power network scheme, and a third power network scheme. The cell density to which the first power network scheme is applicable is defined as A, the cell density to which the second power network scheme is applicable is defined as B, and the cell density to which the third power network scheme is applicable is defined as C, satisfying the condition: A < B < C.

[0018] In the initial power network generation module, the second power network scheme is selected as the baseline scheme.

[0019] Preferably, the power network scheme includes metal layer selection parameters, line width parameters, line spacing parameters, and grid spacing parameters.

[0020] Preferably, the metal layer selection parameters, line width parameters, line spacing parameters, and grid spacing parameters differ between different power network schemes.

[0021] Thirdly, the present invention also provides a computer device, comprising: a memory, a processor, and an adaptive power routing program for the processor stored in the memory and executable on the processor, wherein when the processor executes the adaptive power routing program for the processor, it implements the steps in the adaptive power routing method for the processor as described in any of the above embodiments.

[0022] Fourthly, the present invention also provides a computer-readable storage medium storing an adaptive power routing program for a processor, wherein when executed by the processor, the adaptive power routing program for the processor implements the steps in the adaptive power routing method for the processor as described in any of the above embodiments.

[0023] Compared with existing technologies, this invention establishes multiple power network schemes based on the cell density of different regions of the processor chip; selects one of the multiple power network schemes as a baseline scheme, and initially places the cells of the processor chip based on the baseline scheme to obtain an initial power network; divides the initial power network into regions based on the size of the baseline scheme to obtain multiple physical region cells; counts the number of standard cells or equivalent cell area in each physical region cell and calculates the corresponding cell density to obtain the region cell density corresponding to multiple physical region cells; adjusts the layout and routing of the physical region cells according to the region cell density to the corresponding power network scheme, realizing adaptive power routing of the processor chip. In this way, this invention can save routing resources in regions of different densities, significantly reduce the occupation of routing tracks and metal resources by the power network, and improve the bypassability of long traces and cross-region signals. The reasonable reduction in density reduces the coupling area between signal lines and power lines, reduces parasitic capacitance at the physical level, has a positive effect on critical path timing optimization, and reduces the risk of over-design and local power insufficiency. By releasing routing resources and improving parasitic characteristics, more favorable physical conditions are created for subsequent signal routing and timing optimization, thereby improving the overall back-end timing convergence efficiency. Attached Figure Description

[0024] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings: Figure 1 This is a flowchart of the adaptive power routing method for a processor provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the adaptive power routing system for a processor provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0026] Example 1 Please refer to Figure 1 This invention provides an adaptive power routing method for a processor, the adaptive power routing method comprising the following steps: S1. Establish multiple power network schemes based on the cell density of different regions of the processor chip; In this embodiment of the invention, based on design requirements and process characteristics, the invention defines a power network scheme (PGPattern) with clear hierarchical structure and quantifiable parameters, forming a standardized configuration library.

[0027] In this embodiment of the invention, the power network scheme includes a first power network scheme, a second power network scheme, and a third power network scheme. The first power network scheme is suitable for a cell density of A, the second power network scheme is suitable for a cell density of B, and the third power network scheme is suitable for a cell density of C, satisfying the condition: A < B < C. Specifically, the first power network scheme is suitable for regions with low cell density (e.g., less than 40%) and low power consumption requirements. The second power network scheme is suitable for regions with medium cell density (e.g., greater than or equal to 40% and less than 70%) and medium power consumption requirements. The third power network scheme is suitable for critical regions with high cell density (e.g., greater than or equal to 70%) and high current requirements. It should be noted that the power network scheme is not limited to the above three types; other types of power network schemes are also feasible and can be configured according to actual conditions.

[0028] In this embodiment of the invention, the power network scheme includes metal layer selection parameters, line width parameters, line spacing parameters, and grid spacing parameters. There are clear differences in the metal layer selection parameters, line width parameters, line spacing parameters, and grid spacing parameters between different power network schemes.

[0029] For example, the metal layer selection parameters for the first power network scheme are: only the upper metal layer (M5 / M6), line width of 0.18μm, line spacing of 0.20μm, grid spacing of 200μm, and current carrying capacity ≥0.8mA / μm; The metal layer selection parameters for the second power network scheme are: middle and upper metal layers (M3 / M4+M5 / M6), line width of 0.24μm, line spacing of 0.28μm, grid spacing of 100μm, and current carrying capacity ≥1.2mA / μm; The metal layer selection parameters for the third power network scheme are: lower, middle and upper metal layers (M1 / M2+M3 / M4+M5 / M6), line width of 0.32μm, line spacing of 0.36μm, grid spacing of 50μm, and current carrying capacity ≥1.8mA / μm; S2. Select one of the various power network schemes as a reference scheme, and perform preliminary placement of the processor chip units based on the reference scheme to obtain an initial power network.

[0030] In this embodiment of the invention, the second power network scheme is selected as the baseline scheme in step S2, so that it can be adapted to most common areas and can balance the efficiency of initial layout and the authenticity of data.

[0031] In this embodiment of the invention, the parameter settings in the second power network scheme are called by the EDA tool. These settings include the main lines, branch lines and grid nodes such as the chip's positive power line (VDD) and ground power line (VSS), which meet the initial requirements for power supply integrity. Under the constraints of the baseline scheme, the placement of automated units is performed to generate the initial power network.

[0032] S3. Based on the dimensions of the reference scheme, the initial power network is divided into regions to obtain multiple physical region units; the number of standard units or the area of ​​equivalent units in each physical region unit are counted and the corresponding unit density is calculated to obtain the region unit density corresponding to the multiple physical region units.

[0033] In this embodiment of the invention, the power network scheme adapted to each physical region unit is determined through gridding and density calculation. The region unit density is calculated as: the area occupied by all cells (such as INV / BUF / AND / XOR, etc.) in the region of the initial power network plus / minus the total area of ​​the initial power network.

[0034] In this embodiment of the invention, based on the grid structure of the benchmark scheme, an adaptive grid subdivision strategy is adopted. Regions with a cell density >70% are automatically subdivided into 50μm×50μm grids, and regions with a cell density <40% are merged into 200μm×200μm grids to ensure the accuracy of density analysis. The grid coordinates of the benchmark scheme are called through EDA tool scripts to automatically generate a region partitioning layout. Each region is assigned a corresponding unique ID (such as A001, B023), and manual fine-tuning of boundaries is supported (such as avoiding chip chamfers and I / O pin areas). At the same time, transient current peak data of each region is collected (obtained through power consumption simulation tools). If the current peak of a medium-density region is ≥1.2mA / μm, it is upgraded to the high-density region adaptation standard.

[0035] S4. Based on the density of the physical area units, adjust the layout and wiring of the physical area units to the corresponding power network scheme to realize the adaptive power wiring of the processor chip.

[0036] In this embodiment of the invention, the power network scheme for each region is adjusted differently. For example, for regions with a cell density significantly lower than a threshold (e.g., 40%), the power network scheme is changed from the second power network scheme to the first power network scheme to reduce power network occupancy; for regions with a higher cell density (e.g., greater than 70%), the third power network scheme is maintained or upgraded to meet higher power supply requirements. The adjusted power network scheme only takes effect in the corresponding region, thereby achieving a non-uniform, adaptive distribution of the power network globally. By using the first power network scheme in low cell density regions, this invention effectively reduces the occupancy of power lines on signal routing tracks, improving the routing capability of long traces and cross-regional signals. Simultaneously, by optimizing the power line distribution, the parasitic coupling capacitance between signal lines and the power network is reduced, thereby improving critical path timing.

[0037] Compared with existing technologies, this invention establishes multiple power network schemes based on different cell densities of processor chips. One of these schemes is selected as a baseline, and the processor chip cells are initially placed based on this baseline to obtain an initial power network. The initial power network is then divided into regions based on the dimensions of the baseline, resulting in multiple physical region cells. The number of standard cells or equivalent cell area in each physical region cell is counted, and the corresponding cell density is calculated to obtain the region cell density corresponding to the multiple physical region cells. Based on the region cell density, the layout and routing of the physical region cells are adjusted to the corresponding power network scheme, achieving adaptive power routing for the processor chip. This invention saves routing resources in regions with different densities, significantly reduces the power network's occupation of routing tracks and metal resources, and improves the bypassability of long traces and cross-region signals. The reasonable reduction in density reduces the coupling area between signal lines and power lines, physically reducing parasitic capacitance, which has a positive effect on critical path timing optimization, while also reducing the risk of over-design and local power insufficiency. By releasing routing resources and improving parasitic characteristics, more favorable physical conditions are created for subsequent signal routing and timing optimization, improving the overall back-end timing convergence efficiency.

[0038] Example 2 This invention also provides an adaptive power routing system for a processor, please refer to... Figure 2 , Figure 2 This is a schematic diagram of the adaptive power routing system 200 for a processor provided in an embodiment of the present invention, which includes: 201. Scheme establishment module, used to establish multiple power network schemes based on the cell density of different regions of the processor chip; 202. An initial power network generation module is used to select one of the various power network schemes as a reference scheme, and to initially place the units of the processor chip based on the reference scheme to obtain an initial power network. 203. Region division module, used to divide the initial power network into regions based on the size of the reference scheme to obtain multiple physical region units; count the number of standard units or equivalent unit area in each physical region unit and calculate the corresponding unit density to obtain the region unit density corresponding to the multiple physical region units; 204. An adjustment module, used to adjust the layout and wiring of the physical region units to the corresponding power network scheme based on the region unit density, so as to realize the adaptive power wiring of the processor chip.

[0039] The adaptive power routing system 200 of the processor can implement the steps in the adaptive power routing method of the processor as described in the above embodiments, and can achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.

[0040] Example 3 This invention also provides a computer device, please refer to... Figure 3 , Figure 3 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. The computer device 300 includes: a memory 302, a processor 301, and an adaptive power routing program for the processor stored in the memory 302 and executable on the processor 301.

[0041] The processor 301 calls the processor's adaptive power routing program stored in the memory 302 to execute the steps in the processor's adaptive power routing method provided in this embodiment of the invention. Please refer to... Figure 1 Specifically, it includes the following steps: S1. Establish multiple power network schemes based on the cell density of different regions of the processor chip; In this embodiment of the invention, based on design requirements and process characteristics, the invention defines a power network scheme (PGPattern) with clear hierarchical structure and quantifiable parameters, forming a standardized configuration library.

[0042] In this embodiment of the invention, the power network scheme includes a first power network scheme, a second power network scheme, and a third power network scheme. The first power network scheme is suitable for a cell density of A, the second power network scheme is suitable for a cell density of B, and the third power network scheme is suitable for a cell density of C, satisfying the condition: A < B < C. Specifically, the first power network scheme is suitable for regions with low cell density (e.g., less than 40%) and low power consumption requirements. The second power network scheme is suitable for regions with medium cell density (e.g., greater than or equal to 40% and less than 70%) and medium power consumption requirements. The third power network scheme is suitable for critical regions with high cell density (e.g., greater than or equal to 70%) and high current requirements. It should be noted that the power network scheme is not limited to the above three types; other types of power network schemes are also feasible and can be configured according to actual conditions.

[0043] In this embodiment of the invention, the power network scheme includes metal layer selection parameters, line width parameters, line spacing parameters, and grid spacing parameters. There are clear differences in the metal layer selection parameters, line width parameters, line spacing parameters, and grid spacing parameters between different power network schemes.

[0044] For example, the metal layer selection parameters for the first power network scheme are: only the upper metal layer (M5 / M6), line width of 0.18μm, line spacing of 0.20μm, grid spacing of 200μm, and current carrying capacity ≥0.8mA / μm; The metal layer selection parameters for the second power network scheme are: middle and upper metal layers (M3 / M4+M5 / M6), line width of 0.24μm, line spacing of 0.28μm, grid spacing of 100μm, and current carrying capacity ≥1.2mA / μm; The metal layer selection parameters for the third power network scheme are: lower, middle and upper metal layers (M1 / M2+M3 / M4+M5 / M6), line width of 0.32μm, line spacing of 0.36μm, grid spacing of 50μm, and current carrying capacity ≥1.8mA / μm; S2. Select one of the various power network schemes as a reference scheme, and perform preliminary placement of the processor chip units based on the reference scheme to obtain an initial power network.

[0045] In this embodiment of the invention, the second power network scheme is selected as the baseline scheme in step S2, so that it can be adapted to most common areas and can balance the efficiency of initial layout and the authenticity of data.

[0046] In this embodiment of the invention, the parameter settings in the second power network scheme are called by the EDA tool. These settings include the main lines, branch lines and grid nodes such as the chip's positive power line (VDD) and ground power line (VSS), which meet the initial requirements for power supply integrity. Under the constraints of the baseline scheme, the placement of automated units is performed to generate the initial power network.

[0047] S3. Based on the dimensions of the reference scheme, the initial power network is divided into regions to obtain multiple physical region units; the number of standard units or the area of ​​equivalent units in each physical region unit are counted and the corresponding unit density is calculated to obtain the region unit density corresponding to the multiple physical region units.

[0048] In this embodiment of the invention, the power network scheme adapted to each physical region unit is determined by gridding and density calculation.

[0049] In this embodiment of the invention, based on the grid structure of the benchmark scheme, an adaptive grid subdivision strategy is adopted. Regions with a cell density >70% are automatically subdivided into 50μm×50μm grids, and regions with a cell density <40% are merged into 200μm×200μm grids to ensure the accuracy of density analysis. The grid coordinates of the benchmark scheme are called through EDA tool scripts to automatically generate a region partitioning layout. Each region is assigned a corresponding unique ID (such as A001, B023), and manual fine-tuning of boundaries is supported (such as avoiding chip chamfers and I / O pin areas). At the same time, transient current peak data of each region is collected (obtained through power consumption simulation tools). If the current peak of a medium-density region is ≥1.2mA / μm, it is upgraded to the high-density region adaptation standard.

[0050] S4. Based on the density of the physical area units, adjust the layout and wiring of the physical area units to the corresponding power network scheme to realize the adaptive power wiring of the processor chip.

[0051] In this embodiment of the invention, the power network scheme for each region is adjusted differently. For example, for regions with a cell density significantly lower than a threshold (e.g., 40%), the power network scheme is changed from the second power network scheme to the first power network scheme to reduce power network occupancy; for regions with a higher cell density (e.g., greater than 70%), the third power network scheme is maintained or upgraded to meet higher power supply demands. The adjusted power network scheme only takes effect in the corresponding region, thereby achieving a non-uniform, adaptive distribution of the power network globally.

[0052] The computer device 300 provided in this embodiment of the invention can implement the steps in the adaptive power routing method for the processor as described in the above embodiments, and can achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.

[0053] Example 4 This invention also provides a computer-readable storage medium storing an adaptive power routing program for a processor. When executed by the processor, the adaptive power routing program implements the various processes and steps of the adaptive power routing method for a processor provided in this invention and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0054] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0055] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0056] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0057] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form without departing from the spirit and scope of the claims of the present invention, and all such changes are within the protection scope of the present invention.

Claims

1. An adaptive power routing method for a processor, characterized in that, The adaptive power routing method includes the following steps: S1. Establish multiple power network schemes based on the cell density of different regions of the processor chip; S2. Select one of the various power network schemes as a reference scheme, and perform preliminary placement of the processor chip units based on the reference scheme to obtain an initial power network; S3. Based on the dimensions of the reference scheme, the initial power network is divided into regions to obtain multiple physical region units; the number of standard units or equivalent unit areas in each physical region unit are counted and the corresponding unit density is calculated to obtain the region unit density corresponding to the multiple physical region units. S4. Based on the density of the physical area units, adjust the layout and wiring of the physical area units to the corresponding power network scheme to realize the adaptive power wiring of the processor chip.

2. The adaptive power routing method for a processor as described in claim 1, characterized in that, The power network scheme includes a first power network scheme, a second power network scheme, and a third power network scheme. The first power network scheme is defined as A when it is suitable for the cell density of the processor chip, the second power network scheme is defined as B when it is suitable for the cell density of the processor chip, and the third power network scheme is defined as C when it is suitable for the cell density of the processor chip, satisfying the condition: A < B < C. In step S2, the second power network scheme is selected as the baseline scheme.

3. The adaptive power routing method for a processor as described in claim 1, characterized in that, The power network scheme includes metal layer selection parameters, line width parameters, line spacing parameters, and grid spacing parameters.

4. The adaptive power routing method for a processor as described in claim 3, characterized in that, The metal layer selection parameters, line width parameters, line spacing parameters, and grid spacing parameters differ among the different power network schemes.

5. An adaptive power routing system for a processor, characterized in that, The adaptive power cabling system includes: The scheme establishment module is used to establish various power network schemes based on different cell densities of the processor chip. An initial power network generation module is used to select one of the various power network schemes as a reference scheme, and to initially place the units of the processor chip based on the reference scheme to obtain an initial power network. The region division module is used to divide the initial power network into regions based on the size of the reference scheme to obtain multiple physical region units; count the number of standard units or equivalent unit area in each physical region unit and calculate the corresponding unit density to obtain the region unit density corresponding to the multiple physical region units. The adjustment module is used to adjust the layout and wiring of the physical region units according to the region unit density to the corresponding power network scheme, thereby realizing the adaptive power wiring of the processor chip.

6. The adaptive power routing system for a processor as described in claim 5, characterized in that, The power network scheme includes a first power network scheme, a second power network scheme, and a third power network scheme. The cell density to which the first power network scheme is applicable is defined as A, the cell density to which the second power network scheme is applicable is defined as B, and the cell density to which the third power network scheme is applicable is defined as C, which satisfies the condition: A < B < C. In the initial power network generation module, the second power network scheme is selected as the baseline scheme.

7. The adaptive power routing system for the processor as described in claim 5, characterized in that, The power network scheme includes metal layer selection parameters, line width parameters, line spacing parameters, and grid spacing parameters.

8. The adaptive power routing system for the processor as described in claim 7, characterized in that, The metal layer selection parameters, line width parameters, line spacing parameters, and grid spacing parameters differ among the different power network schemes.

9. A computer device, characterized in that, include: A memory, a processor, and an adaptive power routing program for the processor stored in the memory and executable on the processor, wherein the processor, when executing the adaptive power routing program, implements the steps of the adaptive power routing method for the processor as described in any one of claims 1-4.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores an adaptive power routing program for the processor, which, when executed by the processor, implements the steps of the adaptive power routing method for the processor as described in any one of claims 1-4.

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