Computing power chip, physical design method thereof and three-dimensional integrated circuit chip

Abstract

A computing power chip and a physical design method thereof, and a three-dimensional integrated circuit chip, the method comprising: determining a structure and a design level of the computing power chip, the computing power chip comprising a plurality of computing groups arranged along a first direction, each computing group comprising a plurality of computing units arranged along a second direction, the design level comprises a calculation unit layer, a calculation group layer and a top layer from bottom to top, and the first direction and the second direction intersect; in the calculation unit layer, first layout wiring design is carried out on the calculation units, and the calculation units with time sequence convergence are obtained; in the calculation group layer, calling a plurality of calculation units, flattening the calculation units, deleting wires in the calculation units, and carrying out second layout wiring design on the calculation groups to obtain the calculation groups with time sequence convergence; and at the top layer, calling the calculation group, and carrying out third layout wiring design on the top layer to obtain a designed computing power chip.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of integrated circuit technology, and particularly to a computing chip and its physical design method, and a three-dimensional integrated circuit chip. Background Technology

[0002] Currently, 3D ICs are an emerging field in chip design. In some solutions, memory chips and computing chips are integrated using 3D IC technology to achieve mutual communication. On the computing chip, through-silicon vias (TSVs) need to be designed to power the memory chip, which significantly increases the design complexity of the computing chip's digital back-end process. Furthermore, due to the high computing power requirements of computing chips, extreme optimization of chip density is necessary, which greatly increases the difficulty of wiring and timing convergence.

[0003] Traditional flattened design methods for computing chips involve flattening all computing units during the design process. This results in excessively long iteration times and makes it difficult to achieve optimal design at each level. If additional computing power is required, a complete backend design process must be redesigned. Furthermore, the layout of different computing units may vary, introducing many uncontrollable factors into the critical signal processing at the top level, leading to lower efficiency when using top-level routing strategies. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a physical design method for a computing chip, including: The structure and design hierarchy of the computing chip are determined. The computing chip includes multiple computing groups arranged along a first direction, and each computing group includes multiple computing units arranged along a second direction. The design hierarchy includes a bottom-up computing unit layer, a computing group layer, and a top layer, wherein the first direction and the second direction intersect. In the computing unit layer, a first layout and routing design is performed on the computing unit to obtain the computing unit with time convergence; In the computing group layer, multiple computing units are invoked, the computing units are flattened and the wiring in the computing units is deleted, and a second layout and routing design is performed on the computing group to obtain the computing group with time convergence. At the top layer, the computing group is invoked to perform a third layout and routing design on the top layer, resulting in a designed computing chip.

[0006] This disclosure also provides a computing chip, which is designed using the physical design method for computing chips as described in any embodiment of this disclosure.

[0007] This disclosure also provides a three-dimensional integrated circuit chip, including the computing chip as described above, and a memory chip, wherein the computing chip and the memory chip are interconnected through a hybrid bonding structure.

[0008] The computing chip and its physical design method, as well as the three-dimensional integrated circuit chip provided in this disclosure, achieve timing-converged computing units by performing a first placement and routing design on the computing units at the computing unit layer; at the computing group layer, multiple computing units are invoked, the computing units are flattened and the routing in the computing units is deleted, and a second placement and routing design is performed on the computing group to obtain a timing-converged computing group; at the top layer, the computing group is invoked and a third placement and routing design is performed on the top layer to obtain a well-designed computing chip. This allows for maximum optimization of the design at each design level: high-density utilization can be achieved when designing the computing unit layer; high-level routing resources can be accurately utilized when designing the computing group layer; and clock delay and clock skew can be optimized as much as possible by better combining the actual layout conditions when designing the top layer.

[0009] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0010] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0011] Figure 1 This is a flowchart illustrating a physical design method for a computing chip, which is an exemplary embodiment of this disclosure. Figure 2 This is a top-level design architecture diagram and data flow diagram of the computing chip in an exemplary embodiment of this disclosure; Figure 3 This is a top-level hierarchical layout of the computing chip in an exemplary embodiment of this disclosure; Figure 4 This is a diagram showing the effect of flattening the top layer of the computing chip in an exemplary embodiment of this disclosure; Figure 5 A flowchart illustrating another physical design method for a computing chip, which is an exemplary embodiment of this disclosure; Figure 6 This is a first-version layout plan of the computing unit in an exemplary embodiment of this disclosure; Figure 7 This is a second version layout plan of the computing unit in an exemplary embodiment of this disclosure; Figure 8 The optimized pin location of the first control signal (WT signal) and the WT signal routing diagram of the computing layer design in the exemplary embodiments of this disclosure; Figure 9 A diagram showing the location of trace buffers manually added to the compute group layer in an exemplary embodiment of this disclosure; Figure 10 This is a schematic diagram showing the placement of through-silicon vias (TSVs) in an exemplary embodiment of this disclosure; Figure 11 This is an exemplary embodiment of the present disclosure showing the location of the first register (ACT register) at the top level and its flight path diagram; Figure 12 This is a schematic diagram of the Route strategy for the first register key signal in the top-level design of the exemplary embodiments of this disclosure; Figure 13 This is an HTree wiring network diagram of the top-level design in an exemplary embodiment of this disclosure. Detailed Implementation

[0012] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments and features described herein can be combined arbitrarily.

[0013] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" indicate that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, but do not exclude other elements or objects.

[0014] like Figure 1 As shown, this disclosure provides a physical design method for a computing chip, including: Step 101: Determine the structure and design hierarchy of the computing chip. The computing chip includes multiple computing groups arranged along a first direction. Each computing group includes multiple computing units arranged along a second direction. The design hierarchy includes a bottom-up computing unit layer, a computing group layer, and a top layer, wherein the first direction and the second direction intersect. Step 102: At the computing unit layer, perform the first layout and routing design for the computing units to obtain timing-converged computing units; Step 103: In the computing group layer, call multiple computing units, flatten the computing units and delete the wiring in the computing units, perform a second layout and routing design for the computing group, and obtain a timing-converged computing group. Step 104: At the top level, call the computing group to perform the third layout routing design on the top level to obtain the designed computing chip.

[0015] The physical design method for the computing chip in this embodiment involves: at the computing unit layer, performing a first placement and routing design on the computing units to obtain timing-converged computing units; at the computing group layer, calling multiple computing units, flattening the computing units and deleting the wiring in the computing units, and performing a second placement and routing design on the computing group to obtain a timing-converged computing group; at the top layer, calling the computing group and performing a third placement and routing design on the top layer to obtain the designed computing chip. This method allows for maximum optimization of the design at each design layer: at the computing unit layer, high-density utilization can be achieved (in one instance, 83% utilization can be achieved). At the computing group layer, high-level routing resources can be precisely utilized. At the top layer, the actual layout can be better considered to optimize clock latency and clock skew as much as possible.

[0016] The computing chip in the embodiments of this disclosure can be a tensor computing chip; however, this disclosure does not limit it.

[0017] In this embodiment of the disclosure, when designing the computing group layer, after flattening the computing unit and deleting the wiring in the computing unit, other logic in this layer can be placed in appropriate positions by means of scripts, and corresponding buffers can be inserted. The routing strategy (including the use of higher-level routing and priority routing strategies for WT signal routing) can be redefined to obtain a timing-converged computing group.

[0018] For example, in exemplary embodiments of this disclosure, such as Figures 2 to 4 As shown, the central area of ​​the computing chip is the configuration register area, mainly used to place some configuration registers at the top layer. The top and bottom sides of the configuration register area each include multiple vertically arranged computation groups (wrappers). Each computation group consists of multiple horizontally arranged computation units (elements). For example, the top and bottom sides of the configuration register area each include 16 wrappers (e.g., ...). Figure 2 (0 wrapper to 31 wrapper) Each computation group includes 16 elements (e.g., 0 wrapper to 31 wrapper) Figure 2 Therefore, this computing chip comprises a total of 32*16 Elements (E1 to E16 in the original text). Additionally, a Memory Control (MC) area (e.g., E1 to E16) is interspersed on both the top and bottom sides of the configuration register area. Figure 2The storage control area (containing Mc0_wrapper and Mc1_wrapper) is used to configure the storage control circuit, which manages and controls the storage chip. The main control signals include two paths: a first control signal (WT) and a second control signal (ACT). WT is the horizontal broadcast signal, and ACT is the column-to-column broadcast signal. The ACT signal is sent by the ACT register in the configuration register area. Each ACT register broadcasts to each element in the corresponding column to both sides of the configuration register area. The ACT signal corresponding to each column element is transmitted by a set of first signal buses, which, for example, each set of first signal buses includes 576 bits. The WT signal is sent by the WT register in the right-side module of the computing chip (this module is located on the same printed circuit board as the computing chip). Each WT register broadcasts to each element in the corresponding row to the left. The WT signal corresponding to each row element is transmitted by a set of second signal buses, which, for example, each set of second signal buses includes 576 bits. Additionally, the calculation result of each element is transmitted to the right-side module for reception via a set of third signal buses, which, for example, each set of third signal buses includes 16 bits. For specific data flow details, please refer to [reference needed]. Figure 2 As shown. The specific physical location is as follows. Figure 3 and Figure 4 As shown.

[0019] In this embodiment of the disclosure, the first direction can be Figure 2 The column direction in the middle, the second direction can be Figure 2 The direction of the line is not limited in this disclosure.

[0020] Figure 5 This is a flowchart illustrating a physical design (PnR) implementation of an exemplary embodiment of this disclosure. The physical design method of this embodiment mainly includes three design layers: the computing unit layer, the computing group layer, and the top layer. The computing unit layer uses two-page floorplanning and placement to minimize the routing resources occupied by broadcast signals. The design process of the computing group layer includes assembling and routing, as well as manual optimization of related logic. The top layer design includes manual drawing of HTree and the regular placement of ACT registers.

[0021] In some exemplary embodiments, a first layout and routing design for the computing unit includes: The computing unit is first-version layout planning and placement. During the first-version layout planning and placement, multiple first control signal (WT signal) pins are placed on the edge of the computing unit along the second direction, and multiple second control signal (ACT signal) pins are placed on the edge of the computing unit along the first direction. The first control signal is input to multiple computing units along the second direction, and the second control signal is input to multiple computing units along the first direction. A second version of the layout planning and placement of the computing unit is performed. During the second version of the layout planning and placement, the position of each first control signal pin along the second direction is adjusted according to the position of the signal receiving end of each first control signal pin, and the position of each second control signal pin along the first direction is adjusted according to the position of the signal receiving end of each second control signal pin. Clock tree synthesis (CTS), first routing, and engineering change order (ECO) optimization are performed to obtain a timing-converged computing unit.

[0022] Figure 6 This is a schematic diagram of the first version of the layout plan of an exemplary embodiment of this disclosure. Figure 7 This is a schematic diagram of a second version of the layout plan, representing an exemplary embodiment of this disclosure. Figure 6 As shown, in the first layout plan, the ACT pins and WT pins were placed on the bottom and right edges of the element, respectively. Figure 7 As shown, after the first round of placement, each ACT pin and / or WT pin is moved to the middle position of its corresponding signal receiver (load) according to the distribution of the signal receiver (loads) of the ACT pin and / or WT pin.

[0023] In this embodiment of the disclosure, when adjusting the position of any ACT pin, the vertical position of the ACT pin is adjusted according to the position of one or more signal receivers corresponding to the ACT pin (while keeping the horizontal position unchanged); when adjusting the position of any WT pin, the horizontal position of the WT pin is adjusted according to the position of one or more signal receivers corresponding to the WT pin (while keeping the vertical position unchanged).

[0024] Figure 8 This is a schematic diagram of two signal traces in the second signal bus that transmits the WT signal after routing in the compute group layer. Figure 8In this embodiment, each trace consists of multiple physical traces (nets). Crosses on the traces represent inputs, and circles on the traces represent outputs. This disclosure reduces the net bus length corresponding to the D and Q terminals of the WT register by 20% by adjusting the lateral position of the WT pins in each computing unit. This embodiment effectively reduces the wiring resources occupied by the first and second control signal pins by performing two-page layout planning and placement of the computing units.

[0025] In this embodiment, the computing unit performs the placement and routing (PnR) and timing repair (ECO) processes independently as a computing core. This effectively reduces the timing pressure on the computing group layer.

[0026] In some exemplary embodiments, the first layout and routing design for the computing unit further includes: The computing unit reserves a first position, a second position, and a third position. The first position is reserved for placing multiple second buffers in the computing group layer. The second buffers are used to relay the second control signal (ACT signal). The second position is reserved for placing a through-silicon via (TSV) for the power ground network in the top layer. The third position is reserved for placing multiple fourth buffers in the top layer. The fourth buffers are used to relay at least one of the following signals: a clock signal and a fourth control signal. The clock signal and / or the fourth control signal are output to the computing unit through the wiring network of the H-shaped branch structure (HTree).

[0027] In some exemplary embodiments, the first position is located at the input port of the computing unit along the first direction, the second position is located at the vertex of the computing unit layout position, and the third position is located in the middle row of the computing unit along the first direction.

[0028] For example, such as Figure 6 As shown, the top left and bottom left corners (second positions) of the Element are used to place dummy TSVs (the dummy TSVs are used to reserve space for the real TSVs at the top layer; the real VDD / VSS TSVs need to be optimized at the top layer according to the power supply voltage drop (IR Drop) requirements). The middle row of the Element (third position) is reserved for the top layer to be used as an HTree. The bottom side of the Element (first position) is reserved for the compute group layer to place the ACT feedthrough buffer, i.e., the second buffer.

[0029] In this embodiment of the disclosure, the fourth control signal can be a set of flag signals. In this embodiment of the disclosure, both the clock signal and the flag signals are output to the computing unit through the HTree wiring network. Among them, the flag signals are typically used to identify states or events, such as a start flag (first_flag) and an end flag (last_flag) for identifying a data stream.

[0030] In some exemplary embodiments, the method further includes: In the computing group layer, multiple first buffers, second buffers, and third buffers are arranged. The first buffer is used to relay the first control signal (WT signal), the second buffer is used to relay the second control signal (ACT signal), and the third buffer is used to relay at least one of the following signals: the third control signal (acc signal), the interconnection signal (Vlink signal), and the result output signal (result signal).

[0031] In this embodiment of the disclosure, the acc signal is used to manage power mode switching, and the Vlink signal typically represents a high-speed serial interface signal used for low-latency data transmission between chips or modules.

[0032] In some exemplary embodiments, the method further includes: deleting boundary cells between adjacent computing units in the computing group layer.

[0033] The compute group layer employs a semi-hierarchical design flow. Specifically, after timing closure of the compute units, multiple compute units with different names are invoked in a design tool (such as Innovus) to form a compute group. This allows for different layouts of compute units within a compute group when subsequently placing global registers and buffers. Multiple compute units are flattened using an assemble design approach, removing endcap cells between adjacent compute units and all wiring within each compute unit. Endcap cells and power / ground (PG) networks are planned uniformly in the compute group layer, while trap contact cells (TAP cells) are designed in reverse order from the compute unit layer.

[0034] Since each computing unit has a reserved first position at its input port for placing multiple second buffers, the second buffers can be placed directly in the reserved first position when designing the computing group layer.

[0035] Figure 9 The diagram shows the locations of the first and third buffers designed for the computational layer. The location of the first buffer (WT signal buffer) is indicated by a red line, and the location of the third buffer (acc, Vlink, result signal buffer) is indicated by a pink line.

[0036] In some exemplary embodiments, the method further includes: In the compute group layer, global registers are arranged and a global register clock tree is created.

[0037] In this embodiment, during the second layout and routing design of the computing group, parameters such as the linewidth and spacing of the clock network are adjusted to reduce signal delay and power consumption, thereby improving timing performance. Timing-critical signals are allocated to higher metal layers, utilizing their low resistance characteristics to reduce signal attenuation and crosstalk. During global routing, clock and timing-critical paths are prioritized to ensure timing convergence. Finally, the routing of other signals is completed to ensure the integrity of the overall design.

[0038] In this embodiment of the disclosure, such as Figure 10 As shown, when placing TSVs at the top layer, the top left and bottom left vertices of each computing unit are used as grid points, and they are placed according to a certain pattern.

[0039] In some exemplary embodiments, the method further includes: at the top layer, arranging a plurality of first registers (ACT registers), wherein the first registers are used to provide a second control signal (ACT signal) to a plurality of computing units along a first direction.

[0040] In some exemplary embodiments, the first register is arranged in the central region of the computing chip along the first direction. By arranging the first register in the central region of the computing chip along the first direction, further optimization of chip timing, power consumption, and area (PPA) can be achieved.

[0041] like Figure 11 As shown, ACT registers are placed in the configuration register area. To avoid detours and reduce the use of route resources, we use a script to place the ACT registers, ensuring precise placement. The D pin flying wire of each ACT register is set horizontally, and the Q pin flying wire of each ACT register is set vertically. The flying wires between multiple ACT registers do not intersect, which can effectively reduce the bus length and improve timing stability.

[0042] In some exemplary embodiments, the first register is divided into M groups along the second direction. The layer number of the routing resources of the first register in the i-th group is lower than the layer number of the routing resources of the first register in the j-th group. Here, i is between 2 and M, j is between 1 and M-1 and j is less than i, the first register in the j-th group is located to the left of the first register in the i-th group, and M is an integer greater than 1.

[0043] like Figure 12As shown, a third routing strategy is formulated for the first register at different locations. Higher-level resources are reserved for the D terminal (data input terminal) of the left register, and lower-level route resources are reserved for the D terminal of the right register. By allocating routing resources in a layered manner, the setup time of the left register and the hold time of the right register can be optimized simultaneously.

[0044] For example, Figure 12 In the example, M=5, which means that the first register is divided into five groups. The first group to the fifth group are arranged from left to right. The first register of the first group uses the resource routing of M10, the first register of the second group uses the resource routing of M8, the first register of the third group uses the resource routing of M6, the first register of the fourth group uses the resource routing of M4, and the first register of the fifth group uses the resource routing of M2.

[0045] like Figure 13 As shown, the global distribution of the master clock and key control signals is achieved at the top level through the HTree structure. Combined with the pre-planned buffers inside the computing unit, the impact of clock latency and on-chip variation (OCV) on timing is reduced.

[0046] The embodiments disclosed herein, by manually customizing the HTree, can better integrate with the actual layout and achieve the best possible optimization of clock latency and clock skew.

[0047] This disclosure also provides a computing chip, which is designed using the physical design method for computing chips as described in any embodiment of this disclosure. For example, the computing chip may be a tensor computing chip.

[0048] This disclosure also provides a three-dimensional integrated circuit chip, including a computing chip and a memory chip, wherein the computing chip and the memory chip are interconnected via a hybrid bonding structure. This hybrid bonding structure can be disposed together with a memory control circuit in the memory control region of the computing chip.

[0049] The computing chip and three-dimensional integrated circuit chip of this disclosure utilize the hierarchical design advantages of the aforementioned computing chip physical design method to complete the layout and wiring design of the computing chip. They have the beneficial effects of the computing chip physical design method described in any of the above embodiments, which will not be repeated here.

[0050] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.

[0051] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0052] Furthermore, it should be understood that in the description of this application, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Additionally, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. Moreover, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0053] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to implement and use it. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. A physical design method for a computing chip, characterized in that, include: The structure and design hierarchy of the computing chip are determined. The computing chip includes multiple computing groups arranged along a first direction, and each computing group includes multiple computing units arranged along a second direction. The design hierarchy includes a bottom-up computing unit layer, a computing group layer, and a top layer, wherein the first direction and the second direction intersect. In the computing unit layer, a first layout and routing design is performed on the computing unit to obtain the computing unit with time convergence; In the computing group layer, multiple computing units are invoked, the computing units are flattened and the wiring in the computing units is deleted, and a second layout and routing design is performed on the computing group to obtain the computing group with time convergence. At the top layer, the computing group is invoked to perform a third layout and routing design on the top layer, resulting in a designed computing chip.

2. The method according to claim 1, characterized in that, The first layout and routing design for the computing unit includes: A first layout plan and placement is performed on the computing unit. During the first layout plan and placement, multiple first control signal pins are placed on the edge of the computing unit along the second direction, and multiple second control signal pins are placed on the edge of the computing unit along the first direction. The first control signal is input to the multiple computing units along the second direction, and the second control signal is input to the multiple computing units along the first direction. A second version of the layout planning and placement is performed on the computing unit. During the second version of the layout planning and placement, the position of each first control signal pin along the second direction is adjusted according to the receiving end position of each first control signal pin, and the position of each second control signal pin along the first direction is adjusted according to the receiving end position of each second control signal pin. Clock tree synthesis, first routing, and engineering change instruction optimization are performed to obtain the timing-converged computing unit.

3. The method according to claim 1, characterized in that, Before performing a second layout and routing design on the computing group, the method further includes: In the computing group layer, a plurality of first buffers, second buffers and third buffers are arranged, wherein the first buffer is used to relay a first control signal, the second buffer is used to relay a second control signal, and the third buffer is used to relay at least one of the following signals: a third control signal, an interconnection signal, and a result output signal.

4. The method according to claim 1, characterized in that, The first layout and routing design for the computing unit includes: The computing unit reserves a first position, a second position, and a third position. The first position is reserved for placing multiple second buffers in the computing group layer. The second buffers are used to relay second control signals. The second position is reserved for placing silicon vias for power and ground networks in the top layer. The third position is reserved for placing multiple fourth buffers in the top layer. The fourth buffers are used to relay at least one of the following signals: a clock signal and a fourth control signal. The clock signal and / or the fourth control signal are output to the computing unit through a wiring network with an H-shaped branch structure.

5. The method according to claim 4, characterized in that, The first position is located at the input port of the computing unit along the first direction, the second position is located at the vertex of the layout position of the computing unit, and the third position is located in the middle row of the computing unit along the first direction.

6. The method according to claim 1, characterized in that, The method further includes: arranging a plurality of first registers at the top layer, wherein the first registers are used to provide a second control signal to the plurality of computing units along the first direction.

7. The method according to claim 6, characterized in that, The first register is located in the middle region of the computing chip along the first direction.

8. The method according to claim 6, characterized in that, The first register is divided into M groups along the second direction. The layer number of the routing resources of the first register in the i-th group is lower than the layer number of the routing resources of the first register in the j-th group. Here, i is between 2 and M, j is between 1 and M-1 and j is less than i. The first register in the j-th group is located to the left of the first register in the i-th group. M is an integer greater than 1.

9. A computing chip, characterized in that, The computing chip is designed using the physical design method for computing chips as described in any one of claims 1 to 8.

10. A three-dimensional integrated circuit chip, characterized in that, The device includes the computing chip as described in claim 9, and also includes a storage chip, wherein the computing chip and the storage chip are interconnected through a hybrid bonding structure.

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