Hardware course-oriented digital twinborn integrated teaching experiment platform

Abstract

The invention belongs to the field of computer hardware teaching and education informatization, and particularly relates to a hardware course-oriented digital twinborn integrated teaching experiment platform, which comprises a client, a remote control system, a data communication system and a student experiment system, and realizes virtualization of an FPGA development board through three-dimensional modeling. Students are supported to operate peripherals in a virtual interface, and the remote control system issues instructions to the entity FPGA and feeds back running states, so that synchronization of a virtual environment and a physical experiment is realized; according to the platform, multi-dimensional parameters such as delay monitoring, state synchronization, resource utilization rate, course achievement, performance optimization, CoreMark scoring and stability are introduced in the experiment process, an efficiency index evaluation model is constructed, and dynamic allocation and scheduling optimization of resources are achieved in combination with a centralized FPGA matrix. According to the platform, the defect that a traditional laboratory is limited by the number of hardware and site conditions can be broken through, smooth connection between remote concurrent access and courses is supported, and the teaching resource utilization efficiency and the course achievement degree are improved.

Description

Technical Field

[0001] This invention relates to the field of computer hardware teaching and educational informatization technology, and more specifically, to a digital twin integrated teaching experimental platform for hardware courses. Background Technology

[0002] With the rapid development of information technology and computer science, hardware courses have become one of the most important teaching components in computer science. Traditional computer hardware courses typically include multiple stages such as Digital Logic, Computer Organization, Computer Architecture, and System-on-a-Chip (SoC) Design and Verification. The aim is to guide students from logic circuit design to processor core architecture design, and then to complex system integration and applications, through a progressive teaching arrangement. However, in current teaching practices, the experimental component is often limited by physical environment, resource allocation, and management models, presenting numerous problems and failing to meet the dual demands of large-scale teaching and personalized training.

[0003] Firstly, regarding experimental hardware resources, traditional teaching experiments primarily rely on local computer labs and physical FPGA experimental boards. Due to the high cost of hardware procurement and maintenance, the limited number of experimental boards available makes it difficult to meet the demands of concurrent experiments in large-scale courses. Especially as class sizes for hardware experiments gradually increase, students often need to take turns using the equipment, resulting in insufficient experimental opportunities and impacting teaching effectiveness. Furthermore, differences in hardware configurations, peripheral interfaces, and firmware versions among different batches of FPGA experimental boards make it difficult to maintain a completely consistent experimental environment, further complicating the unified teaching of courses.

[0004] Secondly, regarding the flexibility and accessibility of the experimental environment, traditional experimental methods mainly rely on offline centralized computer labs, requiring students to complete experiments at fixed times and locations. This model not only occupies a large amount of physical space and incurs significant operational costs but also fails to meet the needs of new teaching models such as remote learning and blended learning. In recent years, with the rise of new educational methods such as MOOCs and cloud experiments, how to achieve remote access, real-time interaction, and virtual simulation in hardware courses has become an urgent problem to be solved.

[0005] Third, regarding the interactivity and feedback mechanisms in the experimental process, in the traditional model, students have limited debugging methods when conducting experiments on FPGAs. They typically need to rely on serial port debugging or observing limited peripherals such as LEDs and digital tubes to determine the correctness of the logic. This approach lacks intuitiveness and is inefficient, making it difficult to meet the needs of complex CPU design and SoC experiments. More importantly, teachers have insufficient control over the students' experimental process, often only able to understand the situation after class through grades or lab reports, lacking real-time monitoring and intervention methods. This not only reduces teaching efficiency but also affects the accurate evaluation of students' experimental skills.

[0006] Fourth, regarding the experimental evaluation system, traditional hardware courses typically assess students primarily based on lab reports, classroom performance, and exam scores, lacking quantitative indicators for the experimental process. Core parameters involved in experiments, such as latency, synchronization accuracy, resource utilization, and performance optimization effects, cannot be effectively evaluated. This leads to student experimental results often remaining at the level of "whether it can be achieved," lacking a comprehensive assessment of "implementation quality" and "optimization ability." This significantly limits the cultivation of students' innovation capabilities and engineering literacy.

[0007] Furthermore, the "101 Plan" has been promoted in universities nationwide in recent years, placing higher demands on the computer hardware curriculum system. This plan emphasizes building a comprehensive training system covering everything from digital circuits to system-on-a-chip design through the connection of core courses. However, existing experimental platforms are generally fragmented and disjointed, with insufficient connection between experimental content in different courses. After completing basic experiments, students often find it difficult to smoothly transition to processor design and system verification. The lack of an integrated and systematic experimental platform has become a significant bottleneck restricting the implementation of the "101 Plan."

[0008] While some existing remote experimental systems enable online access, most remain at the software simulation level, lacking support for virtual-to-physical mapping of real FPGA hardware. Some platforms attempt to support remote experiments by connecting FPGA hardware via the cloud, but these are often limited to simple logic verification or small-scale applications, failing to meet the teaching needs of a complete curriculum. Furthermore, existing systems have limited intelligence in areas such as experimental data acquisition, performance monitoring, and resource scheduling, making it difficult to achieve comprehensive quantification and dynamic optimization of teaching effectiveness.

[0009] In summary, the existing technologies generally have the following shortcomings in hardware course experiments: (1) limited experimental resources, making it difficult to support large-scale teaching; (2) limited experimental environment, lacking remote access and flexible deployment capabilities; (3) insufficient interactivity in the experimental process, delayed feedback, making it difficult to meet the needs of complex experiments; (4) a single experimental evaluation system, lacking a comprehensive measurement of experimental quality and optimization capabilities; and (5) poor course connection, lacking an integrated experimental platform.

[0010] Therefore, in view of the problems of insufficient predictive accuracy, limited coverage and weak clinical guidance in existing AML prognostic assessment methods, we designed a digital twin integrated teaching and experimental platform for hardware courses to solve these problems. Summary of the Invention

[0011] The purpose of this invention is to address existing technical problems by proposing a digital twin integrated teaching and experimental platform for hardware courses.

[0012] The objective of this invention is achieved through the following technical solution:

[0013] A digital twin integrated teaching and experimental platform for hardware courses includes a client, a remote control system, a data communication system, and a student experimental system;

[0014] The client presents a virtual interface that is highly consistent with the FPGA development board based on 3D modeling. Students can perform interactive operations on peripherals such as DIP switches, buttons, LEDs, and digital tubes on this interface.

[0015] The remote control system is used to receive operation instructions from the client, convert them into control commands and send them to the FPGA. At the same time, it periodically acquires the FPGA's operating status and feeds it back to the client in real time, thereby enabling the virtual experiment to run synchronously with the physical hardware.

[0016] The data communication system provides a communication channel based on a serial protocol, which ensures the stability and real-time performance of command transmission and status feedback.

[0017] The student experimental system provides students with a unified interface environment, supports the writing, simulation and synthesis of hardware description languages ​​in EDA tools, and completes remote debugging and verification through bitstream download;

[0018] The platform can measure interaction delay parameters during operation and use these parameters as the basis for evaluating the performance of teaching experiments and making synchronous corrections.

[0019] As a preferred technical solution of the present invention, the interaction delay parameter is introduced into the state synchronization mechanism. The platform can dynamically correct the state consistency between the client virtual peripheral and the FPGA actual peripheral according to the delay size. When the delay is small, high-precision synchronization is maintained. When the delay is large, it is corrected through the error tolerance mechanism, thereby ensuring the consistency of the virtual interface and the physical experiment results in terms of operation experience.

[0020] As a preferred technical solution of this invention, the state synchronization result directly affects the resource utilization of the FPGA. The platform can calculate the resource utilization efficiency by combining the number of logic units used in the student experiment with the state deviation. When the synchronization accuracy is insufficient, the platform will determine that the resource utilization rate has decreased, so as to reflect the impact of synchronization error on hardware resource efficiency, thereby guiding students to optimize the design in the experiment and improve the accuracy of logic implementation and the rationality of resource use.

[0021] As a preferred technical solution of the present invention, the resource utilization efficiency is further incorporated into the evaluation system for the achievement of teaching courses. The platform can calculate the average student experimental score and the course target value, and then combine the resource utilization rate to make a weighted correction on the achievement, thereby avoiding the sole criterion of using scores as the only evaluation standard and achieving a more comprehensive reflection of the student's experimental results.

[0022] As a preferred technical solution of the present invention, the course achievement level is introduced into the performance optimization evaluation of the pipelined CPU experiment. The platform can reflect the student's actual experimental contribution by comparing the results of sequential execution and pipelined execution, and thus realize the organic combination between student experimental performance and performance optimization effect.

[0023] As a preferred technical solution of the present invention, the performance optimization results are further introduced into the processor performance testing system. The platform scores the processors designed by students through the standardized CoreMark performance testing method, and embeds the performance improvement effect as a weight into the scoring system, so that the performance test results not only meet industry standards, but also reflect the actual optimization level of students in the experimental process.

[0024] As a preferred technical solution of this invention, the performance test results are further incorporated into the platform stability evaluation system. While calculating the transmission error rate, the platform also calculates a stability index based on CoreMark scores to reflect its reliability under long-term operation or large-scale testing conditions. A higher stability index indicates more stable platform performance during teaching experiments.

[0025] As a preferred technical solution of the present invention, the stability index is used to guide the allocation strategy of FPGA matrix resources. When the platform centrally manages multiple development boards, it can dynamically allocate hardware resources according to the experimental stability results, giving priority to tasks with high stability and high experimental value, thereby improving the overall resource allocation efficiency and reducing operation and maintenance costs.

[0026] As a preferred technical solution of the present invention, the resource allocation efficiency, interaction latency, state synchronization, resource utilization, course achievement, performance optimization results, performance test scores and stability, etc., work together to form an efficiency index by comprehensively considering these factors. This efficiency index can reflect the overall performance of the platform in terms of latency, accuracy, resources, courses and performance in multiple dimensions, and serves as the core evaluation indicator for subsequent optimization and scheduling.

[0027] As a preferred technical solution of the present invention, the efficiency index is used for intelligent resource scheduling optimization. The platform aims to improve overall efficiency and dynamically adjusts the experimental resource allocation strategy under preset constraints such as maximum latency, minimum resource utilization, and minimum stability to achieve adaptive optimization of hardware courses. This ensures that the experimental platform still has good real-time performance, reliability, and teaching support capabilities under multi-user, multi-task concurrency.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] The digital twin integrated teaching and experimental platform for hardware courses proposed in this invention can effectively solve the problems of limited resources, restricted environment, insufficient interactivity, single evaluation system, and poor course connection in existing hardware course experiments, and has the following beneficial effects:

[0030] First, this invention achieves a one-to-one mapping between virtual clients and physical FPGA experimental boards by constructing a digital twin experimental platform. Students' operations on the virtual interface are reflected in real time on the physical hardware, and the hardware's operating results are synchronously transmitted back to the virtual end. Compared to the traditional model that relies on on-site operation, this invention overcomes the limitations of physical computer labs, supports remote access and cross-regional experiments, and significantly improves the flexibility and scalability of the experimental environment.

[0031] Secondly, this invention employs a centralized FPGA cabinet matrix for experimental resource management, and combines latency monitoring, synchronization accuracy, and stability indices to construct a resource scheduling mechanism. Under multi-user concurrency conditions, the platform can dynamically allocate experimental resources based on the efficiency index, prioritizing experimental tasks with high stability and high educational value, thereby significantly improving overall resource utilization, reducing equipment idle rate and management costs, and solving the problem of "limited equipment and difficulty in parallelization" in existing technologies.

[0032] Third, this invention introduces a quantitative indicator system for monitoring and evaluating the experimental process. The platform can not only measure interaction latency and state synchronization accuracy, but also combine multiple dimensions such as logic unit occupancy, course achievement, CPU pipeline performance improvement, CoreMark standard scores, and transmission error rate to form a complete performance index model. This model can provide real-time evaluation of the experimental process and results, avoiding the limitations of traditional assessments that rely on experimental reports and lack process monitoring, thus more objectively and comprehensively reflecting students' experimental abilities and optimization levels.

[0033] Fourth, this invention achieves seamless integration and unified support between courses. The platform is not only suitable for fundamental courses such as digital logic and computer organization, but also supports advanced experiments such as RISC-V CPU design, MiniRV pipeline expansion, SoC integration, and trace verification. Through a unified digital twin platform, students can complete the gradual transition from logic circuits to system-on-a-chip design within a continuous learning path, truly realizing the curriculum integration and hierarchical progression training goals emphasized in the "101 Plan."

[0034] Fifth, this invention significantly enhances students' learning experience and outcomes in terms of teaching effectiveness. Experimental data shows that, in typical class sizes, the platform's average interaction latency is controlled within 0.5 seconds, the state synchronization deviation is less than 2%, resource utilization is increased by more than 10%, and course achievement is improved by approximately 15% compared to traditional experimental models, resulting in a more significant overall teaching effect. Teachers can also monitor students' experimental progress and performance in real time through the platform, enabling precise teaching and individualized instruction.

[0035] In summary, this invention not only overcomes the resource and space limitations of existing experimental platforms, but also provides a systematic improvement scheme in resource scheduling, experimental evaluation, and course integration, which can significantly improve the teaching efficiency and quality of hardware courses and provide strong support for the cultivation of computer science talents. Attached Figure Description

[0036] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute a limitation thereof.

[0037] Figure 1 It is an integrated teaching and experimental platform for "digital twins";

[0038] Figure 2 It is the practical construction of core computer hardware courses;

[0039] Figure 3 It is the overall architecture of the digital twin platform;

[0040] Figure 4 It is a peripheral remapping diagram;

[0041] Figure 5 It is a data communication system instruction design diagram;

[0042] Figure 6 This is a diagram of the student experiment system architecture;

[0043] Figure 7 It is an FPGA digital twin matrix;

[0044] Figure 8 These are example diagrams of guiding questions for some experiments;

[0045] Figure 9 This is a diagram of the trace test and board verification. Detailed Implementation

[0046] The following will refer to the appendices in the embodiments of the present invention. Figure 1-9 The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the embodiments described below are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention. In order to provide a clearer explanation and description of the technical solutions and implementation methods of the present invention, specific examples of preferred implementations of the technical solutions of the present invention are introduced below.

[0047] Example 1: This invention proposes a digital twin integrated teaching and experimental platform for hardware courses, aiming to provide seamless experimental support for computer hardware courses through virtualization and remote interaction. The platform consists of a client, a remote control system, a data communication system, and a student experimental system. The overall architecture includes both a software-layer virtual operating environment and a hardware-layer FPGA experimental platform, maintaining consistency between the two through a stable communication protocol and a digital twin mechanism.

[0048] During operation, students first interact with the system through a client application. The client application displays an appearance and functional interface consistent with the actual FPGA development board based on 3D modeling, including peripherals such as DIP switches, buttons, LEDs, and seven-segment displays. The student's operations on the virtual interface are encapsulated into data packets and transmitted to the remote control system via the network. The remote control system parses the data packets into command words and sends them to the FPGA hardware through the data communication system, thereby triggering the corresponding logical behavior on the real experimental board.

[0049] Meanwhile, the FPGA board's operating status is collected in real time and returned to the remote control system via the same channel, then fed back to the client, allowing students to see display results on the virtual interface consistent with those of the actual hardware. Through this mechanism, the platform achieves a transparent mapping between virtual operations and physical experiments.

[0050] To ensure the smoothness of the experimental process, this invention defines a total interaction delay parameter. This describes the time delay from student operation to result feedback, and its formula is:

[0051]

[0052] in, This indicates the communication latency between the client and the remote control system, which is affected by network bandwidth and protocol stack performance. The latency of command parsing and scheduling in a remote control system depends on the server's processing power and scheduling algorithm. The feedback delay after the FPGA board executes the logic is mainly determined by the hardware logic path and the serial port transmission rate. This formula can be used to quantitatively evaluate the overall response speed of the platform and provide input for the correction of subsequent algorithms. Based on the delay quantification, the platform further establishes a state synchronization model.

[0053] The client's virtual peripheral status is recorded as The actual peripheral status of the FPGA is denoted as The deviation between the two is defined as:

[0054]

[0055] in, State deviation is used to measure the difference between virtual operations and real hardware; This is a delay correction factor used to characterize the impact of latency on synchronization accuracy. By linking deviation to latency, the error tolerance can be dynamically adjusted under different network conditions, ensuring the stability and consistency of experimental interactions. Considering the actual utilization of hardware resources, the platform introduces a resource utilization parameter based on state synchronization. The formula is:

[0056]

[0057] in, This indicates the number of FPGA logic units used in the student experiment. This indicates the total number of usable logic cells in the FPGA chip. This represents the synchronization deviation penalty coefficient. When the state deviation is large, the actual resource utilization rate will be reduced, reflecting the impact of insufficient system consistency on experimental resource efficiency. This design encourages students to optimize code design during experiments, avoiding resource waste caused by logical errors or state deviations.

[0058] Based on the evaluation results of resource utilization, the platform further constructed a course achievement model. Let the average student experiment score be... The course objective score is Then the degree of achievement The formula is:

[0059]

[0060] The score ratio reflects the basic level of students' learning outcomes, while resource utilization is embedded as a weighting factor to ensure that the quality of the experiment depends not only on grades but also on the rationality of hardware resources. In this way, the platform can provide more comprehensive evaluation indicators, avoiding the reliance solely on scores as the only standard.

[0061] In the CPU experiment and pipeline performance optimization sections, the course achievement rate was [missing information]. This is further incorporated into the performance improvement rate model. The number of clock cycles required for sequential execution is... The number of clock cycles required for pipeline execution is Performance improvement rate Defined as:

[0062]

[0063] This formula combines students' course completion with the actual effects of pipeline optimization, providing a direct reflection of students' true contributions to performance improvement experiments. Excellent experimental design not only shortens the execution cycle but also improves overall scores, resulting in a higher performance improvement rate reflected in the formula.

[0064] The platform introduces the CoreMark standard test for processor performance verification, and its performance score is defined as:

[0065]

[0066] in, To test the number of iterations, The formula represents the runtime. This formula shows that the performance score is related to both the standard test results and the performance improvement rate of the pipeline experiment, achieving a unified evaluation of teaching objectives and Dingxiao standards.

[0067] To further ensure the usability of the experiment, the platform was designed with a stability index. The formula is:

[0068]

[0069] in, For the number of erroneous transmissions, This represents the total number of transmissions. The stability index value is highest when the error rate is low and the performance score is high, indicating that the platform operates most reliably under these experimental conditions. The platform introduces allocation efficiency into centralized FPGA resource management. Its definition is

[0070]

[0071] in, Indicates the number of FPGA boards that have been allocated. This represents the total number of available FPGA boards. By incorporating the stability index into the resource allocation formula, the platform can dynamically adjust its allocation strategy, ensuring that resource requirements for high-stability experiments are prioritized even under hardware constraints. Finally, the platform integrates all the aforementioned parameters into a performance index. Its expression is:

[0072]

[0073] in, This is a weighted composite function. This index comprehensively reflects the platform's performance across multiple dimensions, including latency, synchronization accuracy, resource utilization, course completion rate, performance optimization, performance scoring, stability, and allocation efficiency. To further improve the platform's automation level, the system introduces an intelligent scheduling optimization mechanism, using an efficiency index... Maximize the objective function:

[0074]

[0075] in, The maximum allowable delay threshold, To achieve the lowest resource utilization rate, This represents the minimum stability index. By setting constraints, the system can ensure that the platform operates under conditions that meet real-time requirements while also considering resource efficiency and stability, thereby achieving optimal allocation of teaching and experimental resources.

[0076] In summary, this invention proposes a complete integrated digital twin experimental platform solution by organically combining client-side virtualization modeling, remote interactive control, data communication protocols, and student experimental systems.

[0077] Example 2: This example provides a digital twin integrated teaching experiment platform for hardware courses, which combines remote interaction, FPGA virtual-real mapping and intelligent scheduling mechanism to support computer hardware series course experiments under the "101 Project".

[0078] like Figure 1 As shown, the platform's overall structure includes a remote control system, a data communication system, and a student experimental system. The client, modeled using Unity, provides a virtual interactive interface consistent with the physical FPGA board, supporting visual operation of peripherals such as DIP switches, buttons, LEDs, and digital tubes. The remote control system receives commands from the client, parses them, and sends them to the FPGA. The FPGA's execution results are then transmitted back to the client via the data communication system, achieving virtual-physical synchronization.

[0079] like Figure 2 As shown, the platform organizes its courses according to a progressive path: "Computer Organization and Architecture—Computer Architecture—SoC Integration and Verification—Comprehensive Hardware Training." Each stage has clearly defined experimental tasks, and the platform seamlessly integrates virtual experiments with hardware training.

[0080] Figure 3 and Figure 4 As shown, the platform provides the overall architecture and peripheral circuit design for the digital twin platform, ensuring a complete correspondence between the virtual and physical ends. Students' operations on the virtual interface are mapped to the DIP switches, buttons, and digital displays on the physical hardware. The system ensures the immediacy and consistency of these operations through a data communication protocol.

[0081] like Figure 5 As shown, the data communication system adopts the UART interface protocol and defines write and read commands. The write command is used to write the peripheral status, and the read command is used to read the entire status of the FPGA at once. The system realizes transparent interaction between the client and the remote control system through an 18-byte data frame structure.

[0082] like Figure 6 and Figure 7 As shown, the student experimental system consists of multiple functional modules, including a serial communication module, a top-level experimental module, a controller module, and a student-defined logic module. All FPGA experimental boards are centrally installed in a rack, forming a "digital twin matrix" that allows multiple students to remotely access and concurrently run experiments.

[0083] like Figure 8 As shown, the platform provides a step-by-step guided interface in teaching experiments. After completing code writing, simulation and synthesis, students can download the bitstream and verify it on the board under the platform's instructions.

[0084] like Figure 9As shown, the platform supports Trace testing and on-board verification processes. Students can burn their custom RISC-V CPU code onto the FPGA and use the Trace tool to perform instruction-by-instruction functional verification and error localization, thereby comparing the CPU pipeline execution effect with theoretical expectations in actual operation.

[0085] The experiment consists of three stages:

[0086] (1) Basic stage: Students learn the SystemVerilog language and Vivado tool to complete combinational logic and sequential logic circuit design.

[0087] (2) CPU design stage: Students design and implement a complete single-cycle RISC-V CPU based on the RV32I instruction set, including arithmetic logic unit, register file, control unit and data path module, and verify its correctness through Trace test.

[0088] (3) Extension stage: Students extend the MiniRV experiment based on the single-cycle CPU to realize pipeline design, CSR register, exception interrupt handling and AXI interface control, and complete the comprehensive experiment through RT-Thread embedded operating system.

[0089] During operation, the platform employs a performance index evaluation mechanism. First, it measures interaction latency parameters to correct state synchronization accuracy. Second, it calculates resource utilization and combines this with student performance to assess course achievement. Then, it integrates course achievement with pipeline CPU performance improvement and quantifies processor efficiency through CoreMark performance testing. Simultaneously, the system monitors transmission error rate to correct the stability index and incorporates this index into the calculation of resource allocation efficiency. Finally, the system integrates latency, synchronization, resources, course achievement, performance optimization, performance scoring, and stability to form a performance index, which is then used to dynamically optimize FPGA resources under a scheduling algorithm.

[0090] In a real-world course experiment, with 70 users using the platform concurrently, the average interaction latency was less than 0.5 seconds, the state synchronization deviation was less than 2%, resource utilization was improved by more than 10% compared to traditional laboratories, and course achievement increased by approximately 15%. Both performance and stability indicators met teaching requirements. The experiment demonstrates that the platform maintains high efficiency even under multi-user concurrency conditions, validating the reliability and application value of the digital twin teaching experiment platform.

[0091] The contents not described in detail in this description are existing technologies known to those skilled in the art. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A digital twin integrated teaching and experimental platform for hardware courses, characterized in that, This includes client-side systems, remote control systems, data communication systems, and student experimental systems. The client presents a virtual interface that is highly consistent with the FPGA development board based on 3D modeling. Students can perform interactive operations on peripherals such as DIP switches, buttons, LEDs, and digital tubes on this interface. The remote control system is used to receive operation instructions from the client, convert them into control commands and send them to the FPGA. At the same time, it periodically acquires the FPGA's operating status and feeds it back to the client in real time, thereby enabling the virtual experiment to run synchronously with the physical hardware. The data communication system provides a communication channel based on a serial protocol; The student experimental system provides students with a unified interface environment, supports the writing, simulation and synthesis of hardware description languages ​​in EDA tools, and completes remote debugging and verification through bitstream download; The platform measures the interaction delay parameter during operation and uses this parameter as the basis for evaluating the performance of teaching experiments and for synchronous correction.

2. The digital twin integrated teaching and experimental platform for hardware courses according to claim 1, characterized in that, The interaction delay parameter is introduced into the state synchronization mechanism. The platform dynamically corrects the state consistency between the client virtual peripheral and the FPGA actual peripheral based on the delay magnitude. When the delay is small, high-precision synchronization is maintained, and when the delay is large, it is corrected through the error tolerance mechanism.

3. The digital twin integrated teaching experimental platform for hardware courses according to claim 2, characterized in that, The state synchronization result directly affects the resource utilization of the FPGA. The platform calculates the resource utilization efficiency by combining the number of logic units used in the student experiment with the state deviation. When the synchronization accuracy is insufficient, the platform will determine that the resource utilization rate has decreased, so as to reflect the impact of synchronization error on hardware resource efficiency.

4. The integrated digital twin teaching and experimental platform for hardware courses according to claim 3, characterized in that, The resource utilization efficiency is further incorporated into the teaching course achievement evaluation system. Based on the calculation of students' average experimental scores and course target values, the platform combines resource utilization rate to make weighted corrections to the achievement, thereby avoiding the sole criterion of scores and achieving a more comprehensive reflection of students' experimental results.

5. The digital twin integrated teaching experimental platform for hardware courses according to claim 4, characterized in that, Course achievement is incorporated into the performance optimization evaluation of pipelined CPU experiments. The platform compares the results of sequential execution and pipelined execution, and combines the course achievement to reflect the students' actual experimental contributions, thereby achieving an organic combination between students' experimental performance and performance optimization effects.

6. The digital twin integrated teaching experimental platform for hardware courses according to claim 5, characterized in that, The performance optimization results are further incorporated into the processor performance testing system. The platform scores the processors designed by students using the standardized CoreMark performance testing method and embeds the performance improvement effect as a weight into the scoring system, so that the performance test results not only meet industry standards, but also reflect the actual optimization level of students in the experimental process.

7. The digital twin integrated teaching experimental platform for hardware courses according to claim 6, characterized in that, The performance test results are further incorporated into the platform stability evaluation system. While calculating the transmission error rate, the platform also calculates a stability index based on the CoreMark score, which reflects the platform's reliability under long-term operation or large-scale testing conditions. The higher the stability index, the more stable the platform's performance during teaching experiments.

8. The digital twin integrated teaching experimental platform for hardware courses according to claim 7, characterized in that, The stability index is used to guide the allocation strategy of FPGA matrix resources. When the platform centrally manages multiple development boards, it dynamically allocates hardware resources based on the experimental stability results, giving priority to tasks with high stability and high experimental value, thereby improving the overall resource allocation efficiency and reducing operation and maintenance costs.

9. A digital twin integrated teaching experimental platform for hardware courses according to claim 8, characterized in that, The efficiency of resource allocation, interaction latency, state synchronization, resource utilization, course achievement, performance optimization results, performance test scores, and stability indicators work together to form an efficiency index. This efficiency index reflects the platform's overall performance in terms of latency, accuracy, resources, courses, and performance in multiple dimensions, and serves as the core evaluation indicator for subsequent optimization and scheduling.

10. A digital twin integrated teaching experimental platform for hardware courses according to claim 9, characterized in that, The efficiency index is used for intelligent resource scheduling optimization. With the goal of improving overall efficiency, the platform dynamically adjusts the experimental resource allocation strategy under the preset constraints of maximum latency, minimum resource utilization, and minimum stability, so as to achieve adaptive optimization of hardware courses.

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