Memory, operating method thereof and memory system
By dividing the array's common source into multiple independent sources in the memory and providing a higher source voltage for the non-selected memory string, the read interference problem of the non-selected memory cell in the read operation is solved, achieving lower read interference and higher operational flexibility.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECH CO LTD
- Filing Date
- 2024-10-23
- Publication Date
- 2026-04-24
AI Technical Summary
In existing memory, non-selected memory cells are susceptible to read interference during read operations, especially in 3D NAND memory arrays, where the problem becomes more pronounced as the number of layers increases.
By dividing the array common source of the memory block into multiple independent common sources and providing different source voltages to different common sources during read operations, especially providing higher source voltages to non-selected memory strings, the voltage difference between the channel and gate of non-selected memory cells can be reduced.
It effectively reduces read interference to non-selected memory strings, lowers the occurrence of read interference, and has a simple process, low cost, and is less prone to problems such as hot carrier injection.
Smart Images
Figure CN121922178A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of storage technology, and in particular to a memory and its operation method and storage system. Background Technology
[0002] When performing a read operation on a selected memory cell in the memory, a read voltage Vread can be applied to the select word line (WL) to which the selected memory cell is coupled, and an on-state voltage Vpass can be applied to the non-select word line.
[0003] Because the conduction voltage Vpass is relatively high, it can cause read disturbance to the memory cells connected to the non-select word lines. Summary of the Invention
[0004] This application provides a memory and its operation method, as well as a storage system, which can effectively reduce read interference caused by read operations on selected memory cells to non-selected memory cells. The technical solution is as follows:
[0005] In a first aspect, a memory is provided, the memory comprising: a memory block and peripheral circuitry, the memory block comprising: at least one first memory string, at least one second memory string, a first array common source, and a second array common source;
[0006] The at least one first storage string is connected to the common source of the first array, and the at least one second storage string is connected to the common source of the second array;
[0007] The peripheral circuit is connected to the first array common source and the second array common source respectively, and the peripheral circuit is configured to provide a first source voltage to the first array common source and a second source voltage to the second array common source when performing a read operation on the selected memory cell in the at least one first memory string;
[0008] The second source voltage is higher than the first source voltage.
[0009] Optionally, the storage block includes a first finger storage area and a second finger storage area;
[0010] The first storage area includes multiple first storage strings, and all multiple first storage strings are connected to the common source of the first array;
[0011] The second storage area includes multiple second storage strings, all of which are connected to the common source of the second array.
[0012] Optionally, the storage block includes a first storage string and a second storage string, and the number of storage strings connected to the common source of the first array is 1, and the number of storage strings connected to the common source of the second array is 1;
[0013] In this configuration, the multiple select tubes included in the first storage string are all SSL connected to the first string select line, and the multiple select tubes included in the second storage string are all connected to the second SSL.
[0014] Optionally, the storage block further includes a third storage string and a third array common source connected to the third storage string;
[0015] The number of storage strings connected to the common source of the third array is 1, and the multiple upper selection tubes included in the third storage string are all connected to the third SSL.
[0016] The peripheral circuit is further configured to provide a third source voltage to the common source of the third array when performing a read operation on a selected memory cell in the first memory string, the third source voltage being higher than the first source voltage.
[0017] Optionally, the peripheral circuit is further configured as follows:
[0018] When performing a read operation on a selected memory cell in the first memory string, a read voltage is applied to the selected word line coupled to the selected memory cell, and an on-state voltage is applied to the non-selected word lines other than the selected word line.
[0019] Wherein, the second source voltage is lower than the turn-on voltage.
[0020] Optionally, the peripheral circuit applies a read voltage to the select word line coupled to the select memory cell, including:
[0021] The peripheral circuit applies a first read voltage and a second read voltage to the select word line in sequence, wherein the second read voltage is higher than the first read voltage.
[0022] Optionally, the voltage difference between the second source voltage and the first source voltage is greater than or equal to 0.5V.
[0023] Optionally, the first source voltage is 0V.
[0024] Secondly, a method for operating a memory is provided, the method comprising:
[0025] The memory includes: a memory block, the memory block including: at least one first memory string, at least one second memory string, a first array common source, and a second array common source; wherein, the at least one first memory string is connected to the first array common source, and the at least one second memory string is connected to the second array common source; the method includes:
[0026] When performing a read operation on a selected memory cell in at least one first memory string, a first source voltage is provided to the common source of the first array;
[0027] A second source voltage is provided to the common source of the second array, the second source voltage being higher than the first source voltage.
[0028] Optionally, the method further includes:
[0029] When performing a read operation on a selected memory cell in the first memory string, a read voltage is applied to the selected word line coupled to the selected memory cell, and an on-state voltage is applied to the non-selected word lines other than the selected word line.
[0030] Wherein, the second source voltage is lower than the turn-on voltage.
[0031] Optionally, applying a read voltage to the select word line coupled to the select memory cell includes:
[0032] A first read voltage and a second read voltage are sequentially applied to the select word line, wherein the second read voltage is higher than the first read voltage.
[0033] Optionally, the voltage difference between the second source voltage and the first source voltage is greater than or equal to 0.5V.
[0034] Optionally, the first source voltage is 0V.
[0035] Thirdly, a storage system is provided, the storage system comprising: at least one memory as provided in the first aspect above, and a controller coupled to the at least one memory and configured to control the at least one memory.
[0036] The technical solution provided in this application can include at least the following beneficial effects:
[0037] This application provides a memory and its operation method, as well as a memory system. In the solution provided by this application, the memory includes a memory block and peripheral circuitry. The memory block includes a first array common source and a second array common source, and at least one first memory string in the memory block is connected to the first array common source, and at least one second memory string is connected to the second array common source. When performing a read operation on a selected memory cell in at least one first memory string, the second source voltage provided by the peripheral circuitry to the second array common source is higher than the first source voltage provided to the first array common source. Therefore, the voltage difference between the channel and gate of each memory cell in at least one second memory string can be effectively reduced, thereby reducing read interference caused by the read operation to at least one second memory string. Attached Figure Description
[0038] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0039] Figure 1 This is a schematic diagram of the structure of a memory provided in an embodiment of this application;
[0040] Figure 2 This is a schematic diagram of another memory structure provided in an embodiment of this application;
[0041] Figure 3 This is a cross-sectional schematic diagram of a storage array provided in an embodiment of this application;
[0042] Figure 4 This is a schematic diagram of another memory structure provided in an embodiment of this application;
[0043] Figure 5 This is a schematic diagram of another memory structure provided in an embodiment of this application;
[0044] Figure 6 This is a schematic diagram of another memory structure provided in an embodiment of this application;
[0045] Figure 7 This is a schematic diagram of a cross-sectional structure of a memory provided in an embodiment of this application;
[0046] Figure 8 This is a schematic diagram of another memory structure provided in an embodiment of this application;
[0047] Figure 9 This is a timing diagram of the driving voltage provided by the peripheral circuit to the memory block according to an embodiment of this application;
[0048] Figure 10 This is a flowchart of a memory operation method provided in an embodiment of this application;
[0049] Figure 11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;
[0050] Figure 12 This is a schematic diagram of the structure of a memory card provided in an embodiment of this application;
[0051] Figure 13 This is a schematic diagram of the structure of a solid-state driver provided in an embodiment of this application. Detailed Implementation
[0052] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.
[0053] Figure 1 This is a schematic diagram of a memory provided in an embodiment of this application. For example... Figure 1 As shown, the memory may include a storage array 110 and peripheral circuitry 120.
[0054] like Figure 1 and Figure 2 As shown, the storage array 110 includes multiple storage strings 111, and each storage string 111 includes multiple storage cell strings 1110. Each storage cell string 1110 includes multiple storage cells 114 connected in series between a bit line (BL) 112 and a source line 113. Figure 1 As shown, each memory cell string 1110 may further include a drain select gate (DSG) 115 located at the top and a source select gate (SSG) 116 located at the bottom. The drain select gate 115 is also called the top select gate (TSG) or drain select transistor. The source select gate 116 is also called the bottom select gate (BSG) or source select transistor. Figure 2As can be seen, the drain selection gate 115 of each storage string 111 comprising multiple storage cell strings 1110 is connected to the same string select line (SSL). That is, each storage string 111 comprising multiple storage cell strings 1110 is controlled by the same SSL. Furthermore, the source selection gate 116 of each storage string 111 comprising multiple storage cell strings 1110 in the storage block 130 is connected to the same ground select line (GSL). The SSL is also called the DSG line 117, and the GSL is also called the SSG line 118. The source selection gate 116 and the drain selection gate 115 can be configured to activate the selected storage string 111 during read and program operations.
[0055] like Figure 1 and Figure 2 As shown, the storage strings 111 can be organized into multiple storage blocks 130. For any one of the storage blocks 130, the storage block 130 typically has a source line (SL) 113, through which the sources of all storage strings 111 in the storage block 130 are coupled. This source line 113 is also called a common source line or array common source (ACS), meaning that each storage block 130 typically has one ACS.
[0056] The source line 113 can be used for grounding, so that the sources of each memory cell 114 of the memory string 111 in the memory block 130 can be grounded in some subsequent operations. Optionally, in some other operations, the sources of each memory cell 114 of the memory string 111 in the memory block 130 can also be connected to a high voltage through the source line 113.
[0057] Continue to refer to Figure 1 and Figure 2 In the same storage block 130, the same layer storage cells 114 of adjacent storage strings 111 can be coupled through word lines (WL) 119. Word lines 119 are used to select which layer storage cell 114 in the storage block 130 is affected by read and program operations.
[0058] The peripheral circuit 120 is coupled to bit line 112, source line 113 and word line 119, and is configured to perform the memory operation method provided in the embodiments of this application.
[0059] In this embodiment of the application, the storage array 110 may be a NAND flash memory storage array. For example... Figure 1 and Figure 2As shown, the NAND flash memory array includes multiple memory strings 111 arranged in an array on a substrate, with each memory string 111 extending vertically above the substrate (not shown). That is, each memory string 111 includes multiple serially coupled memory cells 114 stacked vertically above the substrate.
[0060] In some embodiments, the drain selection gate 115 of each memory string 111 is coupled to a corresponding bit line 112, and data can be read from or written to the bit line 112 via an output bus (not shown).
[0061] In some embodiments, each memory string 111 is configured to apply a selection voltage (e.g., higher than the threshold voltage of the transistor having the drain select gate 115) or a deselect voltage (e.g., 0V) to the corresponding drain select gate 115 via DSG line 117. And / or, in some embodiments, each memory string 111 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the source select gate 116) or a deselect voltage (e.g., 0V) to the corresponding source select gate 116 via SSG line 118.
[0062] Each memory block 130 is the basic data unit for the erase operation, meaning all memory cells 114 on the same memory block 130 are erased simultaneously. To erase memory cells 114 in a selected memory block 130, an erase voltage (Vers) (e.g., a high positive voltage (20V or higher)) can be biased and coupled to the source line 113 of the selected block. It should be understood that in other embodiments, the erase operation can be performed at the half-block level, at the quarter-block level, or at any suitable fractional level with any suitable number of blocks.
[0063] In some embodiments, each word line 119 is coupled to the page to which the memory cell 114 belongs, and a page is a basic unit of data used for programming operations. The size of a page may be related to the number of memory strings 111 coupled by word lines 119 in a memory block 130. Each word line 119 may be coupled to the control gate (i.e., gate electrode) of each memory cell 114 in the corresponding page. It is understood that a memory cell row is a plurality of memory cells 114 located on the same page.
[0064] Multiple word lines 119 are configured to perform operations such as programming (i.e., writing data), reading data, and erasing data on selected memory rows among multiple memory rows, the selected memory rows being the memory rows coupled to the selected word lines.
[0065] It is understandable that storage cells 114 at the same level in a storage block 130 correspond to the same word line 119, but storage cells 114 at the same level can be divided into one or more pages. That is, a word line 119 can couple one or more pages. For example, for a single-level cell (SLC), a word line 119 couples to one page, and for a triple-level cell (TLC), a word line 119 couples to three pages.
[0066] Figure 3 This is a cross-sectional schematic diagram of a storage array 110 including a string of storage cells 1110, provided in an embodiment of this application. Figure 3 As shown, the memory cell string 1110 can extend vertically over the substrate 101 and through the stacked layer 102. The substrate 101 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.
[0067] The stacked layer 102 may include alternating gate conductive layers 103 and gate-to-gate dielectric layers 104. The number of pairs of gate conductive layers 103 and gate-to-gate dielectric layers 104 in the stacked layer 102 can determine the number of memory cells 114 in the memory array 110.
[0068] The gate conductive layer 103 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 103 includes a metal layer, such as a tungsten layer. In other embodiments, each gate conductive layer 103 includes a doped polysilicon layer. Furthermore, each gate conductive layer 103 may include a control gate surrounding the memory cell 114, and may extend laterally at the top of the stacked layer 102 as a DSG line 117, at the bottom of the stacked layer 102 as an SSG line 118, or between the DSG line 117 and the SSG line 118 as a word line 119.
[0069] like Figure 3 As shown, the memory cell string 1110 includes a channel structure 105 extending vertically through the stacked layer 102. In some embodiments, the channel structure 105 includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). The semiconductor channel includes silicon, such as polycrystalline silicon. The memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer.
[0070] In some embodiments, the channel structure 105 has a cylindrical shape (e.g., a pillar shape). The layers in the semiconductor channel and the memory film are arranged radially from the center of the cylinder toward the outer surface of the cylinder in this order.
[0071] It should be understood that, despite Figure 3 As not shown, the memory array 110 may also include other additional components, including but not limited to gate line gaps / source contacts, local contacts, interconnect layers, etc.
[0072] Return to reference Figure 1 The peripheral circuitry 120 can be coupled to the memory array 110 via bit line 112, word line 119, source line 113, SSG line 118, and DSG line 117. The peripheral circuitry 120 may include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory array 110 by applying voltage and / or current signals to and sensing voltage and / or current signals from the memory cells 114 via bit line 112, word line 119, source line 113, SSG line 118, and DSG line 117.
[0073] Peripheral circuitry 120 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 4 Some exemplary peripheral circuitry 120 is shown, including a page buffer / sensor amplifier 121, a column decoder / bit line (BL) driver 122, a row decoder / WL driver 123, a voltage generator 124, a control logic unit 125, a register 126, an interface 127, and a data bus 128. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 4 Additional peripheral circuitry not shown.
[0074] Page buffer / sensor amplifier 121 can be configured to read data from and program (write) data to memory array 110 based on control signals from control logic unit 125. For example, page buffer / sensor amplifier 121 can store a page of programming data (write data) to be programmed into a page 120 of memory array 110. Page buffer / sensor amplifier 121 can also perform a verification operation to ensure that data has been correctly programmed into memory cell 114 coupled to selected word line 119. Page buffer / sensor amplifier 121 can also sense a low-power signal from bit line 112, which represents a data bit stored in memory cell 114, and amplify a small voltage swing to a recognizable logic level during read operations.
[0075] The column decoder / bit line driver 122 can be configured to be controlled by the control logic unit 125 and to select one or more memory cell strings 1110 by applying a bit line voltage generated from the voltage generator 124.
[0076] The row decoder / word line driver 123 can be configured to be controlled by the control logic unit 125 and to select / deselect block 120 of the memory array 110 and to select / deselect word lines 119 of block 120. The row decoder / word line driver 123 can also be configured to drive word lines 119 using word line voltages (VWL) generated from the voltage generator 124. In some embodiments, the row decoder / word line driver 123 can also select / deselect and drive SSG lines 118 and DSG lines 117. Furthermore, the row decoder / word line driver 123 can also be configured to perform erase operations on memory cells 114 coupled to one or more selected word lines 119.
[0077] Voltage generator 124 can be configured to be controlled by control logic unit 125 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 110.
[0078] The control logic unit 125 can be coupled to various circuits in the peripheral circuit 120 described above, and is configured to control the operation of each circuit.
[0079] Register 126 can be coupled to control logic unit 125. The register may include a status register, a command register, and an address register to store status information, command opcodes (OP codes), and command addresses for controlling the operation of each circuit in peripheral circuit 120.
[0080] Interface (I / F) 127 can be coupled to control logic unit 125 and act as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 125, as well as to buffer status information received from control logic unit 125 and relay it to the host. Interface 127 can also be coupled to column decoder / bit line driver 122 via data bus 128 and act as a data I / O interface and data buffer to buffer data and relay it to or from memory array 110.
[0081] When performing a data read operation on the selected memory cell 114 in the memory array 110, the peripheral circuit 120 needs to apply a read voltage Vread to the select word line 119 coupled to the selected memory cell 114, and apply an on-state voltage Vpass to other non-select word lines 119. Furthermore, for the selected memory string 111 where the selected memory cell 114 is located, the peripheral circuit 120 can apply a read voltage Vread to the select SSL (i.e., ...) connected to the selected memory string 111. Figure 2 The peripheral circuit 120 applies a conduction voltage Vpass to the non-selection SSL (i.e., sel.SSL) in the non-selection memory string 111 to enable the drain selection gate 115 in the non-selection memory string 111. Furthermore, the peripheral circuit 120 can supply power to the non-selection SSL (i.e., sel.SSL) connected to the non-selection memory string 111. Figure 2 The external circuit 120 applies a shutdown voltage to the unsel.SSL) to turn off the drain select gate 115 in the non-selected memory string 111. Furthermore, the external circuit 120 can apply a conduction voltage Vpass to the SSG line 118 connected to the source select gate 115 in each memory string 111 to turn on the source select gate 115 in each memory string 111. For example... Figure 5 As shown, the source selection gate 115 (i.e., BSG) of each memory string 111 in a single memory block 130 is usually connected to the same ACS, and the ACS is applied with a low voltage VSS (e.g., 0V), so the channel voltage of the non-selected memory string 111 will remain low.
[0082] Because the aforementioned turn-on voltage Vpass is relatively high, it leads to a high voltage difference between the channel and gate of the non-selected memory cell 114 in the non-selected memory string 111, thereby causing read interference to the non-selected memory cell 114. With the development of 3D NAND, the number of layers in the memory array 110 gradually increases, resulting in a gradual increase in the number of turn-on voltage Vpass cycles experienced by a single word line 119. Correspondingly, the read interference of the non-selected memory cell 114 also gradually increases.
[0083] In some embodiments, read interference can be improved by adjusting the thickness and / or material of the gate stack of the memory array 110. However, this approach requires balancing device durability and has significant limitations.
[0084] In other embodiments, the source select gate 116 in memory block 130 can be diced (i.e., the GSL / SSG line 118 can be diced) so that the source select gate 116 in different memory strings 111 can be controlled independently. Accordingly, when performing a data read operation on the selected memory cell 114 in memory array 110, the peripheral circuit 120 can apply a turn-off voltage to the SSG line 118 connected to the source select gate 116 in the non-selected memory string 111 to turn off the source select gate 116 in the non-selected memory string 111. Since both the drain select gate 115 and the source select gate 116 in the non-selected memory string 111 are turned off, the channel potential of the non-selected memory string 111 is increased by coupling with the word line 119. As a result, the voltage difference between the channel and gate of the non-selected memory cell 114 can be reduced, thereby reducing read interference.
[0085] However, the process of cutting the source selection gate 116 described above is relatively complex and costly. Furthermore, since the channel potential of the non-selection memory string 111 in this scheme is coupled by the word line 119, and the voltage of different word lines 119 may be different, abnormal channel potential may occur, leading to problems such as hot carrier injection (HCI).
[0086] This application provides a memory. For example... Figure 1 As shown, the memory provided in this embodiment includes: a storage block 130 and peripheral circuitry 120. For example... Figure 2 and Figure 6 As shown, the storage block 130 includes: at least one first storage string STR1, at least one second storage string STR2, a first array common source ACS1, and a second array common source ACS2. At least one first storage string STR1 is connected to the first array common source ACS1, and at least one second storage string STR2 is connected to the second array common source ACS2.
[0087] The peripheral circuit 120 is connected to the first array common source ACS1 and the second array common source ACS2, respectively. Furthermore, the peripheral circuit 120 is configured to provide a first source voltage VSS to the first array common source ACS1 and a second source voltage Vbias1 to the second array common source ACS2 when performing a read operation on at least one selected memory cell in the first memory string STR1. The second source voltage Vbias1 is higher than the first source voltage VSS.
[0088] contrast Figure 5 and Figure 6As can be seen, in the solution provided by this application embodiment, the ACS in the memory block 130 is at least divided into a first array common source ACS1 and a second array common source ACS2. Furthermore, different memory strings in the memory block 130 can be connected to different ACS. Correspondingly, the peripheral circuit 120 can provide different source voltages to different ACS, thereby effectively improving the flexibility of memory operation. Here, the ACS can also be called a high-voltage N-well (HVNW).
[0089] Specifically, when performing a read operation on a selected memory cell in at least one first memory string STR1, the first source voltage VSS provided by the peripheral circuit 120 to the first array common source ACS1 can be a low voltage, for example, 0V. Furthermore, for the second array common source ACS2 connected to at least one second memory string STR2, the second source voltage Vbias1 provided by the peripheral circuit 120 can be relatively high, for example, 0.5V. Since at least one second memory string STR2 is a non-selected memory string, by providing a higher second source voltage Vbias1 to the source of the at least one second memory string STR2, the channel voltage of the at least one second memory string STR2 can be increased. Correspondingly, the voltage difference between the channel and gate of the non-selected memory cells in the at least one second memory string STR2 can be effectively reduced, thereby effectively reducing read interference to the non-selected memory cells.
[0090] As the first optional implementation method, such as Figure 6 and Figure 7 As shown, the storage block 130 may include a first pointer storage area F1 and a second pointer storage area F2. The first pointer storage area F1 includes multiple first storage strings STR1, and each of these first storage strings STR1 is connected to the common source of the first array ACS1. The second pointer storage area F2 includes multiple second storage strings STR2, and each of these second storage strings STR2 is connected to the common source of the second array ACS2. For example, as... Figure 6 As shown, the first memory area F1 may include two first memory strings STR1, and the second memory area F2 may include two second memory strings STR2.
[0091] Understandably, in this first implementation, the ACS in storage block 130 can be segmented at the finger storage area level. That is, storage block 130 can include multiple finger storage areas and multiple ACS corresponding one-to-one with the multiple finger storage areas. Each finger storage area includes multiple storage strings, each connected to a corresponding ACS.
[0092] It is also understandable that Figure 7This is a schematic diagram of the cross-section of the memory. This cross-section is a plane parallel to the substrate 101. From... Figure 7 As can be seen, the memory block 130 may also include multiple gate isolation structures, which can divide the memory block 130 into multiple pointer memory regions. (Continue to refer to...) Figure 7 The number of memory regions included in the memory block 130 can be greater than two. For example, Figure 7 The storage block 130 may further include a third finger storage area F3, and correspondingly, the storage block 130 may also include a third array common source ACS3 connected to the third finger storage area F3. When performing a read operation on at least one selected storage cell in the first storage string STR1, the peripheral circuit 120 can provide a third source voltage Vbias2 to the third array common source ACS3. The third source voltage Vbias2 is higher than the first source voltage VSS. Furthermore, the third source voltage Vbias2 may be equal to or unequal to the second source voltage Vbias1; this embodiment does not limit this.
[0093] As a second optional implementation, such as Figure 8 As shown, storage block 130 may include a first storage string STR1 and a second storage string STR2. Furthermore, the first array common source ACS1 is connected to one storage string, and the second array common source ACS2 is connected to one storage string. The first storage string STR1 includes multiple selectors (TSGs) that are all connected to a first SSL, and the second storage string STR2 includes multiple selectors (TSGs) that are all connected to a second SSL. For example, refer to... Figure 2 The first SSL connected to the first storage string STR1 can be Figure 2 In the sel.SSL, the second SSL connected to the second storage string STR2 can be... Figure 2 The unsel.SSL in the middle.
[0094] Understandably, in this second implementation, the ACS in storage block 130 can be segmented at the granularity of storage string 111. That is, storage block 130 can include multiple storage strings 111, and multiple ACS corresponding one-to-one with the multiple storage strings 111, with each storage string 111 connected to a corresponding ACS.
[0095] Continue to refer to Figure 8 The number of storage strings included in the storage block 130 can be greater than 2. For example, Figure 8The storage block 130 may also include a third storage string STR3, and correspondingly, the storage block 130 may also include a third array common source ACS3 connected to the third storage string STR3. Furthermore, the number of storage strings connected to the third array common source ACS3 is also 1, and the multiple upselect transistors included in the third storage string STR3 are all connected to the third SSL.
[0096] The peripheral circuit 120 is further configured to provide a third source voltage Vbias2 to the third array common source ACS3 when performing a read operation on a selected memory cell in the first memory string STR1. This third source voltage Vbias2 is higher than the first source voltage VSS. Furthermore, the third source voltage Vbias2 may be equal to or unequal to the second source voltage Vbias1; this embodiment does not limit this.
[0097] Optionally, such as Figure 8 As shown, storage block 130 may further include a fourth storage string STR4, and correspondingly, storage block 130 may further include a fourth array common source ACS4 connected to the fourth storage string STR4. Furthermore, the number of storage strings connected to the fourth array common source ACS4 is also 1, and the multiple upselect transistors included in the fourth storage string STR4 are all connected to the fourth SSL.
[0098] The peripheral circuit 120 is further configured to provide a fourth source voltage Vbias3 to the fourth array common source ACS4 when performing a read operation on a selected memory cell in the first memory string STR1. This fourth source voltage Vbias3 is higher than the first source voltage VSS. Furthermore, the fourth source voltage Vbias3 may be equal to or unequal to the second source voltage Vbias1; this embodiment does not limit this.
[0099] Based on the above analysis, it can be seen that for each memory string 111 in memory block 130, there is an independent ACS connected to it. When performing a read operation on the selected memory cell in the first memory string STR1, the peripheral circuit 120 can apply a relatively high source voltage (also called bias voltage Vbias) to the ACS connected to other memory strings. Furthermore, the source voltages applied by the peripheral circuit 120 to the ACS connected to other memory strings can be equal or unequal. For example, to reduce the complexity of the drive, the source voltages applied by the peripheral circuit 120 to the ACS connected to other memory strings can be equal, such as all being 0.5V.
[0100] The above provides two methods for partitioning (i.e., cutting) the ACS in storage block 130. It is understood that the ACS can also be partitioned in other ways. For example, the ACS in storage block 130 can be divided into n array common sources, where n is greater than or equal to 2 and less than the number of finger storage areas included in storage block 130. Each array common source can be connected to one or more finger storage areas in storage block 130, and the number of finger storage areas connected to different array common sources can be equal or unequal. For example, assuming n = 2, the first array common source ACS1 can be connected to the finger storage area with odd index in storage block 130, and the second array common source ACS2 can be connected to the finger storage area with even index in storage block 130.
[0101] Alternatively, n is greater than or equal to 2 and less than the number of storage strings 111 included in storage block 130. Each array common source can be connected to one or more storage strings 111 in storage block 130, and the number of storage strings 111 connected to different array common sources can be equal or unequal. For example, assuming n = 2, the first array common source ACS1 can be connected to the storage string 111 with an odd index in storage block 130, and the second array common source ACS2 can be connected to the storage string 111 with an even index in storage block 130.
[0102] Optionally, Figure 9 This is a timing diagram of the driving voltage provided by a peripheral circuit to a memory block, according to an embodiment of this application. (Reference) Figure 9 The peripheral circuit 120 can also be configured to: when performing a read operation on a selected memory cell in the first memory string STR1, apply a read voltage Vread to the selected word line coupled to the selected memory cell, and apply a conduction voltage Vpass to the non-selected word lines other than the selected word line. The second source voltage Vbias1 is lower than the conduction voltage Vpass.
[0103] It is understandable that, in the scenario where the storage block 130 also includes a third array common source ACS3, or even a fourth array common source ACS4 or more other array common sources, the source voltage applied by the peripheral circuit 120 to the other array common sources besides the first array common source ACS1 is lower than the turn-on voltage Vpass.
[0104] For example, assuming the conduction voltage Vpass ranges from 5V to 10V, the source voltage applied by the peripheral circuit 120 to the common source of other arrays besides the first array common source ACS1 can be lower than 5V.
[0105] Optionally, to ensure a small voltage difference between the channel and gate of the non-selected memory cell, the voltage difference between the second source voltage Vbias1 and the first source voltage VSS can be greater than or equal to 0.5V. Similarly, the voltage difference between the third source voltage Vbias2 and the first source voltage VSS, and the voltage difference between the fourth source voltage Vbias3 and the first source voltage VSS, can also be greater than or equal to 0.5V.
[0106] For example, assuming the first source voltage VSS is 0V, the second source voltage Vbias1 can be greater than or equal to 0.5V. Similarly, the third source voltage Vbias2 and the fourth source voltage Vbias3 can also be greater than or equal to 0.5V.
[0107] Optionally, continue to refer to Figure 9 The process by which the peripheral circuit 120 applies a read voltage Vread to the select word line coupled to the selected memory cell may include: the peripheral circuit 120 sequentially applying a first read voltage Vrd1 and a second read voltage Vrd2 to the select word line. The second read voltage Vrd2 may be higher than the first read voltage Vrd1.
[0108] It is understood that the first read voltage Vrd1 and the second read voltage Vrd2 can correspond to different programming states of the memory cell. By applying multiple different read voltages to the select word line, reading different programming states in the memory cell can be achieved. It is also understood that the peripheral circuit 120 can apply a third read voltage Vrd3 to the select word line, which can be higher than the second read voltage Vrd2. Therefore, reading more programming states can be achieved. This application embodiment does not limit the number of read voltages applied by the peripheral circuit 120 to the select word line during the read phase.
[0109] It is also understandable that the read voltage Vread (such as the first read voltage Vrd1 and the second read voltage Vrd2) applied to the select word line by the peripheral circuit 120 during the read phase can be lower than the turn-on voltage Vpass applied to the non-select word line.
[0110] In summary, this application provides a memory whose memory blocks include a first array common source connected to at least one first memory string and a second array common source connected to at least one second memory string. When performing a read operation on a selected memory cell in at least one first memory string, the first source voltage provided by the peripheral circuit to the first array common source is relatively low, and the second source voltage provided to the second array common source is relatively high. Since at least one second memory string is a non-selected memory string, by providing a higher second source voltage to the source of the at least one second memory string, the channel voltage of the at least one second memory string can be effectively increased. Correspondingly, the voltage difference between the channel and gate of the non-selected memory cells in the at least one second memory string can be effectively reduced, thereby effectively reducing read interference to the non-selected memory cells.
[0111] Furthermore, the solution provided in this application embodiment involves dicing the array common source in the memory block. Compared to dicing the source selection gate 116 in the memory block, dicing the array common source is simpler and less costly. Moreover, compared to the solution of dicing the source selection gate 116 in the memory block, the solution provided in this application embodiment does not need to consider problems such as HCI caused by abnormal channel potential, and its adjustability and expected benefits are higher. Compared to the solution of adjusting the gate stack layer, the solution provided in this application embodiment is more flexible and has fewer limitations. Of course, the solution provided in this application embodiment can also be combined with the solution of adjusting the gate stack layer to further improve the read interference problem.
[0112] Figure 10 This is a flowchart illustrating a memory operation method provided in an embodiment of this application. This operation method can be applied to the memory provided in the above embodiment, and the method can be executed by peripheral circuitry within the memory. As described above, the memory block includes: at least one first memory string, at least one second memory string, a first array common source, and a second array common source. At least one first memory string is connected to the first array common source, and at least one second memory string is connected to the second array common source. Figure 10 As shown, the operation method of this memory includes:
[0113] Step S1: When performing a read operation on a selected memory cell in at least one first memory string, a first source voltage is provided to the common source of the first array.
[0114] Step S2: Provide a second source voltage to the common source of the second array. The second source voltage is higher than the first source voltage.
[0115] Optionally, the first source voltage VSS can be 0V. The voltage difference between the second source voltage Vbias1 and the first source voltage VSS can be greater than or equal to 0.5V.
[0116] As mentioned above, the memory may also include a greater number of array common sources, such as a third array common source and a fourth array common source. Correspondingly, in step S2 above, the peripheral circuit, in addition to providing a second source voltage to the second array common source, can also provide a corresponding source voltage to each of the other array common sources besides the first and second array common sources. Furthermore, the source voltage provided by the peripheral circuit to each of the other array common sources is higher than the first source voltage.
[0117] It is understandable that steps S2 and S1 can be executed synchronously, meaning that the peripheral circuit can simultaneously provide the corresponding source voltage to the common source of each array.
[0118] Optionally, the method may further include:
[0119] Step S3: When performing a read operation on the selected memory cell in the first memory string, a read voltage is applied to the select word line coupled to the selected memory cell, and an on-state voltage is applied to the non-select word lines other than the select word line. The second source voltage is lower than the on-state voltage.
[0120] As mentioned above, the memory may also include a greater number of array common sources, such as a third array common source and a fourth array common source. Accordingly, in step S2 above, the source voltage provided by the peripheral circuit to each array common source other than the second array common source is also lower than the turn-on voltage Vpass.
[0121] For example, the voltage range of the turn-on voltage Vpass can be 5V to 10V, the first source voltage VSS provided by the external circuit to the first array common source can be 0V, and the voltage range of the source voltage provided to other array common sources (such as the second array common source) can be 0.5V to 5V, for example, all of them can be 0.5V.
[0122] Optionally, such as Figure 9 As shown, the process of applying a read voltage to the select word line coupled to the selected memory cell in step S3 above may include: applying a first read voltage Vrd1 and a second read voltage Vrd2 to the select word line in sequence, wherein the second read voltage Vrd2 is higher than the first read voltage Vrd1.
[0123] It is understood that the first read voltage Vrd1 and the second read voltage Vrd2 can correspond to different programming states of the memory cell. By applying multiple different read voltages to the select word line, different programming states of the memory cell can be read. Furthermore, both the first read voltage Vrd1 and the second read voltage Vrd2 can be lower than the turn-on voltage Vpass.
[0124] Optionally, continue to refer to Figure 9 When performing a read operation on the selected memory cell in the first memory string, the peripheral circuit can also provide a turn-on voltage Vpass to the bit line, the TSG in the selected memory string and the BSG in each memory string, and provide a turn-off voltage to the TSG in the non-selected memory string.
[0125] In summary, this application provides a method for operating a memory, wherein a memory block includes a first array common source connected to at least one first memory string and a second array common source connected to at least one second memory string. In this method, when performing a read operation on a selected memory cell in at least one first memory string, the first source voltage provided to the first array common source is relatively low, and the second source voltage provided to the second array common source is relatively high. Since at least one second memory string is a non-selected memory string, by providing a higher second source voltage to the source of the at least one second memory string, the channel voltage of the at least one second memory string can be effectively increased. Correspondingly, the voltage difference between the channel and gate of the non-selected memory cells in the at least one second memory string can be effectively reduced, thereby effectively reducing read interference to the non-selected memory cells.
[0126] It is understood that the description of the above-described memory operation method embodiments has similar beneficial effects to the above-described memory embodiments. Furthermore, for any technical details not disclosed in the memory operation method embodiments, please refer to the description of the above-described memory embodiments for clarification.
[0127] This application also provides a storage system, such as... Figure 11 As shown, the storage system 10 includes: a controller 200, and at least one memory 100 as provided in the above embodiments, the controller 200 being coupled to the at least one memory 100 and configured to control the at least one memory 100.
[0128] Example, Figure 11 The diagram illustrates multiple memories 100. Each memory 100 can be a three-dimensional (3D) memory, such as a 3D NAND flash memory. Each memory 100 can include at least one storage plane, each storage plane includes multiple storage blocks, and each storage block includes multiple storage pages. A controller 200 is connected to both the memory 100 and the host 20. The controller 200 manages the data stored in the memory 100 and communicates with the host 20.
[0129] In this embodiment, the controller 200 can be configured to control operations performed by the memory 100, such as read, erase, and program operations. The controller 200 can also be configured to manage various functions related to data stored or to be stored in the memory 100, including but not limited to bad block management, garbage collection (GC), logical address to physical address translation, and wear leveling. Optionally, the controller 200 can also be configured to process error correcting codes (ECC) for data read from or written to the memory 100. The controller 200 can also perform any other suitable functions, such as formatting the memory 100.
[0130] The controller 200 can also communicate with external devices according to specific communication protocols. For example, the controller 200 can communicate with external devices through at least one of various interface protocols. Interface protocols may include Universal Serial Bus (USB) protocol, Multi-Media Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-E protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Drive Interface (ESDI) protocol, Integrated Development Environment (IDE) protocol, and FireWire protocol, etc.
[0131] In some embodiments, the controller 200 and one or more memories 100 may be integrated into various types of storage devices.
[0132] As an example, such as Figure 12As shown, the controller 200 and a single memory 100 can be integrated into the memory card 300. The memory card 300 may include PCMCIA cards, compact flash (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC), secure digital (SD) cards, and universal flash storage (UFS), etc. Figure 12 As shown, the memory card 300 may also include a connector 310 for coupling with the host 20.
[0133] As another example, such as Figure 13 As shown, the controller 200 and multiple memories 100 can be integrated into a solid-state disk (SSD) 400. The SSD 400 may also include a connector 410 for coupling with the host 20. The storage capacity and / or operating speed of the SSD 400 is greater than that of the memory card 300.
[0134] also, Figures 11 to 13 The memory 100 in this application can be any memory involved in the embodiments of this application. For example, it can be a 3D NAND (NAND gate) memory. The solution provided in the embodiments of this application can be applied to electronic devices. The electronic device can be a mobile terminal, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein.
[0135] This application also provides an electronic device, such as... Figure 11 As shown, the electronic device may include a storage system 10 as provided in the above embodiments, and a host 20. The host 20 may be a central processing unit (CPU) or a system-on-chip (SOC) of the electronic device. The host 20 is used to send data to the storage system 10 for storage, or to read data from the storage system 10.
[0136] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" means one or more, and the term "multiple" means two or more, unless otherwise expressly defined.
[0137] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. The scope of protection of this application should be determined by the scope of the claims.
Claims
1. A memory, characterized in that, The memory includes: a memory block and peripheral circuitry. The memory block includes: at least one first memory string, at least one second memory string, a first array common source, and a second array common source. The at least one first storage string is connected to the common source of the first array, and the at least one second storage string is connected to the common source of the second array; The peripheral circuit is connected to the first array common source and the second array common source respectively, and the peripheral circuit is configured to provide a first source voltage to the first array common source and a second source voltage to the second array common source when performing a read operation on the selected memory cell in the at least one first memory string; The second source voltage is higher than the first source voltage.
2. The memory according to claim 1, characterized in that, The storage block includes a first finger storage area and a second finger storage area; The first storage area includes multiple first storage strings, and all multiple first storage strings are connected to the common source of the first array; The second storage area includes multiple second storage strings, all of which are connected to the common source of the second array.
3. The memory according to claim 1, characterized in that, The storage block includes a first storage string and a second storage string, and the number of storage strings connected to the common source of the first array is 1, and the number of storage strings connected to the common source of the second array is 1. In this configuration, the multiple select tubes included in the first storage string are all SSL connected to the first string select line, and the multiple select tubes included in the second storage string are all connected to the second SSL.
4. The memory according to claim 3, characterized in that, The storage block also includes a third storage string and a third array common source connected to the third storage string; The number of storage strings connected to the common source of the third array is 1, and the multiple upper selection tubes included in the third storage string are all connected to the third SSL. The peripheral circuit is further configured to provide a third source voltage to the common source of the third array when performing a read operation on a selected memory cell in the first memory string, the third source voltage being higher than the first source voltage.
5. The memory according to any one of claims 1 to 4, characterized in that, The peripheral circuit is also configured to: When performing a read operation on a selected memory cell in the first memory string, a read voltage is applied to the selected word line coupled to the selected memory cell, and an on-state voltage is applied to the non-selected word lines other than the selected word line. Wherein, the second source voltage is lower than the turn-on voltage.
6. The memory according to claim 5, characterized in that, The peripheral circuit applies a read voltage to the select word line coupled to the select memory cell, including: The peripheral circuit applies a first read voltage and a second read voltage to the select word line in sequence, wherein the second read voltage is higher than the first read voltage.
7. The memory according to any one of claims 1 to 4, characterized in that, The voltage difference between the second source voltage and the first source voltage is greater than or equal to 0.5V.
8. The memory according to any one of claims 1 to 4, characterized in that, The first source voltage is 0V.
9. A method for operating a memory, characterized in that, The memory includes: a memory block, the memory block including: at least one first memory string, at least one second memory string, a first array common source, and a second array common source; wherein, the at least one first memory string is connected to the first array common source, and the at least one second memory string is connected to the second array common source; the method includes: When performing a read operation on a selected memory cell in at least one first memory string, a first source voltage is provided to the common source of the first array; A second source voltage is provided to the common source of the second array, the second source voltage being higher than the first source voltage.
10. The method according to claim 9, characterized in that, The method further includes: When performing a read operation on a selected memory cell in the first memory string, a read voltage is applied to the selected word line coupled to the selected memory cell, and an on-state voltage is applied to the non-selected word lines other than the selected word line. Wherein, the second source voltage is lower than the turn-on voltage.
11. The method according to claim 10, characterized in that, Applying a read voltage to the select word line coupled to the select memory cell includes: A first read voltage and a second read voltage are sequentially applied to the select word line, wherein the second read voltage is higher than the first read voltage.
12. The method according to any one of claims 9 to 11, characterized in that, The voltage difference between the second source voltage and the first source voltage is greater than or equal to 0.5V.
13. The method according to any one of claims 9 to 11, characterized in that, The first source voltage is 0V.
14. A storage system, characterized in that, The storage system includes: a controller, and at least one memory as described in any one of claims 1 to 8, the controller being coupled to the memory and configured to control the memory.