Double-transistor flyback circuit control method, circuit and chip

Abstract

The invention discloses a double-transistor flyback circuit control method, circuit and chip, and the method comprises the steps: a drive controller detects whether a drive power supply of a first switching tube needs to be forcibly charged, if yes, a second pin is controlled to output a high level, and if not, a second pin is controlled to output a high level; the second pin is controlled to charge a driving power supply of the first switch tube through a power supply connected with the third pin, after charging is completed, the second pin is controlled to output a low level, otherwise, the second pin and the first pin are controlled to output a high level at the same time, so that the second switch tube and the first switch tube are turned on at the same time; when a signal for turning off the switching tube is detected, the first pin is controlled to output a low level to turn off the first switching tube, and the second pin is controlled to output a low level to turn off the second switching tube after waiting for a first preset time.

Description

Technical Field

[0001] This invention relates to the field of converter technology, specifically to a dual-transistor flyback circuit control method, circuit, and chip. Background Technology

[0002] The flyback circuit is a high-efficiency, compact switching power supply topology widely used in consumer electronics (such as chargers and home appliances), communication equipment (such as routers and base stations), industrial control, medical equipment, and LED lighting. It is also used in solar chargers, automotive electronics, and building automation, and is particularly suitable for small to medium power supply needs due to its simple structure, low cost, high efficiency, and small size.

[0003] Figure 1 This is a common single-transistor flyback circuit schematic. Its operation is divided into two stages: switch Q closed and switch Q open. During the closed stage, the primary coil of transformer T is connected to the input voltage Vin. The current in the primary coil and the magnetic field in the transformer core increase, storing energy in the core. The voltage generated in the secondary coil is reverse-biased, causing diode D to be reverse-biased and unable to conduct. At this time, capacitor C0 provides voltage and current to the load RL. During the open stage, the current in the primary coil is zero, and the magnetic field in the core begins to decrease, inducing a forward voltage in the secondary coil. Diode D is now forward-biased, and the conducting current flows into capacitor C0 and the load RL. The energy stored in the core is transferred to capacitor C0 and the load RL. The single-transistor flyback circuit is simple, compact, and low-cost.

[0004] Figure 2 This is a schematic diagram of a common two-transistor flyback circuit. The two-transistor flyback circuit uses two switching transistors, Q1 and Q2, to more effectively control the output voltage and current by turning the two switching transistors on and off.

[0005] Compared to the traditional single-transistor flyback circuit, the dual-transistor flyback circuit has the following advantages:

[0006] High-efficiency recovery of leakage inductance energy—the dual-transistor flyback diode feeds leakage inductance energy back to the input power supply. V in This avoids the problem of leakage inductance energy being consumed by the clamping resistor in a single-tube flyback circuit, thus significantly improving system efficiency.

[0007] Reduce voltage stress on the switching transistor – the voltage across the switching transistor is clamped at the input voltage level, eliminating the need for additional snubber circuitry.

[0008] High reliability design – the leakage inductance energy recovery path reduces voltage spikes, while the dual-tube structure reduces voltage stress on individual devices, making it particularly suitable for high-voltage input scenarios.

[0009] However, compared to a single-transistor flyback circuit, a dual-transistor flyback circuit requires an additional switching transistor and a corresponding driver circuit. For example... Figure 2 As shown, the source terminal of the upper transistor Q1 is not on the system's GND; it is a floating-ground drive. Therefore, the drive circuit for the upper transistor Q1 requires special handling. Currently, two main technical solutions are used: Solution 1, as... Figure 3 As shown, the auxiliary power supply VCC bootstrap and the addition of an extra winding on the transformer provide power for the upper transistor drive. The upper transistor power supply pin BST of the drive controller U1 is charged through the chip power supply VCC and the auxiliary winding power supply VA. SW is the floating ground pin of the upper transistor, and GH is the upper transistor drive pin. Scheme two, as shown... Figure 4 As shown, by adding an external isolation power supply, the same purpose as Scheme 1 can be achieved. When GH / GL are turned on at the same time, the dual-tube flyback transformer is energized. When GH / GL are turned off at the same time, the dual-tube flyback transformer is demagnetized. At this time, the transformer transfers energy to the secondary side.

[0010] Adding an auxiliary winding in Scheme 1 or adding an external isolation power supply in Scheme 2 both increase the complexity of the two-transistor flyback circuit implementation. Therefore, a solution is needed that simplifies the overall design and better leverages the advantages of the two-transistor flyback circuit. Summary of the Invention

[0011] Based on the above situation, the main objective of this invention is to provide a control method, circuit, and chip for a dual-transistor flyback circuit that features a simple control strategy, reduces the complexity of circuit system design, and enhances the application flexibility of the dual-transistor flyback circuit.

[0012] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A control method for a dual-transistor flyback circuit, wherein the dual-transistor flyback circuit includes a drive controller, a first switching transistor, and a second switching transistor. A first pin of the drive controller is connected to the first switching transistor, a second pin of the drive controller is connected to the second switching transistor, a third pin of the drive controller is connected to a power supply via a compensation diode, a fourth pin of the drive controller is connected to the first switching transistor and serves as a floating ground for the first switching transistor, a fourth pin of the drive controller is grounded via a first diode, and a bootstrap capacitor is connected between the third and fourth pins. The method includes the following steps: S1, when the circuit is driving the output normally, control the first pin and the second pin so that the first switch and the second switch are turned on at the same time. S2, when a signal to turn off the switching transistor is detected, the first pin is first controlled to turn off the first switching transistor, while the second switching transistor continues to be turned on. The first diode is turned on, so that the fourth pin is clamped to ground. The power supply charges the bootstrap capacitor through the charging diode. After waiting for a first preset time, the second pin is then controlled to turn off the second switching transistor.

[0013] Preferably, the method further includes: the drive controller detects whether the drive power supply of the first switch needs to be forcibly charged; if so, it controls the second pin to turn on the second switch, controls the first pin to turn off the first switch, and discharges the fourth pin until the drive power supply of the first switch is charged through the power supply connected to the third pin. After charging is completed, it controls the second pin to turn off the second switch.

[0014] Preferably, the drive controller detects whether forced charging of the drive power supply for the first switching transistor is required, including: The drive controller detects whether it is the first startup. If so, it determines that the drive power supply of the first switching transistor needs to be forcibly charged. Otherwise, the drive controller detects whether no drive signal is output within a second preset time. If so, it determines that the drive power supply of the first switching transistor needs to be forcibly charged.

[0015] Preferably, the drive controller detects whether no drive signal is output within the second preset time period by: the drive controller detects whether neither the first pin nor the second pin outputs a drive signal within the second preset time period; if so, it determines that the drive power supply of the first switching transistor needs to be forcibly charged.

[0016] Preferably, the charging of the drive power supply for the first switching transistor by the power supply connected through the third pin includes: When the second switch is turned on, the fourth pin is discharged, and the voltage value of the fourth pin gradually decreases. When the voltage value of the fourth pin decreases to a preset voltage value, the power supply connected to the third pin begins to charge the bootstrap capacitor.

[0017] Preferably, after the second switch is turned off upon completion of charging, a third preset time is waited before the first and second switches are simultaneously turned on.

[0018] Preferably, the signal detecting the turn-off switch includes: The current values ​​of the first and second switching transistors are detected to have reached the target current threshold, or... The on-time of the first and second switching transistors has reached the target on-time.

[0019] Preferably, the target current threshold is the current threshold of the peak current comparator obtained by the dual-transistor flyback circuit based on the closed-loop feedback signal; the larger the closed-loop feedback signal, the larger the target current threshold. The target conduction time is the drive target conduction time obtained by the dual-transistor flyback circuit based on the closed-loop feedback signal; the larger the closed-loop feedback signal, the longer the target conduction time.

[0020] Preferably, the first preset time is 100 ns.

[0021] Preferably, the first preset time is determined using an adaptive adjustment method, including: The drive controller detects the voltage value of the third pin; When the voltage value is greater than the preset maximum voltage value, the first preset time is reduced by a preset unit time. When the voltage value is less than the preset minimum voltage value, the first preset time is increased by a preset unit time.

[0022] The present invention also provides a dual-transistor flyback circuit, wherein the control method described above is used to control the dual-transistor flyback circuit.

[0023] The present invention also provides a power control chip, the chip including a processor, the processor executing the dual-transistor flyback circuit control method described above to achieve power output control.

[0024] Beneficial effects: In the dual-transistor flyback circuit control method of this invention, during normal output drive, the second pin GL and the first pin GH are simultaneously set high. After detecting the signal to turn off the switching transistor, the first pin GH is first controlled to output a low level to turn off the first switching transistor Q1, while the second switching transistor Q2 remains on. The first diode is turned on, causing the fourth pin to be clamped to ground. The power supply charges the bootstrap capacitor through the supplementary diode. After a delay, the second pin GL is then controlled to output a low level to turn off the second switching transistor Q2. That is, GH / GL are turned on simultaneously, but GL is turned off with a delay relative to GH, which is an asymmetrical drive. During the delayed turn-off period, since the transformer's magnetizing inductance has just completed excitation, the current flows from GND to the first diode, then through the transformer to the second switching transistor Q2, and finally back to the system GND. At this time, since the first diode is on, the fourth pin SW is clamped to GND, and the power supply charges the bootstrap capacitor through the supplementary diode, thereby ensuring the reliability and effectiveness of the upper transistor drive power supply. Compared with existing technologies, it eliminates the need for auxiliary windings and isolation power supply modules, simplifies the control strategy, thereby reducing the design complexity of the circuit system and improving the flexibility of dual-tube flyback circuit applications.

[0025] Furthermore, the system detects the state of not driving for a long time: the drive controller detects whether the drive power supply of the first switch needs to be forcibly charged. If so, it controls the second pin to turn on the second switch, controls the first pin to turn off the first switch, and discharges the fourth pin until the drive power supply of the first switch is charged through the power supply connected to the third pin. After charging is completed, it controls the second pin to turn off the second switch, thereby avoiding insufficient power supply to the first switch and ensuring that the first switch can be effectively turned on in the future.

[0026] Other beneficial effects of the present invention will be explained in detail through the introduction of specific technical features and technical solutions in specific embodiments. Those skilled in the art should be able to understand the beneficial technical effects brought about by these technical features and technical solutions through the introduction of these technical features and technical solutions. Attached Figure Description

[0027] A preferred embodiment of the dual-transistor flyback circuit control method according to the present invention will now be described with reference to the accompanying drawings. In the drawings: Figure 1 This is a schematic diagram of the principle of a single-transistor flyback circuit in the prior art; Figure 2 This is a schematic diagram of the principle of a dual-transistor flyback circuit in the prior art; Figure 3 A schematic diagram of a dual-transistor flyback circuit that adds a winding to power the upper transistor in the existing technology; Figure 4 A schematic diagram of a dual-transistor flyback circuit that adds an isolation power supply module to the existing technology to achieve power supply for the upper transistor drive. Figure 5 This is a flowchart of a dual-transistor flyback circuit control method according to a preferred embodiment of the present invention; Figure 6 This is a schematic diagram of a dual-transistor flyback circuit according to a preferred embodiment of the present invention; Figure 7 A timing diagram for charging the drive power supply of the first switching transistor in a dual-transistor flyback circuit according to a preferred embodiment of the present invention. Figure 8 This is a timing diagram of a GL delay shutdown control strategy according to a preferred embodiment of the present invention; Figure 9 This is a schematic diagram of the current flow direction within a first preset time according to a preferred embodiment of the present invention; Figure 10 The schematic diagram shows the application circuit of the power control chip designed using the technical solution of this invention. Detailed Implementation

[0028] To provide a more detailed description of the technical solutions of this application and to facilitate a better understanding of this application, specific embodiments of this application are described below in conjunction with the accompanying drawings. However, it should be understood that all illustrative embodiments and their descriptions are used to explain this application and do not constitute the sole limitation of this application.

[0029] In this application, terms such as "first" and "second" are used merely for descriptive purposes and should not be construed as indicating or implying relative importance.

[0030] Figure 5 The flowchart of a dual-transistor flyback circuit control method according to a preferred embodiment of the present invention is shown below. Figure 6 As shown, the dual-transistor flyback circuit includes a drive controller U1, a first switch Q1, and a second switch Q2. The first pin GH of the drive controller U1 is connected to the first switch Q1, and the second pin GL of the drive controller U1 is connected to the second switch Q2. The third pin BST of the drive controller U1 is connected to the power supply VCC through a compensation diode D3. The fourth pin SW of the drive controller U1 is connected to the first switch Q1 and serves as the floating ground for the first switch. A bootstrap capacitor C is connected between the third pin BST and the fourth pin SW. BST . Figure 6 The diagram shows an N-channel enhancement-mode MOSFET. The second pin GL of the drive controller U1 is connected to the gate of the second switch Q2, and the first pin GH of the drive controller is connected to the gate of the first switch Q1. In other embodiments, other types of MOSFETs may be used; this invention does not impose specific limitations. Figure 5 As shown, the control method for a dual-transistor flyback circuit includes the following steps: S1, when the circuit is driving the output normally, control the first pin and the second pin so that the first switch and the second switch are turned on at the same time. S2, when a signal to turn off the switching transistor is detected, the first pin is first controlled to turn off the first switching transistor, and the second switching transistor continues to be turned on. The first diode is turned on, so that the fourth pin is clamped to ground. The power supply charges the bootstrap capacitor through the charging diode. After waiting for a first preset time, the second pin is controlled to turn off the second switching transistor.

[0031] Existing control strategies control the simultaneous on / off of the first switch Q1 and the second switch Q2 by controlling the output signals of the first pin GH and the second pin GL. However, the dual-transistor flyback circuit control method of this invention, during normal output drive, simultaneously sets the first pin GH and the second pin GL high. Upon detecting a signal to turn off the switches, it first controls the first pin GH to output a low level to turn off the first switch Q1. After a delay, it then controls the second pin GL to output a low level to turn off the second switch Q2. In other words, GH / GL are turned on simultaneously, but GL is turned off with a delay relative to GH, resulting in an asymmetrical drive. During the delayed turn-off period, since the transformer's magnetizing inductance has just completed energizing, the current flows from GND to the first diode, then through the transformer to the second switch Q2, and finally back to the system GND. At this time, because the first diode is conducting, the fourth pin SW is clamped to GND, and the power supply charges the bootstrap capacitor through the supplementary diode, thereby ensuring the reliability and effectiveness of the upper transistor drive power supply. Compared with existing technologies, it eliminates the need for auxiliary windings and isolation power supply modules, simplifies the control strategy, thereby reducing the design complexity of the circuit system and improving the flexibility of dual-transistor flyback circuit applications.

[0032] In a specific embodiment, the drive controller may include a drive circuit, which controls the drive circuit to output high and low level signals on the first pin GH and the second pin GL. In other embodiments, the drive circuit may be external to the drive controller; this invention is not limited thereto. The drive circuit is typically implemented using digital circuitry, but it can also be implemented using analog circuitry, or a combination of digital and analog circuitry.

[0033] In a preferred embodiment, the method further includes first detecting the dual-transistor flyback circuit. When forced charging of the drive power supply of the first switching transistor is required, only the second pin GL is controlled to output a high level to charge the drive power supply of the first switching transistor. Specifically, the drive controller's detection of whether forced charging of the drive power supply of the first switching transistor is required includes: the drive controller detecting whether it is the first startup; if so, it determines that forced charging of the drive power supply of the first switching transistor is required; otherwise, the drive controller detecting whether a drive signal has been output within a second preset time; if so, it determines that forced charging of the drive power supply of the first switching transistor is required.

[0034] In one embodiment, detecting whether forced charging of the drive power supply for the first switching transistor is equivalent to detecting whether the system has not output drive for an extended period, such as during the system's initial startup or when it is in a Burst OFF state. Burst OFF is a power control technique, also known as a low-power state or drive shutdown state. It refers to the situation where, when the load on the dual-transistor flyback circuit decreases to a light load or no load, the drive controller stops outputting drive signals to reduce system standby power consumption. When the load increases again, the dual-transistor flyback circuit needs to resume operation, and the drive controller needs to output drive signals normally. The load size is usually determined based on the system's closed-loop feedback signal (Feedback, FB). When FB is high, the system is in normal operating condition; when FB decreases, the system enters a Burst state, and the drive is shut down. When the drive stops outputting, although the drive circuit is in a stopped state (dormant, standby), it is not completely power-free; its power supply voltage will gradually decrease. If it is not pre-charged to meet normal operating conditions, the drive will not output. FB indicates the load size of a two-transistor flyback circuit. It is usually a voltage signal. The higher the FB, the larger the load. FB is usually 0~3.3V. The closer to 3.3V, the higher the FB, and the closer to 0V, the lower the FB.

[0035] like Figure 6 In the diagram, the voltage difference between the third pin BST and the fourth pin SW is denoted as V. BST Let the voltage difference between the fourth pin SW and PGND be denoted as V. SW The drive signal for the first switch Q1 is denoted as GH, and the drive signal for the second switch Q2 is denoted as GL. When the system is detected to be starting up for the first time or in a burst OFF state, V BST The voltage does not meet the turn-on condition of the first switch Q1, causing the dual-transistor flyback circuit to be unable to output energy to provide power to the load circuit. Therefore, the drive controller first checks whether it is the first start-up or whether no drive signal has been output within a second preset time. If so, it first charges the drive power supply of the first switch Q1 to make the circuit parameters meet the turn-on condition of the first switch Q1.

[0036] In a preferred embodiment, the initial startup of the circuit system can be determined based on a system flag bit or register value. For example, when the drive controller has never output a drive signal, the flag bit or register value is 0; after outputting a drive signal, the flag bit or register value is set to 1. Therefore, the drive controller's detection of whether it is the first startup may include: the drive controller detecting whether the system startup flag bit or the system startup register value is set to 1; if it is not set to 1, it determines that the drive power supply of the first switching transistor needs to be forcibly charged.

[0037] In a preferred embodiment, when the dual-transistor flyback circuit enters the burst OFF state, neither the second pin nor the first pin outputs a drive signal. Therefore, the drive controller's detection of whether no drive signal is output within a second preset time specifically includes: the drive controller detecting whether neither the first pin nor the second pin outputs a drive signal within the second preset time; if so, it determines that the drive power supply of the first switching transistor needs to be forcibly charged. In a specific embodiment, the second preset time can be 500µs or 1ms, etc.

[0038] In a preferred embodiment, charging the drive power supply of the first switching transistor through the power supply connected to the third pin includes: when the second pin outputs a high level, the voltage value of the fourth pin gradually decreases; when the voltage value of the fourth pin decreases to a preset voltage value, the power supply connected to the third pin begins to charge the bootstrap capacitor.

[0039] by Figure 6 and Figure 7 For example, when the second pin GL outputs a high level and the second switching transistor is turned on, the voltage value V at the fourth pin SW will be... SW Discharge begins, voltage V at that point SW From the bus voltage V BUS The voltage is gradually reduced from half to a preset value, for example, 0V. The power supply VCC then becomes the value of the bootstrap capacitor C. BST During charging, once fully charged, the second pin GL stops outputting a high level, thus preventing insufficient power supply to the first switch Q1 and ensuring its effective conduction. In the diagram, the high-level output time of the second pin GL is T. ON_CHG Specifically, T ON_CHG Values ​​can be 5µs or 10µs, etc. Generally, the larger the bootstrap capacitor, the longer the charging time.

[0040] In a preferred embodiment, it further includes: when the bootstrap capacitor C BST After charging is complete, the second pin GL outputs a low level, then waits for a third preset time (T). DRV_DLY Then, normal driving operations are performed. Specifically, after completing the bootstrap capacitor C... BST After charging, the drive circuit resumes from sleep or standby mode and receives normal voltage. It needs a period of initialization before it can work normally. The third preset time (T) DRV_DLY This is to wait for the drive circuit to enter normal working state. Therefore, after the second pin GL outputs a low level, a certain period of time (the third preset time) is elapsed before the normal drive control of the system begins. In a specific implementation, the third preset time can be 20µs.

[0041] In a preferred embodiment, detecting the signal to turn off the switching transistor in step S2 includes: detecting that the current value of the first switching transistor and the second switching transistor reaches the target current threshold, or detecting that the conduction time of the first switching transistor and the second switching transistor reaches the target conduction time.

[0042] In a preferred embodiment, the target current threshold is the current threshold of the peak current comparator obtained by the dual-transistor flyback circuit based on the closed-loop feedback signal. The larger the closed-loop feedback signal, the larger the target current threshold. Specifically, peak current control obtains the current threshold of the peak current comparator based on the closed-loop feedback signal (FB) of the dual-transistor flyback circuit. When the sampled current values ​​of the first and second switches exceed the current threshold, they are driven to shut down. Typically, sampling resistors are used to obtain the current flowing through the first and second switches. The larger the closed-loop feedback signal, the larger the current threshold of the peak current comparator, and the higher the energy that can be transferred.

[0043] In another preferred embodiment, the target on-time is the drive target on-time obtained by the dual-transistor flyback circuit based on the closed-loop feedback signal. The larger the closed-loop feedback signal, the longer the target on-time. Specifically, constant on-time control also obtains the drive target on-time based on the closed-loop feedback signal (FB), uses a timer to time the on-time, and turns off the drive when the drive on-time equals the target on-time. Similar to peak current control, the larger the closed-loop feedback signal, the longer the target on-time, and the more energy the dual-transistor flyback circuit transfers.

[0044] like Figure 8 As shown, the control strategy proposed in this invention is that GH and GL simultaneously output high levels during normal operation, the first and second switching transistors are simultaneously turned on, and the driving circuit of the first switching transistor continuously consumes power, therefore V BST The current continuously decreases. When the current values ​​of the first and second switching transistors reach the target current threshold, or when the conduction time of the first and second switching transistors reaches the target conduction time, GH first turns off, that is, outputs a low level, and then remains low for a first preset time (T). DLY_CHG During this period, since GL is not set to low level, the power supply of the drive circuit for the first switching transistor can be replenished. BST It rises again. Delay T DLY_CHG GL is then turned off. During the delayed shutdown T... DLY_CHG During this period, the direction of current flow is as follows Figure 9As shown, since the transformer's magnetizing inductance has just completed magnetization, when GH is turned off and GL remains on, the current flows from GND to the first diode D1, then through the transformer to the second switch Q2, and finally back to the system GND. At this time, because the first diode D1 is on, SW is clamped to GND, and VCC can flow through the compensation diode D3 to the bootstrap capacitor C. BST Charging ensures the reliability and effectiveness of the power supply for the first switching transistor Q1.

[0045] In a preferred embodiment, the first preset time (T) DLY_CHG () can be 100ns.

[0046] In another preferred embodiment, an adaptive adjustment method can be used to determine the first preset time (T). DLY_CHG Specifically, this can include: the drive controller detecting the voltage value of the third pin BST; when the voltage value is greater than a preset maximum voltage value, decreasing the first preset time by a preset unit time; and when the voltage value is less than a preset minimum voltage value, increasing the first preset time by a preset unit time. Specifically, the detection circuit can be integrated into the drive circuit of the drive controller, acting as a circuit to detect the power supply to prevent it from being too low, below the normal operating range of the drive circuit. The preset maximum voltage value is the maximum value within the normal operating range of the drive circuit, and the preset minimum voltage value is the minimum value within the normal operating range of the drive circuit. For example, the preset maximum voltage value can be 11.5V, and the preset minimum voltage value can be 9V. In a specific implementation, the preset unit time can be 5ns.

[0047] The present invention also discloses a dual-transistor flyback circuit, wherein the control method described in any one of the present invention is used to control the dual-transistor flyback circuit.

[0048] The present invention also discloses a power control chip, the chip including a processor, the processor executing the dual-transistor flyback circuit control method according to any one of the present invention to realize power output control.

[0049] Figure 10 The diagram shows the application circuit schematic of the power control chip designed using the technical solution of this invention. L and N on the left are the AC power input terminals, and the right side is the voltage output terminal after voltage conversion, supplying the circuit load with the output voltage. U1 is a control chip integrating the control strategy of this invention. This chip can be used for dual-transistor flyback circuit control, controlling the output voltage by controlling GH and GL.

[0050] The functions of each pin in U1 are as follows: V BUS Bus voltage; PFCDRAIN: Enables high-voltage startup of the system; PFCG: Logic driver for PFC circuits; ACIN: Input voltage detection; VCC: Chip power supply pin; ZCD: Dual-tube flyback zero-crossing detection; GH and GL: provide drive signals for the switching transistors in the dual-transistor flyback circuit, respectively. BST: Dual-tube flyback top-side power supply; SW: Dual-tube flyback top tube floating ground; CS: Samples the current and performs peak current control and protection.

[0051] FB: Acquires the voltage signal of external compensation, thereby controlling the system's operating mode and peak current control command value.

[0052] When U1 detects that the system is starting up for the first time or that neither GH nor GL outputs a drive signal within a second preset time (500us or 1ms), U1 controls the GL pin to output a high level. At this time, the voltage of the SW pin is controlled by the bus voltage V. BUS As the voltage gradually decreases from half to near 0V, the chip's power supply pin VCC begins charging the bootstrap capacitor until it is fully charged. U1 then controls the GL pin to output a low level. After a third preset time (e.g., 20µs), the GL and GH pins are simultaneously controlled to output a high level, causing the upper and lower transistors to conduct simultaneously. Subsequently, when the current sampling value of the CS pin is detected to be greater than the target current threshold, the GH pin is first controlled to output a low level. After a first preset time (e.g., 100ns), the GL pin is then controlled to output a low level.

[0053] It should be noted that the use of step numbers (letter or number) to refer to certain specific method steps in this invention is merely for the purpose of convenience and brevity in description, and is by no means intended to restrict the order of these method steps. Those skilled in the art will understand that the order of the relevant method steps should be determined by the technology itself and should not be unduly restricted by the existence of step numbers.

[0054] Those skilled in the art will understand that, without conflict, the above-mentioned preferred solutions can be freely combined and superimposed.

[0055] It should be understood that the above embodiments are merely exemplary and not restrictive. Various obvious or equivalent modifications or substitutions that can be made by those skilled in the art regarding the above details without departing from the basic principles of the present invention will be included within the scope of the claims of the present invention.

Claims

1. A control method for a dual-transistor flyback circuit, wherein the dual-transistor flyback circuit includes a drive controller, a first switching transistor, and a second switching transistor; a first pin of the drive controller is connected to the first switching transistor; a second pin of the drive controller is connected to the second switching transistor; a third pin of the drive controller is connected to a power supply via a compensation diode; a fourth pin of the drive controller is connected to the first switching transistor and serves as a floating ground for the first switching transistor; the fourth pin of the drive controller is grounded via a first diode; and a bootstrap capacitor is connected between the third pin and the fourth pin. The method is characterized in that... The method includes the following steps: S1, when the circuit is driving the output normally, control the first pin and the second pin so that the first switch and the second switch are turned on at the same time. S2, when a signal to turn off the switching transistor is detected, the first pin is first controlled to turn off the first switching transistor, while the second switching transistor continues to be turned on. The first diode is turned on, so that the fourth pin is clamped to ground. The power supply charges the bootstrap capacitor through the charging diode. After waiting for a first preset time, the second pin is then controlled to turn off the second switching transistor.

2. The dual-transistor flyback circuit control method according to claim 1, characterized in that, Also includes: The drive controller detects whether the drive power supply of the first switch needs to be forcibly charged. If so, it controls the second pin to turn on the second switch, controls the first pin to turn off the first switch, and discharges the fourth pin until the drive power supply of the first switch is charged through the power supply connected to the third pin. After charging is completed, it controls the second pin to turn off the second switch.

3. The dual-transistor flyback circuit control method according to claim 2, characterized in that, The drive controller detects whether forced charging of the drive power supply for the first switching transistor is required, including: The drive controller detects whether it is the first startup. If so, it determines that the drive power supply of the first switching transistor needs to be forcibly charged. Otherwise, the drive controller detects whether no drive signal is output within a second preset time. If so, it determines that the drive power supply of the first switching transistor needs to be forcibly charged.

4. The dual-transistor flyback circuit control method according to claim 3, characterized in that, The drive controller detects whether no drive signal is output within a second preset time period by detecting whether neither the first pin nor the second pin outputs a drive signal within the second preset time period. If so, it determines that the drive power supply of the first switching transistor needs to be forcibly charged.

5. The dual-transistor flyback circuit control method according to claim 2, characterized in that, After the second switch is turned off upon completion of charging, a third preset time is waited before the first and second switches are turned on simultaneously.

6. The dual-transistor flyback circuit control method according to claim 1, characterized in that, The detected signal of the off-switch transistor includes: The current values ​​of the first and second switching transistors are detected to have reached the target current threshold, or... The on-time of the first and second switching transistors has reached the target on-time.

7. The dual-transistor flyback circuit control method according to claim 6, characterized in that, The target current threshold is the current threshold of the peak current comparator obtained by the dual-tube flyback circuit based on the closed-loop feedback signal. The larger the closed-loop feedback signal, the larger the target current threshold. The target conduction time is the drive target conduction time obtained by the dual-tube flyback circuit based on the closed-loop feedback signal. The larger the closed-loop feedback signal, the longer the target conduction time.

8. The dual-transistor flyback circuit control method according to any one of claims 1-7, characterized in that, The first preset time is 100ns.

9. The dual-transistor flyback circuit control method according to any one of claims 1-7, characterized in that, The first preset time is determined using an adaptive adjustment method, including: The drive controller detects the voltage value of the third pin; When the voltage value is greater than the preset maximum voltage value, the first preset time is reduced by a preset unit time. When the voltage value is less than the preset minimum voltage value, the first preset time is increased by a preset unit time.

10. A dual-transistor flyback circuit, characterized in that, The circuit uses the control method described in any one of claims 1-9 to control the dual-transistor flyback circuit.

11. A power control chip, the chip comprising a processor, characterized in that, The processor executes the dual-transistor flyback circuit control method as described in any one of claims 1-9 to achieve power output control.

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