Programmable communication analysis system of power sensor

Abstract

The invention relates to the technical field of power system testing, and discloses a power sensor programmable communication analysis system which comprises a multi-mode signal acquisition module, a dynamic protocol analysis module, an intelligent topology identification module, an intelligent diagnosis and risk assessment module, an autonomous power supply module, a topology self-healing module and a visual diagnosis module. The acquisition module synchronously acquires a bus physical waveform through three channels, the analysis module decodes a logic message by using a double-buffer mechanism, the intelligent diagnosis module quantifies the health degree based on multi-dimensional characteristics, and the topology self-healing module performs address arbitration and network reconstruction in combination with a time division multiplexing controller and a signal time delay ranging algorithm. The visualization module generates a stacked waveform and a topological thermodynamic diagram. Through time sequence fusion of physical characteristics and logic data and an active conflict arbitration strategy, accurate traceability of communication faults and automatic reconstruction of networking topology are realized.

Description

Technical Field

[0001] This invention relates to the field of power system testing technology, specifically to a programmable communication analysis system for power sensors. Background Technology

[0002] Power sensors are core components of the sensing layer of smart grids. Communication reliability directly determines the accuracy of data acquisition. Power sensor communication analysis systems are mainly used to comprehensively detect the consistency of communication protocols, physical layer electrical characteristics, and network topology of field devices. They are key tools to ensure the interconnection of equipment and the safe operation of the system.

[0003] Current power sensor communication testing mainly relies on general-purpose oscilloscopes in conjunction with computer-based serial port debugging software. Typically, the oscilloscope is used to observe the physical waveform of the bus, or the debugging software is used to capture application layer messages according to preset parameters to verify connectivity. This testing mode usually treats physical signal analysis and logical message parsing as two independent and separate steps, and mainly relies on manual comparison to evaluate communication quality.

[0004] However, due to the lack of a unified time-base synchronization mechanism for physical signal characteristics and protocol logic data in existing technologies, it is difficult to distinguish whether the fault is caused by waveform distortion, power supply fluctuation or timing violation when encountering communication errors, resulting in the inability to accurately locate the root cause of the fault. In addition, conventional tools lack the ability to automatically identify network topology and self-heal address conflicts. When multiple devices are networked and address overlap occurs, it will lead to bus communication paralysis, forcing maintenance personnel to use the inefficient method of disconnecting and isolating each device one by one to troubleshoot, which seriously reduces the efficiency of on-site maintenance. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a programmable communication analysis system for power sensors, aiming to solve the problems of difficulty in fault location due to the fragmentation of physical and logical data and inefficient operation and maintenance caused by the lack of conflict self-healing mechanisms.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] This invention provides a programmable communication analysis system for power sensors, comprising:

[0008] The system includes a dynamic protocol parsing module, a multimodal signal acquisition module, an intelligent topology recognition module, an intelligent diagnosis and risk assessment module, an autonomous power supply module, a topology self-healing module, and a visualization diagnosis module.

[0009] The dynamic protocol parsing module is configured to perform logical parsing of communication data based on preset and user-defined protocol templates. Specifically, it includes: a protocol storage unit for storing a protocol template library containing byte order, data offset, data type, and verification rules; a parameter configuration unit for providing a human-machine interface to receive user configuration instructions for protocol parameters; and a protocol loading unit configured to transmit protocol data structures to the parsing buffer via a direct memory access controller. The parsing buffer adopts a double buffering mechanism, allowing the auxiliary buffer to receive new protocol configuration data while the main buffer performs the current protocol parsing.

[0010] The multimodal signal acquisition module, with its input end connected to the communication bus, is configured to synchronously acquire physical layer signals and load monitoring signals on the communication bus. Specifically, it includes: a signal conditioning unit integrating three physically isolated acquisition channels and equipped with a programmable gain amplifier to perform dynamic range management; an analog-to-digital conversion unit configured to synchronously sample the three physically isolated acquisition channels based on a unified clock source; a signal processing unit configured to perform anti-aliasing filtering and waveform distortion rate calculation on the sampled data; and a time synchronization unit configured to append a unified timestamp to the acquired data.

[0011] The intelligent topology identification module, communicatively connected to the dynamic protocol parsing module, is configured to send probe sequences and identify device nodes and address conflict events on the communication bus. Specifically, it includes: a baud rate sweep unit, configured to cyclically send handshake signal sequences using an exponential backoff algorithm within a preset baud rate range; and an address conflict detection unit, configured to execute a three-level decision process based on an instruction feature library and a response feature library, including response time consistency detection, data format compliance detection, and abnormal behavior pattern detection, for outputting a list of conflicting addresses.

[0012] The intelligent diagnosis and risk assessment module is connected to the dynamic protocol parsing module and the multimodal signal acquisition module, respectively, and is configured to assess the system health based on physical layer signal characteristics and protocol logic characteristics. Specifically, it includes: a fault feature extraction unit, configured to extract feature vectors from three dimensions: communication quality, timing behavior, and protocol compliance; a health assessment unit, configured to normalize the feature vectors and calculate the system health score based on preset weights; and a risk warning unit, configured to trigger a graded alarm signal according to the interval in which the system health score is located.

[0013] The autonomous power supply module is configured to provide isolated DC power, collect the current signal of the power supply circuit in real time, and output it as the load monitoring signal to the multi-mode signal acquisition module; specifically, it includes: an isolated power conversion unit, which adopts a flyback topology and a linear regulator to provide a two-stage regulated output; a load monitoring unit, connected in series in the power supply output circuit, configured to collect the circuit current and convert it into an analog voltage value for output to the multi-mode signal acquisition module; and an intelligent protection unit, configured to compare the collected real-time current with a preset threshold, cut off the output when an overcurrent or short circuit is detected, and execute an intermittent automatic restart strategy until the fault is eliminated.

[0014] The topology self-healing module, connected to the intelligent topology identification module and the dynamic protocol parsing module, is configured to take over control of the communication bus for arbitration and reconstruct the bus topology when an address conflict event is detected. Specifically, it includes: a time-division multiplexing controller unit configured to broadcast arbitration instructions to the conflicting devices and allocate discrete response time slices to achieve time-division communication response; and a topology reconstruction unit configured to calculate the electrical distance based on signal transmission delay and signal attenuation characteristics, and construct a bus topology model. Specifically, the topology reconstruction unit calculates the electrical distance between the device and the master station by subtracting a preset internal processing delay constant from the measured total round-trip response delay time to obtain the net delay time; and multiplying the net delay time by the nominal signal transmission rate in the cable and the cable aging correction factor to obtain the electrical distance.

[0015] The visualization diagnostic module, connected to both the intelligent diagnostic and risk assessment module and the topology self-healing module, is configured to display signal waveforms, topology structure, and health status. Specifically, it includes: a layered waveform display unit, configured to simultaneously present physical layer waveforms and logical layer waveforms for multi-dimensional comparison, employing double-buffered memory technology and a persistence accumulation algorithm to present the signal jitter range by overlaying historical frame data; and a topology heatmap generation unit, configured to generate a network topology structure diagram and visually identify the status of topology nodes based on the system health score.

[0016] This invention provides a programmable communication analysis system for power sensors. It has the following advantages:

[0017] 1. This invention constructs a real-time time-series mapping of physical waveforms, logic data and load current through multi-modal signal synchronous acquisition and dynamic protocol parsing, overcoming the limitations of data fragmentation and improving the diagnostic accuracy of faults caused by waveform distortion or power fluctuations in power sensor communication networks.

[0018] 2. This invention achieves automated address conflict resolution and topology reconstruction through time-division multiplexing arbitration and signal delay ranging technology. It can solve the problem of confusion in multi-node power sensor networking without manual intervention, and reduce the operation and maintenance cost of field communication bus.

[0019] 3. This invention, through intelligent isolated power supply and multi-dimensional visual diagnostics, ensures electrical safety during the testing process of power sensors while intuitively quantifying signal quality and network status, enabling proactive early warning and efficient investigation of potential risks in communication links. Attached Figure Description

[0020] Figure 1 This is a system framework diagram of an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of the internal structure of the dynamic protocol parsing module in an embodiment of the present invention;

[0022] Figure 3 This is a flowchart of the intelligent topology identification and address conflict detection process according to an embodiment of the present invention;

[0023] Figure 4 This is a schematic diagram of the time-division multiplexing control logic and topology reconstruction of the topology self-healing module in an embodiment of the present invention. Detailed Implementation

[0024] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] See attached document Figure 1-4 This invention provides a programmable communication analysis system for power sensors, comprising:

[0026] The dynamic protocol parsing module 100 has a pre-built industrial communication protocol template library and provides a user-programmable interface. The dynamic protocol parsing module 100 can be configured with byte order parameters, data offset parameters, data type parameters and CRC check enable status parameters.

[0027] The multimodal signal acquisition module 200 includes three independent acquisition channels. Each channel achieves time-aligned sampling through a synchronous trigger circuit. The input terminal of the multimodal signal acquisition module 200 is connected to the 485 communication bus physical interface, and the output terminal is connected to the signal characteristic input terminal of the intelligent diagnosis and risk assessment module 400.

[0028] The intelligent topology identification module 300 integrates a baud rate sweep unit and an address conflict detection unit. The baud rate sweep unit transmits handshake signal sequences in the range of 2400bps to 115200bps. The address conflict detection unit compares data based on an instruction feature library and a response feature library.

[0029] The intelligent diagnosis and risk assessment module 400 receives protocol anomaly data output by the dynamic protocol parsing module 100, and simultaneously receives physical layer signal characteristics output by the multimodal signal acquisition module 200.

[0030] The self-powered module 500 provides isolated DC output and integrates load impedance monitoring circuitry. The power output is connected to the communication bus via an optocoupler isolation device, and the overcurrent protection threshold is set to 600mA.

[0031] The topology self-healing module 600 includes a time-division multiplexing controller unit and a topology reconfiguration unit. The time-division multiplexing controller unit activates a 50ms communication time window switching function when an address conflict event is triggered. The topology reconfiguration unit generates a bus branch structure diagram based on device response latency parameters.

[0032] The visualization diagnostic module 700 integrates a layered waveform display unit and a topology heatmap generation unit. The layered waveform display unit displays the original signal waveform and the distorted signal waveform side by side. The topology heatmap generation unit uses different colors to mark nodes with address conflicts.

[0033] The following will provide a detailed explanation of each of the above modules.

[0034] The dynamic protocol parsing module 100 includes a protocol storage unit 110, a parameter configuration unit 120, and a protocol loading unit 130.

[0035] Protocol storage unit 110 uses non-volatile memory to partition and store the protocol template library. This template library contains structured data records for 200 industrial communication protocols, each record containing the following fields:

[0036] Instruction identifier field: 16-bit unsigned integer, identifying the type of communication instruction;

[0037] Byte order identifier field: 8-bit unsigned integer, 0 indicates big-endian mode (high byte first), 1 indicates little-endian mode (low byte first).

[0038] Data offset field: 8-bit unsigned integer, with a value range of 0-255 bytes, defining the starting position of valid data in the data stream;

[0039] Data type encoding field: 8-bit unsigned integer, 1 represents 1-byte integer, 2 represents 2-byte integer, 3 represents 4-byte integer, 4 represents 4-byte floating-point number;

[0040] CRC check enable flag: 8-bit unsigned integer, 0 indicates that check is disabled, 1 indicates that CRC16 check is enabled;

[0041] The memory is managed using the FAT32 file system, and the data storage format is a binary array.

[0042] The parameter configuration unit 120 provides a touchscreen human-machine interface through which users configure four types of parameters:

[0043] Byte order selection parameter: Big-endian or Little-endian;

[0044] Data offset parameter: an integer value from 0 to 255 bytes;

[0045] Data type parameter: 1-byte integer, 2-byte integer, 4-byte integer, or 4-byte floating-point number;

[0046] CRC check enable status parameter: Enabled or disabled

[0047] Input parameters are verified by the data validation circuit: if the offset exceeds 255, it is automatically truncated to 255; if the data type is invalid, it is set to a 4-byte integer by default. After successful verification, it is converted to a 32-bit configuration code and written to the register (address 0x2000C000).

[0048] Protocol loading unit 130 uses a direct memory access controller. When the user selects a preset protocol:

[0049] Retrieve protocol storage unit 110 according to protocol identifier;

[0050] The protocol data structure is transferred to the protocol parsing buffer via the DMA channel;

[0051] Start the protocol parsing state machine;

[0052] When a user configures a custom protocol, the output of the parameter configuration unit 120 is directly written to the protocol parsing buffer.

[0053] The protocol parsing buffer employs a double-buffering mechanism. The primary buffer (address 0x20001000) stores the currently active protocol structure, while the secondary buffer (address 0x20002000) is used to receive new protocol data. Buffer switching is triggered by a hardware interrupt (IRQ15), which occurs when the secondary buffer is fully written, with a switching time of less than 10μs.

[0054] During protocol parsing, signal quality needs to be evaluated. The degree of signal distortion is quantified by the waveform distortion rate parameter. The waveform distortion rate is calculated using a normalized cross-correlation algorithm, which is expressed as follows:

[0055] ;

[0056] In the formula, Waveform distortion rate; This is a sequence of standard waveform sampling points; The measured waveform sampling point sequence (acquired in real time through the 200-channel 1 multi-mode signal acquisition module); The number of sampling points within a single bit period; The sampling point number (ranging from 1 to...) (integers).

[0057] The output interface of the dynamic protocol parsing module 100 uses a parallel data bus. The bus includes 16 data lines, 3 address lines, and read / write control signal lines, and is physically connected to the data input port of the intelligent diagnostic and risk assessment module 400. The protocol parsing result transmission format includes the following fields:

[0058] Frame header: 2-byte synchronization word; Instruction identifier: 2-byte unsigned integer; Timestamp: 4-byte time data; Data length: 1 byte; Parsed data payload: 0-256 bytes of valid data; CRC checksum: 2 bytes;

[0059] The protocol parsing state machine contains four working states:

[0060] Idle state: Waiting for instruction trigger signal; Data acquisition state: Reading data stream from bus buffer; Parsing execution state: Parsing data according to protocol structure; Verification state: Performing CRC16 check calculation;

[0061] State transitions are periodically triggered by a hardware timer. The status register address is 0x2000F000, and the lower two bits of the register store the current status code. The CRC16 check uses the standard Modbus polynomial algorithm. The polynomial expression is: (Hexadecimal 0xA001), initial value 0xFFFF, the verification calculation is implemented through hardware acceleration circuit, the calculation clock frequency is 48MHz, and the calculation result is stored in the result register (address 0x2000D000).

[0062] The multimodal signal acquisition module 200 consists of a signal conditioning unit 210, an analog-to-digital conversion unit 220, a signal processing unit 230, and a time synchronization unit 240, and is responsible for high-precision synchronous acquisition and feature extraction of multi-dimensional signals on the power communication bus.

[0063] The signal conditioning unit 210 integrates three physically isolated acquisition channels, each optimized for different signal types. Channel 1 is designed with high input impedance to accommodate the characteristics of high-impedance signal sources in industrial environments. Its voltage range covers the typical range specified by industrial communication standards and includes a built-in overvoltage protection circuit with a response time in the microsecond range. This circuit can quickly activate when the input voltage exceeds the safe operating range, protecting delicate downstream components. The channel's built-in programmable gain amplifier (PGA) supports switching between several discrete gain levels, with gain error controlled at a low level.

[0064] The analog-to-digital converter (ADC) 220 adopts a synchronous sampling architecture, with a multi-channel ADC at its core. The sampling rate of the ADC 220 is configurable over a wide frequency range to accommodate different communication protocols from low to high speeds; the resolution is typically 16 bits or higher to ensure fine quantization of the signal; the ADC 220 is powered by a low-jitter master clock provided by an FPGA or a dedicated clock chip to achieve high synchronization of sampling times between channels.

[0065] The signal processing unit 230 contains a continuous data processing pipeline. The first step is anti-aliasing filtering, typically implemented using an FIR digital filter. The order is selected between tens and hundreds of points depending on the processing capability. The filter's cutoff frequency is not fixed but dynamically adjusted within a relevant range (e.g., 1.2 to 1.8 times the signal frequency) based on the currently detected main signal frequency. This design aims to effectively suppress high-frequency aliasing components while preserving the effective components of the signal to the maximum extent, avoiding the loss of critical information due to over-filtering.

[0066] Secondly, there is a dynamic range management mechanism. By monitoring the peak-to-peak value of the input signal in real time and comparing it with multiple preset amplitude thresholds, it automatically decides and switches to the optimal PGA gain level. The response time of the entire gain switching process is strictly limited to a few sampling cycles, thereby ensuring the continuity of the data stream and avoiding the loss of effective data due to range switching.

[0067] The system also provides flexible digital filtering processing functions. Users can select low-pass, band-pass and other filter types and set the corresponding cutoff frequency parameters by configuring specific control registers (such as address 0x2000A000), thereby realizing the extraction and noise suppression of signals in specific frequency bands.

[0068] During the feature extraction stage, the system calculates key signal parameters, such as the effective voltage value. The formula for calculating the effective voltage value is:

[0069] ;

[0070] In the formula, This is the effective value of the voltage. The first of the signal voltages Instantaneous values ​​at each sampling point; This represents the total number of sampling points within the analysis window.

[0071] The time synchronization unit 240 provides a unified, high-precision timing reference for the entire module. It typically integrates a satellite timing module, with absolute time accuracy usually on the order of hundreds of nanoseconds. Each acquired data point is appended with a 32-bit timestamp generated based on a high-frequency reference clock. This mechanism ensures that data between different acquisition channels and between this module and the protocol parsing module 100 have clear and consistent time stamps, with synchronization errors controlled within hundreds of nanoseconds.

[0072] In terms of module performance characteristics, the inter-channel isolation voltage of the signal conditioning unit must meet industrial safety standards, and the signal crosstalk between channels must be suppressed to a low level (e.g., less than -80dB at a specific frequency) to ensure the independence and accuracy of each signal when multiple channels are acquired synchronously.

[0073] In terms of system interface design, the multimodal signal acquisition module 200 is physically connected to the protocol parsing module 100 via a high-speed differential serial interface. Data transmission follows a specific frame format, which typically includes the following fields:

[0074] The frame header contains a fixed synchronization word; the timestamp records the sampling time; the channel identifier is used to distinguish the signal source; the payload area carries the original sampled data; and the frame tail contains a checksum used to verify data integrity. The entire data transmission process employs a hardware flow control mechanism to ensure that the end-to-end transmission delay remains stable at a low level. The intelligent topology identification module 300 consists of a baud rate sweep unit 310 and an address conflict detection unit 320.

[0075] The baud rate sweep unit 310 scans within the standard baud rate range of 2400bps to 115200bps. The scanning process employs an exponential backoff algorithm with an initial interval of 100 milliseconds and a maximum number of retries of 3.

[0076] The baud rate sweep unit 310 incorporates the standard Modbus RTU instruction set and probes bus nodes by cyclically sending device identification commands (function code 0x17). To cope with different line conditions, the baud rate sweep unit 310 has a transmit power adjustment function, which is based on monitoring the amplitude of the received signal. When the signal is too weak, the transmit power is increased in fixed steps to ensure that the probe commands can effectively cover all nodes.

[0077] The address conflict detection unit 320 includes an instruction feature library 321 and a response feature library 322. The instruction feature library stores standard protocol instruction templates and includes the mapping relationship between device type identifiers and function codes. The response feature library records historical communication data and establishes a correlation model between device response time and data pattern.

[0078] The conflict detection process employs a three-level decision-making process. The first level is response time consistency detection, which calculates the standard deviation of latency for multiple responses from the same address; if it exceeds 20% of the average latency, it is considered abnormal. The second level is data format compliance detection, which verifies the length, checksum, and frame structure of the response data. The third level is behavioral pattern anomaly detection; in this step, a machine learning model that analyzes communication behavior sequences identifies abnormal behaviors that do not conform to standards or historical normal patterns.

[0079] The topology identification process is executed in the following four stages in sequence:

[0080] The first stage is the initial scan, which establishes an initial device list through full-baud rate broadcast queries; the second stage is address verification, which sends a unique identification command to each address in the list to confirm its authenticity; the third stage is conflict resolution, which identifies device addresses with inconsistent response characteristics by comparing multiple rounds of probe data; the fourth stage is result reporting, which packages conflicting addresses, anomaly types, and statistically based confidence values ​​into structured data frames for transmission.

[0081] The intelligent diagnosis and risk assessment module 400 consists of a fault feature extraction unit 410, a health assessment unit 420, and a risk warning unit 430, and is used to monitor and warn of the operating status of the bus communication system.

[0082] The fault feature extraction unit 410 is configured to extract feature vectors from three levels: communication quality, timing behavior, and protocol compliance.

[0083] At the communication quality level, the fault feature extraction unit 410 calculates physical layer parameters such as bit error rate and signal-to-noise ratio based on the received data packets; at the timing behavior level, it calculates the time interval distribution of adjacent data frames, the number of response timeouts, and the retransmission frequency; at the protocol compliance level, it detects abnormal values ​​in protocol fields, conflicts in function codes, and drifting of device addresses.

[0084] The health assessment unit 420 adopts a weighted quantitative scoring mechanism to establish a health index system comprising three dimensions; these three dimensions and their preset weights are as follows:

[0085] Communication link health (weight 40%), mainly related to bit error rate and signal strength indicators; device status health (weight 35%), mainly related to response success rate and load rate indicators; protocol stack health (weight 25%), mainly related to protocol consistency and field integrity indicators.

[0086] During the evaluation, the health assessment unit 420 first normalizes the input feature values ​​of each dimension and maps them to standard scores from 0 to 100. Then, it performs a weighted summation based on the weights mentioned above to calculate the final health score of the system.

[0087] Risk warning unit 430 implements a tiered warning strategy based on health score.

[0088] When the health score is greater than or equal to 80, it is judged as a Level 1 warning (normal state), and the system only records the operation log; when the health score is between 60 and 80 (excluding 80), it is judged as a Level 2 warning (attention state), and the system starts the enhanced monitoring mode and increases the sampling frequency; when the health score is lower than 60, it is judged as a Level 3 warning (alarm state), and the unit will send a trigger signal to the topology self-healing module 600.

[0089] The diagnostic analysis process includes two modes: real-time monitoring and periodic assessment. The real-time monitoring mode is used to respond immediately to sudden failures such as communication interruptions and verification errors. The periodic assessment mode performs the above-mentioned comprehensive health assessment calculation once at a preset time interval (e.g., every 5 minutes) and updates the system's risk assessment report.

[0090] Regarding data interface connections, the input end of module 400 is connected to the diagnostic data output end of protocol parsing module 100 to obtain parsed abnormal information and statistical data; the output end is connected to the control input end of topology self-healing module 600 via CAN bus for transmitting repair strategy instructions.

[0091] The self-powered module 500 consists of an isolated power conversion unit 510, a load monitoring unit 520, and an intelligent protection unit 530. It is responsible for providing stable and safe isolated DC power to sensors and bus devices, and for monitoring the status of the power supply circuit in real time.

[0092] The 510 isolated power conversion unit adopts a flyback topology, connecting to an external 24V industrial DC power supply on the input side and providing 12V DC voltage on the output side, with a maximum output current of 500mA. The core component of this unit is a high-frequency transformer, achieving 3000Vrms electrical isolation between its primary and secondary windings. A filter network combining low-ESR electrolytic capacitors and ceramic capacitors is connected in parallel at the rectified output of the transformer secondary to control the output ripple voltage below 20mV, reducing power supply noise interference to communication signals. Furthermore, a linear regulator is designed at the output as a secondary voltage regulation stage, ensuring that the voltage fluctuation rate is less than 0.5% during load changes.

[0093] The load monitoring unit 520 is connected in series in the power supply output circuit, integrating a high-precision current sampling resistor and a differential amplifier. This unit acquires the circuit current signal in real time and converts it into an analog voltage value, which is then output to the interference analysis channel of the multi-mode signal acquisition module 200. This design enables the system to analyze the high-frequency noise components in the current waveform, thereby determining whether there are potential hazards such as electromagnetic interference or poor contact in the power supply line. Simultaneously, the monitoring unit also has a voltage feedback function to monitor the actual value of the output voltage, preventing insufficient power supply to remote equipment due to line voltage drop.

[0094] The intelligent protection unit 530 integrates overcurrent, short-circuit, and overheat protection functions. This unit has a built-in programmable comparator that compares the real-time current collected by the load monitoring unit 520 with a preset overcurrent protection threshold. When the current exceeds the threshold, the protection unit will cut off the power MOSFET on the output side within 10 microseconds, quickly blocking the fault current. For short-circuit faults, the unit employs an intermittent automatic restart strategy, specifically: after cutting off the output, it attempts to automatically restart every second until the short-circuit fault is cleared.

[0095] In addition, an NTC thermistor is placed on the PCB board, close to the power device. When the temperature exceeds 85°C, the protection unit will reduce the output current limit or directly shut down the output to prevent the module from overheating and being damaged.

[0096] In terms of power output interface design, the self-powered module 500 controls the output switching through optocoupler isolation devices, which not only achieves electrical isolation between the control signal and the power circuit, but also has reverse connection protection. A transient suppression diode is connected in parallel at the interface to absorb surge voltages that may occur on the bus and protect the internal circuitry of the module.

[0097] The topology self-healing module 600 consists of a time-division multiplexing controller unit 610 and a topology reconstruction unit 620, and is designed to resolve bus address conflicts and automatically rebuild the network topology.

[0098] The time-division multiplexing controller unit 610 is used to take over bus control when an address conflict is detected. When the intelligent topology identification module 300 detects that two or more devices are responding to the same logical address, this unit activates the conflict arbitration mechanism. The arbitration process employs a strategy such as switching between 50ms communication time windows, with the specific logic as follows:

[0099] The controller sends a broadcast command carrying a random delay parameter to the conflicting address, dividing the subsequent response period into several discrete time slices with a width of 50ms. The conflicting device selects a specific time window to respond based on the hash value of its unique hardware serial number. The time-division multiplexing controller unit 610 separates the conflicting devices by monitoring the valid data frames in different time windows and sends reallocation address commands to them in sequence to complete the replanning of logical addresses.

[0100] The topology reconstruction unit 620 is responsible for generating the spatial branch structure diagram of the bus based on physical parameters. This unit receives device response delay parameters from the intelligent topology identification module 300 and signal attenuation characteristics from the multi-mode signal acquisition module 200. The topology reconstruction algorithm calculates the electrical distance between the device and the master station based on transmission line theory; the calculation formula is as follows:

[0101] ;

[0102] In the formula, This refers to the calculated electrical distance between the equipment and the main station; This represents the measured total round-trip response time. This is the preset internal processing delay constant of the device; This is the nominal transmission rate of the signal in the twisted-pair cable; This is the cable aging correction factor.

[0103] The topology reconstruction unit 620 further analyzes the signal impedance differences between different nodes, identifies the branch points of the bus, and thus constructs a hierarchical topology model that includes the trunk and branch lines.

[0104] Regarding interface connections and control logic, the trigger input of the topology self-healing module 600 is connected to the conflict detection output of the intelligent topology identification module 300 to receive a list containing conflicting addresses. The control signal output is connected to the instruction scheduling interface of the dynamic protocol parsing module 100 for inserting arbitration instructions and duplicate address instructions. The topology data output is connected to the visualization diagnostic module 700 to transmit the generated topology structure data.

[0105] The visualization diagnostic module 700 consists of a stacked waveform display unit 710 and a topology heatmap generation unit 720, and is used to provide a human-computer interaction interface to display signal waveforms and network topology.

[0106] The stacked waveform display unit 710 uses dual-buffered memory technology to drive the LCD screen. This unit divides the screen vertically into independent waveform display channels. The first channel is used to draw the original physical signal waveform input by the multimodal signal acquisition module 200, and the second channel is used to draw the logic analysis waveform output by the dynamic protocol parsing module 100. The display control logic adopts the persistence accumulation algorithm, which presents the jitter range of the signal by superimposing historical frame data.

[0107] The stacked waveform display unit 710 has an automatic cursor measurement function, which can lock a specific time point on the waveform based on touch operation and display the voltage amplitude and time difference corresponding to that point in real time.

[0108] The topology heatmap generation unit 720 is responsible for drawing the logical connection structure diagram of the bus. This unit receives the bus branch structure data generated by the topology self-healing module 600 and renders it as a tree-like or mesh-like node diagram. Simultaneously, this unit reads the device health score output by the intelligent diagnosis and risk assessment module 400 and performs color-coding mapping on the node icons based on the score values. The color mapping rules are set as follows:

[0109] Normal state (green): Health score ≥ 80 points, RGB setting is (0,255,0);

[0110] Warning status (yellow): Health score 60 points ≤ Health score < 80 points, RGB setting is (255,255,0);

[0111] Fault / Conflict Status (Red): Health score < 60 points or address conflict exists, RGB setting is (255,0,0).

[0112] In addition, when a disconnection fault is detected, the unit will mark an "×" symbol on the corresponding connection line and flash it as a warning.

[0113] In terms of data interface and interaction logic, the data input terminal of the visualization diagnostic module 700 is connected to the dynamic protocol parsing module 100 (acquiring logic data), the multimodal signal acquisition module 200 (acquiring waveform data), the intelligent diagnosis and risk assessment module 400 (acquiring health data), and the topology self-healing module 600 (acquiring topology data) respectively via the system bus.

[0114] The module has a built-in touch controller. When the user clicks on a specific node on the heat map, the stacked waveform display unit 710 will automatically switch to display the real-time communication waveform of that node.

Claims

1. A programmable communication analysis system for power sensors, characterized in that, include: The dynamic protocol parsing module is configured to perform logical parsing of communication data based on preset and user-defined protocol templates; The multimodal signal acquisition module has its input end connected to the communication bus and is configured to synchronously acquire physical layer signals and load monitoring signals on the communication bus. The intelligent topology identification module is communicatively connected to the dynamic protocol parsing module and is configured to send probe sequences and identify device nodes and address conflict events on the communication bus. The intelligent diagnosis and risk assessment module is connected to the dynamic protocol parsing module and the multimodal signal acquisition module, respectively, and is configured to assess the system health based on physical layer signal characteristics and protocol logic characteristics; The self-powered module is configured to provide isolated DC power, collect the current signal of the power supply circuit in real time, and output it as the load monitoring signal to the multi-mode signal acquisition module. The topology self-healing module is connected to the intelligent topology identification module and the dynamic protocol parsing module, respectively, and is configured to take over the control of the communication bus for arbitration and reconstruct the bus topology when the address conflict event is detected. The visualization diagnostic module is connected to the intelligent diagnostic and risk assessment module and the topology self-healing module, respectively, and is configured to display signal waveforms, topology structure and health status.

2. The programmable communication analysis system for power sensors according to claim 1, characterized in that, The dynamic protocol parsing module specifically includes: Protocol storage unit, used to store protocol template library containing byte order, data offset, data type and verification rules; The parameter configuration unit provides a human-machine interface to receive user configuration instructions for protocol parameters; The protocol loading unit is configured to transfer protocol data structures to the parsing buffer via the direct memory access controller; The parsing buffer adopts a double buffering mechanism, which allows the auxiliary buffer to receive new protocol configuration data while the main buffer performs the parsing of the current protocol.

3. The programmable communication analysis system for power sensors according to claim 1, characterized in that, The multimodal signal acquisition module specifically includes: The signal conditioning unit integrates three physically isolated acquisition channels and is equipped with a programmable gain amplifier to perform dynamic range management; The analog-to-digital conversion unit is configured to synchronously sample the three physically isolated acquisition channels based on a unified clock source; The signal processing unit is configured to perform anti-aliasing filtering and waveform distortion rate calculation on the sampled data; The time synchronization unit is configured to attach a uniform timestamp to the collected data.

4. The programmable communication analysis system for power sensors according to claim 1, characterized in that, The intelligent topology recognition module specifically includes: The baud rate sweep unit is configured to cyclically send a handshake signal sequence using an exponential backoff algorithm within a preset baud rate range; The address conflict detection unit is configured to perform a three-level decision process based on the instruction feature library and the response feature library, including response time consistency detection, data format compliance detection, and behavior pattern anomaly detection, in order to output a list of conflicting addresses.

5. The programmable communication analysis system for power sensors according to claim 1, characterized in that, The intelligent diagnosis and risk assessment module specifically includes: The fault feature extraction unit is configured to extract feature vectors from three dimensions: communication quality, timing behavior, and protocol compliance. The health assessment unit is configured to normalize the feature vector and calculate the system health score based on preset weights. The risk warning unit is configured to trigger a graded alarm signal based on the interval in which the system health score is located.

6. The programmable communication analysis system for power sensors according to claim 1, characterized in that, The autonomous power supply module specifically includes: The isolated power conversion unit adopts a flyback topology and a linear regulator to provide a two-stage regulated output. A load monitoring unit is connected in series in the power supply output circuit. The load monitoring unit is configured to collect the circuit current and convert it into an analog voltage value, which is then output to the multi-mode signal acquisition module. The intelligent protection unit is configured to compare the collected real-time current with a preset threshold, and cut off the output when an overcurrent or short circuit is detected, and execute an intermittent automatic restart strategy until the fault is eliminated.

7. The programmable communication analysis system for power sensors according to claim 1, characterized in that, The topology self-healing module specifically includes: The time-division multiplexing controller unit is configured to broadcast arbitration instructions to conflicting devices and allocate discrete response time slices to the conflicting devices to achieve time-division communication response; The topology reconfiguration unit is configured to calculate the electrical distance based on signal transmission delay and signal attenuation characteristics, and to construct a bus topology model.

8. The programmable communication analysis system for power sensors according to claim 7, characterized in that, The electrical distance between the topology reconstruction unit computing device and the main station is determined as follows: Subtract the preset internal processing delay constant of the device from the measured total round-trip response time to obtain the net delay time; The electrical distance is obtained by multiplying the net delay time by the nominal transmission rate of the signal in the cable and the cable aging correction factor.

9. The programmable communication analysis system for power sensors according to claim 1, characterized in that, The visualization diagnostic module specifically includes: The stacked waveform display unit is configured to synchronously present physical layer waveforms and logic layer waveforms to achieve multi-dimensional comparison. The topology heatmap generation unit is configured to generate a network topology diagram and visualize the status of topology nodes based on the system health score.

10. A programmable communication analysis system for power sensors according to claim 9, characterized in that, The stacked waveform display unit uses dual-buffered memory technology and a persistence accumulation algorithm to present the signal jitter range by superimposing historical frame data.

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