Formation method of semiconductor structure

Abstract

A forming method of a semiconductor structure comprises the steps that a substrate comprises a first region and a second region; patterning the first core material layer to form a first core layer; forming a first side wall; patterning the second core material layer to form a second core layer; performing modification treatment on the second core layer exposed in the second region to form a third core layer having an etching selection ratio with the remaining second core layer; forming a second side wall covering the side walls of the second core layer and the third core layer; the second side walls and the third core layer are used as masks to pattern the target material layer, first target structures and second target structures are formed, and the pitch of the adjacent first target structures is smaller than or equal to the pitch of the adjacent second target structures. According to the invention, the SAQP process and the SALELE process are formed at the same time, the degree of freedom of design in the patterning process is improved, and a part of redundant first target structures in the first region adopting the SAQP process can be removed under the condition that a photomask and process steps are not increased.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration. Photolithography is a commonly used patterning method and one of the most critical production technologies in semiconductor manufacturing. As the critical dimension (CD) and pitch of patterns continue to shrink, self-aligned double patterning (SADP) can no longer meet current process requirements, leading to the development of self-aligned quadruple patterning (SAQP). Generally, the smallest pitch that SADP can achieve under DUV technology is about half the single-exposure pitch limit of 76nm, or 38nm. Similarly, the limit of SAQP under DUV technology is a pitch of 19nm. While maintaining good yield, the typical SADP limit is around 40nm, and the SAQP limit is around 24nm. In the back-end process, instead of SADP or SAQP processes, self-aligned lithography (SALELE, Spacer Assisted Litho-Etch, SALELE) is often used to form metal line patterns. SALELE has the advantage of greater design freedom compared to SADP, but the limit of metal line pitch is similar to that of SADP, with a minimum pitch of about 40nm.

[0003] However, with the miniaturization of transistors and chip sizes, the pitch of back-end metal lines also needs to reach less than 40nm to 30nm or even smaller. Traditional Self-Aligned Quadruple Patterning (SAQP) can achieve smaller pitches, but like SADP, it has significant limitations in metal line layout design. Metal line layout generally needs to balance smaller and larger pitches on the same chip, as well as the freedom to freely place metal lines—something that SAQP alone struggles to provide. However, without extreme ultraviolet (EUV) lithography for exposure, achieving both pitch miniaturization and design freedom using only DUV lithography-based SAQP is relatively difficult, which also significantly limits the production of more advanced chips.

[0004] The 2015 SPIE conference paper "Impact of a SADP flow on the design and process for N10 / N7 Metal" (doi:10.1117 / 12.2085923) details the harmful effects of redundant metal lines and methods for removal in the SADP process. However, the paper primarily uses the method of adding an additional photomask to remove excess metal lines, such as... Figure 33 As shown, Figure 33 (a) The target structure for removing redundant metal lines; however, in the case of only a cut process, the only method described in the paper is as follows: Figure 33 (b) shows that redundant metal lines are retained in the final structure. Therefore, it can be seen that while processes like SADP and SAQP can create denser patterns, they are often the most tightly packed configurations, meaning there are many redundant metal lines. These metal lines do not participate in transistor interconnects, but they are difficult to remove during the manufacturing process without adding a photomask, thus affecting the capacitance between adjacent interconnecting metal lines. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which improves the design freedom in the patterning process, and can also remove redundant first target structures in the first region.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a target material layer located on the substrate, wherein a second core material layer and a first core material layer are formed on the substrate, the substrate includes a first region for forming a plurality of first target structures and a second region for forming a plurality of second target structures, wherein the first target structures and the second target structures both extend along a first direction, and the pitch of adjacent first target structures is less than or equal to the pitch of adjacent second target structures; patterning the first core material layer to form a first core layer discrete in the first region, wherein the plurality of first core layers extend along the first direction and are arranged in parallel along a second direction, the first direction being perpendicular to the second direction; forming a first sidewall covering the sidewalls of the first core layer; removing the first core layer; and in the second region... A first protective layer is formed on the two core material layers, and multiple independent openings extending along a first direction and arranged parallel to a second direction are formed in the first protective layer. The second core material layer is patterned using the first sidewall and the first protective layer as masks to form a second core layer. The first sidewall and the first protective layer are removed. A second protective layer is formed on the second core layer, and the second protective layer located in the second region is set separately. The second core layer exposed in the second region is modified using the second protective layer as a mask to form a third core layer with an etching selectivity ratio to the remaining second core layer. The second protective layer is removed. A second sidewall is formed covering the sidewalls of the second core layer and the third core layer. The second core layer is removed. The target material layer is patterned using the second sidewall and the third core layer as masks to form a first target structure located in the first region and a second target structure located in the second region.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] In the formation method provided by this embodiment of the invention, the substrate includes a first region for forming a plurality of first target structures and a second region for forming a plurality of second target structures. The pitch of adjacent first target structures is less than or equal to the pitch of adjacent second target structures. A second sidewall and a third core layer are used as a mask to pattern a target material layer, forming a first target structure in the first region and a second target structure in the second region. In this embodiment, a first core layer is formed in the first region, forming a first sidewall covering the sidewall of the first core layer. A first protective layer is formed on the second core material layer in the second region. The first protective layer has a plurality of discrete openings extending along a first direction and arranged parallel to each other along a second direction. The first sidewall and the first protective layer are used as a mask to pattern a second core material layer, forming a second core layer. For the first region, a second sidewall covering the sidewall of the second core layer is formed, and the second sidewall is used as a mask to pattern the target material layer, employing the SAQP process. The SAQP process can form first target structures with smaller pitches. For the second region, a portion of the second core layer is modified using the second protective layer as a mask, transforming it into a third core layer with an etch selectivity ratio similar to the second core layer. This forms a second sidewall covering the sidewalls of both the second and third core layers. The second sidewall and the third core layer are then used as masks to pattern the target material layer, enabling the formation of a second target structure with a larger pitch using the SALELE process. In other words, this embodiment of the invention effectively integrates the SAQP and SALELE processes, allowing the formation of both a first target structure with a smaller pitch and a second target structure with a larger pitch on the same substrate. This facilitates process integration, meeting more semiconductor process requirements and increasing design freedom in patterning processes.

[0009] In an optional embodiment, during the step of forming a second protective layer on the second core layer, a second protective layer opening is formed in the second protective layer located in the first region, exposing the second core layer. The second protective layer opening extends along a first direction. In the step of modifying the second core layer exposed in the second region using the second protective layer as a mask, the second core layer exposed by the second protective layer opening in the first region is also modified to form a third core layer located in the second region. In this embodiment of the invention, a third core layer is also formed in the first region. When the target material layer is patterned using the second sidewall and the third core layer as a mask, the target material layer corresponding to the third core layer in the first region is retained to block the formation of part of the first target structure. Therefore, in this embodiment of the invention, some redundant first target structures in the first region using the SAQP process can be removed without increasing the photomask and process steps. Attached Figure Description

[0010] Figures 1 to 32 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;

[0011] Figure 33 This is a schematic diagram comparing the target structures of two semiconductor structures. Detailed Implementation

[0012] As the background technology indicates, a common approach in back-end patterning is self-aligned lithography (also known as Spacer-Assisted Litho-Etch or SALELE process), which offers two core advantages in patterning. The first advantage is that the spacing between the metal lines defined by the two lithography steps is determined by the sidewall thickness during the process. These sidewalls are typically formed using a highly uniform atomic layer deposition (ALD) process. This ensures that the overlay between the two lithography steps does not cause changes in the spacing between adjacent metal lines, resulting in a highly uniform and consistent spacing. This opens a larger process window for reliability testing, such as time-dependent dielectric breakdown (TDDB) and breakdown voltage (VBD). The second advantage is that the tip-to-tip cut of the metal lines defined by the two Lithos can be formed very small using other photomasks to create patterning cuts, and the cuts corresponding to the first Litho and the second Litho can be made without interfering with each other. This is also known in the industry as the self-aligned block process.

[0013] The above two advantages are why SALELE balances process difficulty and provides great design freedom in the later-stage patterning. There are various similar solutions for the SALELE process, such as the process solution shown in CN111640668B, and the process solution disclosed in US10991596B2.

[0014] However, in general, the smallest pattern feature pitch formed by a single immersion DUV (ArFi) lithography is about 80nm. Therefore, SALELE can achieve a minimum pattern pitch of 38nm to 40nm using DUV equipment, while more advanced chips require smaller pitches, such as 32nm, 28nm, 24nm, etc.

[0015] In traditional fin patterning, SAQP (Self-Regulating Qt) is typically used when the pitch reaches around 30nm. This is because SADP (Self-Regulating Difference) can only form fins with a minimum pitch of 38nm, requiring a repeat of SADP to become SAQP. SAQP technology effectively meets the needs of fin patterning because the fin patterns are relatively regular, the fin pitch within a chip region is generally fixed and regular, and the differences between regions are not significant. However, SAQP has significant limitations in back-end processes where metal lines have higher degrees of freedom. For example, in SRAM metal patterning, the metal lines formed by SAQP are difficult to match with the pattern of the first metal layer of traditional SRAM. Furthermore, the relatively fixed width of the metal lines formed by SAQP makes the design of other bypass circuits more difficult.

[0016] Therefore, it can be concluded that in the current semiconductor structure, within the same region, back-end patterning struggles to balance smaller pitch with design freedom, making it difficult to meet the demands of various semiconductor processes and consequently hindering the improvement of design freedom in patterning processes. Furthermore, traditional SAQP processes struggle to remove redundant metal lines without adding a photomask. In other words, SAQP processes often produce the densest metal line arrangement, and the spacing between these densely packed lines is fixed, determined by the second sidewall in the SAQP process. However, metal winding often requires not only providing a smaller metal pitch but also considering smaller in-layer capacitance. The 2015 SPIE conference paper "Impact of a SADPflow on the design and process for N10 / N7 Metal" (doi:10.1117 / 12.2085923) details the harmful effects of redundant metal lines and methods for removal in SADP processes. However, the paper primarily uses the method of adding an additional photomask to remove excess metal lines, such as... Figure 33 As shown, Figure 33 (a) The target structure for removing redundant metal lines; however, in the case of only a cut process, the only method described in the paper is as follows: Figure 33 (b) shows that all redundant metal lines are retained in the final structure.

[0017] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a target material layer located on the substrate, forming a second core material layer on the substrate and a first core material layer located on the second core material layer, the substrate including a first region for forming a plurality of first target structures and a second region for forming a plurality of second target structures, wherein the first target structures and the second target structures both extend along a first direction, and the pitch of adjacent first target structures is less than or equal to the pitch of adjacent second target structures; patterning the first core material layer to form a first core layer discrete in the first region, the plurality of first core layers extending along the first direction and arranged parallel to each other along a second direction, the first direction being perpendicular to the second direction; forming a first sidewall covering the sidewalls of the first core layer; removing the first core layer; and in the second region... A first protective layer is formed on the second core material layer, and a plurality of separate openings extending along a first direction and arranged parallel to a second direction are formed in the first protective layer. The second core material layer is patterned using the first sidewall and the first protective layer as masks to form a second core layer. The first sidewall and the first protective layer are removed. A second protective layer is formed on the second core layer, and the second protective layer located in the second region is separately arranged. The second core layer exposed in the second region is modified using the second protective layer as a mask to form a third core layer with an etching selectivity ratio to the remaining second core layer. The second protective layer is removed. A second sidewall is formed covering the sidewalls of the second core layer and the third core layer. The second core layer is removed. The target material layer is patterned using the second sidewall and the third core layer as masks to form a first target structure located in the first region and a second target structure located in the second region.

[0018] In this embodiment of the invention, a first core layer is formed in a first region, forming a first sidewall covering the sidewalls of the first core layer. A first protective layer is formed on the second core material layer in the second region. The first protective layer has multiple discrete openings extending along a first direction and arranged parallel to each other along a second direction. The second core material layer is patterned using the first sidewall and the first protective layer as a mask to form the second core layer. For the first region, a second sidewall is formed covering the sidewalls of the second core layer. The target material layer is patterned using the second sidewall as a mask, employing the SAQP process. The SAQP process can form a first target structure with a small pitch. For the second region, a portion of the second core layer in the second region is modified using the second protective layer as a mask, transforming a portion of the second core layer into a third core layer with an etching selectivity ratio to the second core layer. A second sidewall is formed covering the sidewalls of the second and third core layers. The target material layer is patterned using the second sidewall and the third core layer as a mask, employing the SALELE process to form a second target structure with a larger pitch. In other words, the embodiments of the present invention can effectively integrate the SAQP process and the SALELE process, enabling the formation of both a first target structure with a small pitch and a second target structure with a large pitch on the same substrate. This facilitates process integration, meets more semiconductor process requirements, and increases the design freedom in patterning processes.

[0019] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0020] Figures 1 to 32 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0021] refer to Figure 1 A substrate 100 is provided, including a substrate 180 and a target material layer 170 located on the substrate 180. A second core material layer 200 is formed on the substrate 100, and a first core material layer 400 is located on the second core material layer 200. The substrate 100 includes a first region 100a for forming a plurality of first target structures and a second region 100b for forming a plurality of second target structures, wherein the first target structures and the second target structures are both along a first direction (e.g., Figure 1 Extending in the X direction, the pitch of the adjacent first target structure is less than or equal to the pitch of the adjacent second target structure.

[0022] The substrate 100 provides the basis for the process operation of forming semiconductor structures. These semiconductor structures include metal interconnects, barrier layers, adhesion layers, and cap layers.

[0023] In this embodiment, the substrate 180 is a wafer on which transistors and some interconnects are formed.

[0024] In this embodiment, the substrate 100 includes a first region 100a for forming a plurality of first target structures and a second region 100b for forming a plurality of second target structures, wherein the pitch of adjacent first target structures is less than or equal to the pitch of adjacent second target structures.

[0025] It should be noted that during the formation of a semiconductor structure, a relatively dense first target structure and a relatively sparse second target structure need to be formed. That is, the pitch between adjacent first target structures is less than or equal to the pitch between adjacent second target structures. While the SAQP process can form a relatively dense target structure, it is difficult to form a relatively sparse one. Furthermore, the pitch between target structures is relatively fixed and difficult to adjust freely according to the layout requirements. The SALELE process can define the pitch between target structures according to the layout, and the pitch is easily adjustable. It also enables self-aligned block lithography, but it is difficult to form a relatively dense target structure (pitch less than 38nm). Specifically, this embodiment uses the SAQP process to realize the first region 100a, and simultaneously uses a self-aligned lithography (SALELE) process to realize the second region 100b. Therefore, in this embodiment, the substrate 100 includes a first region 100a for forming a plurality of first target structures and a second region 100b for forming a plurality of second target structures. This means that this embodiment can simultaneously form a first target structure with a small pitch that is difficult to form by the SALELE process and a second target structure with a large pitch that is difficult to form by the SAQP process on the same substrate 100 (e.g., the same wafer), allowing for more flexible design.

[0026] In this embodiment, the first region 100a includes a logic device region, and the second region 100b includes a peripheral device region. The graphics in the logic device region are denser, while the graphics in the peripheral device region are sparser. Specifically, the logic device region includes device regions such as a central processing unit (CPU) and a graphics processing unit (GPU), while the peripheral device region includes device regions such as static random-access memory (SRAM) and input / output (IO) devices.

[0027] In this embodiment, the minimum pitch of adjacent first target structures is 24nm to 38nm; the minimum pitch of adjacent second target structures is 38nm to 200nm.

[0028] The minimum pitch refers to the sum of the minimum width of the first target structure and the minimum spacing between adjacent first target structures when the first target structure and the second target structure are subsequently formed.

[0029] Therefore, it can be seen that the first target structure can be formed by SAQP process and the second target structure can be formed by SALELE process, forming the first target structure with a minimum pitch of 24nm to 38nm and the second target structure with a minimum pitch of 38nm to 200nm in the same substrate 100.

[0030] In this embodiment, the thickness of the gate oxide layer in the logic device region is less than the thickness of the gate oxide layer in the peripheral device region. Generally, the operating voltage of CPU or GPU transistors is lower than that of transistors in the I / O device region; for example, the operating voltage of a CPU transistor is 0.75V, while the operating voltage of transistors in the I / O device region is 1.2V or even 1.8V. Therefore, typically, for the sake of reliability and electrical performance of transistors in the I / O device region, the gate oxide layer of transistors in the I / O device region is thicker than that in the logic device region. This difference in thickness mainly comes from the thickness of the interface layer (i.e., silicon oxide layer) between the high-k dielectric (High-K, HK) dielectric layer and the transistor channel in the High-K Metal Gate (HKMG). In other words, the interface layer in the gate oxide layer of the logic device region is thinner than the interface layer in the I / O device region, while the HK dielectric layer above the interface layer in both regions is the same thickness. The interface layer and the HK dielectric layer together form the gate dielectric layer of the corresponding transistor, thus the thickness of the gate oxide layer in the logic device region is less than that in the peripheral device region.

[0031] The target material layer 170 is used to provide a process platform for forming the first target structure and the second target structure.

[0032] In this embodiment, in the step of providing the substrate 100, the target material layer 170 is a dielectric layer, the first target structure is a first trench, and the second target structure is a second trench.

[0033] The first and second trenches provide space for subsequent processes, and the target material layer 170 is a dielectric layer used to isolate the structures formed in the first and second trenches.

[0034] In this embodiment, the dielectric layer material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, silicon carbonitride, LK (low-K dielectric layer) and ULK (ultralow-K dielectric layer).

[0035] In this embodiment, during the step of providing the substrate 100, a mask material layer 110 is also formed between the target material layer 170 and the second core material layer 200.

[0036] The mask material layer 110 is used to subsequently form the second pattern transfer layer.

[0037] Specifically, in this embodiment, the mask material layer 110 has a stacked structure, including a titanium nitride layer and a silicon oxide layer located on the titanium nitride layer.

[0038] The second core material layer 200 is used to subsequently form the second core layer, the third core layer, and the fourth core layer.

[0039] In this embodiment, after the second and fourth core layers are formed, they will be removed subsequently. Therefore, the material of the second core material layer 200 is an easily removable material, thereby reducing the difficulty of removing the second and fourth core layers and minimizing damage to other film layers located below the second core material layer 200. Therefore, the material of the second core material layer 200 includes one or more of amorphous silicon, polycrystalline silicon, monocrystalline silicon, silicon oxide, advanced patterning film (APF) materials, spin-on carbon (SOC), and silicon carbide. In this embodiment, the material of the second core material layer 200 is amorphous silicon (a-Si).

[0040] In this embodiment, during the step of providing the substrate 100, an etch stop layer 300 is also formed between the first core material layer 200 and the second core material layer 400.

[0041] The etch stop layer 300 is used to form the first pattern transfer layer in the future. The etch stop layer 300 is also used as an etch stop layer when the first core material layer 400 is patterned in the future, and protects the second core material layer 200 from damage.

[0042] In this embodiment, the etching stop layer 300 is made of one or more of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, titanium, titanium oxide, titanium nitride, tantalum, tantalum oxide, tantalum nitride, boron nitride, copper nitride, aluminum nitride, and tungsten nitride. In this embodiment, the etching stop layer 300 is made of silicon oxide.

[0043] The first core material layer 400 is used to form the first core layer in the subsequent process.

[0044] In this embodiment, after the first core layer is formed, it will be removed subsequently. Therefore, the material of the first core material layer 400 is one that is easy to remove, thereby reducing the difficulty of removing the first core layer and minimizing damage to other film layers located below the first core material layer 400. Therefore, the material of the first core material layer 400 includes one or more of amorphous silicon, polycrystalline silicon, monocrystalline silicon, silicon oxide, advanced patterning film (APF) materials, spin-on carbon (SOC), and silicon carbide. In this embodiment, the material of the first core material layer 400 is amorphous silicon (a-Si).

[0045] Reference Figure 2 and Figure 3 The first core material layer 400 is graphically represented to form a first core layer 410 discrete in the first region 100a. Multiple first core layers 410 extend along a first direction and are arranged in parallel along a second direction, with the first direction perpendicular to the second direction.

[0046] The first core layer 410 is used to provide support for the subsequent formation of the first sidewall.

[0047] In this embodiment, the first core material layer 400 is patterned using a dry etching process. Dry etching of amorphous silicon is relatively easy to stop on the silicon oxide material, which serves as the first etching stop layer 300 in this embodiment.

[0048] Dry etching is a dry etching process with anisotropic etching characteristics. Its longitudinal etching rate is much greater than its transverse etching rate. Therefore, by selecting the dry etching process, it is beneficial to improve the pattern transfer accuracy. At the same time, dry etching is more directional, which is beneficial to improve the sidewall morphology quality and dimensional accuracy of the first core layer 410.

[0049] Accordingly, in this embodiment, the material of the first core layer 410 is amorphous silicon (a-Si), which reduces damage to the etch stop layer 300 during the patterning of the first core material layer 400. After the first core material layer 400 is patterned, the etch stop layer 300 still maintains good dimensional and morphological accuracy. Furthermore, the first core layer 410 is made of an easy-to-remove material, and the subsequent removal of the first core layer 410 has little impact on the etch stop layer 300.

[0050] It should be noted that in this embodiment, the size and pitch of the first core layer 410 are set according to the size and pitch of the first target structure subsequently formed in the first region 100a.

[0051] refer to Figure 2The step of graphically representing the first core material layer 400 includes forming a first mask layer 320 discretely distributed on the first core material layer 400 in the first region 100a.

[0052] The first mask layer 320 is used as an etching mask for patterning the first core material layer 400.

[0053] In this embodiment, the first mask layer 320 includes a SOC layer, an anti-reflective coating (Si-ARC) on the SOC, and a photoresist layer on the anti-reflective coating (Si-ARC). The first mask layer 320 can be formed by photolithography and several etching steps.

[0054] refer to Figure 3 The first core material layer 400 is patterned along the first mask layer 320 to form the first core layer 410 discrete in the first region 100a.

[0055] In this embodiment, after forming the first core layer 410, the method further includes: removing the first mask layer 320.

[0056] Remove the first mask layer 320 to prepare for the subsequent formation of the first sidewall.

[0057] Reference Figure 4 and Figure 5 This forms the first sidewall 510, which covers the sidewall of the first core layer 410.

[0058] The first sidewall 510 is used as an etching mask for the subsequent patterning of the second core material layer 200.

[0059] In this embodiment, the material of the first sidewall 510 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0060] Titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide can form a good etching selectivity with the first core layer 410, thereby reducing damage to the first sidewall 510 in the subsequent step of removing the first core layer 410.

[0061] Specifically, refer to Figure 4 The step of forming a first sidewall 510 covering the sidewalls of the first core layer 410 includes forming a first sidewall material layer 500 covering the sidewalls and top of the first core layer 410 and the top of the second core material layer 200.

[0062] Specifically, in this embodiment, the first sidewall material layer 500 covers the sidewalls and top of the first core layer 410, as well as the top of the etching stop layer 300.

[0063] The first sidewall material layer 500 is used to directly form the first sidewall 510. Accordingly, the material of the first sidewall material layer 500 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0064] In this embodiment, an atomic layer deposition process is used to form a first sidewall material layer 500 covering the sidewalls and top of the first core layer 410 and the top of the etch stop layer 300.

[0065] The first sidewall material layer 500 formed by atomic layer deposition has good thickness uniformity and good step coverage, which enables the first sidewall material layer 500 to cover the sidewalls and top of the first core layer 410 and the top of the second core material layer 200 in good conformal manner.

[0066] refer to Figure 5 Remove the first sidewall material layer 500 located on top of the first core layer 410 and above the second core material layer 200, and retain the first sidewall material layer 500 located on the sidewall of the first core layer 410 as the first sidewall 510.

[0067] Specifically, in this embodiment, the first sidewall material layer 500 located on top of the first core layer 410 and the etching stop layer 300 is removed.

[0068] In this embodiment, a dry etching process is used to remove the first sidewall material layer 500 at the top of the first core layer 410 and the top of the etching stop layer 300.

[0069] Dry etching is an anisotropic dry etching process. Therefore, by selecting the dry etching process, it is beneficial to reduce the damage to the first core layer 410 and the etching stop layer 300. At the same time, dry etching is more directional, which is beneficial to improve the sidewall morphology quality and dimensional accuracy of the first sidewall 510.

[0070] refer to Figure 6 Remove the first core layer 410.

[0071] The first core layer 410 is removed to prepare for the subsequent patterning etching of the stop layer 300 and the second core material layer 200 using the first sidewall 510 as a mask.

[0072] In this embodiment, a wet etching process is used to remove the first core layer 410.

[0073] Wet etching has the characteristics of isotropic etching, which is beneficial to completely remove the first core layer 410. Moreover, wet etching has relatively low cost and simple operation steps, and can achieve a large etching selectivity, which helps to reduce damage to the first sidewall 510 during the removal of the first core layer 410.

[0074] refer to Figure 7 Before the first protective layer is formed on the second core material layer 200 of the second region 100b, the process also includes: using the first sidewall 510 as a mask to pattern an etch stop layer 300 to form a first pattern transfer layer 310.

[0075] The first pattern transfer layer 310 is used as an etching mask for the second core material layer 200 of the subsequent patterning of the first region 100a.

[0076] Reference Figure 8 and Figure 9 A first protective layer 610 is formed on the second core material layer 200 of the second region 100b. The first protective layer 610 has a plurality of separate first protective layer openings 620 extending in the first direction and arranged in parallel in the second direction.

[0077] The first protective layer 610 is used as an etching mask for the subsequent patterning of the second core material layer 200.

[0078] In this embodiment, the first protective layer 610 is patterned from the planarization layer. The material of the first protective layer 610 includes spin-on carbon (SOC) material or spin-on carbon and a residual portion of the second mask layer 330. Whether the second mask layer 330 remains is related to the process selection and does not affect subsequent steps. Spin-on carbon is formed by a spin coating process, which has a low process cost. Moreover, by using spin-on carbon, it is beneficial to improve the flatness of the top surface of the planarization layer, thereby providing a good interface for the formation of the first protective layer 610.

[0079] refer to Figure 8 The step of forming a first protective layer 610 on the second core material layer 200 of the second zone 100b includes: forming a first protective material layer 600 covering the second core material layer 200, the first sidewall 510, and the sidewall of the first graphic transfer layer 310.

[0080] In this embodiment, a second mask layer 330 is also formed on the first protective material layer 600. The second mask layer 330 exposes the first protective material layer 600 in the first region 100a and is located on the first protective material layer 600 in the second region 100b.

[0081] The second mask layer 330 is used to pattern the first protective material layer 600.

[0082] In this embodiment, the second mask layer 330 includes an anti-reflective coating (Si-ARC) and a photoresist layer located on the anti-reflective coating (Si-ARC).

[0083] It should be noted that in this embodiment, a single photomask and related photolithography and etching processes are used to pattern the second mask layer 330 located in the first region 100a and the second region 100b. The first protective material layer 600 is patterned using the second mask layer 330 to form the first protective layer 610. Then, the first protective layer 610 located in the second region 100b and the first sidewall 510 located in the first region are used as masks to pattern the second core material layer 200 to form the second core layer 220. Because the process of using a single photomask to define and form the second mask layer 330 offers high flexibility and diverse patterns, the design is relatively free within the limits allowed by a single photolithography operation. That is, the size and pitch of the first protective layer opening 620 within the first protective layer 610 are relatively free, as long as they meet the limits of single DUV photolithography, such as a pitch greater than approximately 76nm. Correspondingly, the design of the groove formed by the second sidewall material layer supported by the sidewall of the second core layer 220 is relatively free in terms of size and pitch. This allows for the acquisition of second target structures with larger pitches in the second zone 100b, and increases the degree of freedom in graphical design.

[0084] refer to Figure 9 The first protective material layer 600 located in the second region 100b is graphically represented, and the first protective material layer 600 in the first region 100a is removed to form a first protective material layer 600 separate in the second region 100b as the first protective layer 610.

[0085] Specifically, in this embodiment, the second mask layer 330 is used as the etching mask to pattern the first protective material layer 600.

[0086] In this embodiment, after forming the first protective material layer 600 discretely located in the second region 100b as the first protective layer 610, the method further includes: removing the second mask layer 330.

[0087] refer to Figure 10 The second core material layer 200 is patterned using the first sidewall 510 and the first protective layer 610 as a mask to form the second core layer 220.

[0088] Specifically, the second core layer 220 formed in the first region 100a has the same shape as the first sidewall 510, extending along the first direction and arranged in parallel along the second direction, and the second core layer 220 formed in the second region 100b has the same opening shape as the first protective layer opening 620, extending along the first direction and arranged in parallel along the second direction.

[0089] The second core layer 220 is used to provide support for the subsequent formation of the second sidewall.

[0090] Accordingly, in this embodiment, the material of the second core layer 220 is amorphous silicon (a-Si).

[0091] In this embodiment, in the step of patterning the second core material layer 200 using the first sidewall 510 and the first protective layer 610 as a mask to form the second core layer 220, the second core material layer 200 of the first region 100a is patterned using the first pattern transfer layer 310 as a mask to form the second core layer 220 discrete in the first region 100a.

[0092] Using the first pattern transfer layer 310 as a mask to pattern the second core material layer 200 of the first region 100a, forming the second core layer 220 discrete in the first region 100a, is beneficial to improving the pattern transfer accuracy, thereby improving the pattern size accuracy of the second core layer 220.

[0093] It should be noted that the second core layer 220 of the first region 100a is derived from the first sidewall 510. The pitch of the first sidewall 510 has been halved based on the pitch of the first mask layer 320. This is also a SADP process, achieving a reduction from the single DUV lithography etching limit of approximately 80nm to approximately 40nm. This prepares for the subsequent formation of the second sidewall on the sidewall of the second core layer, achieving a further halving of the second sidewall pitch compared to the first sidewall 510. This is also a characteristic of the SAQP process, and the reason why SAQP can form patterns with a pitch of approximately 24nm.

[0094] Reference Figure 10 and Figure 11 Remove the first sidewall 510 and the first protective layer 610.

[0095] Remove the first sidewall 510 and the first protective layer 610 to prepare for the subsequent formation of the second protective layer.

[0096] In this embodiment, the first protective layer 610 is removed by etching.

[0097] In this embodiment, either isotropic or anisotropic etching processes can be used. It is only necessary to ensure the etching selectivity of the etching process so that the etching selectivity of the first protective layer 610 and the second core layer 220 is large, thereby reducing the damage to the second core layer 220 during the removal of the first protective layer 610.

[0098] In this embodiment, after forming the second core layer 220, the method further includes removing the first graphics transfer layer 310.

[0099] Remove the first graphic transfer layer 310 to prepare for the subsequent formation of the second sidewall.

[0100] In this embodiment, a wet etching process is used to remove the first sidewall 510 and the first pattern transfer layer 310.

[0101] Wet etching has the characteristics of isotropic etching, which is beneficial for removing the first sidewall 510 and the first pattern transfer layer 310 cleanly. Moreover, wet etching has a relatively low cost and simple operation steps, and can achieve a large etching selectivity, which helps to reduce damage to the second core layer 220 during the removal of the first sidewall 510 and the first pattern transfer layer 310.

[0102] Reference Figure 12 and Figure 13 A second protective layer 710 is formed on the second core layer 220, and the second protective layer 710 located in the second region 100b is separately provided.

[0103] The second protective layer 710 of the first region 100a is used to cover the first region 100a and protect the second core layer 220 of the first region 100a from damage. The second protective layer 710 of the second region 100b is used as an implantation mask for subsequent ion implantation of the second core layer 220 of the second region 100b.

[0104] In this embodiment, during the step of forming the second protective layer 710 on the second core layer 220, a second protective layer opening 720 is also formed in the second protective layer 710 located in the first region 100a, exposing the second core layer 220, and the second protective layer opening 720 extends along the first direction.

[0105] The second protective layer opening 720 exposes part of the second core layer 220, allowing the subsequently exposed second core layer 220 to undergo modification treatment.

[0106] In other embodiments, in the step of forming a second protective layer on the second core layer, the second protective layer covers the second core layer of the first region, that is, the second protective layer completely covers the second core layer of the first region without forming an opening in the second protective layer in the first region.

[0107] In this embodiment, the material of the second protective layer 710 includes spin-on carbon (SOC) material.

[0108] Specifically, refer to Figure 12 The step of forming a second protective layer 710 that is separate on the second core layer 220 of the second region 100b and covers the second core layer 220 of the first region 100a includes: forming a second protective material layer 700 covering the second core layer 220.

[0109] The second protective material layer 700 is used to form the second protective layer 710.

[0110] Accordingly, in this embodiment, the second protective material layer 700 is a planarization layer, and the material of the second protective material layer 700 includes spin-on carbon (SOC) material. Spin-on carbon is formed by a spin coating process, which has a low process cost; moreover, by using spin-on carbon, it is beneficial to improve the flatness of the top surface of the second protective material layer 700, thereby providing a good interface for the formation of the first protective layer.

[0111] In this embodiment, a third mask layer 340 is also formed on the second protective material layer 700. The third mask layer 340 covers the second protective material layer 700 of the first region 100a and is separate from the second protective material layer 700 of the second region 100b. A mask opening extending in the first direction is formed in the third mask layer 340 of the first region 100a.

[0112] The third mask layer 340 is used to pattern the second protective material layer 700.

[0113] In this embodiment, the third mask layer 340 includes an anti-reflective coating (Si-ARC) and a photoresist layer located on the anti-reflective coating (Si-ARC).

[0114] refer to Figure 13 The second protective material layer 700 is graphically located in the second region 100b, and a separate second protective layer 710 is formed on the second core layer 220 in the second region 100b. The second protective layer 710 is formed in the first region 100a, covering the second core layer 220 and having a second protective layer opening 720 that exposes the second core layer 220.

[0115] Specifically, in this embodiment, the third mask layer 340 is used as the etching mask to pattern the second protective material layer 700.

[0116] refer to Figure 14 Using the second protective layer 710 as a mask, the second core layer 220 exposed in the second region 100b is modified to form a third core layer 230 with an etching selectivity ratio to the remaining second core layer 220.

[0117] The second core layer 220 exposed in the second region 100b is modified to obtain a third core layer 230 with an etching selectivity ratio to the second core layer 220, which makes it easier to remove the remaining second core layer 220 in the future. At the same time, the damage to the third core layer 230 is reduced during the removal of the remaining second core layer 220. The third core layer 230 is used to prepare for the subsequent patterning of the target material layer 170 in the second region 100b.

[0118] In this embodiment, in the step of modifying the second core layer 220 exposed in the second region 100b using the second protective layer 710 as a mask, the second core layer 220 exposed in the second protective layer opening 720 in the first region 100a is also modified to form a third core layer 230 located in the first region 100a, so that the third core layer 230 in the first region 100a is retained in the subsequent removal of the second core layer 220.

[0119] In this embodiment, a third core layer 230 is also formed in the first region 100a. When the target material layer 170 is patterned using the second sidewall and the third core layer 230 as a mask, the target material layer 170 corresponding to the third core layer 230 in the first region 100a is retained to block the formation of part of the first target structure. Therefore, in this embodiment, some redundant first target structures in the first region 100a using the SAQP process can be removed without adding photomasks and process steps.

[0120] Specifically, in this embodiment, in the step of modifying the second core layer 220 exposed in the second region 100b using the second protective layer 710 as a mask, the second core layer 220 exposed in the second region 100b is subjected to ion implantation treatment using the second protective layer 710 as a mask to form a third core layer 230 having an etching selectivity ratio with the remaining second core layer 220.

[0121] Ion implantation technology has the advantages of uniform large-area ion implantation, more accurate control of ion doping depth and high repeatability. Using ion implantation to obtain the third core layer 230 is beneficial for precise control of the doping concentration and distribution of the third core layer 230, as well as the penetration depth of the second core layer 220, so that the ion distribution in the third core layer 230 is more uniform.

[0122] Accordingly, in this embodiment, in the step of modifying the second core layer 220 exposed in the second region 100b using the second protective layer 710 as a mask, the second core layer 220 exposed in the first region 100a is also subjected to ion implantation using the second protective layer 710 as a mask to form a third core layer 230 having an etching selectivity ratio with the remaining second core layer 220.

[0123] In this embodiment, in the step of performing ion implantation on the exposed second core layer 220 of the second region 100b using the second protective layer 710 as a mask, the ions implanted in the ion implantation process include one or more of boron, phosphorus, arsenic, boron chloride, boron dichloride and carbon.

[0124] In this embodiment, the material of the second core layer 220 is amorphous silicon. Implanting one or more ions from boron, phosphorus, arsenic, boron chloride, boron dichloride and carbon into the second core layer 220 can transform the amorphous silicon into a material with a higher etch selectivity than the amorphous silicon, thereby obtaining a third core layer 230 with a higher etch selectivity than the second core layer 220.

[0125] Accordingly, in this embodiment, the material of the second core layer 220 is amorphous silicon (a-Si), and the material of the third core layer 230 is amorphous silicon doped with boron, phosphorus or arsenic.

[0126] It should be noted that in this embodiment, a photomask and photolithography etching process are used to pattern the third mask layer 340 located in the second region 100b and the third mask layer 340 located in the first region 100a. The second protective material layer 700 is patterned using the third mask layer 340 to form the second protective layer 710. Then, the second core layer 220 is ion implanted using the second protective layer 710 as a mask to form the third core layer 230 with an etching selectivity ratio to the second core layer 220. The process of forming the second protective layer 710 has high flexibility, and the width and pitch of the second protective layer 710 are easy to adjust. Correspondingly, the width and pitch of the remaining second core layers 220 located in the second region 100b are easy to adjust, thereby enabling the acquisition of some second target structures with larger pitches in the second region 100b and improving the design freedom of patterning.

[0127] Specifically, in this embodiment, in the step of modifying the exposed second core layer 220 of the second region 100b using the second protective layer 710 as a mask, the remaining second core layer 220 is along the second direction (e.g., Figure 15 The dimensions of the third core material layer 230 (shown in the Y direction) are 35nm to 200nm and the pitch is 76nm to 200nm. The dimensions of the third core material layer 230 along the second direction are 35nm to 200nm and the pitch is 76nm to 200nm.

[0128] refer to Figure 15 Remove the second protective layer 710 and the third mask layer 340.

[0129] Remove the second protective layer 710 to prepare for the subsequent removal of the second core layer 220.

[0130] In this embodiment, a dry etching process is used to remove the second protective layer 710.

[0131] In this embodiment, either isotropic or anisotropic etching processes can be used. It is only necessary to ensure the etching selectivity of the etching process, so that the etching process has a large etching selectivity for the second protective layer 710 and the second core layer 220, as well as for the second protective layer 710 and the third core layer 230, thereby reducing the damage to the second core layer 220 and the third core layer 230 during the removal of the second protective layer 710.

[0132] Reference Figure 16 and Figure 17 After removing the second protective layer 710, before forming the second sidewall covering the sidewalls of the second core layer 220 and the third core layer 230, the system further includes: a portion of the second core layer 220 of the first region 100a and a portion of the second core layer 220 and the third core layer 230 of the second region 100b, forming a first partition opening 910 that cuts off the second core layer 220 of the first region 100a in a first direction, and a second partition opening 920 that cuts off a portion of the second core layer 220 in a first direction.

[0133] The first partition opening 910 is used to subsequently form the first partition structure, and the second partition opening 920 is used to subsequently form the second partition structure.

[0134] Specifically, in this embodiment, the steps of graphically representing a portion of the second core layer 220 of the first region 100a, and a portion of the second core layer 220 and the third core layer 230 of the second region 100b, forming a first partition opening 910 that cuts off the second core layer 220 of the first region 100a in a first direction, and a second partition opening 920 that cuts off the second core layer 220 of the second region 100b in a first direction, include: referring to Figure 16 A third protective layer 350 is formed, covering the second core layer 220 and the third core layer 230. A fourth mask layer 360 is also formed on the third protective layer 350. The fourth mask layer 360 has openings 361 formed in the fourth mask layer 360, which span the second core layer 220 in the first region 100a along the second direction and the second core layer 220 in the second region 100b. (Reference) Figure 17 The second core layer 220 is patterned along the fourth mask layer opening 361 and through the third protective layer 350, forming a first partition opening 910 that cuts through the second core layer 220 of the first region 100a in the first direction, and a second partition opening 920 that cuts through the second core layer 220 of the second region 100b in the first direction.

[0135] In this embodiment, the third protective layer 350 is a planarization layer, and the material of the third protective layer 350 includes spin-coated carbon (SOC). Spin-coated carbon is formed by a spin coating process, which has a low process cost; moreover, by using spin-coated carbon, it is beneficial to improve the flatness of the top surface of the third protective layer 350, thereby providing a good interface for the formation of the fourth mask layer 360.

[0136] The fourth mask layer 360 is used to pattern the second core layer 220 and the fourth core layer 240 through the third protective layer 350.

[0137] In this embodiment, the fourth mask layer 360 includes an anti-reflective coating (Si-ARC) and a photoresist layer located on the anti-reflective coating (Si-ARC).

[0138] Continue to refer to Figure 17 After forming the first partition opening 910 that cuts through the second core layer 220 of the first region 100a in the first direction and the second partition opening 920 that cuts through the second core layer 220 of the second region 100b in the first direction, the method further includes: removing the third protective layer 350 and the fourth mask layer 360.

[0139] It should be noted that in actual manufacturing processes, the above can be repeated based on specific process requirements. Figure 16 and Figure 17 The steps involve forming multiple first partition openings 910 and second partition openings 920 at the target location.

[0140] As an example, in this embodiment, the steps of forming the first partition opening 910 and the second partition opening 920 are performed twice, as follows: Figure 18 and Figure 19 As shown, a third protective layer 350 is formed covering the second core layer 220 and the third core layer 230. A fourth mask layer 360 is also formed on the third protective layer 350. The fourth mask layer 360 has a fourth mask layer opening 361 that spans the second core layer 220 in the first region 100a along the second direction and spans the second core layer 220 in the second region 100b. The second core layer 220 is patterned through the third protective layer 350 along the fourth mask layer opening 361, forming a first partition opening 910 that cuts through the second core layer 220 in the first region 100a in the first direction and a second partition opening 920 that cuts through the second core layer 220 in the second region 100b in the first direction.

[0141] Reference Figures 20 to 26 This forms a second sidewall 810 that covers the sidewalls of the second core layer 220 and the third core layer 230.

[0142] The second sidewall 810 is used as a partial etching mask for the target material layer 170 of the subsequent patterning of the first region 100a and the second region 100b.

[0143] In this embodiment, the material of the second sidewall 810 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0144] Titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide can form a good etching selectivity with the second core layer 220 and the third core layer 230, thereby reducing damage to the second sidewall 810 in the subsequent step of removing the second core layer 220.

[0145] In this embodiment, in the step of forming the second sidewall 810 covering the sidewalls of the second core layer 220 and the third core layer 230, the second sidewall 810 also covers the sidewall of the first partition opening 910 and the sidewall of the second partition opening 920, and the second sidewall 810, which is twice as thick, is larger than the dimensions of the first partition opening 910 and the second partition opening 920 along the first direction. Therefore, the second sidewalls 810 of the sidewalls of the first partition opening 910 are in contact with each other to form the first partition structure 930, and the second sidewalls 810 of the sidewalls of the second partition opening 920 are in contact with each other to form the second partition structure 940.

[0146] The first partition structure 930 and the second partition structure 940 are used to transfer the pattern to the target material layer 170, thereby enabling the partition of the first target structure and the second target structure to be formed directly in the target material layer 170. This allows the first target structure and the second target structure to be divided to be directly divided when the target material layer 170 is subsequently patterned, while the first target structure and the second target structure are being formed in the target material layer 170.

[0147] Specifically, refer to Figure 20 The step of forming a second sidewall 810 covering the sidewalls of the second core layer 220 and the third core layer 230 includes forming a second sidewall material layer 800 covering the sidewalls and top of the second core layer 220 and the third core layer 230, as well as the top of the base 100.

[0148] The second sidewall material layer 800 is used to directly form the second sidewall 810. Accordingly, the material of the second sidewall material layer 800 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0149] In this embodiment, an atomic layer deposition process is used to form a second sidewall material layer 800 covering the sidewalls and top of the second core layer 220 and the third core layer 230, as well as the top of the substrate 100.

[0150] The second sidewall material layer 800 formed by atomic layer deposition has good thickness uniformity and good step coverage, which enables the second sidewall material layer 800 to cover the sidewalls and top of the second core layer 220 and the third core layer 230, as well as the top of the substrate 100 in good conformal manner.

[0151] In this embodiment, in the step of forming a second sidewall material layer 800 covering the sidewalls and top of the second core layer 220, the third core layer 230 and the fourth core layer 240, and the top of the base 100, the second sidewall material layer 800 is further filled with the first partition opening 910 and the second partition opening 920.

[0152] Specifically, the second sidewall material layer 800 covering the sidewalls of the second core layer 220 and the third core layer 230 serves as the second sidewall 810, the second sidewall material layer 800 filling the first partition opening 910 serves as the first partition structure 930, and the second sidewall material layer 800 filling the second partition opening 920 serves as the second partition structure 940.

[0153] In this embodiment, in the second sidewall material layer 800 that forms the sidewalls and top of the second core layer 220 and the third core layer 230, as well as the top of the base 100, the second sidewall material layer 800 located on the opposite sidewalls forms a groove 950.

[0154] It should be noted that the first partition structure 930 only blocks the first target structure corresponding to (directly below) the second core layer 220 of the first zone 100a, and does not block the groove 950 formed by the second sidewall 810 of the second core layer 220 of the first zone 100a and the first target structure corresponding to the groove 950. This is also a special feature of the SAB (self-aligned block) technology mentioned in the background art. Similarly, the second partition structure 940 only blocks the second target structure corresponding to the second core layer 220 of the second zone 100b, and does not block the second target structure corresponding to the groove 950 formed by the third core layer 230 of the second zone 100b and the second sidewall material layer 800 of the sidewall of the second core layer 220.

[0155] Reference Figures 21 to 25 After forming the second sidewall 810 covering the sidewalls of the second core layer 220 and the third core layer 230, before subsequently removing the second sidewall material layer 800 located on top of the second core layer 220 and the third core layer 230 and on top of the base 100, the method further includes: forming a third partition structure 960 extending in the second direction and contacting the second sidewall 810 in the groove 950 of the first region 100a and the second region 100b, the third partition structure 960 partitioning the groove 950 in the first direction.

[0156] The third partition structure 960 is used to transfer the pattern to the target material layer 170, thereby enabling the direct formation of partitions between the first target structure and the second target structure corresponding to the grooves 950 in the first region 100a and the second region 100b in the target material layer 170. This allows the first target structure and the second target structure to be divided to be directly partitioned while the first target structure and the second target structure to be divided are formed in the target material layer 170 after the target material layer 170 is patterned.

[0157] It should be noted that the third partition structure 960 only blocks the first target structure corresponding to (directly below) the groove 950 of the first region 100a, and does not block the first target structure corresponding to the second core layer 220 of the first region 100a. This is also a special feature of the SAB (self-aligned block) technology mentioned in the background art. Similarly, the third partition structure 960 only blocks the second target structure corresponding to the groove 950 of the second region 100b, and does not block the second target structure corresponding to the second core layer 220 of the second region 100b.

[0158] It should also be noted that in the first region 100a, the partitions transferred from the third partition structure 960 to the target material layer 170 and the partitions transferred from the first partition structure 930 to the target material layer 170 are partitions of adjacent first target structures. In the second region 100b, the partitions transferred from the third partition structure 960 to the target material layer 170 and the partitions transferred from the second partition structure 940 to the target material layer 170 are partitions of adjacent second target structures. Thus, by pre-forming the first partition structure 930, the second partition structure 940, and the third partition structure 960, adjacent first target structures or adjacent second target structures can be simultaneously partitioned in the target material layer 170, providing a better forming method for partitions with close pitch.

[0159] Specifically, in this embodiment, the step of forming a third partition structure 960 extending in the second direction and contacting the second sidewall 810 in the groove 950 of the first region 100a and the second region 100b includes: referring to... Figure 21 and Figure 22 , Figure 22 yes Figure 21 A cross-sectional view along the BB direction shows a fourth protective layer 370 that covers the second sidewall material layer 800 and fills the groove 950. A fifth mask layer 380 is also formed on the fourth protective layer 370. An opening 381 of the fifth mask layer 380 is formed in the fifth mask layer 380 that spans the groove 950 along the second direction. The fourth protective layer 370 is removed from the groove 950 at the corresponding position of the fifth mask layer opening 381 through the patterned fourth protective layer 370 along the fifth mask layer opening 381, forming a third partition opening 970.

[0160] In this embodiment, the fourth protective layer 370 is a planarization layer, and the material of the fourth protective layer 370 includes spin-coated carbon (SOC). Spin-coated carbon is formed by a spin coating process, which has a low process cost; moreover, by using spin-coated carbon, it is beneficial to improve the flatness of the top surface of the fourth protective layer 370, thereby providing a good interface for the formation of the fifth mask layer 380.

[0161] The fifth mask layer 380 is used to pattern the fourth protective layer 370 to form the third isolation opening 970.

[0162] In this embodiment, the fifth mask layer 380 includes an anti-reflective coating (Si-ARC) and a photoresist layer located on the anti-reflective coating (Si-ARC).

[0163] Reference Figure 23 and Figure 24 , Figure 24 yes Figure 23 A cross-sectional view along the BB direction shows a partition material layer 390 that fills the third partition opening 970.

[0164] The partition material layer 390 is used to form the third partition structure 960.

[0165] refer to Figure 25 After forming the partition material layer 390 that fills the third partition opening 970, it also includes: removing the fourth protective layer 370, the fifth mask layer 380 and the partition material layer 390 that is higher than the second sidewall material layer 800.

[0166] refer to Figure 26 The second sidewall material layer 800 located on top of the second core layer 220 and the third core layer 230, as well as on top of the base 100, is removed. The second sidewall material layer 800 located on the sidewalls of the second core layer 220 and the third core layer 230 is retained as the second sidewall 810. The second sidewall material layer 800 below the third partition material layer 390 within the groove 950 formed by the second sidewall material layer 800 is retained to form the third partition structure 960.

[0167] In this embodiment, a dry etching process is used to remove the second sidewall material layer 800 located on top of the second core layer 220 and the third core layer 230, as well as on top of the substrate 100.

[0168] The dry etching process is an anisotropic dry etching process. Therefore, by selecting the dry etching process, it is beneficial to reduce the damage to the second core layer 220 and the third core layer 230. At the same time, the dry etching process is more directional, which is beneficial to improve the sidewall morphology quality and dimensional accuracy of the second sidewall 810.

[0169] In this embodiment, in the step of removing the second sidewall material layer 800 located on top of the second core layer 220 and the third core layer 230, as well as on top of the base 100, the partition material layer 390 above the top of the second core layer 220 and the third core layer 230 is also removed, and the partition material layer 390 in the third partition opening 970 is retained as the third partition structure 960 for subsequent graphic transfer to the target material layer 170.

[0170] refer to Figure 27 Remove the second core layer 220.

[0171] The second core layer 220 is removed to prepare for the subsequent patterning of the target material layer 170 of the first region 100a and the second region 100b using the second sidewall 810 and the third core layer 230 as masks.

[0172] In this embodiment, a wet etching process is used to remove the second core layer 220.

[0173] Wet etching has the characteristics of isotropic etching, which is beneficial to completely remove the second core layer 220. Moreover, wet etching has relatively low cost and simple operation steps, and can achieve a large etching selectivity, which helps to reduce damage to the second sidewall 810 during the removal of the second core layer 220.

[0174] In this embodiment, in the step of removing the second core layer 220 using a wet etching process, the etching solution of the wet etching process includes one or more of KOH solution, THMA solution and SC1 solution.

[0175] In this embodiment, the second core layer 220 is undoped silicon, while the third core layer 230 is doped silicon. KOH or THMA solutions have a high etching rate for undoped silicon but almost no etching rate for doped silicon (especially doped with boron ions). Therefore, using KOH or THMA solutions as etching solutions can remove the second core layer 220 completely while minimizing damage to the third core layer 230. Furthermore, alkaline solutions such as KOH, SCl, and THMA solutions have almost no etching rate on the third partition structure 960 and the second sidewall 810 formed by the partition material layer 390. This ensures that the removal of the second core layer 220 has almost no impact on other components during the entire pattern transfer process.

[0176] It should be noted that in this embodiment, the second core layer 220 is removed, while the third core layer 230 in the second region 100b and the third core layer 230 in the first region 100a are retained.

[0177] Reference Figure 28 and Figure 29 Using the second sidewall 810 and the third core layer 230 as a mask, a target material layer 170 is patterned to form a first target structure 131 located in the first region 100a and a second target structure 141 located in the second region 100b.

[0178] Specifically, in this embodiment, the second sidewall 810, the third core layer 230, the first partition structure 930, the second partition structure 940, and the third partition structure 960 are used as mask patterning target material layers 170 to form a first target structure 131 located in the first region 100a and a second target structure 141 located in the second region 100b.

[0179] In this embodiment, a first core layer 410 is formed in a first region 100a, and a first sidewall 510 is formed covering the sidewalls of the first core layer 410. A first protective layer 610 is formed on the second core material layer 200 in the second region 100b. The first protective layer 610 has multiple discrete openings 620 extending in a first direction and arranged parallel to each other in a second direction. The second core material layer 200 is patterned using the first sidewall 810 and the first protective layer 610 as masks to form a second core layer 220. For the first region 100a, a second sidewall 810 is formed covering the sidewalls of the second core layer 220. The target material layer 170 is patterned using the second sidewall 810 as a mask, employing the SAQP process. The SAQP process can form a first target structure 131 with a small pitch. For the second region 100b, a portion of the second core layer 220 of the second region 100b is modified using the second protective layer 710 as a mask. This portion of the second core layer 220 is transformed into a third core layer 230 with an etching selectivity ratio to the second core layer 220, forming a second sidewall 810 covering the sidewalls of the second core layer 220 and the third core layer 230. The second sidewall 810 and the third core layer 230 are used as masks to pattern the target material layer 170, enabling the formation of a second target structure 141 with a larger pitch using the SALELE process. In other words, this embodiment can effectively integrate the SAQP and SALELE processes, enabling the formation of both a first target structure 131 with a smaller pitch and a second target structure 141 with a larger pitch on the same substrate 100. This facilitates process integration, meeting more semiconductor process requirements and increasing design freedom in the patterning process.

[0180] Specifically, in this embodiment, in the step of forming a first target structure 131 located in the first region 100a and a second target structure 141 located in the second region 100b by using the second sidewall 810 and the third core layer 230 as mask patterned target material layers 170, the first partition structure 930 and the second partition structure 940 are also used as mask patterned target material layers 170 to obtain a target material layer 170 corresponding to the first partition structure 930 that blocks the first target structure 131 in a first direction, and a target material layer 170 corresponding to the second partition structure 940 that blocks the second target structure 141 in a first direction.

[0181] In this embodiment, in the step of forming a first target structure 131 located in the first region 100a and a second target structure 141 located in the second region 100b by using the second sidewall 810 and the third core layer 230 as mask patterning target material layers 170, a third partition structure 960 is also used as mask patterning target material layer 170 to obtain a target material layer 170 corresponding to the third partition structure 960 that blocks the first target structure 131 and the second target structure 141 in the first direction.

[0182] In this embodiment, in the step of using the second sidewall 810 and the third core layer 230 as a mask to pattern the target material layer 170, the second sidewall 810 and the third core layer 230 are used as a mask to pattern the medium layer, forming the first trench 130 and the second trench 140 located in the medium layer.

[0183] The first trench 130 provides space for the subsequent formation of the first metal line, and the second trench 140 provides space for the subsequent formation of the second metal line.

[0184] It should be noted that the target material layer 170 obtained by the third core layer 230 in the first area 100a can isolate the first trench 130 along the first direction, so as to realize the design freedom of the first trench 130 in the first direction. Moreover, when the pattern is transferred to form the first trench 130, the pattern can be directly not transferred to the target material layer 170 at the position where the first trench 130 does not need to be formed. The process is simple and efficient.

[0185] The first trench 130 can be divided into a type A first trench 130a and a type B first trench 130b, which are spaced apart from each other. The type A first trench 130a is the first trench 130 corresponding to the fourth core layer 240, and the type B first trench 130b is the first trench 130 corresponding to the groove 950 formed by the second sidewall material layer 800 of the fourth core layer 240.

[0186] The second trench 140 can also be divided into type A second trench 140a and type B second trench 140b. Type A second trench 140a is the second trench 140 corresponding to the second core layer 220, and type B second trench 140b is the second trench 140 corresponding to the groove 950 formed by the second sidewall material layer 800 of the sidewall of the second core layer 220 and the third core layer 230.

[0187] Accordingly, in this embodiment, the dielectric layer corresponding to the first partition structure 930 blocks the type A first trench 130a in the first direction, the dielectric layer corresponding to the second partition structure 940 blocks the type A second trench 140a in the first direction, and the dielectric layer corresponding to the third partition structure 960 blocks the type B first trench 130b and the type B second trench 140b in the first direction.

[0188] Specifically, refer to Figure 28 The step of patterning the target material layer 170 using the second sidewall 810 and the third core layer 230 as a mask includes: patterning the mask material layer 110 using the second sidewall 810 and the third core layer 230 as a mask to form a second pattern transfer layer 120.

[0189] The second pattern transfer layer 120 is used as an etching mask for the patterning target material layer 170.

[0190] In this embodiment, after the second pattern transfer layer 120 is formed, before the target material layer 170 is patterned using the second pattern transfer layer 120 as a mask, the method further includes: removing the second sidewall 810 and the third core layer 230 to prepare for the subsequent patterning of the target material layer 170 using the second pattern transfer layer 120 as a mask.

[0191] refer to Figure 29 The second pattern transfer layer 120 is used as a mask to pattern the target material layer 170.

[0192] The second graphic transfer layer 120 transfers the graphics of the second sidewall 810 and the third core layer 230 to the target material layer 170, which helps to improve the graphic transfer accuracy and makes the dimensional accuracy of the first target structure 131 and the second target structure 141 higher.

[0193] It should be noted that the second pattern transfer layer 120 is used as a mask to pattern the target material layer 170 using an etching process, thereby thinning the second pattern transfer layer 120 in the step of patterning the target material layer 170, for example, by removing the silicon oxide layer in the second pattern transfer layer 120.

[0194] refer to Figure 30 After forming the first target structure 131 and the second target structure 141, the process also includes: removing the second graphics transfer layer 120.

[0195] Remove the second pattern transfer layer 120 to prepare for the subsequent formation of the first and second metal lines.

[0196] refer to Figure 31 After forming the first target structure 131 located in the first region 100a and the second target structure 141 located in the second region 100b, the forming method further includes: forming a first metal line 150 in the first trench 130; and forming a second metal line 160 in the second trench 140.

[0197] The first metal line 150 and the second metal line 160 are metal interconnects used in subsequent process steps.

[0198] It should be noted that the dielectric layer obtained by the third core layer 230 in the first region 100a can isolate the first metal line 150 in the first trench 130 along the first direction, thereby realizing the design freedom of the first metal line 150 in the first direction. Furthermore, when transferring patterns to form the first metal line 150, patterns can be directly omitted from the dielectric layer at locations where the first metal line 150 is not needed. Without adding photomasks and process steps, some redundant first metal lines 150 in the first region 100a can be removed, thereby reducing the capacitance between some first metal lines 150 in the first region 100a using the SAQP process. This improves the performance of the semiconductor structure circuit and chip (e.g., better standard cell (STC) performance), and the process is simple and efficient. Therefore, this embodiment can efficiently and cost-effectively form... Figure 33 The target structure shown in (a)

[0199] in, Figure 31 (b) indicates a distinction Figure 31 (a) The first metal wire 150 and the second metal wire 160 of different types.

[0200] Specifically, the first metal wire 150 can be divided into type A first metal wires 150a arranged at intervals (e.g., ...). Figure 31 (b) The first metal line 150 filled with black in the first area 100a (as shown in the image), and the first metal line 150b of type B (as shown in the image). Figure 31 (b) The first metal line 150 filled with white in the first area 100a is shown. Type A first metal line 150a is the metal line corresponding to the second core layer 220 in the first area 100a, and Type B first metal line 150b is the metal line corresponding to the groove 950 surrounded by the second sidewall material layer 800 of the second core layer 220 in the first area 100a.

[0201] Similarly, the second metal wire can also be classified as type A second metal wire 160a (e.g. Figure 31(b) The second metal wire 160 with white filling in the second zone 100b is shown in (b) and the second metal wire 160b of type B (as shown in the image). Figure 31 (b) The second metal line 160 filled in black in the second zone 100b is shown. Type A second metal line 160a is the metal line corresponding to the second core layer 220 in the second zone 100b, and Type B second metal line 160b is the metal line corresponding to the groove 950 formed by the second sidewall material layer 800 of the sidewalls of the second core layer 220 and the third core layer 230 in the second zone 100b. Type A second metal line 160a and Type B second metal line 160b can be set alternately, and the pitch, width and length between them can be adjusted, so the design is more flexible than that of the first metal line 150.

[0202] Accordingly, in this embodiment, the dielectric layer corresponding to the first partition structure 930 blocks the type A first metal wire 150a in the first direction, the dielectric layer corresponding to the second partition structure 940 blocks the type A second metal wire 160a in the first direction, and the dielectric layer corresponding to the third partition structure 960 blocks the type B first metal wire 150b and the type B second metal wire 160b in the first direction.

[0203] The dielectric layer is an inter-metal dielectric (IMD) layer, which is used to achieve electrical isolation between metal interconnects in the back end of line (BEOL) process.

[0204] As an example, such as Figure 32 The present invention illustrates the formation method of simultaneously forming a 6T Standard Cell, a 7.5T Standard Cell, and a memory / input / output (SRAM / IO) region on a substrate, wherein the black areas indicate the corresponding device regions.

[0205] Specifically, such as Figure 32 (a) In a 6T standard cell region, the metal pitch reaches approximately 30nm, and uniform metal lines are required for routing, along with wide power rails. Therefore, the SAQP process is used for fabrication. Figure 32 (b) In the 7.5T standard cell area, the metal pitch is around 40nm, and uniform metal lines are required for routing, along with wide power rails. Therefore, the SALELE process is used for fabrication. Figure 32(c) In the memory / input / output area, if the metal pitch is greater than 50nm and metal wiring without a clear layout rule is required, the SALELE process is used for formation. It can be seen that by using the method of this embodiment, combining SAQP and SALELE, it is possible to simultaneously realize the formation of 6T standard cell area, 7.5T standard cell area and memory / input / output area with different pitch requirements on the same substrate.

[0206] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including a substrate and a target material layer located on the substrate, a second core material layer is formed on the substrate, and a first core material layer is located on the second core material layer. The substrate includes a first region for forming a plurality of first target structures and a second region for forming a plurality of second target structures, wherein the first target structures and the second target structures both extend along a first direction, and the pitch of adjacent first target structures is less than or equal to the pitch of adjacent second target structures. The first core material layer is graphically represented to form a first core layer discrete in the first region. Multiple first core layers extend along a first direction and are arranged in parallel along a second direction, with the first direction perpendicular to the second direction. A first sidewall is formed that covers the sidewall of the first core layer; Remove the first core layer; A first protective layer is formed on the second core material layer in the second region, and a plurality of separate first protective layer openings are formed in the first protective layer extending along the first direction and arranged in parallel along the second direction. The second core material layer is patterned using the first sidewall and the first protective layer as a mask to form the second core layer; Remove the first sidewall and the first protective layer; A second protective layer is formed on the second core layer, and the second protective layer located in the second area is set separately; Using the second protective layer as a mask, the second core layer exposed in the second region is modified to form a third core layer with an etching selectivity ratio to the remaining second core layer; Remove the second protective layer; A second sidewall is formed that covers the sidewalls of the second and third core layers; Remove the second core layer; The target material layer is patterned using the second sidewall and the third core layer as a mask to form a first target structure located in the first region and a second target structure located in the second region.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, the target material layer is a dielectric layer, the first target structure is a first trench, and the second target structure is a second trench; In the step of patterning the target material layer using the second sidewall and the third core layer as a mask, the dielectric layer is patterned using the second sidewall and the third core layer as a mask to form a first trench and a second trench located in the dielectric layer. After forming the first target structure located in the first region and the second target structure located in the second region, the forming method further includes: forming a first metal wire in the first trench; A second metal wire is formed in the second trench.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, the first region includes a logic device region and the second region includes a peripheral device region.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The thickness of the gate oxide layer in the logic device region is less than the thickness of the gate oxide layer in the peripheral device region.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The minimum pitch between adjacent first target structures is 24 nm to 38 nm; the minimum pitch between adjacent second target structures is 38 nm to 200 nm.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of graphically representing the first core material layer includes: forming a first mask layer discrete on the first core material layer in the first region; The first core material layer is patterned along the first mask layer to form a first core layer discrete in the first region; After forming the first core layer, the process also includes: removing the first mask layer.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a first sidewall covering the sidewall of the first core layer includes: forming a first sidewall material layer covering the sidewall and top of the first core layer, and above the second core material layer; Remove the first sidewall material layer located on top of the first core layer and above the second core material layer, and retain the first sidewall material layer located on the sidewall of the first core layer as the first sidewall.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a first protective layer on the second core material layer in the second region includes: forming a first protective material layer covering the second core material layer and the first sidewall; The first protective material layer located in the second region is graphically represented, and the first protective material layer in the first region is removed to form a first protective material layer separate in the second region as the first protective layer.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of modifying the second core layer exposed in the second region using the second protective layer as a mask, the second core layer exposed in the second region is subjected to ion implantation treatment using the second protective layer as a mask to form a third core layer with an etching selectivity ratio to the second core layer.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of providing the substrate, the material of the second core material layer includes one or more of amorphous silicon, polycrystalline silicon, monocrystalline silicon, silicon oxide, advanced patterning materials, spin-coated carbon, and silicon carbide; In the step of performing ion implantation on the second core layer exposed in the second region using the second protective layer as a mask, the ions implanted in the ion implantation process include one or more of boron, phosphorus, arsenic, boron chloride, boron dichloride, and carbon.

11. The method for forming a semiconductor structure as described in claim 1 or 9, characterized in that, In the step of forming a second protective layer on the second core layer, the second protective layer covers the second core layer of the first region; or, In the step of forming a second protective layer on the second core layer, a second protective layer opening is formed in the second protective layer located in the first region, exposing the second core layer, and the second protective layer opening extends along the first direction; In the step of modifying the second core layer exposed in the second region using the second protective layer as a mask, the second core layer exposed in the opening of the second protective layer in the first region is also modified to form the third core layer located in the second region.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of forming a second protective layer on the second core layer, a second protective layer opening is formed in the second protective layer located in the first region, exposing the second core layer, and the second protective layer opening extends along the first direction; The step of forming a second protective layer on the second core layer includes: forming a second protective material layer covering the second core layer; The second protective material layer is graphically represented, a discrete second protective layer is formed on the second core layer in the second region, and a second protective layer is formed in the first region that covers the second core layer and has an opening in the second protective layer that exposes the second core layer.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of modifying the second core layer exposed in the second region using the second protective layer as a mask, the remaining second core layer has a size of 35nm to 200nm and a pitch of 76nm to 200nm along the second direction, and the third core layer has a size of 35nm to 200nm and a pitch of 76nm to 200nm along the second direction.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a second sidewall covering the sidewalls of the second core layer and the third core layer includes: forming a second sidewall material layer covering the sidewalls and top of the second core layer and the third core layer, as well as the top of the substrate; Remove the second sidewall material layer located on top of the second core layer and the third core layer, as well as on top of the base, and retain the second sidewall material layer located on the sidewalls of the second core layer and the third core layer as the second sidewall.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, an etch stop layer is also formed between the first core material layer and the second core material layer; Before forming the first protective layer on the second core material layer of the second region, the method further includes: using the first sidewall as a mask to pattern an etch stop layer to form a first pattern transfer layer; In the step of patterning the second core material layer using the first sidewall and the first protective layer as a mask to form the second core layer, the second core material layer of the first region is patterned using the first pattern transfer layer as a mask to form the second core layer separate from the first region. After forming the second core layer, the process also includes: removing the first graphics transfer layer.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, The second core layer was removed using a wet etching process; The etching solution used in the wet etching process includes one or more of KOH solution, THMA solution, and SC1 solution.

17. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, a mask material layer is also formed between the target material layer and the second core material layer; The step of patterning the target material layer using the second sidewall and the third core layer as a mask includes: patterning the mask material layer using the second sidewall and the third core layer as a mask to form a second pattern transfer layer; The target material layer is patterned using the second pattern transfer layer as a mask; After forming the first target structure and the second target structure, the method further includes: removing the second graphics transfer layer.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, After the second pattern transfer layer is formed, before patterning the target material layer using the second pattern transfer layer as a mask, the method further includes: removing the second sidewall and the third core layer.

19. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before forming a second sidewall covering the sidewalls of the second core layer and the third core layer after removing the second protective layer, the method further includes: graphically representing a portion of the second core layer in the first region, and a portion of the second core layer and the third core layer in the second region, forming a first partition opening that cuts off the second core layer in the first region in the first direction, and a second partition opening that cuts off the second core layer in the second region in the first direction. In the step of forming a second sidewall covering the sidewalls of the second core layer and the third core layer, the second sidewall also covers the sidewall of the first partition opening and the sidewall of the second partition opening, and the second sidewalls of the sidewalls of the first partition opening are in contact with each other to form a first partition structure, and the second sidewalls of the sidewalls of the second partition opening are in contact with each other to form a second partition structure. In the step of patterning the target material layer using the second sidewall and the third core layer as masks to form a first target structure in the first region and a second target structure in the second region, the target material layer is further patterned using the first partition structure and the second partition structure as masks to obtain a target material layer corresponding to the first partition structure that blocks the first target structure in the first direction, and a target material layer corresponding to the second partition structure that blocks the second target structure in the first direction.

20. The method for forming a semiconductor structure as described in claim 14, characterized in that, In the step of forming a second sidewall material layer covering the sidewalls and top of the second core layer and the third core layer, as well as the top of the substrate, the second sidewall material layer on the opposite sidewall forms a groove; After forming a second sidewall material layer covering the sidewalls and top of the second core layer and the third core layer, and the top of the base, before removing the second sidewall material layer located on the top of the second core layer and the third core layer, and the top of the base, the method further includes: forming a third partition structure extending along the second direction and contacting the second sidewall in the grooves of the first and second regions, the third partition structure partitioning the grooves in the first direction; In the step of patterning the target material layer using the second sidewall and the third core layer as a mask to form a first target structure located in the first region and a second target structure located in the second region, the target material layer is also patterned using the third partition structure as a mask to obtain a target material layer corresponding to the third partition structure that partitions the first target structure and the second target structure in the first direction.

Images