Three-dimensional integrated circuit chip and design method thereof

Abstract

The invention relates to a three-dimensional integrated circuit chip and a design method thereof, the three-dimensional integrated circuit chip comprises a first chip layer, a second chip layer and a buffer chip layer arranged between the first chip layer and the second chip layer, and the buffer chip layer and the first chip layer are vertically connected through a three-dimensional stack structure. An interconnection signal connection point between the buffer chip layer and the first chip layer is a first signal connection point; the buffer chip layer and the second chip layer are vertically connected through a three-dimensional stacked structure, and an interconnection signal connection point between the buffer chip layer and the second chip layer is a second signal connection point; at least one first signal connection point and one second signal connection point meet the condition that the first signal connection point and the second signal connection point are connected with each other through a metal wire in the buffer chip layer; and the orthographic projection of the first signal connection point on the first chip layer and the orthographic projection of the second signal connection point on the first chip layer are different in position.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of chip design technology, and in particular to a three-dimensional integrated circuit chip and its design method. Background Technology

[0002] With the development of integrated circuits, large-scale circuits and very large-scale circuits emerged. Correspondingly, the transistor density in integrated circuits has increased exponentially. Connecting transistors using interconnects within a plane occupies excessive chip area, and as manufacturing processes have iterated to a certain scale with Moore's Law, interconnect delay has become a significant factor. Therefore, three-dimensional stacking technology has become the mainstream breakthrough solution in chip design.

[0003] As a completely new field, the design process of 3D integrated circuits (3DIC) presents the following challenges: (1) As chip cell density increases or the number of stacked chips increases, the number of interconnect signals between chips increases. More interconnect signals make routing more difficult, and may even lead to areas where routing is impossible. For example... Figure 1 As shown, the large number and high density of interconnect signals in region A of the upper-layer chip cause congestion in the wiring of this region. This poses a challenge to 3DIC design, limiting the number of 3DIC chips that can be stacked or the number of interconnect signals between chips.

[0004] (2) When the location of the interconnect signal connection point between 3DIC chips overlaps with the location of the hard IP, a custom hard IP needs to be created, and interconnect signal connection points need to be reserved inside the hard IP. For example Figure 2 As shown, the upper-layer chip has a hard core located in region A', while some interconnect signal connection points of the lower-layer chip overlap vertically with the hard core. In this case, only by customizing the hard core and reserving interconnect signal connection points within it can data transmission and signal exchange between chips be achieved through interconnect signals. This has a significant impact on the design cycle and cost of 3D ICs.

[0005] (3) In the design process of 3DIC multilayer stacked chips, when the position of the interconnect signal connection point between the chips of one of the stacked chips needs to be modified, the stacked chip at the other end of the interconnect signal also needs to be modified accordingly. For example Figure 3 As shown, if the interconnect signal connection points in region A'' of the upper-layer chip need to be moved to region B'', then the corresponding interconnect signal connection points in the lower-layer chip also need to be moved to the corresponding region. This has a significant impact on the design cycle and design cost of 3DIC. Summary of the Invention

[0006] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0007] This disclosure provides a three-dimensional integrated circuit chip, including a first chip layer, a second chip layer, and a buffer chip layer disposed between the first chip layer and the second chip layer, wherein: The buffer chip layer and the first chip layer are vertically interconnected through a three-dimensional stacking structure, and the interconnection signal connection point between the buffer chip layer and the first chip layer is the first signal connection point. The buffer chip layer and the second chip layer are vertically interconnected through a three-dimensional stacking structure, and the interconnection signal connection point between the buffer chip layer and the second chip layer is the second signal connection point; There exists at least one first signal connection point and one second signal connection point that satisfy the following conditions: the first signal connection point and the second signal connection point are interconnected by metal traces in the buffer chip layer, and the orthographic projection of the first signal connection point on the first chip layer is different from the orthographic projection of the second signal connection point on the first chip layer.

[0008] This disclosure also provides a method for designing a three-dimensional integrated circuit chip, including: The first chip layer is divided into multiple sub-modules; For each sub-module, the following operations are performed: Detecting whether the sub-module can be vertically interconnected with the second chip layer through a three-dimensional stacking structure; when at least some areas of the sub-module cannot be vertically interconnected with the second chip layer through a three-dimensional stacking structure, determining the signal to be transferred by the sub-module and the target area to be transferred. The buffer chip layer is designed based on the signal to be transferred in each of the sub-modules and the target area for transfer.

[0009] The three-dimensional integrated circuit chip and its design method provided in this disclosure solve problems such as wiring congestion caused by the increase in the number of interconnection signals between chips in the current design process, the need to customize the hard core when the position of the interconnection signal connection point between 3DIC chips overlaps with the hard core position, and the need to modify the chips at both ends of the interconnection signal between chips at the same time.

[0010] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0011] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0012] Figures 1 to 3 This is a schematic diagram illustrating three application scenarios of 3D integrated circuit chips in related technologies; Figure 4 This is a schematic cross-sectional view of a three-dimensional integrated circuit chip, which is an exemplary embodiment of the present disclosure. Figures 5 to 7 Schematic diagrams of three application scenarios of the three-dimensional integrated circuit chip as an exemplary embodiment of this disclosure; Figure 8 This is a flowchart illustrating a three-dimensional integrated circuit chip design method as an exemplary embodiment of the present disclosure. Detailed Implementation

[0013] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments and features described herein can be combined arbitrarily.

[0014] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" indicate that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, but do not exclude other elements or objects.

[0015] refer to Figures 4 to 7 This disclosure provides a three-dimensional integrated circuit chip, including: a first chip layer 101, a second chip layer 102, and a buffer chip layer 103 disposed between the first chip layer 101 and the second chip layer 102.

[0016] The buffer chip layer 103 and the first chip layer 101 are vertically interconnected through a three-dimensional stacked structure, and the interconnection signal connection point between the buffer chip layer 103 and the first chip layer 101 is the first signal connection point N1. The buffer chip layer 103 and the second chip layer 102 are vertically interconnected through a three-dimensional stacked structure, and the interconnection signal connection point between the buffer chip layer 103 and the second chip layer 102 is the second signal connection point N2. There exists at least one first signal connection point N1 and one second signal connection point N2 that satisfy the following conditions: the first signal connection point N1 and the second signal connection point N2 are interconnected by metal traces in the buffer chip layer 103, and the positions of the orthographic projection of the first signal connection point N1 on the first chip layer 101 and the orthographic projection of the second signal connection point N2 on the first chip layer 101 are different.

[0017] The three-dimensional integrated circuit chip of this disclosure provides a buffer chip layer 103 between the first chip layer 101 and the second chip layer 102. By utilizing the routing resources on the buffer chip layer 103, the position of the interconnection signal connection point between chips can be changed. This can solve problems such as routing congestion caused by the increase in the number of interconnection signals between chips in the current design process, the need to customize the hard core when the position of the interconnection signal connection point between 3DIC chips overlaps with the position of the hard core, and the need to modify the chips at both ends of the interconnection signal between chips at the same time.

[0018] In some exemplary embodiments, buffer chip layer 103 and first chip layer 101 can be vertically interconnected via a first through silicon via (TSV) 201, and buffer chip layer 103 and second chip layer 102 can be vertically interconnected via a second through silicon via 202. However, this disclosure is not limiting. Buffer chip layer 103 and first chip layer 101, and buffer chip layer 103 and second chip layer 102 can also be vertically interconnected via other 3D stacking structures. For example, they can be vertically interconnected via hybrid bonding (HB) contacts, which can achieve high-bandwidth data communication.

[0019] Three-dimensional integrated circuits require a large number of TSVs to achieve interconnection between lower-level and upper-level chips, and this connection can only be a vertical interconnection. TSVs will occupy some of the chip's routing resources. When a local area of ​​the upper-level chip receives too many TSV connections from the lower-level chip, it can be determined whether the upper-level chip can achieve routing by using the routing congestion heat map in the placement phase or the error markers in the design rule checking (DRC) in the routing phase. Figure 1 In the upper-layer chip, due to the large number and high density of interconnect signals in region A, the routing in this region becomes congested. For example... Figure 5 As shown, in this embodiment of the present disclosure, in the first chip layer 101 (i.e. Figure 1 The upper layer chip) and the second chip layer 102 (i.e. Figure 1 A buffer chip layer 103 is set between the lower-level chips in the buffer chip layer 103. By utilizing the routing resources of the buffer chip layer 103, the position of some interconnect signal connection points in region A is transformed and transferred to region B, which has sparse TSVs and low chip density. This reduces the interconnect signal density in region A and solves the routing congestion problem.

[0020] Figure 2 In this scenario, the upper-layer chip has a hard core located in region A', while some interconnect signal connection points of the lower-layer chip overlap vertically with the hard core. Only by customizing the hard core and reserving interconnect signal connection points within it can data transmission and signal exchange between chips be achieved through interconnect signals. For example... Figure 6 As shown, in this embodiment of the present disclosure, in the first chip layer 101 (i.e. Figure 2 The upper layer chip) and the second chip layer 102 (i.e. Figure 2 A buffer chip layer 103 is set between the lower-level chips in the buffer chip layer 103. By utilizing the routing resources of the buffer chip layer 103, the signal connection points can be flexibly adjusted. For example, the interconnection signal connection points in region A can be changed and transferred to region B. In this way, the interconnection between the first chip layer 101 and the second chip layer 102 can be achieved without customizing the hard core.

[0021] Figure 3 In this scenario, if the interconnect signal connection points in region A'' of the upper-layer chip need to be moved to region B'', then the corresponding interconnect signal connection points in the lower-layer chip also need to be moved to the corresponding region. For example... Figure 7 As shown, in this embodiment of the present disclosure, in the first chip layer 101 (i.e. Figure 3 The upper layer chip) and the second chip layer 102 (i.e. Figure 3 A buffer chip layer 103 is set between the lower-level chips in the first chip layer 101 and the second chip layer 102. By utilizing the routing resources of the buffer chip layer 103, when the interconnect signal connection point in the A'' region of the first chip layer 101 needs to be transferred to the B'' region, the position of the corresponding interconnect signal connection point in the second chip layer 102 remains unchanged, so that the second chip layer 102 can achieve the interconnection between the first chip layer 101 and the second chip layer 102 without modification.

[0022] In some exemplary embodiments, the first chip layer 101 includes at least one computing chip, the second chip layer 102 includes at least one memory chip, and the buffer chip layer 103 includes at least one buffer chip. However, this disclosure does not limit the number of chip stacks included in each of the first chip layer 101, the second chip layer 102, and the buffer chip layer 103.

[0023] In this embodiment of the disclosure, the buffer chip refers to the chip that realizes the position change of the interconnection signal connection point between the first chip layer 101 and the second chip layer 102.

[0024] The computing chip in the embodiments of this disclosure can be used to perform large-scale neural network calculations, or it can be used to perform other calculations, such as proof-of-work operations, etc. However, this disclosure does not limit it.

[0025] The computing chip in the embodiments of this disclosure may be an application-specific integrated circuit (ASIC) processor or a many-core processor, etc., however, this disclosure does not limit it.

[0026] In some exemplary embodiments, the second chip layer 102 may include a plurality of memory chips vertically interconnected by a three-dimensional stacked structure. However, this disclosure is not limiting in this regard.

[0027] For example, such as Figure 4 As shown, multiple memory chips can be vertically interconnected via a third through-silicon via 203. However, this disclosure is not limiting. Multiple memory chips can also be vertically interconnected via other 3D stacking structures, for example, via hybrid bonding contacts.

[0028] In some exemplary embodiments, the metal trace connection line between the first signal connection point N1 and the second signal connection point N2 is provided with any of the following devices: buffer, inverter, etc., however, this disclosure does not limit this.

[0029] In this embodiment, the logic on the buffer chip layer 103 is relatively simple compared to the first chip layer 101. Generally, it only contains buffers, inverters, etc., used to solve DRC errors. The chip density is low and the routing resources are abundant.

[0030] In this embodiment of the disclosure, the buffer chip layer 103 can not only realize the position change of the interconnection signal connection point between 3DIC chips, but also realize basic logic conversion.

[0031] In some exemplary embodiments, the buffer chip layer 103 may further include a selection circuit configured to turn on or off at least one first signal connection point N1 and at least one second signal connection point N2 according to an input selection signal.

[0032] This embodiment of the disclosure allows the buffer chip layer 103 to adapt to different numbers of memory chip layers according to different customer needs by setting a selection circuit in the buffer chip layer 103.

[0033] In some exemplary embodiments, the buffer chip layer 103 may further include a detection circuit configured to detect the connection path between the first chip layer 101 and the second chip layer 102 based on an input detection signal.

[0034] For example, the memory chip layer can be divided into multiple memory modules (one memory chip can be divided into one memory module, or one memory chip can be divided into multiple memory modules). The detection circuit can receive externally input address configuration parameter information and data configuration parameter information. The detection circuit determines the memory module to be detected based on the address configuration parameter information. The detection circuit fills the memory module with data based on the data configuration parameter information. The detection circuit sends a read request to the memory module to be detected and receives the data returned by the read request. The detection circuit compares the data returned by the read request with the filled data to determine whether the memory module detection is successful based on the comparison result. Based on the detection result of the memory module, the detection circuit determines whether the connection path between the first chip layer 101 and the second chip layer 102 is connected.

[0035] In some exemplary embodiments, the buffer chip layer 103 may further include at least one of the following circuits: a serial-to-parallel conversion circuit and a parallel-to-serial conversion circuit. The serial-to-parallel conversion circuit is configured to perform at least one of the following: performing serial-to-parallel conversion on a signal input to at least one first signal connection point N1 and outputting the converted signal to a plurality of second signal connection points N2; and performing serial-to-parallel conversion on a signal input to at least one second signal connection point N2 and outputting the converted signal to a plurality of first signal connection points N1. The parallel-to-serial conversion circuit is configured to perform at least one of the following: performing parallel-to-serial conversion on a signal input to a plurality of first signal connection points N1 and outputting the converted signal to at least one second signal connection point N2; and performing parallel-to-serial conversion on a signal input to a plurality of second signal connection points N2 and outputting the converted signal to at least one first signal connection point N1.

[0036] This embodiment of the present disclosure, by providing a serial-to-parallel conversion circuit in the buffer chip layer 103, can reduce at least one of the following: the number of ports that need to be connected to the first chip layer 101 and the second chip layer 102, according to user requirements. This embodiment of the present disclosure, by providing a parallel-to-serial conversion circuit in the buffer chip layer 103, can increase at least one of the following: the number of ports that need to be connected to the first chip layer 101 and the second chip layer 102, according to user requirements.

[0037] In some exemplary embodiments, the buffer chip layer 103 may further include at least one of the following circuits: a cache circuit for caching data, a redundant circuit for managing the ports of the second chip layer, and a function detection circuit for detecting the function of the second chip layer.

[0038] When the second chip layer includes one or more memory chips, it is technically equivalent to memory. By setting a cache circuit on the buffer chip layer 103, the memory access performance of each memory chip interface can be improved. For example, a large number of concurrent memory accesses may access the same or adjacent memory addresses (i.e., the so-called spatial / temporal locality). In this case, the data read from the memory chip can be placed in the cache circuit first to facilitate a fast response to other similar memory access requests. For example, the cache circuit can be a static random access memory (SRAM) circuit.

[0039] Redundant circuits can manage the ports of the second chip layer (memory chip), achieving a certain degree of redundancy design and improving yield. For example, the second chip layer (memory chip) provides N independent memory interfaces. When the redundant circuit powers on (or dynamically), it selects M good memory interfaces and connects them to the logic circuits in the first chip layer, where M and N are natural numbers, and M < N. From the perspective of the logic circuits in the first chip layer, the second chip layer always provides M interfaces, simplifying the design of the logic circuits in the first chip layer and significantly improving the yield.

[0040] The primary function of buffer chip layer 103 is to connect the first chip layer 101 and the second chip layer 102. By setting up buffer chip layer 103, the first chip layer 101 and the second chip layer 102 can be better bonded together (including routing and signal speed matching). When the second chip layer 102 includes one or more memory chips, the memory chips are technically equivalent to memory. However, since a large number of logic circuits cannot be placed on the memory chips themselves, some memory-related functions can also be placed on buffer chip layer 103, such as function testing circuits for detecting the functions of the second chip layer. Function testing circuits can be used for wafer-level dynamic random access memory (DRAM) testing, as well as DRAM functional testing after bonding and packaging.

[0041] Since the buffer chip layer 103 of this embodiment has a relatively simple function, it is usually implemented using a lower-end process than other stacked chips, and it usually integrates fewer logic resources and metal layers. Its design cycle and production cost are usually much lower than other stacked chips.

[0042] In some exemplary implementations, such as Figure 4 As shown, the three-dimensional integrated circuit chip also includes a substrate 104, and the first chip layer 101 and the substrate 104 are electrically connected through bumps 204.

[0043] In this embodiment, the substrate 104 can be a packaging substrate. When packaging the three-dimensional integrated circuit chip, the bare chip, which includes a first chip layer, a buffer chip layer 103, and a second chip layer 102, is flipped face-up. The bare chip is connected to the packaging substrate by bumps on its surface. The packaging substrate and the printed circuit board can be connected by a ball grid array (BGA), that is, many solder balls are arranged in an array on the bottom of the packaging substrate. The solder balls serve as external pins, allowing the bare chip on the packaging substrate to connect to the printed circuit board for signal transmission.

[0044] like Figure 8 As shown in the embodiments of this disclosure, a design method for a three-dimensional integrated circuit chip is also provided. The three-dimensional integrated circuit chip includes a first chip layer, a second chip layer, and a buffer chip layer disposed between the first chip layer and the second chip layer. The design method includes: Step 801: Divide the first chip layer into multiple sub-modules; Step 802: Perform the following operations for each sub-module: detect whether the sub-module can be vertically interconnected with the second chip layer through the three-dimensional stacking structure; when at least some areas of the sub-module cannot be vertically interconnected with the second chip layer through the three-dimensional stacking structure, determine the signal to be transferred and the target area to be transferred in the sub-module. Step 803: Design a buffer chip layer based on the signal to be transferred in each submodule and the target area to be transferred.

[0045] The chip design method for three-dimensional integrated circuits disclosed in this embodiment divides a first chip layer into multiple sub-modules and detects whether each sub-module can be vertically interconnected with a second chip layer through a three-dimensional stacking structure. When at least some areas of a sub-module cannot be vertically interconnected with the second chip layer through a three-dimensional stacking structure, the signal to be transferred and the target area to be transferred are determined. A buffer chip layer is designed according to the signal to be transferred and the target area to be transferred for each sub-module. This allows the use of the routing resources on the buffer chip layer to realize the position transformation of the interconnection signal connection points between chips. This solves the problems of routing congestion caused by the increase in the number of interconnection signals between chips in the current design process, the need to customize the hard core when the position of the interconnection signal connection point between 3DIC chips overlaps with the position of the hard core, and the need to modify the chips at both ends of the interconnection signal between chips simultaneously.

[0046] In this embodiment of the present disclosure, in step 801, the first chip layer can be divided into multiple sub-modules according to functional modules; however, the present disclosure does not limit this.

[0047] In some exemplary embodiments, in step 802, detecting whether the submodule can be vertically interconnected with the second chip layer via a three-dimensional stacked structure includes at least one of the following: The detection submodule is found to have at least one region where the interconnect signal density between that region and the second chip layer exceeds a preset first density threshold. The detection submodule is used to determine if there is at least one region where the density of through-silicon vias in that region exceeds a preset second density threshold. The detection submodule is found to have at least one region where the density of functional logic circuits in that region exceeds a preset third density threshold. The signal mapping relationship between the detection submodule and the second chip layer is detected.

[0048] In this embodiment of the disclosure, when a submodule has at least one region and the interconnection signal density between that region and the second chip layer exceeds a preset first density threshold, the submodule cannot be vertically interconnected with the second chip layer through a three-dimensional stacking structure; when the interconnection signal density between each region in the submodule and the second chip layer is less than the preset first density threshold, the submodule can be vertically interconnected with the second chip layer through a three-dimensional stacking structure.

[0049] In this embodiment of the disclosure, when a submodule has at least one region and the silicon via density of that region exceeds a preset second density threshold, the submodule cannot be vertically interconnected with the second chip layer through a three-dimensional stacked structure; when the silicon via density of each region in the submodule is less than the preset second density threshold, the submodule can be vertically interconnected with the second chip layer through a three-dimensional stacked structure.

[0050] In this embodiment of the disclosure, when a submodule has at least one region and the functional logic circuit density of that region exceeds a preset third density threshold, the submodule cannot be vertically interconnected with the second chip layer through a three-dimensional stacking structure; when the functional logic circuit density of each region in the submodule is less than the preset third density threshold, the submodule can be vertically interconnected with the second chip layer through a three-dimensional stacking structure.

[0051] In this embodiment of the disclosure, when detecting the signal mapping relationship between the submodule and the second chip layer, if at least one of the following situations occurs: there is an obstructed area within the submodule (for example, part of the signal mapping area corresponding to the second chip layer in the submodule is occupied by a hard core), there is a missing pin location within the submodule, or the logic signal mapping relationship within the submodule changes, then the submodule cannot be vertically interconnected with the second chip layer through the three-dimensional stacking structure. In this embodiment of the present disclosure, the preset first density threshold, the preset second density threshold, and the preset third density threshold can all be set according to actual needs. When designing different chips, the preset first density threshold, the preset second density threshold, and the preset third density threshold can be different, and this disclosure does not limit this.

[0052] In this embodiment of the disclosure, when detecting whether each sub-module can be vertically interconnected with the second chip layer through the three-dimensional stacked structure, the determination can also be made by combining the densities of multiple sub-modules (interconnection signal density / through-silicon via density / functional logic circuit density, etc.).

[0053] In some exemplary embodiments, in step 802, determining the signal to be transferred by the submodule includes: Prioritize the signals within the submodule according to their timing. Signals with timing priorities higher than the preset timing priority threshold are identified as signals to be transferred by the submodule.

[0054] In this embodiment of the disclosure, the timing priority of signals within a submodule can be determined according to the ease of implementation. Signals that are more difficult to implement are identified as signals with higher timing priority, while signals that are easier to implement are identified as signals with lower timing priority.

[0055] For example, there are two groups of signals: group A and group B. If the logic of group A is more complex (or group A is a critical path) and timing is tight, then the priority is lower. Moving it to another location may increase the timing, so try not to move group A signals. Group B signals have relatively simpler logic (non-critical path), so the priority is higher, and try to move group B signals.

[0056] In some exemplary embodiments, determining the signal to be transferred for the submodule further includes: Determine the correlation between signals within the submodule; Signals whose correlation with the signals already identified as sub-modules to be transferred is higher than a preset correlation threshold are also identified as signals to be transferred by sub-modules.

[0057] This embodiment of the disclosure determines that signals with a correlation higher than a preset correlation threshold to be transferred by the submodule are also signals to be transferred by the submodule. This allows one or more groups of signals with high correlation to be moved to the target area.

[0058] In some exemplary implementations, the target region satisfies the following conditions: The interconnect signal density between the target region and the second chip layer is less than a preset first density threshold. The density of through-silicon vias within the target area is less than a preset second density threshold; The density of functional logic circuits within the target area is less than the preset third density threshold; The signal mapping between the target area and the second chip layer is not blocked (e.g., not blocked by a hard core), and the target area does not lack pin locations.

[0059] In some other exemplary embodiments, the target area also satisfies the following condition: the distance between the target area and the area where the signal was located before the transfer is less than or equal to a preset distance threshold.

[0060] In this embodiment of the disclosure, the preset distance threshold can be set as needed. For example, when there are multiple target areas that meet the above conditions to choose from, the target area with the shortest distance to the area where the signal was located before the transfer can be selected as the most suitable target area. Alternatively, one or more target areas can be selected as the most suitable target areas by comprehensively considering the signal correlation and the distance between multiple target areas that meet the above conditions and the area where the signal was located before the transfer.

[0061] In some exemplary embodiments, the method further includes: The signal mapping relationship between the first chip layer and the second chip layer is compared; Based on the comparison results and the physical location of the logic function, corresponding logic circuits are added to the buffer chip layer. The logic circuits include at least one of the following: selection circuit, detection circuit, serial-to-parallel conversion circuit, and parallel-to-serial conversion circuit.

[0062] In this embodiment, the added logic circuit can be a selection circuit, a detection circuit, a serial-to-parallel conversion circuit, a parallel-to-serial conversion circuit, or other circuits required to meet the chip's functional requirements; this disclosure does not limit this. For example, in the design of a 3DIC multilayer stacked chip, when the interconnect signal connection point in region A'' of the upper chip needs to be moved to region B'', if only the connection position changes, a buffer and adjusted metal traces can be added to the buffer chip layer; if it involves adjustments to the circuit function, a detection circuit or port-optimized serial-to-parallel conversion circuit, parallel-to-serial conversion circuit, or other corresponding logic circuits can be added to the buffer chip layer to increase or decrease port connections. Thus, when the interconnect signal connection point in region A of the upper chip needs to be moved to region B, the position of the corresponding interconnect signal connection point in the lower chip can remain unchanged, allowing the lower chip to achieve interconnection between the two chips without modification.

[0063] In this embodiment of the disclosure, the signals of the first chip layer and the signals of the second chip layer can be compared according to the signal flow direction.

[0064] In some exemplary embodiments, the method further includes: providing at least one of the following circuits in the buffer chip layer: a cache circuit for caching data, a redundant circuit for managing ports of the second chip layer, and a function detection circuit for detecting the function of the second chip layer.

[0065] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0066] It should be noted that the above embodiments or implementation methods are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the content specifically shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the implementations without departing from the scope of this disclosure.

Claims

1. A three-dimensional integrated circuit chip, characterized in that, It includes a first chip layer, a second chip layer, and a buffer chip layer disposed between the first chip layer and the second chip layer, wherein: The buffer chip layer and the first chip layer are vertically interconnected through a three-dimensional stacking structure, and the interconnection signal connection point between the buffer chip layer and the first chip layer is the first signal connection point. The buffer chip layer and the second chip layer are vertically interconnected through a three-dimensional stacking structure, and the interconnection signal connection point between the buffer chip layer and the second chip layer is the second signal connection point; There exists at least one first signal connection point and one second signal connection point that satisfy the following conditions: the first signal connection point and the second signal connection point are interconnected by metal traces in the buffer chip layer, and the orthographic projection of the first signal connection point on the first chip layer is different from the orthographic projection of the second signal connection point on the first chip layer.

2. The three-dimensional integrated circuit chip according to claim 1, characterized in that, The buffer chip layer is vertically interconnected with the first chip layer through a first through-silicon via, and the buffer chip layer is vertically interconnected with the second chip layer through a second through-silicon via. The first chip layer includes at least one computing chip, the second chip layer includes at least one storage chip, and the buffer chip layer includes at least one buffer chip, which is a chip that realizes the position change of the interconnection signal connection point between the first chip layer and the second chip layer.

3. The three-dimensional integrated circuit chip according to claim 2, characterized in that, The second chip layer includes a plurality of memory chips, which are vertically interconnected through a third through-silicon via.

4. The three-dimensional integrated circuit chip according to claim 1, characterized in that, The buffer chip layer includes one or more metal traces, and at least one of the metal traces is provided with any one of the following devices: a buffer or an inverter.

5. The three-dimensional integrated circuit chip according to claim 1, characterized in that, The buffer chip layer includes a selection circuit configured to turn on or off at least one of the first signal connection points and at least one of the second signal connection points according to an input selection signal.

6. The three-dimensional integrated circuit chip according to claim 1, characterized in that, The buffer chip layer includes a detection circuit configured to detect the connection path between the first chip layer and the second chip layer based on an input detection signal.

7. The three-dimensional integrated circuit chip according to claim 1, characterized in that, The buffer chip layer includes at least one of the following: a serial-to-parallel conversion circuit and a parallel-to-serial conversion circuit. The serial-to-parallel conversion circuit is configured to perform at least one of the following: perform serial-to-parallel conversion on a signal input to at least one first signal connection point and output the converted signal to a plurality of second signal connection points; and perform serial-to-parallel conversion on a signal input to at least one second signal connection point and output the converted signal to a plurality of first signal connection points. The parallel-to-serial conversion circuit is configured to perform parallel-to-serial conversion on a signal input to a plurality of first signal connection points and output the converted signal to at least one second signal connection point; and perform parallel-to-serial conversion on a signal input to a plurality of second signal connection points and output the converted signal to at least one first signal connection point.

8. The three-dimensional integrated circuit chip according to claim 1, characterized in that, The buffer chip layer includes at least one of the following: a cache circuit for caching data, a redundant circuit for managing the ports of the second chip layer, and a function detection circuit for detecting the function of the second chip layer.

9. A design method for a three-dimensional integrated circuit chip, characterized in that, The three-dimensional integrated circuit chip includes a first chip layer, a second chip layer, and a buffer chip layer disposed between the first chip layer and the second chip layer; the design method includes: The first chip layer is divided into multiple sub-modules; For each sub-module, the following operations are performed: Detecting whether the sub-module can be vertically interconnected with the second chip layer through a three-dimensional stacking structure; when at least some areas of the sub-module cannot be vertically interconnected with the second chip layer through a three-dimensional stacking structure, determining the signal to be transferred by the sub-module and the target area to be transferred. The buffer chip layer is designed based on the signal to be transferred in each of the sub-modules and the target area for transfer.

10. The design method according to claim 9, characterized in that, The detection of whether the submodule can be vertically interconnected with the second chip layer through a three-dimensional stacking structure includes at least one of the following: Detect whether the submodule has at least one region where the interconnect signal density between the region and the second chip layer exceeds a preset first density threshold; The submodule is detected to have at least one region where the density of through-silicon vias in the region exceeds a preset second density threshold. Detect whether the submodule has at least one region where the density of functional logic circuits within the region exceeds a preset third density threshold; Detect the signal mapping relationship between the submodule and the second chip layer.

11. The design method according to claim 9, characterized in that, The signal used to determine the submodule to be transferred includes: Perform timing priority sorting on the signals within the submodule; Signals with timing priorities lower than a preset timing priority threshold are identified as signals to be transferred by the submodule.

12. The design method according to claim 11, characterized in that, The signal for determining the submodule to be transferred also includes: Determine the correlation between signals within the submodule; Signals whose correlation with the signals to be transferred by the sub-module is higher than a preset correlation threshold are also identified as signals to be transferred by the sub-module.

13. The design method according to claim 10, characterized in that, The method further includes: The signal mapping relationship between the first chip layer and the second chip layer is compared. Based on the comparison results and the physical location of the logic function, a corresponding logic circuit is added to the buffer chip layer. The logic circuit includes at least one of the following: a selection circuit, a detection circuit, a serial-to-parallel conversion circuit, and a parallel-to-serial conversion circuit.

14. The design method according to claim 9, characterized in that, The method further includes: The buffer chip layer includes at least one of the following circuits: a cache circuit for caching data, a redundant circuit for managing the ports of the second chip layer, and a function detection circuit for detecting the function of the second chip layer.

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